Floating gate type split-gate flash memory device with double halo ring structure and manufacturing method of floating gate type split-gate flash memory device

Abstract

The invention provides a floating gate type split-gate flash memory device with a double-halo ring structure. The floating gate type split-gate flash memory device comprises a P-type substrate; the deep N well is formed by ion implantation; the high-voltage P well is positioned on the deep N well; a tunneling oxide layer is formed on the substrate, a storage cell is formed on the tunneling oxide layer, the storage cell comprises a first laminated structure and a second laminated structure, and the exposed tunneling oxide layer is etched to a preset thickness; the lightly-doped drain region and the lightly-doped leakage halo ring region of the storage cell are formed by ion implantation, and the first lightly-doped leakage halo ring region has a first doping concentration; a self-aligned source n-type heavily doped region and a self-aligned source pocket region are formed on a substrate between a first laminated structure and a second laminated structure by utilizing ion implantation of a self-aligned source, the self-aligned source pocket region has a second doping concentration, and the first doping concentration and the second doping concentration jointly adjust the channel carrier concentration so as to adjust the threshold voltage of the device. According to the invention, a CVT photomask can be omitted, and the threshold voltage of the device is almost the same as that when the device is not changed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a floating gate type split-gate flash memory device with a double halo structure and a manufacturing method thereof. Background Art

[0002] The threshold voltage (Vt) is one of the main performance parameters of transistors. Generally, the threshold voltage depends on a variety of device materials and process parameters, such as substrate doping concentration, gate electrode material, gate dielectric material and thickness, dielectric and interface charge density. However, when the gate dielectric and electrode materials and process conditions are determined, the only parameter that can adjust the device threshold voltage is the substrate doping concentration, that is, the well region doping. Research results show that the impurity concentration in the channel region under the gate dielectric is the main factor affecting the threshold voltage. In the device manufacturing process, the threshold voltage adjustment injection (Vtadjust injection) method is usually used to achieve the purpose of adjusting the threshold voltage. For N-type devices, that is, after the well ion injection, a P-type impurity is injected so that the transistor surface has a suitable P-type impurity concentration distribution and the expected threshold voltage is obtained.

[0003] The CVT (Cell Vt adjust) ion implantation requires a separate photolithography plate for CVT ion implantation, and this ion implantation is only to increase the impurity concentration in the device channel to obtain the expected threshold voltage, which increases the manufacturing cost.

[0004] In order to solve the above problems, it is necessary to propose a novel floating gate split-gate flash memory device with a double halo structure and a manufacturing method thereof. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a floating gate split-gate flash memory device with a double halo structure and a method for manufacturing the same, so as to solve the problem in the prior art that ion implantation for adjusting the threshold voltage of the storage cell requires a separate photolithography plate, resulting in increased manufacturing costs.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a floating gate split-gate flash memory device with a double halo ring structure, comprising:

[0007] P-type substrate;

[0008] Shallow trench isolation is formed on the substrate to define the active area of ​​the storage cell;

[0009] A deep N-well formed by ion implantation and a high-voltage P-well located on the deep N-well;

[0010] A tunneling oxide layer is formed on the substrate, on which a tunneling oxide layer, a floating gate polysilicon layer, an inter-electrode dielectric layer, and a control gate polysilicon layer are sequentially stacked from bottom to top;

[0011] A storage cell formed by the tunneling oxide layer, the floating gate polysilicon layer, the inter-electrode dielectric layer, and the control gate polysilicon layer stacked in sequence in a graphic manner, wherein the storage cell comprises a first and a second stacked structure, and the exposed tunneling oxide layer is etched to a preset thickness;

[0012] A lightly doped drain region and a lightly doped drain halo region of the storage cell formed by ion implantation, wherein the first lightly doped drain halo region has a first doping concentration, and the lightly doped drain region and the lightly doped drain halo region are located on the sides of the first and second stacked structures and between them;

[0013] A self-aligned source n-type heavily doped region and a self-aligned source pocket region are formed on the substrate between the first and second stacked structures by self-aligned source ion implantation, wherein the self-aligned source pocket region has a second doping concentration, and the first and second doping concentrations jointly adjust the channel carrier concentration to adjust the threshold voltage of the device;

[0014] Sidewalls, the sidewalls being located on the sidewalls of the patterned first and second stacked structures and the gap therebetween;

[0015] The source and drain regions of the storage cell are formed by ion implantation.

[0016] Preferably, the inter-electrode dielectric layer is an ONO layer, which is composed of a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top.

[0017] Preferably, the doping ions of the first lightly doped halo ring region are boron ions.

[0018] Preferably, the doping ions in the self-aligned source pocket region are boron ions.

[0019] Preferably, the sidewall is an ONO layer, which is composed of a third oxide layer, a second nitride layer, and a fourth oxide layer stacked in sequence from bottom to top.

[0020] The present invention also provides a method for manufacturing the above-mentioned floating gate split-gate flash memory device with a double halo ring structure, comprising:

[0021] Step 1, providing a P-type substrate, and sequentially forming a first hard mask layer and a second hard mask layer on the substrate;

[0022] Step 2: forming shallow trench isolation on the first and second hard mask layers and the substrate thereunder to define an active area of ​​a storage cell, and removing the second hard mask layer; forming a deep N well and a high-voltage P well on the deep N well by ion implantation;

[0023] Step 3: removing the first hard mask layer, forming a tunneling oxide layer on the substrate, and forming a tunneling oxide layer, a floating gate polysilicon layer, an inter-electrode dielectric layer, and a control gate polysilicon layer stacked in sequence from bottom to top on the tunneling oxide layer;

[0024] Step 4: patterning the tunneling oxide layer, floating gate polysilicon layer, inter-electrode dielectric layer, and control gate polysilicon layer stacked in sequence to form a storage cell, wherein the storage cell includes a first and a second stacked structure, and etching the exposed tunneling oxide layer to a preset thickness;

[0025] Step 5: forming a lightly doped drain region and a lightly doped drain halo region of the storage cell by ion implantation, wherein the first lightly doped drain halo region has a first doping concentration, and the lightly doped drain region and the lightly doped drain halo region are located on the sides of the first and second stacked structures and between them;

[0026] Step 6: using self-aligned source ion implantation to form a self-aligned source n-type heavily doped region and a self-aligned source pocket region on the substrate between the first and second stacked structures, wherein the self-aligned source pocket region has a second doping concentration, and the first and second doping concentrations jointly adjust the channel carrier concentration to adjust the threshold voltage of the device;

[0027] Step 7: forming sidewalls by deposition and back etching, wherein the sidewalls are located on the sidewalls of the patterned first and second stacked structures and the gap therebetween;

[0028] Step eight: forming the source and drain regions of the storage cell by ion implantation.

[0029] Preferably, the first hard mask layer in step one is a pad oxide layer.

[0030] Preferably, the second hard mask layer in step one is a second oxide layer.

[0031] Preferably, in step 2, the second hard mask layer is removed by wet etching.

[0032] Preferably, step 2 further comprises a step of annealing the shallow trench isolation after forming the shallow trench isolation.

[0033] Preferably, in step three, the first hard mask layer is removed by wet etching.

[0034] Preferably, the inter-electrode dielectric layer in step three is an ONO layer, which is composed of a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top.

[0035] Preferably, in step four, the storage cell is formed by photolithography and etching.

[0036] Preferably, the doping ions of the first lightly doped halo ring region in step five are boron ions.

[0037] Preferably, the doping ions in the self-aligned source pocket region in step six are boron ions.

[0038] Preferably, the sidewall in step seven is an ONO layer, which is composed of a third oxide layer, a second nitride layer, and a fourth oxide layer stacked in sequence from bottom to top.

[0039] As described above, the floating gate split-gate flash memory device with a double halo structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0040] The present invention can omit the CVT (Cell Vt adjust) mask, and the threshold voltage of the device is almost the same as when no change is made. The process has a small change in the ions in the self-aligned source region and the lightly doped drain region, which will not affect the performance of the storage cell device, and has little impact on other devices on the platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Shown is a schematic diagram of the process flow of the present invention;

[0042] Figure 2 It is a schematic diagram showing the formation of the first and second hard mask layers of the present invention;

[0043] Figure 3 It is a schematic diagram showing the formation of shallow trench isolation and removal of the second hard mask layer according to the present invention;

[0044] Figure 4 It is a schematic diagram showing the formation of a tunnel oxide layer and a stacked layer according to the present invention;

[0045] Figure 5 Shown is a schematic diagram of forming a storage cell of the present invention;

[0046] Figure 6 It is a schematic diagram showing the formation of a lightly doped drain region and a lightly doped drain halo region according to the present invention;

[0047] Figure 7 Shown is a schematic diagram of forming a side wall of the present invention;

[0048] Figure 8 Shown is a schematic diagram of forming source and drain regions according to the present invention;

[0049] Fig. 9 Shown is a schematic diagram of device simulation results of the present invention. DETAILED DESCRIPTION

[0050] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] The present invention reduces the number of plates in order to improve product competitiveness. Considering that the CVT (Cell Vt adjust) implant requires a separate photolithography plate for CVT ion implantation, and this ion implantation is only to increase the impurity concentration at the device channel to obtain the expected threshold voltage, in order to save costs, the present invention attempts to omit this photolithography compared to the prior art, and attempts to combine this implantation with other boron ion implantations, so as to achieve the purpose of saving plates without affecting the threshold voltage of the device.

[0052] Considering the Boron injection of the storage cell device, only the high-voltage P well 109 and the self-aligned source n-type heavily doped region 110-2 (SelfAligned Source) contain Boron ion injection. However, changes in the ion injection of the high-voltage P well 109 will also have corresponding effects on other MOS devices. The halo ion injection in the self-aligned source n-type heavily doped region 110-2 ion injection is concentrated, and the doping dose required is relatively high, which will lead to problems such as increased resistance of the self-aligned source n-type heavily doped region 110-2 when the device is working. Therefore, a lightly doped drain halo region 112-1 ion injection is added to the original storage cell lightly doped drain ion injection. The self-aligned source pocket region 110-1 of the self-aligned source n-type heavily doped region 110-2 is appropriately concentrated to form a double halo structure, so that the device threshold voltage reaches the expected value. Thereby, the CVT mask is omitted without affecting the device.

[0053] Embodiment 1

[0054] See also Figure 8 The present invention provides a floating gate split-gate flash memory device with a double halo ring structure, comprising:

[0055] A P-type substrate 101;

[0056] Shallow trench isolation is formed on the substrate 101 to define the active area of ​​the memory cell;

[0057] A deep N-well 108 formed by ion implantation and a high-voltage P-well 109 located on the deep N-well 108;

[0058] A tunneling oxide layer 103 is formed on the substrate 101, and a tunneling oxide layer 103, a floating gate polysilicon layer 104, an inter-electrode dielectric layer 105, and a control gate polysilicon layer 106 are sequentially stacked from bottom to top on the tunneling oxide layer 103;

[0059] In some embodiments, the inter-electrode dielectric layer 105 is an ONO layer, which is composed of a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top.

[0060] A storage cell is formed by a tunneling oxide layer 103, a floating gate polysilicon layer 104, an inter-electrode dielectric layer 105, and a control gate polysilicon layer 106 which are sequentially stacked in a patterned manner, and the storage cell includes a first and a second stacked structure, and the exposed tunneling oxide layer 103 is etched to a preset thickness;

[0061] The lightly doped drain region 107 and the lightly doped drain halo region 112-1 of the storage cell are formed by ion implantation, the first lightly doped drain halo region 112-1 has a first doping concentration, and the lightly doped drain region 107 and the lightly doped drain halo region 112-1 are located on the sides of the first and second stacked structures and between them;

[0062] In some embodiments, the doping ions of the first lightly doped halo region 112 - 1 are boron ions. In other embodiments, the ions implanted therein may also be other Group III elements.

[0063] By using self-aligned source ion implantation, a self-aligned source n-type heavily doped region 110-2 and a self-aligned source pocket region 110-1 are formed on the substrate 101 between the first and second stacked structures. The self-aligned source pocket region 110-1 has a second doping concentration. The first and second doping concentrations jointly adjust the channel carrier concentration to adjust the threshold voltage of the device.

[0064] In some embodiments, the doping ions of the self-aligned source pocket region 110 - 1 are boron ions. In other embodiments, the ions implanted therein may also be other Group III elements.

[0065] Sidewalls 111, the sidewalls 111 are located on the sidewalls of the patterned first and second stacked structures and the gap therebetween;

[0066] In some embodiments, the spacer 111 is an ONO layer, which is composed of a third oxide layer, a second nitride layer, and a fourth oxide layer stacked in sequence from bottom to top. In other embodiments, the spacer 111 can also be other known spacer materials.

[0067] The source and drain regions 112 - 2 of the memory cell are formed by ion implantation.

[0068] The simulation results are as follows Fig. 9As shown in the figure, after skipping the CVT ion implantation, the threshold voltage of the device drops from 1.609V to 0.212V, a decrease of nearly 90%. However, by adopting the manufacturing process of the present invention, CVT lithography and ion implantation are omitted. The device threshold voltage is effectively increased by relying on the double halo ring structure, and the final device threshold voltage reaches 1.605V. Compared with the prior art value of 1.609V, the deviation is less than 0.3%.

[0069] Embodiment 2

[0070] The present invention also provides a method for manufacturing the above-mentioned floating gate split-gate flash memory device with a double halo ring structure, comprising:

[0071] Step 1: Provide a P-type substrate 101, and sequentially form a first hard mask layer and a second hard mask layer on the substrate 101 to form a Figure 2 The structure shown;

[0072] In some embodiments, the first hard mask layer 102 in step 1 is a pad oxide layer.

[0073] In some embodiments, the second hard mask layer 501 in step 1 is a second oxide layer.

[0074] Step 2: shallow trench isolation is formed on the first and second hard mask layers and the substrate 101 thereunder to define the active area of ​​the storage cell, and the second hard mask layer 501 is removed; a deep N well 108 and a high voltage P well 109 located on the deep N well 108 are formed by ion implantation, so as to form Figure 3 The structure shown;

[0075] In some embodiments, in step 2, the second hard mask layer 501 is removed by wet etching, and the first hard mask layer 102 serves as an etching protection layer.

[0076] In some embodiments, step 2 further includes a step of annealing the shallow trench isolation after forming the shallow trench isolation.

[0077] Step 3: remove the first hard mask layer 102, form a tunnel oxide layer 103 on the substrate 101, and form a tunnel oxide layer 103, a floating gate polysilicon layer 104, an inter-electrode dielectric layer 105, and a control gate polysilicon layer 106 stacked from bottom to top on the tunnel oxide layer 103 to form a Figure 4 The structure shown;

[0078] In some embodiments, in step three, the first hard mask layer 102 is removed by wet etching.

[0079] In some embodiments, the inter-electrode dielectric layer 105 in step three is an ONO layer, which is composed of a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top.

[0080] Step 4: Patterning the tunneling oxide layer 103, the floating gate polysilicon layer 104, the inter-electrode dielectric layer 105, and the control gate polysilicon layer 106 stacked in sequence to form a storage cell. The storage cell includes a first and a second stacked structure. The exposed tunneling oxide layer 103 is etched to a preset thickness to form a storage cell. Figure 5 The structure shown;

[0081] In some embodiments, in step 4, the storage cells are formed by photolithography and etching methods.

[0082] Step 5: Use ion implantation to form a lightly doped drain region 107 and a lightly doped drain halo region 112-1 of the storage cell. The first lightly doped drain halo region 112-1 has a first doping concentration. The lightly doped drain region 107 and the lightly doped drain halo region 112-1 are located on the sides of the first and second stacked structures and between them, forming a structure as shown in FIG. Figure 6 The structure shown;

[0083] In some embodiments, the doping ions of the first lightly doped halo region 112 - 1 in step 5 are boron ions. In other embodiments, the ions implanted there may also be other Group III elements.

[0084] Step 6: using self-aligned source ion implantation, a self-aligned source n-type heavily doped region 110-2 and a self-aligned source pocket region 110-1 are formed on the substrate 101 between the first and second stacked structures. The self-aligned source pocket region 110-1 has a second doping concentration. The first and second doping concentrations jointly adjust the channel carrier concentration to adjust the threshold voltage of the device.

[0085] In some embodiments, the doping ions of the self-aligned source pocket region 110 - 1 in step 6 are boron ions. In other embodiments, the ions implanted there may also be other Group III elements.

[0086] Step 7: Form a sidewall 111 by deposition and back etching. The sidewall 111 is located on the sidewalls of the first and second stacked structures after patterning and the gap between them, forming a sidewall 111. Figure 7 The structure shown;

[0087] In some embodiments, the sidewall spacer 111 in step seven is an ONO layer, which is composed of a third oxide layer, a second nitride layer, and a fourth oxide layer stacked sequentially from bottom to top. In other embodiments, the sidewall spacer 111 can also be other known sidewall spacer materials.

[0088] Step 8: Use ion implantation to form the source and drain regions 112-2 of the storage cell, forming Figure 8In the structure shown, the self-aligned source n-type heavily doped region 110-2 and the self-aligned source pocket region 110-1 have been completely filled and covered by the sidewall 111, so the self-aligned source n-type heavily doped region 110-2 and the self-aligned source pocket region 110-1 will not undergo ion implantation of the source and drain regions 112-2.

[0089] The simulation results are as follows Fig. 9 As shown in the figure, after skipping the CVT ion implantation, the threshold voltage of the device drops from 1.609V to 0.212V, a decrease of nearly 90%. However, by adopting the manufacturing process of the present invention, CVT lithography and ion implantation are omitted. The device threshold voltage is effectively increased by relying on the double halo ring structure, and the final device threshold voltage reaches 1.605V. Compared with the prior art value of 1.609V, the deviation is less than 0.3%.

[0090] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0091] In summary, the present invention can omit the CVT (Cell Vt adjust, storage cell threshold voltage adjustment) mask, and the threshold voltage of the device is almost exactly the same as when no change is made. The process has small changes in the ions in the self-aligned source region and the lightly doped drain region, and will not affect the performance of the storage cell device, and has little impact on other devices on the platform. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0092] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A floating gate split-gate flash memory device with a double halo ring structure, It is characterized in that include: P-type substrate; Shallow trench isolation is formed on the substrate to define the active area of ​​the storage cell; A deep N-well formed by ion implantation and a high-voltage P-well located on the deep N-well; A tunneling oxide layer is formed on the substrate, on which a tunneling oxide layer, a floating gate polysilicon layer, an inter-electrode dielectric layer, and a control gate polysilicon layer are sequentially stacked from bottom to top; A storage cell formed by the tunneling oxide layer, the floating gate polysilicon layer, the inter-electrode dielectric layer, and the control gate polysilicon layer stacked in sequence in a graphic manner, wherein the storage cell comprises a first and a second stacked structure, and the exposed tunneling oxide layer is etched to a preset thickness; A lightly doped drain region and a lightly doped drain halo region of the storage cell formed by ion implantation, wherein the first lightly doped drain halo region has a first doping concentration, and the lightly doped drain region and the lightly doped drain halo region are located on the sides of the first and second stacked structures and between them; A self-aligned source n-type heavily doped region and a self-aligned source pocket region are formed on the substrate between the first and second stacked structures by self-aligned source ion implantation, wherein the self-aligned source pocket region has a second doping concentration, and the first and second doping concentrations jointly adjust the channel carrier concentration to adjust the threshold voltage of the device; Sidewalls, the sidewalls being located on the sidewalls of the patterned first and second stacked structures and the gap therebetween; The source and drain regions of the storage cell are formed by ion implantation.

2. The floating gate split-gate flash memory device with a double halo structure according to claim 1, Features: The inter-electrode dielectric layer is an ONO layer, which is composed of a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top.

3. The floating gate split-gate flash memory device with a double halo structure according to claim 1, Features: The doping ions of the first lightly doped halo ring region are boron ions.

4. The floating gate split-gate flash memory device with a double halo structure according to claim 1, Features: The doping ions of the self-aligned source pocket region are boron ions.

5. The floating gate split-gate flash memory device with a double halo structure according to claim 1, Features: The side wall is an ONO layer, which is composed of a third oxide layer, a second nitride layer, and a fourth oxide layer stacked in sequence from bottom to top.

6. A method for manufacturing a floating gate split-gate flash memory device with a double halo structure according to any one of claims 1 to 5, It is characterized in that At least: Step 1, providing a P-type substrate, and sequentially forming a first hard mask layer and a second hard mask layer on the substrate; Step 2: forming shallow trench isolation on the first and second hard mask layers and the substrate thereunder to define an active area of ​​a storage cell, and removing the second hard mask layer; forming a deep N well and a high-voltage P well on the deep N well by ion implantation; Step 3: removing the first hard mask layer, forming a tunneling oxide layer on the substrate, and forming a tunneling oxide layer, a floating gate polysilicon layer, an inter-electrode dielectric layer, and a control gate polysilicon layer stacked in sequence from bottom to top on the tunneling oxide layer; Step 4: patterning the tunneling oxide layer, floating gate polysilicon layer, inter-electrode dielectric layer, and control gate polysilicon layer stacked in sequence to form a storage cell, wherein the storage cell includes a first and a second stacked structure, and etching the exposed tunneling oxide layer to a preset thickness; Step 5: forming a lightly doped drain region and a lightly doped drain halo region of the storage cell by ion implantation, wherein the first lightly doped drain halo region has a first doping concentration, and the lightly doped drain region and the lightly doped drain halo region are located on the sides of the first and second stacked structures and between them; Step 6: using self-aligned source ion implantation to form a self-aligned source n-type heavily doped region and a self-aligned source pocket region on the substrate between the first and second stacked structures, wherein the self-aligned source pocket region has a second doping concentration, and the first and second doping concentrations jointly adjust the channel carrier concentration to adjust the threshold voltage of the device; Step 7: forming sidewalls by deposition and back etching, wherein the sidewalls are located on the sidewalls of the patterned first and second stacked structures and the gap therebetween; Step eight: forming the source and drain regions of the storage cell by ion implantation.

7. The method for manufacturing the floating gate split-gate flash memory device with a double halo structure according to claim 6, Features: The first hard mask layer in step one is a pad oxide layer.

8. The method for manufacturing the floating gate split-gate flash memory device with a double halo structure according to claim 6, Features: The second hard mask layer in step one is a second oxide layer.

9. The method for manufacturing a floating gate split-gate flash memory device with a double halo structure according to claim 6, Features: In step 2, the second hard mask layer is removed by wet etching.

10. The method for manufacturing a floating gate split-gate flash memory device with a double halo structure according to claim 6, Features: Step 2: After forming the shallow trench isolation, the step further includes a step of annealing the shallow trench isolation.

11. The method for manufacturing a floating gate split-gate flash memory device with a double halo structure according to claim 6, Features: In step three, the first hard mask layer is removed by wet etching.

12. The method for manufacturing a floating gate split-gate flash memory device with a double halo structure according to claim 6, Features: The inter-electrode dielectric layer in step three is an ONO layer, which is composed of a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top.

13. The method for manufacturing a floating gate split-gate flash memory device with a double halo structure according to claim 6, Features: In step 4, the storage cell is formed by photolithography and etching.

14. The method for manufacturing a floating gate split-gate flash memory device with a double halo structure according to claim 6, Features: The doping ions of the first lightly doped halo ring region in step five are boron ions.

15. The method for manufacturing a floating gate split-gate flash memory device with a double halo structure according to claim 6, Features: The doping ions of the self-aligned source pocket region in step six are boron ions.

16. The method for manufacturing a floating gate split-gate flash memory device with a double halo structure according to claim 6, Features: The side wall in step seven is an ONO layer, which is composed of a third oxide layer, a second nitride layer, and a fourth oxide layer stacked in sequence from bottom to top.

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