Formation method of semiconductor structure

Abstract

The invention relates to a method for forming a semiconductor structure, which comprises the following steps of: providing a substrate which comprises an NMOS (N-channel Metal Oxide Semiconductor) region and a PMOS (P-channel Metal Oxide Semiconductor) region, and respectively arranging a gate layer and a source-drain region formed in the substrate at two sides of the gate layer on the surface of the substrate in the NMOS region and the PMOS region; stress layers are formed on the surface of the substrate and the side wall and the top surface of the gate layer; carrying out stress relief treatment on the stress layer of the PMOS region; carrying out annealing treatment on the stress layer of the NMOS region; patterning the stress layer after the stress relief treatment and the annealing treatment until the top surface of the gate layer and the top surface of the source-drain region are exposed; forming metal silicide on the exposed top surface of the gate layer and the exposed top surface of the source and drain region; therefore, the cost can be saved, the manufacturing time can be shortened, the performance of the formed semiconductor structure is not influenced, and the method has a wide application range.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the development of CMOS integrated circuit manufacturing technology and the reduction of key dimensions, many new methods have been applied to device manufacturing technology to improve device performance. High stress silicon nitride film has been introduced into the integrated circuit manufacturing process because it can effectively improve the carrier mobility of MOS tubes and thus increase the operating speed of the device.

[0003] Metal silicide is widely used in source / drain contacts or gate contacts of integrated circuit devices due to its low resistivity and easy bonding with silicon substrates. When the semiconductor process feature size is miniaturized to below deep submicron, refractory metal is used to react with the silicon in the active area of ​​the device and the gate in direct contact to form silicide, and the metal will not react with the contacting materials such as silicon dioxide, silicon nitride, silicon oxynitride, etc., so the silicide can be well aligned with the active area and the gate.

[0004] However, the performance and production process of CMOS devices still need to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an NMOS region and a PMOS region, the substrate surfaces of the NMOS region and the PMOS region respectively having a gate layer and source / drain regions formed in the substrate on both sides of the gate layer; forming a stress layer on the surface of the substrate and on the sidewalls and top surface of the gate layer; performing stress relief treatment on the stress layer in the PMOS region; performing annealing treatment on the stress layer in the NMOS region; patterning the stress layer after the stress relief treatment and the annealing treatment until the top surface of the gate layer and the top surface of the source / drain region are exposed; and forming metal silicide on the exposed top surface of the gate layer and the top surface of the source / drain region.

[0007] Optionally, the material of the stress layer includes silicon nitride.

[0008] Optionally, the method of performing stress relief treatment on the stress layer in the PMOS region includes irradiating the stress layer in the PMOS region with ultraviolet rays.

[0009] Optionally, the method of performing stress relief treatment on the stress layer in the PMOS region includes bombarding the stress layer in the PMOS region by an ion bombardment process.

[0010] Optionally, the process parameters of the annealing treatment include an annealing time of less than 10 seconds and a temperature range of 900° C. to 1100° C.

[0011] Optionally, the stress layer has a thickness ranging from 400 to 600 angstroms.

[0012] Optionally, the method of patterning the stress layer after the stress relief treatment and the annealing treatment to expose the top surface of the gate layer and the top surface of the source and drain region includes: forming a mask layer on the surface of the stress layer after the stress relief treatment and the annealing treatment; using the mask layer as a mask, patterning the stress layer to expose the top surface of the gate layer and the top surface of the source and drain region.

[0013] Optionally, before forming the gate layer, the method further includes forming a gate dielectric layer on the surface of the substrate.

[0014] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0015] In the method for forming a semiconductor structure of the present invention, after forming stress layers on the surface of the substrate and the sidewalls and top surfaces of the gate layer, the stress layers in the PMOS region are subjected to stress relief treatment, and the stress layers in the NMOS region are subjected to annealing treatment. On the one hand, the stress layers in the PMOS region are subjected to stress relief treatment to eliminate the influence of the stress layers on the PMOS region; on the other hand, the stress layers in the NMOS region are subjected to annealing treatment to transfer tensile stress to the source / drain region and the gate layer, thereby significantly increasing the electron mobility in the NMOS region and thus improving the driving current of the device in the NMOS region. At the same time, since the stress layers are subjected to stress relief treatment and annealing treatment, the stress layers will no longer generate tensile stress on the channel, but only play a blocking role. At this time, the stress layers are subjected to patterning treatment to expose the surface of the gate layer and the surface of the source / drain region where metal silicide is required to be formed, and metal silicide is formed on the exposed surface of the gate layer and the surface of the source / drain region, and no additional silicide barrier layer is required to be formed before the metal silicide is formed. This can save costs and shorten the manufacturing time, and at the same time, the performance of the formed semiconductor structure is not affected, and the method has a wide range of uses. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1 to 5 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0017] As mentioned in the background art, the performance of existing semiconductor structures is relatively poor, which will be described in detail below.

[0018] Currently, after forming the source and drain (S / D), a liner with tensile stress (usually an oxide buffer layer + a SIN stress layer) is deposited on the device polysilicon gate and source and drain regions. At the same time, in order to prevent the PMOS from being affected, the stress film layer in the PMOS region needs to be removed; annealing is then performed, and then the entire stress film layer is removed. Through the annealing process, the stress is memorized by the NMOS, and the device structure does not change.

[0019] At the same time, in order to reduce the contact resistance of the device, the salicide process needs to be applied, but high-resistance devices need to be used in the chip, so a metal silicide barrier layer needs to be added to selectively grow metal silicide.

[0020] The inventors found that this process not only requires additional steps but also has high costs and is not suitable for green production.

[0021] The inventor has found through research that after forming stress layers on the surface of the substrate and the sidewalls and top surfaces of the gate layer, the stress layers in the PMOS region are subjected to stress relief treatment, and the stress layers in the NMOS region are subjected to annealing treatment. On the one hand, the stress layers in the PMOS region are subjected to stress relief treatment to eliminate the influence of the stress layers on the PMOS region; on the other hand, the stress layers in the NMOS region are subjected to annealing treatment to transfer tensile stress to the source / drain region and the gate layer, thereby significantly increasing the electron mobility in the NMOS region and thus improving the driving current of the device in the NMOS region; at the same time, since the stress layers are subjected to stress relief treatment and annealing treatment, the stress layers will no longer generate tensile stress on the channel, but only play a blocking role. At this time, the stress layers are subjected to patterning treatment to expose the surface of the gate layer and the surface of the source / drain region where metal silicide needs to be formed, and metal silicide is formed on the exposed surface of the gate layer and the surface of the source / drain region, without the need to form an additional silicide barrier layer before forming the metal silicide, which can save costs and shorten the manufacturing time, and at the same time does not affect the performance of the formed semiconductor structure, and has a wide range of uses.

[0022] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0023] Figures 1 to 5 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0024] First, please refer to Figure 1, providing a substrate 100, the substrate 100 includes an NMOS region and a PMOS region, the surfaces of the substrate 100 of the NMOS region and the PMOS region respectively have a gate layer 101 and source and drain regions 102 formed in the substrate 100 on both sides of the gate layer 101.

[0025] In this embodiment, the substrate 100 is made of silicon.

[0026] In other embodiments, the material of the substrate 100 may be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; the substrate 100 may also be a silicon-on-insulator substrate 100 or a germanium-on-insulator substrate 100.

[0027] In this embodiment, a portion of the substrate 100 is etched to form a groove in the substrate 100 , an isolation layer is formed in the groove, and the isolation layer is planarized to form an isolation structure 103 .

[0028] In this embodiment, an N well (NW) is formed in the substrate 100 to constitute the PMOS region, so as to form a PMOS device.

[0029] In this embodiment, a P well (PW) is formed in the substrate 100 to constitute the NMOS region, so as to form an NMOS device.

[0030] In this embodiment, the material of the gate layer 101 is polysilicon.

[0031] In this embodiment, before forming the gate layer 101 , a gate dielectric layer (not marked in the figure) is further formed on the surface of the substrate 100 .

[0032] In this embodiment, the material of the gate dielectric layer is silicon oxide.

[0033] In this embodiment, before forming the source and drain regions 102 , the process further includes: forming a sidewall spacer (not marked in the figure) on the sidewall of the gate layer 101 .

[0034] Please refer to Figure 2 A stress layer 104 is formed on the surface of the substrate 100 and on the sidewalls and top surface of the gate layer 101 .

[0035] In this embodiment, the material of the stress layer 104 includes silicon nitride (Si 3 N 4 ).

[0036] In this embodiment, the stress layer 104 is formed by a plasma enhanced chemical vapor deposition (PECVD) process.

[0037] In other embodiments, the stress layer 104 may be formed by a physical vapor deposition process or an atomic layer deposition process.

[0038] In this embodiment, the purpose of forming the stress layer 104 is to transfer stress to the source, drain and gate through high temperature annealing, and then transfer stress to the channel through them, and at the same time, the stress will be memorized by the source, drain and gate.

[0039] In this embodiment, the gas used to prepare the silicon nitride (Si3N4) film includes SiH4, NH3, N2 and H atoms. The H atoms exist in the form of Si-H and NH. The stress of the silicon nitride (Si3N4) film can be adjusted by changing the content of the H atoms.

[0040] In this embodiment, the thickness of the stress layer 104 is generally in the range of 400 to 600 angstroms. A stress layer of this thickness can meet the performance requirements of the device and can also serve as a SAB layer.

[0041] Please refer to Figure 3 , respectively perform stress relief treatment on the stress layer 104 in the PMOS region.

[0042] The arrowed lines in the figure represent stress relief treatment.

[0043] In this embodiment, the method of performing stress relief treatment on the stress layer 104 in the PMOS region includes irradiating the stress layer 104 in the PMOS region with ultraviolet rays.

[0044] In some embodiments, the method of performing stress relief treatment on the stress layer 104 in the PMOS region includes bombarding the stress layer 104 in the PMOS region by an ion bombardment process.

[0045] Whether ultraviolet rays are used to irradiate the stress layer 104 in the PMOS region or ion bombardment is used to bombard the stress layer 104 in the PMOS region, the purpose is to prevent the stress layer 104 from affecting the speed of the devices in the PMOS region and ensure the performance of the devices in the PMOS region.

[0046] In this embodiment, during the stress relief treatment, a sacrificial layer is used to cover the stress layer on the NMOS region to protect the stress layer on the NMOS region and avoid damage to the stress layer in the NMOS region. After the stress relief treatment is completed, the sacrificial layer is also removed, so it is not shown in the figure.

[0047] Please refer to Figure 4 , the stress layer 104 in the NMOS region is annealed.

[0048] In this embodiment, the process parameters of the annealing treatment include an annealing time of less than 10 seconds and a temperature range of 900° C. to 1100° C.

[0049] In this embodiment, the purpose of annealing is to transfer stress to the source, drain and gate, and then transfer the stress to the channel through the source, drain and gate, thereby significantly accelerating the electron mobility of the device in the NOMS region and improving the driving current of the device in the NMOS region.

[0050] In this embodiment, after the stress layer 104 has been subjected to stress relief treatment and annealing treatment, the stress layer 104 will no longer generate tensile stress on the channel, but only plays a blocking role.

[0051] The arrowed line in the figure indicates the annealing treatment.

[0052] Please refer to Figure 5 , patterning the stress layer 104 after the stress relief treatment and the annealing treatment until the top surface of the gate layer 101 and the top surface of the source and drain region 102 are exposed, and forming a metal silicide 105 on the exposed top surface of the gate layer 101 and the top surface of the source and drain region 102.

[0053] In the present embodiment, since the stress layer 104 no longer has stress after the stress relief treatment and the annealing treatment, it only serves as a barrier layer. At this time, the stress layer is patterned to expose the surface of the gate layer 101 and the surface of the source and drain region 102 on which the metal silicide 105 needs to be formed, and the metal silicide 105 is formed on the exposed surface of the gate layer 101 and the surface of the source and drain region 102. There is no need to form an additional silicide barrier layer before forming the metal silicide 105, which can save costs and shorten manufacturing time. At the same time, it does not affect the performance of the formed semiconductor structure and has a wider range of uses.

[0054] In this embodiment, the method of patterning the stress layer 104 after the stress relief treatment and the annealing treatment to expose the top surface of the gate layer 101 and the top surface of the source and drain region 102 includes: forming a mask layer on the surface of the stress layer 104 after the stress relief treatment and the annealing treatment; using the mask layer as a mask, patterning the stress layer 104 after the stress relief treatment and the annealing treatment to expose the top surface of the gate layer 101 and the top surface of the source and drain region 102.

[0055] In this embodiment, the material of the mask layer is photoresist.

[0056] In this embodiment, the method for forming the metal silicide 105 includes: depositing a metal layer on the top surface of the gate layer 101 and the top surface of the source and drain regions 102 that are exposed; depositing titanium compound on the metal layer; reacting the metal layer with the substrate 100 (source and drain regions 102) through N2 under the process conditions of a first rapid thermal annealing to generate a high-resistance metal silicide 105; selectively etching the metal layer and the titanium compound to eliminate the titanium compound and the unreacted metal layer; and then performing a second rapid thermal annealing treatment to convert the high-resistance metal silicide 105 into a low-resistance metal silicide 105.

[0057] In this embodiment, the material of the metal layer includes cobalt.

[0058] In this embodiment, the material of the titanium compound includes titanium nitride (TiN).

[0059] In this embodiment, after forming the metal silicide 105 , a contact hole is further formed.

[0060] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an NMOS region and a PMOS region, wherein the surfaces of the substrates of the NMOS region and the PMOS region respectively have a gate layer and source and drain regions formed in the substrate on both sides of the gate layer; forming a stress layer on the surface of the substrate and the sidewall and top surface of the gate layer; Performing stress relief treatment on the stress layer in the PMOS region; Performing annealing on the stress layer of the NMOS region; Patterning the stress layer after the stress relief treatment and the annealing treatment until the top surface of the gate layer and the top surface of the source and drain regions are exposed; Metal silicide is formed on the exposed top surface of the gate layer and the top surface of the source and drain regions.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the stress layer includes silicon nitride.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method for performing stress relief treatment on the stress layer in the PMOS region includes irradiating the stress layer in the PMOS region with ultraviolet rays.

4. The method for forming a semiconductor structure according to claim 1, wherein: The method of performing stress relief treatment on the stress layer in the PMOS region includes bombarding the stress layer in the PMOS region by an ion bombardment process.

5. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of the annealing treatment include an annealing time of less than 10 seconds and a temperature range of 900° C. to 1100° C.

6. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the stress layer is usually in the range of 400 to 600 angstroms.

7. The method for forming a semiconductor structure according to claim 1, wherein: The method for patterning the stress layer after the stress relief treatment and the annealing treatment to expose the top surface of the gate layer and the top surface of the source and drain region comprises: forming a mask layer on the surface of the stress layer after the stress relief treatment and the annealing treatment; using the mask layer as a mask, patterning the stress layer to expose the top surface of the gate layer and the top surface of the source and drain region.

8. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the gate layer, the method further includes forming a gate dielectric layer on the surface of the substrate.

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