Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

The invention provides a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes: a channel structure including a first pillar portion and a second pillar portion extending from the first pillar portion; a barrier insulating layer surrounding a sidewall of the first pillar portion; a data storage layer disposed between the first pillar portion and the barrier insulating layer; an upper selection line overlapping an end portion of the barrier insulating layer facing an extending direction of the second pillar portion and an end portion of the data storage layer, the upper selection line surrounding a sidewall of the second pillar portion; and a tunnel insulating layer disposed between the first pillar portion and the data storage layer, the tunnel insulating layer extending between the second pillar portion and the upper selection line.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202110591933.2 (application date: May 28, 2021, invention name: semiconductor memory device and method for manufacturing semiconductor memory device). Technical Field

[0002] The present disclosure may generally relate to semiconductor memory devices and methods of manufacturing semiconductor memory devices, and more particularly, to three-dimensional semiconductor memory devices and methods of manufacturing three-dimensional semiconductor memory devices. Background Art

[0003] A semiconductor memory device includes a plurality of memory cells capable of storing data. The memory cells of a three-dimensional semiconductor memory device may be arranged three-dimensionally. When manufacturing a three-dimensional semiconductor memory device, failures may occur due to various reasons. As a result, the operating characteristics of the semiconductor memory device may be degraded. Summary of the invention

[0004] According to one aspect of the present disclosure, a semiconductor memory device may include a channel structure, a blocking insulating layer, a data storage layer, an upper selection line, and a tunnel insulating layer. The channel structure may include a first column portion and a second column portion extending from the first column portion. The blocking insulating layer may surround the sidewall of the first column portion of the channel structure. The data storage layer may be disposed between the first column portion of the channel structure and the blocking insulating layer. The upper selection line may overlap with an end portion of the blocking insulating layer and an end portion of the data storage layer, the end portion of the blocking insulating layer and the end portion of the data storage layer facing the extension direction of the second column portion, and the upper selection line surrounds the sidewall of the second column portion of the channel structure. The tunnel insulating layer may be disposed between the first column portion of the channel structure and the data storage layer, and the tunnel insulating layer extends between the second column portion of the channel structure and the upper selection line.

[0005] According to another aspect of the present disclosure, a semiconductor memory device may include a first channel structure, a second channel structure, a tunnel insulating layer, a data storage layer, a blocking insulating layer, a first lower selection line, a second lower selection line, an isolation layer, a first upper selection line, a second upper selection line, an interlayer insulating layer, and a word line. The first channel structure and the second channel structure may extend parallel to each other. The tunnel insulating layer may surround the sidewalls of each of the first channel structure and the second channel structure. The data storage layer may surround the sidewalls of each of the first channel structure and the second channel structure, and the tunnel insulating layer is interposed between the data storage layer and the sidewalls of each of the first channel structure and the second channel structure. The blocking insulating layer may surround the sidewalls of each of the first channel structure and the second channel structure, and the data storage layer and the tunnel insulating layer are interposed between the blocking insulating layer and the sidewalls of each of the first channel structure and the second channel structure. The first lower selection line may surround the first channel structure, and the blocking insulating layer, the data storage layer, and the tunnel insulating layer are interposed between the first lower selection line and the first channel structure. The second lower selection line may surround the second channel structure, and the blocking insulating layer, the data storage layer and the tunnel insulating layer are interposed between the second lower selection line and the second channel structure. The isolation layer may be disposed between the first lower selection line and the second lower selection line. The first upper selection line may surround the first channel structure, and the tunnel insulating layer is interposed between the first upper selection line and the first channel structure, and the first upper selection line is disposed on the first lower selection line. The second upper selection line may surround the second channel structure, and the tunnel insulating layer is interposed between the second upper selection line and the second channel structure, and the second upper selection line is disposed on the second lower selection line. The interlayer insulating layer and the word line may be alternately stacked between the first lower selection line and the first upper selection line, wherein the interlayer insulating layer and the word line extend between the second lower selection line and the second upper selection line.

[0006] According to another aspect of the present disclosure, a method for manufacturing a semiconductor memory device may include: forming a first conductive layer on a substrate; alternately stacking first material layers and second material layers on the first conductive layer; forming a hole penetrating the first material layer and the second material layer, the hole extending to the interior of the substrate; sequentially stacking a blocking insulating layer, a data storage layer and a tunnel insulating layer on the surface of the hole; forming a channel structure filling a central area of ​​the hole on the tunnel insulating layer; removing the substrate so that the first conductive layer and the blocking insulating layer are exposed; sequentially removing a portion of the blocking insulating layer and a portion of the data storage layer so that a recessed area is defined between the first conductive layer and the tunnel insulating layer; and forming a second conductive layer filling the recessed area, the second conductive layer surrounding the tunnel insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Example embodiments will now be described hereinafter with reference to the accompanying drawings. However, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

[0008] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the text, like reference numerals refer to like elements.

[0009] Figure 1 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2 is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 3A is an example Figure 2 FIG. 1 is a plan view of a layout of bit lines of a semiconductor memory device shown.

[0012] Figure 3B It is along Figure 3A A cross-sectional view of the semiconductor memory device taken along line II' is shown.

[0013] Figure 4 yes Figure 3B An enlarged cross-sectional view of region A is shown in FIG.

[0014] Figure 5A yes Figure 4 , a cross-sectional view of a first portion of a channel structure, a tunnel insulating layer, and a second conductive pattern shown in Figure 5B yes Figure 4 0014 is a cross-sectional view of a first pillar portion, a tunnel insulating layer, a data storage layer, and a first blocking insulating layer of a channel structure shown in FIG.

[0015] Figure 6 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figure 7 is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Fig. 8A is an example Figure 7 FIG. 1 is a plan view of a layout of bit lines of a semiconductor memory device shown.

[0018] Figure 8B It is along Fig. 8A A cross-sectional view of the semiconductor memory device taken along line II-II' is shown.

[0019] Fig. 9 yes Figure 8B An enlarged cross-sectional view of region B is shown in FIG.

[0020] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 10E , Fig.11 , Fig.12 , Fig.13 , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B and Fig. 17C is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0021] Fig.18A , Fig.18B , Fig.18C , Fig.18D , Fig.18E , Fig.18F , Figure 18G , Fig.18H , Fig.18I , Fig.18J , Figure 18K , Figure 18L , Figure 18M and Fig.18N is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0022] Fig.19 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0023] Fig. 20 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The specific structural or functional descriptions disclosed herein are merely exemplified for the purpose of describing the embodiments of the concepts according to the present disclosure. The embodiments of the concepts according to the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0025] Embodiments provide a semiconductor memory device and a method of manufacturing the semiconductor memory device that can improve operating characteristics of the semiconductor memory device.

[0026] Figure 1 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0027] Reference Figure 1, the semiconductor memory device may include a plurality of memory blocks BLK, wherein each memory block BLK may include a plurality of memory cell strings MS1 , MS2 , and MS3 connected to a common source layer CSL and a bit line BL.

[0028] Each of the memory cell strings MS1, MS2, and MS3 may include a plurality of memory cells MC connected in series, a source selection transistor SST, and at least one drain selection transistor DST. In an embodiment, each of the memory cell strings MS1, MS2, and MS3 may include one drain selection transistor DST connected between the plurality of memory cells MC and the bit line BL. In another embodiment, each of the memory cell strings MS1, MS2, and MS3 may include two or more drain selection transistors DST connected between the plurality of memory cells MC and the bit line BL.

[0029] The plurality of memory cells MC may be connected to the common source layer CSL via a source select transistor SST, and may be connected to a bit line BL via a drain select transistor DST.

[0030] Gates of source select transistors SST disposed at the same height may be connected to source select lines SSL1, SSL2, and SSL3 isolated from each other. Gates of drain select transistors DST disposed at the same height may be connected to drain select lines DSL1, DSL2, and DSL3 isolated from each other.

[0031] In an embodiment, the memory block BLK may include a first source selection line SSL1, a second source selection line SSL2, and a third source selection line SSL3 isolated from each other at the same height. The memory block may also include a first drain selection line DSL1, a second drain selection line DSL2, and a third drain selection line DSL3 isolated from each other at the same height. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, the memory block BLK may include two source selection lines isolated from each other at the same height, or may include four or more source selection lines isolated from each other at the same height. In addition, the memory block BLK may include two drain selection lines isolated from each other at the same height, or may include four or more drain selection lines isolated from each other at the same height, wherein the number of drain selection lines isolated from each other at the same height may be equal to or different from the number of source selection lines isolated from each other at the same height.

[0032] Gates of a plurality of memory cells MC may be connected to a plurality of word lines WL, wherein the word lines WL may be disposed at different heights, and gates of memory cells MC disposed at the same height may be connected to a single word line WL.

[0033] A plurality of memory cell strings MS1, MS2, and MS3 may be connected to each word line WL. In an embodiment, the plurality of memory cell strings MS1, MS2, and MS3 may be divided into first, second, and third groups that may be individually selected by first, second, and third source select lines SSL1, SSL2, and SSL3.

[0034] The first group may include a first memory cell string MS1. The second group may include a second memory cell string MS2.

[0035] The third group may include a third memory cell string MS3.

[0036] The first memory cell string MS1 may be connected to the bit line BL via a drain selection transistor DST connected to the first drain selection line DSL1, respectively. The second memory cell string MS2 may be connected to the bit line BL via a drain selection transistor DST connected to the second drain selection line DSL2, respectively. The third memory cell string MS3 may be connected to the bit line BL via a drain selection transistor DST connected to the third drain selection line DSL3, respectively. One of the first memory cell string MS1, one of the second memory cell string MS2, and one of the third memory cell string MS3 may be connected to a single bit line BL.

[0037] According to the gate signal applied to the first source selection line SSL1, the first memory cell string MS1 can be connected to the common source layer CSL. According to the gate signal applied to the second source selection line SSL2, the second memory cell string MS2 can be connected to the common source layer CSL. The third memory cell string MS3 can be connected to the common source layer CSL according to the gate signal applied to the third source selection line SSL3. Therefore, a plurality of memory cell strings MS1, MS2, and MS3 can be isolated as a group that can be individually selected simultaneously for each of the source selection lines SSL1, SSL2, and SSL3 in a read operation or a verification operation. In an embodiment, in a read operation or a verification operation, one of the first source selection line SSL1, the second source selection line SSL2, and the third source selection line SSL3 can be selected so that one group among the first memory cell string MS1 of the first group, the second memory cell string MS2 of the second group, and the third memory cell string MS3 of the third group can be connected to the common source layer CSL. Therefore, in an embodiment of the present disclosure, compared with a case where the first memory cell string MS1, the second memory cell string MS2, and the third memory cell string MS3 are simultaneously connected to a common source layer in a read operation or a verification operation, the channel resistance can be reduced. Therefore, in an embodiment of the present disclosure, read disturbance can be reduced.

[0038] Figure 2is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0039] Reference Figure 2 , the semiconductor memory device may include a peripheral circuit structure PS, a bit line BL, gate stack structures GST1 and GST2, and a common source layer CSL. Each of the gate stack structures GST1 and GST2 may constitute a memory block.

[0040] In order to control the operation of the memory cell, the peripheral circuit structure PS may include a peripheral circuit.

[0041] Each of the gate stack structures GST1 and GST2 may overlap with the peripheral circuit structure PS and may be disposed between the bit line BL and the common source layer CSL. The peripheral circuit structure PS may overlap with the gate stack structures GST1 and GST2, with the bit line BL interposed therebetween. The common source layer CSL may overlap with the bit line BL, with the gate stack structures GST1 and GST2 interposed therebetween.

[0042] The gate stacked structures GST1 and GST2 may include a first gate stacked structure GST1 and a second gate stacked structure GST2 facing each other.

[0043] Each of the first gate stack structure GST1 and the second gate stack structure GST2 may include an upper selection group including an upper selection line, a lower selection group including a lower selection line, and a word line WL disposed between the upper selection group and the lower selection group. In an embodiment, the upper selection line may be configured as source selection lines SSL1, SSL2, and SSL3. The lower selection line may be configured as drain selection lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B.

[0044] Each of the source selection lines SSL1, SSL2, and SSL3, the word lines WL, and the drain selection lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B may extend in a first direction D1 and a second direction D2, wherein the first direction D1 may be defined as a direction of an X-axis in an XYZ coordinate system and the second direction D2 may be defined as a direction of a Y-axis in the XYZ coordinate system.

[0045] The source selection lines SSL1, SSL2, and SSL3 may be isolated from each other at the same height. In an embodiment, the source selection lines SSL1, SSL2, and SSL3 may be spaced apart from each other in the first direction D1. The source selection lines SSL1, SSL2, and SSL3 may be disposed between a common source layer CSL and a stack structure including word lines WL.

[0046] The word lines WL may be spaced apart from each other in a third direction D3 , which may be defined as a direction of a Z axis in an XYZ coordinate system.

[0047] Each word line WL may extend to overlap the source selection lines SSL1 , SSL2 , and SSL3 that are isolated from each other.

[0048] The drain selection lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B may be disposed in at least one layer between the bit lines BL and the stacked structure including the word lines WL. In an embodiment, the drain selection lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B may include drain selection lines DSL1A, DSL2A, and DSL3A of a first height and drain selection lines DSL1B, DSL2B, and DSL3B of a second height. The drain selection lines DSL1B, DSL2B, and DSL3B of the second height may be spaced apart from the drain selection lines DSL1A, DSL2A, and DSL3A of the first height in the third direction D3. The drain selection lines DSL1A, DSL2A, and DSL3A of the first height may be spaced apart from each other in the extension direction of the bit lines BL, and the drain selection lines DSL1B, DSL2B, and DSL3B of the second height may also be spaced apart from each other in the extension direction of the bit lines BL. In an implementation, the drain selection lines DSL1A, DSL2A, and DSL3A of the first height and the drain selection lines DSL1B, DSL2B, and DSL3B of the second height may be spaced apart from each other in the first direction D1.

[0049] The peripheral circuit structure PS may overlap with the upper selection group including the source selection lines SSL1, SSL2, and SSL3. In addition to the lower selection group including the drain selection lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B, the bit line BL may be disposed between the peripheral circuit structure PS and the upper selection group including the source selection lines SSL1, SSL2, and SSL3.

[0050] Each of the bit line BL and the common source line may extend to overlap the first and second gate stacked structures GST1 and GST2 .

[0051] Figure 3A is an example Figure 2 FIG. 1 is a plan view of a layout of bit lines of a semiconductor memory device shown.

[0052] Reference Figure 3A , the bit lines BL may extend in parallel with each other and may be spaced apart from each other. In an embodiment, the bit lines BL may extend in the first direction D1 and may be spaced apart from each other in the second direction D2.

[0053] The bit line BL may be connected to the channel structure CH extending in the third direction D3 , and may be connected to the channel structure CH via a bit line contact structure CT.

[0054] The channel structure CH may run through the first gate stack structure GST1 and the second gate stack structure GST2, and may be divided into groups controlled by source selection lines SSL1, SSL2, and SSL3 spaced apart from each other. In an embodiment, the channel structure CH may include a first group configured with the first channel structure CH1, a second group configured with the second channel structure CH2, and a third group configured with the third channel structure CH3. The sidewall of the first channel structure CH1 may be surrounded by the first source selection line SSL1 of the first gate stack structure GST1. The first channel structure CH1 may be controlled by the first source selection line SSL1. The sidewall of the second channel structure CH2 may be surrounded by the second source selection line SSL2 of the first gate stack structure GST1, and the second channel structure CH2 may be controlled by the second source selection line SSL2. The sidewall of the third channel structure CH3 may be surrounded by the third source selection line SSL3 of the second gate stack structure GST2. The third channel structure CH3 may be controlled by the third source selection line SSL3.

[0055] One of the first channel structures CH1 , one of the second channel structures CH2 , and one of the third channel structures CH3 may be connected in parallel to a single bit line BL.

[0056] The word line WL of the first gate stacked structure GST1 may extend to surround sidewalls of the first channel structure CH1 and the second channel structure CH2 .

[0057] The embodiments shown in the drawings illustrate a case where the isolation structure between the drain selection lines DSL1A, DSL2A, and DSL3A at the first height and the isolation structure between the drain selection lines DSL1B, DSL2B, and DSL3B at the second height are similar to the isolation structure between the second source selection line SSL2 and the third source selection line SSL3. More specifically, the drain selection lines DSL1A, DSL2A, and DSL3A at the first height may include the first drain selection line to the third drain selection line at the first height. The drain selection lines DSL1B, DSL2B, and DSL3B at the second height may include the first drain selection line to the third drain selection line at the second height.

[0058] The first channel structure CH1 may penetrate the first drain selection line DSL1A at the first height and the first drain selection line DSL1B at the second height. The second channel structure CH2 may penetrate the second drain selection line DSL2A at the first height and the second drain selection line DSL2B at the second height. The third channel structure CH3 may penetrate the third drain selection line DSL3A at the first height and the third drain selection line DSL3B at the second height.

[0059] Reference Figure 3A In the embodiment, line II′ overlaps with the single bit line BL. The channel structure CH overlapping with the single bit line BL may include: a channel structure connected to the single bit line BL via a bit line contact structure CT overlapping with line II′; and a channel structure connected to another bit line BL via a bit line contact structure CT not overlapping with line II′.

[0060] Figure 3B It is along Figure 3A A cross-sectional view of the semiconductor memory device taken along line II' is shown.

[0061] Reference Figure 3B , the source selection lines SSL1, SSL2, and SSL3 may be isolated from each other by the trenches T, and the trenches T may be filled with the upper insulating layer 197. The upper insulating layer 197 may extend between the common source layer CSL and the upper selection group including the source selection lines SSL1, SSL2, and SSL3.

[0062] The common source layer CSL may include a doped semiconductor layer 199A, a conductive metal barrier layer 199B, and a metal layer 199C sequentially stacked on the upper insulating layer 197. The doped semiconductor layer 199A may include at least one of n-type impurities and p-type impurities.

[0063] The word lines WL of the first gate stack structure GST1 may be spaced apart from the word lines WL of the second gate stack structure GST2 by the gate isolation layer 151. The word lines WL of the first gate stack structure GST1 may also be insulated from the word lines WL of the second gate stack structure GST2 by the gate isolation layer 151. The gate isolation layer 151 may extend between a first lower selection group including the drain selection lines DSL1A, DSL2A, DSL1B, and DSL2B of the first gate stack structure GST1 and a second lower selection group including the drain selection lines DSL3A and DSL3B.

[0064] Each of the first gate stack structure GST1 and the second gate stack structure GST2 may further include interlayer insulating layers 111 stacked to be spaced apart from each other in the third direction D3. Conductive layers and the interlayer insulating layers 111 provided for the word lines WL and the drain selection lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B may be alternately disposed in the third direction D3.

[0065] The first drain selection line DSL1A at the first height included in the first gate stack structure GST1 may be spaced apart from the second drain selection line DSL2A at the first height included in the first gate stack structure GST1 by the drain isolation layer 153. The first drain selection line DSL1A at the first height included in the first gate stack structure GST1 may be insulated from the second drain selection line DSL2A at the first height included in the first gate stack structure GST1 by the drain isolation layer 153. The drain isolation layer 153 may extend between the first drain selection line DSL1B at the second height and the second drain selection line DSL2B at the second height. The first drain selection line DSL1B at the second height is included in the first gate stack structure GST1. The second drain selection line DSL2B at the second height is included in the first gate stack structure GST1.

[0066] Each of the channel structures CH may include a channel layer 131 and a core insulating layer 133, wherein the channel layer 131 may include a semiconductor material. The channel layer 131 may surround the sidewalls of the core insulating layer 133 and may extend along a first surface of the core insulating layer 133. The core insulating layer 133 faces the common source layer CSL and may also overlap with the doped semiconductor pattern 135. The doped semiconductor pattern 135 may contact a second surface of the core insulating layer 133 facing the bit line BL. The channel layer 131 may extend to surround the sidewalls of the doped semiconductor pattern 135.

[0067] Each channel structure CH may include a first pillar portion PA and a second pillar portion PB extending from the first pillar portion PA in a third direction D3, wherein a central region of the first pillar portion PA may be filled with a core insulating layer 133 and a doped semiconductor pattern 135, and the core insulating layer 133 may extend to a central region of the second pillar portion PB. Outer walls of the first pillar portion PA and the second pillar portion PB may be configured with a channel layer 131.

[0068] Referring to the first gate stacked structure GST1, the sidewall of the first pillar portion PA may be surrounded not only by the interlayer insulating layer 111 and the word line WL, but also by the drain selection line DSL1A or DSL2A corresponding to the first height of the first pillar portion PA and the drain selection line DSL1B or DSL2B corresponding to the second height of the first pillar portion PA. The sidewall of the second pillar portion PB may be surrounded by the source selection line SSL1 or SSL2 corresponding to the second pillar portion PB, wherein the second pillar portion PB of the channel structure CH may extend in the third direction D3 to penetrate the upper insulating layer 197, and may extend to the inside of the common source layer CSL.

[0069] The sidewall of the first pillar portion PA may be surrounded by the first blocking insulating layer 121, the data storage layer 123, and the tunnel insulating layer 125. The first blocking insulating layer 121, the data storage layer 123, and the tunnel insulating layer 125 may be disposed between the first pillar portion PA1 and each of the interlayer insulating layer 111 and the word line WL. The first blocking insulating layer 121, the data storage layer 123, and the tunnel insulating layer 125 may extend between the first pillar portion PA and the drain selection line DSL1A or DSL2A corresponding to the first height of the first pillar portion PA, and may extend between the first pillar portion PA and the drain selection line DSL1B or DSL2B corresponding to the second height of the first pillar portion PA.

[0070] The data storage layer 123 may be disposed between the first blocking insulating layer 121 and the first pillar portion PA. The tunnel insulating layer 125 may be disposed between the data storage layer 123 and the first pillar portion PA, and may extend between the second pillar portion PB and the source selection line SSL1 or SSL2 corresponding to the second pillar portion PB.

[0071] The second pillar portion PB of each channel structure CH may protrude further in the third direction D3 than the tunnel insulating layer 125. Each channel structure CH may have a tapered shape. As the channel structure CH becomes closer to the bit line BL and the peripheral circuit structure PS, the width of the channel structure CH becomes wider.

[0072] The bit line BL may be spaced apart from the channel structure CH by the insulating layer 161 , and the insulating layer 161 may extend between the bit line BL and each of the first and second gate stack structures GST1 and GST2 . The bit line contact structure CT may electrically connect some of the channel structure CH to the bit line BL while penetrating the insulating layer 161 .

[0073] The bit line BL may be spaced apart from the peripheral circuit structure PS by a first insulating structure 163 , which may include two or more insulating layers stacked between the bit line BL and the peripheral circuit structure PS.

[0074] The first interconnect structure 165 and the first conductive bonding pad 167 may be buried in the first insulating structure 163, wherein the first interconnect structure 165 may include a plurality of conductive patterns. The first conductive bonding pad 167 may be connected to the first interconnect structure 165 and may face the peripheral circuit structure PS. In an embodiment, the first conductive bonding pad 167 may be electrically connected to the bit line BL via the first interconnect structure 165.

[0075] The peripheral circuit structure PS may include a substrate 171 including transistors 180A and 180B, a second insulating structure 191 , a second interconnect structure 193 , and a second conductive bonding pad 195 .

[0076] The transistors 180A and 180B may be disposed in an active region of the substrate 171 separated by the isolation layer 173. Each of the transistors 180A and 180B may include a gate insulating layer 181 disposed on the active region, a gate electrode 183 disposed on the gate insulating layer 181, and junctions 185 formed in the active region on both sides of the gate electrode 183. Some of the transistors 180A and 180B (e.g., 180B) may constitute a page buffer circuit for controlling a precharge operation and a discharge operation of a bit line BL.

[0077] The second insulating structure 191 may be disposed between the first insulating structure 163 and the substrate 171 , may include two or more insulating layers, and may be bonded to the first insulating structure 163 .

[0078] The second interconnect structure 193 and the second conductive bonding pad 195 may be buried in the second insulating structure 191, wherein the second interconnect structure 193 may include a plurality of conductive patterns. The second conductive bonding pad 195 may be connected to the second interconnect structure 193 and may face the first conductive bonding pad 167. The second conductive bonding pad 195 may be bonded to the first conductive bonding pad 167 and may be electrically connected to the transistor 180B of the page buffer circuit via the second interconnect structure 193.

[0079] According to the above-described embodiments, the bit line BL may be connected to the transistor 180B of the page buffer circuit via the first interconnect structure 165 , the first conductive bonding pad 167 , the second conductive bonding pad 195 , and the second interconnect structure 193 .

[0080] Figure 4 yes Figure 3B An enlarged cross-sectional view of region A is shown in FIG.

[0081] Reference Figure 4, the first blocking insulating layer 121 may include an end portion EG1 facing the third direction D3, and the data storage layer 123 may further include an end portion EG2 facing the third direction D3. According to the etching amount of the first blocking insulating layer 121 and the etching amount of the data storage layer 123, the positions of the end portion EG1 of the first blocking insulating layer 121 and the end portion EG2 of the data storage layer 123 may vary. The end portion EG1 of the first blocking insulating layer 121 may be disposed at the same height as the end portion EG2 of the data storage layer 123, or may be disposed at a different height from the end portion EG2 of the data storage layer 123.

[0082] The source selection line (e.g., SSL1) may overlap the end EG1 of the first blocking insulating layer 121 and the end EG2 of the data storage layer 123. Depending on the etching amount of the first blocking insulating layer 121 and the etching amount of the data storage layer 123, the interface between the source selection line SSL1 and the end EG1 of the first blocking insulating layer 121 and the interface between the source selection line SSL1 and the end EG2 of the data storage layer 123 may be set at a height substantially equal to or different from the height of the interface between the source selection line SSL1 and the interlayer insulating layer 111.

[0083] The source selection line SSL1 may include a first conductive pattern 101 and a second conductive pattern 103, wherein the first conductive pattern 101 may extend in a planar direction to cross the second pillar portion PB. In an embodiment, the first conductive pattern 101 may extend in a first direction D1 and a second direction D2 to be parallel to the word line WL. The second conductive pattern 103 may be disposed between the first conductive pattern 101 and the tunnel insulating layer 125.

[0084] The second conductive pattern 103 may include at least one of silicon, metal silicide, and a conductive metal barrier, wherein the metal silicide may include tungsten silicide or nickel silicide, and the conductive metal barrier may include titanium and titanium nitride.

[0085] The second pillar portion PB of the channel structure CH may include a first portion P1 surrounded by the source selection line SSL1, a second portion P2 extending from the first portion P1 in the third direction D3, and a third portion P3 extending from the second portion P2 in the third direction D3. The second portion P2 and the third portion P3 may protrude further than the source selection line SSL1 in the third direction D3. A sidewall of the second portion P2 may be surrounded by an upper insulating layer 197. The third portion P3 may be in contact with the doped semiconductor layer 199A of the common source layer.

[0086] The core insulating layer 133 of the channel structure CH may extend from the central area of ​​the first pillar portion PA to the central area of ​​each of the first portion P1, the second portion P2, and the third portion P3. The channel layer 131 of the channel structure CH may extend to constitute the outer wall of each of the first portion P1, the second portion P2, and the third portion P3. The doped semiconductor layer 199A of the common source layer may contact the channel layer 131 of the third portion P3.

[0087] The word line WL may include a conductive metal barrier layer 143 and a metal layer 145. The second blocking insulating layer 141 may be disposed between the word line WL and the first blocking insulating layer 121, and may extend between the interlayer insulating layer 111 and the word line WL. Like the word line WL, Figure 3B Each of the drain selection lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B shown in FIG. 1 may include a conductive metal barrier layer 143 and a metal layer 145. The second blocking insulating layer 141 may be disposed between the first blocking insulating layer 121 and the Figure 3B Between each of the drain selection lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B, and DSL3B shown in FIG. 1 , and between the interlayer insulating layer 111 and Figure 3B The drain select lines DSL1A, DSL2A, DSL3A, DSL1B, DSL2B and DSL3B shown in FIG.

[0088] The second blocking insulating layer 141 may include an insulating material having a higher dielectric constant than that of the first blocking insulating layer 121 , and although not shown in the drawings, the second blocking insulating layer 141 may be omitted.

[0089] Figure 5A yes Figure 4 0 is a cross-sectional view of a first portion of a channel structure, a tunnel insulating layer, and a second conductive pattern shown in FIG. Figure 5B yes Figure 4 0014 is a cross-sectional view of a first pillar portion, a tunnel insulating layer, a data storage layer, and a first blocking insulating layer of a channel structure shown in FIG.

[0090] Reference Figure 5A and Figure 5B , a sidewall of the core insulation layer 133 of the channel structure CH may be surrounded by the channel layer 131 of the channel structure CH, wherein a sidewall of the channel layer 131 may be surrounded by the tunnel insulation layer 125 .

[0091] Reference Figure 5AThe tunnel insulating layer 125 may extend to surround a portion of the sidewall of the second pillar portion PB. The sidewall of the first portion P1 of the second pillar portion PB may be surrounded by the tunnel insulating layer 125, wherein the tunnel insulating layer 125 may be in contact with the first portion P1 of the second pillar portion PB. The first portion P1 of the second pillar portion PB may be formed by a source selection line (e.g., Figure 4 The second conductive pattern 103 of the SSL1 shown in FIG. 1 is surrounded with a tunnel insulating layer 125 interposed therebetween, so that a source selection transistor having a gate all around (GAA) can be defined at a crossing portion of the first portion P1 and the source selection line.

[0092] Reference Figure 5B The tunnel insulating layer 125 may extend to surround the sidewall of the first pillar portion PA. The sidewall of the first pillar portion PA may be surrounded not only by the tunnel insulating layer 125 but also by the data storage layer 123 surrounding the sidewall of the tunnel insulating layer 125 and the first blocking insulating layer 121 surrounding the sidewall of the data storage layer 123.

[0093] In an embodiment, the data storage layer 123 may be formed as a material layer capable of storing data changed using Fowler-Nordheim tunneling. The material layer may include a nitride layer capable of capturing charges. The first blocking insulating layer 121 may include an oxide layer capable of blocking charges. The tunnel insulating layer 125 may be formed as a silicon oxide layer through which charges can pass by tunneling.

[0094] Figure 6 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0095] Reference Figure 6 , the semiconductor memory device may include a plurality of memory blocks BLK′, wherein each memory block BLK′ may include a plurality of memory cell strings MS1′, MS2′, and MS3′ connected to a common source layer CSL′ and a bit line BL′.

[0096] Each of the memory cell strings MS1′, MS2′, and MS3′ may include a plurality of memory cells MC′ connected in series, a drain select transistor DST′, and at least one source select transistor SST′. In an embodiment, each of the memory cell strings MS1′, MS2′, and MS3′ may include one source select transistor SST′ connected between the plurality of memory cells MC′ and a common source layer CSL′. In another embodiment, each of the memory cell strings MS1′, MS2′, and MS3′ may include two or more source select transistors SST′ connected in series between the plurality of memory cells MC′ and a common source layer CSL′.

[0097] The plurality of memory cells MC' may be connected to the common source layer CSL' via the source select transistor SST'. The plurality of memory cells MC' may be connected to the bit line BL' via the drain select transistor DST'.

[0098] Gates of the drain selection transistors DST′ disposed at the same height may be connected to drain selection lines DSL1 ′, DSL2 ′, and DSL3 ′ that are isolated from each other.

[0099] In an embodiment, the memory block BLK′ may include a first drain selection line DSL1′, a second drain selection line DSL2′, and a third drain selection line DSL3′ isolated from each other at the same height. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, the memory block BLK′ may include two drain selection lines isolated from each other at the same height, or may include four or more drain selection lines isolated from each other at the same height.

[0100] Gates of the source select transistors SST′ disposed at the same height may be connected to a single source select line SSL′.

[0101] Gates of a plurality of memory cells MC′ may be connected to a plurality of word lines WL′, wherein the word lines WL′ may be disposed at different heights, and gates of memory cells MC′ disposed at the same height may be connected to a single word line WL′.

[0102] A plurality of memory cell strings MS1′, MS2′, and MS3′ may be connected to each word line WL′. In an embodiment, a plurality of memory cell strings MS1′, MS2′, and MS3′ may be divided into a first group, a second group, and a third group, which may be individually selected by a first drain selection line DSL1′, a second drain selection line DSL2′, and a third drain selection line DSL3′. The first group may include a first memory cell string MS1′, a second group may include a second memory cell string MS2′, and a third group may include a third memory cell string MS3′.

[0103] The first memory cell string MS1′ may be connected to the bit line BL′ via the drain selection transistor DST′ connected to the first drain selection line DSL1′, respectively. The second memory cell string MS2′ may be connected to the bit line BL′ via the drain selection transistor DST′ connected to the second drain selection line DSL2′, respectively. The third memory cell string MS3′ may be connected to the bit line BL′ via the drain selection transistor DST′ connected to the third drain selection line DSL3′, respectively. One of the first memory cell string MS1′, one of the second memory cell string MS2′, and one of the third memory cell string MS3′ may be connected to a single bit line BL′.

[0104] The first, second, and third memory cell strings MS1 ′, MS2 ′, and MS3 ′ may be connected to the common source layer CSL′ according to a gate signal applied to a source selection line SSL′.

[0105] Figure 7 is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0106] Reference Figure 7 , the semiconductor memory device may include a peripheral circuit structure PS′, a common source layer CSL′, gate stack structures GST1′ and GST2′, and a bit line BL′, wherein each of the gate stack structures GST1′ and GST2′ may constitute a memory block.

[0107] The peripheral circuit structure PS′ may include a peripheral circuit for controlling the operation of the memory cell, and may overlap the gate stack structures GST1 ′ and GST2 ′ with the common source layer CSL′ interposed therebetween.

[0108] The common source layers CSL′ may be spaced apart from each other at the same height, and may overlap the bit lines BL′ with the gate stack structures GST1 ′ and GST2 ′ interposed therebetween.

[0109] The gate stacked structures GST1 ′ and GST2 ′ may include a first gate stacked structure GST1 ′ and a second gate stacked structure GST2 ′ facing each other.

[0110] Each of the first gate stack structure GST1′ and the second gate stack structure GST2′ may include an upper selection group including an upper selection line, a lower selection group including a lower selection line, and a word line WL′ disposed between the upper selection group and the lower selection group. In an embodiment, the upper selection line may be configured with drain selection lines DSL1′, DSL2′, and DSL3′, and the lower selection line may be configured with source selection lines SSL′[A] and SSL′[B].

[0111] Each of the drain selection lines DSL1′, DSL2′ and DSL3′, the word line WL′ and the source selection lines SSL′[A] and SSL′[B] can extend in a first direction D1 and a second direction D2, wherein the first direction D1 can be defined as the direction of the X-axis in an XYZ coordinate system, and the second direction D2 can be defined as the direction of the Y-axis in the XYZ coordinate system.

[0112] The drain selection lines DSL1′, DSL2′, and DSL3′ may be isolated from each other at the same height and may be spaced apart from each other in the extending direction of the bit line BL′. In an embodiment, the drain selection lines DSL1′, DSL2′, and DSL3′ may be spaced apart from each other in the first direction D1. The drain selection lines DSL1′, DSL2′, and DSL3′ may be disposed between the bit line BL′ and a stacked structure including the word line WL′.

[0113] The word lines WL' may be spaced apart from each other in a third direction D3, which may be defined as a direction of a Z axis in an XYZ coordinate system. Each of the word lines WL' may extend to overlap drain selection lines DSL1', DSL2', and DSL3' isolated from each other.

[0114] The source selection lines SSL′[A] and SSL′[B] may be disposed in at least one layer between the common source layer CSL′ and the stacked structure including the word line WL′. In an embodiment, the source selection lines SSL′[A] and SSL′[B] may include a source selection line SSL′[A] of a first height and a source selection line SSL′[B] of a second height. The source selection line SSL′[B] of the second height may be spaced apart from the source selection line SSL′[A] of the first height.

[0115] The peripheral circuit structure PS' may overlap with the upper selection group including the drain selection lines DSL1', DSL2', and DSL3'. In addition to the lower selection group including the source selection lines SSL'[A] and SSL'[B], a common source layer CSL' may be disposed between the peripheral circuit structure PS' and the upper selection group including the drain selection lines DSL1', DSL2', and DSL3'.

[0116] The bit line BL′ may extend to overlap the first and second gate stacked structures GST1′ and GST2′. The common source layer CSL′ may overlap the first and second gate stacked structures GST1′ and GST2′, respectively.

[0117] Fig. 8A is an example Figure 7 FIG. 1 is a plan view of a layout of bit lines of a semiconductor memory device shown.

[0118] Reference Fig. 8A , the bit lines BL′ may extend in parallel with each other and may be spaced apart from each other. In an embodiment, the bit lines BL′ may extend in the first direction D1 and may be spaced apart from each other in the second direction D2.

[0119] The bit line BL′ may be connected to the channel structure CH′ extending in the third direction D3 , and may be connected to the channel structure CH′ through a bit line contact structure CT′.

[0120] The channel structure CH′ may penetrate the first gate stack structure GST1′ and the second gate stack structure GST2′, and the channel structure CH′ may be divided into groups controlled by drain selection lines DSL1′, DSL2′, and DSL3′ spaced apart from each other. In an embodiment, the channel structure CH′ may include a first group configured with the first channel structure CH1′, a second group configured with the second channel structure CH2′, and a third group configured with the third channel structure CH3′. The sidewall of the first channel structure CH1′ may be surrounded by the first drain selection line DSL1′ of the first gate stack structure GST1′ and may be controlled by the first drain selection line DSL1′. The sidewall of the second channel structure CH2′ may be surrounded by the second drain selection line DSL2′ of the first gate stack structure GST1′ and may be controlled by the second drain selection line DSL2′. The sidewall of the third channel structure CH3′ may be surrounded by the third drain selection line DSL3′ of the second gate stack structure GST2′ and may be controlled by the third drain selection line DSL3′.

[0121] One of the first channel structures CH1 ′, one of the second channel structures CH2 ′, and one of the third channel structures CH3 ′ may be connected in parallel to a single bit line BL′.

[0122] Each of the word line WL′ of the first gate stack structure GST1 ′ and the source selection lines SSL′[A] and SSL′[B] of the first gate stack structure GST1 ′ may extend to surround sidewalls of the first channel structure CH1 ′ and the second channel structure CH2 ′.

[0123] Reference Fig. 8A , line II-II′ overlaps with the single bit line BL′. The channel structure CH overlapping with the single bit line BL′ may include a channel structure connected to the single bit line BL′ via a bit line contact structure CT′ overlapping with line II-II′, and a channel structure connected to another bit line BL′ via a bit line contact structure CT not overlapping with line II-II′.

[0124] Figure 8B It is along Fig. 8A A cross-sectional view of the semiconductor memory device taken along line II-II' is shown.

[0125] Reference Figure 8B, the word line WL′ of the first gate stack structure GST1′ may be separated from the word line WL′ of the second gate stack structure GST2′ by the first trench T1′, wherein the first trench T1′ may extend between a first lower selection group including source selection lines SSL′[A] and SSL′[B] of the first gate stack structure GST1′ and a second lower selection group including source selection lines SSL′[A] and SSL′[B] of the second gate stack structure GST2′.

[0126] Each of the first gate stack structure GST1′ and the second gate stack structure GST2′ may further include interlayer insulating layers 211 stacked to be spaced apart from each other in the third direction D3. Conductive layers provided for the word lines WL′ and the source selection lines SSL′[A] and SSL′[B] and the interlayer insulating layers 211 may be alternately disposed in the third direction D3.

[0127] The common source layer CSL′ may be disposed between the first gate stack structure GST1′ and the second gate stack structure GST2′ and the peripheral circuit structure PS′. The first trench T1′ may extend between the common source layer CSL′ and may be filled with a gate isolation layer 251 filling the first trench T1′. The gate isolation layer 251 and the common source layer CSL′ may face the peripheral circuit structure PS′, and the first insulating structure 261 is interposed therebetween.

[0128] An upper selection group including drain selection lines DSL1′, DSL2′, and DSL3′ may overlap with a common source layer CSL′, and a lower selection group including source selection lines SSL′[A] and SSL′[B] and a word line WL′ may be interposed therebetween. The drain selection lines DSL1′, DSL2′, and DSL3′ may be isolated from each other by a second trench T2′, wherein the second trench T2′ may be filled with a first upper insulating layer 295. The first upper insulating layer 295 may extend between the bit line BL′ and the upper selection group including the drain selection lines DSL1′, DSL2′, and DSL3′. The bit line BL′ may be spaced apart from the drain selection lines DSL1′, DSL2′, and DSL3′, and a second upper insulating layer 297 and the first upper insulating layer 295 may be interposed therebetween.

[0129] The bit line BL′ may include a metal layer 299B and a conductive metal barrier layer 299A disposed between the metal layer 299B and the second upper insulating layer 297 , and may be connected to the channel structure CH′ via a bit line contact structure CT′.

[0130] The bit line contact structure CT′ may penetrate the first upper insulating layer 295 and the second upper insulating layer 297 to electrically connect some of the channel structures CH′ to the bit lines BL′.

[0131] Referring to the first gate stack structure GST1′, each channel structure CH′ may include a channel layer 231 and a core insulating layer 233, wherein a sidewall of the core insulating layer 233 may be surrounded by the first gate stack structure GST1′ and the first upper insulating layer 295. The channel layer 231 may include a semiconductor material, may be disposed between the core insulating layer 233 and the first gate stack structure GST1′, may extend between the core insulating layer 233 and the first upper insulating layer 295, and may extend between the common source layer CSL′ and the first gate stack structure GST1′.

[0132] Referring to the common source layer CSL′ corresponding to the first gate stack structure GST1′, the common source layer CSL′ may include a horizontal pattern HP extending parallel to the word line WL′ and a vertical pattern VP extending from the horizontal pattern HP in the third direction D3 toward the core insulating layer 233. The channel layer 231 may extend to surround the sidewall of the vertical pattern VP and extend between the horizontal pattern HP and the first gate stack structure GST1′. The common source layer CSL′ may be formed as a doped semiconductor layer including at least one of an n-type impurity and a p-type impurity.

[0133] Each channel structure CH′ may include a first pillar portion PA′ and a second pillar portion PB′ extending from the first pillar portion PA′ in a third direction D3. A central region of the first pillar portion PA′ may be filled with a vertical pattern VP of a core insulating layer 233 and a common source layer CSL′, and the core insulating layer 233 may extend to a central region of the second pillar portion PB′. An outer wall of the first pillar portion PA′ and an outer wall of the second pillar portion PB′ may be configured with a channel layer 231.

[0134] Referring to the first gate stack structure GST1′, the sidewall of the first pillar portion PA′ may be surrounded not only by the interlayer insulating layer 211 and the word line WL′, but also by the source selection line SSL′[A] corresponding to the first height of the first pillar portion PA′ and the source selection line SSL′[B] corresponding to the second height of the first pillar portion PA′. The sidewall of the second pillar portion PB′ may be surrounded by the drain selection line DSL1′ or DSL2′ corresponding to the second pillar portion PB′, and the second pillar portion PB′ of the channel structure CH′ may extend to the inside of the first upper insulating layer 295.

[0135] The sidewall of the first pillar portion PA′ may be surrounded by a first blocking insulating layer 221, a data storage layer 223, and a tunnel insulating layer 225, wherein the first blocking insulating layer 221, the data storage layer 223, and the tunnel insulating layer 225 may be disposed between the first pillar portion PA′ and each of the interlayer insulating layer 211 and the word line WL′. The first blocking insulating layer 221, the data storage layer 223, and the tunnel insulating layer 225 may extend between the source selection line SSL′[A] at a first height and the first pillar portion PA′, may extend between the source selection line SSL′[B] at a second height and the first pillar portion PA′, and may extend between the first gate stack structure GST1′ and the channel layer 231.

[0136] The data storage layer 223 may be disposed between the first blocking insulating layer 221 and the first pillar portion PA′. The tunnel insulating layer 225 may be disposed between the data storage layer 223 and the first pillar portion PA′ and may extend between the second pillar portion PB′ and the drain selection line DSL1′ or DSL2′ corresponding to the second pillar portion PB′.

[0137] Each channel structure CH′ may have a cone shape. As the channel structure CH′ becomes closer to the common source layer CSL′ and the peripheral circuit structure PS′, the width of the channel structure CH′ becomes wider. Some channel structures CH′ may be connected to the bit line BL′ via a bit line contact structure CT′. The bit line contact structure CT′ may penetrate the first upper insulating layer 295 and the second upper insulating layer 297, and may extend to contact the channel layer 231 of the channel structure CH′.

[0138] The common source layer CSL′ may be spaced apart from the peripheral circuit structure PS′ by a first insulating structure 261 , wherein the first insulating structure 261 may be bonded to the peripheral circuit structure PS′.

[0139] The peripheral circuit structure PS′ may include a substrate 271 including transistors 280A and 280B, a second insulating structure 291 , and an interconnect structure 293 .

[0140] The transistors 280A and 280B may be disposed in an active region of the substrate 271 separated by the isolation layer 273, and each of the transistors 280A and 280B may include a gate insulating layer 281, a gate electrode 283, and a junction 285, as shown in FIG. Figure 3B Some (eg, 280B) of the transistors 280A and 280B may constitute a page buffer circuit for controlling a precharge operation and a discharge operation of the bit line BL′.

[0141] The second insulating structure 291 may be disposed between the first insulating structure 261 and the substrate 271 , may include two or more insulating layers, and may be bonded to the first insulating structure 261 .

[0142] The interconnection structure 293 may be buried in the second insulating structure 291 , may include a plurality of conductive patterns, may be electrically connected to the transistor 280B of the page buffer circuit, and may be connected to the bit line BL′ through the first and second via contact structures V1 and V2 .

[0143] The first via contact structure V1 may penetrate the gate isolation layer 251, may penetrate the first insulating structure 261 and the second insulating structure 291 to contact the interconnection structure 293, and may extend in the third direction D3 to penetrate the first upper insulating layer 295. The second via contact structure V2 may contact the first via contact structure V1, and may extend to penetrate the second upper insulating layer 297. The first via contact structure V1 may include a conductive metal barrier layer 296A and a metal layer 296B, and the second via contact structure V2 may also include a conductive metal barrier layer 298A and a metal layer 298B.

[0144] According to the above-described embodiment, the bit line BL′ may be connected to the transistor 280B of the page buffer circuit via the first via contact structure V1 , the second via contact structure V2 , and the interconnection structure 293 .

[0145] Fig. 9 yes Figure 8B An enlarged cross-sectional view of region B is shown in FIG.

[0146] Reference Fig. 9 , the first blocking insulating layer 221 may include an end portion EG1 ′ facing the third direction D3 , and the data storage layer 223 may also include an end portion EG2 ′ facing the third direction D3 .

[0147] The drain selection line (eg, DSL1 ′) may overlap an end portion EG1 ′ of the first blocking insulating layer 221 and an end portion EG2 ′ of the data storage layer 223 .

[0148] The drain selection line DSL1′ may include a first conductive pattern 201 and a second conductive pattern 203. The first conductive pattern 201 may extend in a planar direction to intersect with the second pillar portion PB′. Specifically, the first conductive pattern 201 may extend in a first direction D1 and a second direction D2 to be parallel to the word line WL′. The second conductive pattern 203 may be disposed between the first conductive pattern 201 and the tunnel insulating layer 225, and a drain selection transistor having a gate all around (GAA) structure may be provided at a cross portion between the drain selection line DSL1′ and the second pillar portion PB′.

[0149] The second conductive pattern 203 may include at least one of silicon, metal silicide, and a conductive metal barrier, wherein the metal silicide may include tungsten silicide or nickel silicide, and the conductive metal barrier may include titanium and titanium nitride.

[0150] The second pillar portion PB′ of the channel structure CH′ may include a first portion P1′ surrounded by the drain selection line DSL1′, a second portion P2′ extending from the first portion P1′ in the third direction D3, and a third portion P3′ extending from the second portion P2′ in the third direction D3. The second portion P2′ and the third portion P3′ may protrude further than the drain selection line DSL1′ in the third direction D3 and may be covered by the first upper insulating layer 295.

[0151] The bit line contact structure CT′ may penetrate the first upper insulating layer 295 and may extend to contact the channel layer 231 of the third portion P3′. The conductive metal barrier layer 298A of the bit line contact structure CT′ may be disposed between the metal layer 298B of the bit line contact structure CT′ and the channel layer 231 and may extend between the metal layer 298B of the bit line contact structure CT′ and the first upper insulating layer 295.

[0152] The core insulation layer 233 of the channel structure CH′ may extend from the central region of the first pillar portion PA′ to central regions of the first portion P1 ′, the second portion P2 ′, and the third portion P3 ′.

[0153] As reference Figure 4 As described, the word line WL′ may include a conductive metal barrier layer 243 and a metal layer 245. Figure 4 As described above, the second blocking insulating layer 241 may be disposed between the word line WL′ and the first blocking insulating layer 221. Similar to the word line WL′, Figure 8B Each of the source selection lines SSL′[A] and SSL′[B] shown in FIG. 1 may include a conductive metal barrier layer 243 and a metal layer 245. The second blocking insulating layer 241 may be disposed between the first blocking insulating layer 221 and the Figure 8B The source selection lines SSL′[A] and SSL′[B] shown in FIG. 1 and the source selection lines SSL′[A] and SSL′[B] shown in FIG. 1 may be formed between the interlayer insulating layer 211 and the Figure 8B Extends between each of the source select lines SSL′[A] and SSL′[B] shown in FIG.

[0154] The tunnel insulating layer 225, the data storage layer 223 and the first blocking insulating layer 221 may be formed by referring to Figure 5B The second blocking insulating layer 241 may include an insulating material having a higher dielectric constant than that of the first blocking insulating layer 221 .

[0155] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 10E , Fig.11 , Fig.12 , Fig.13 , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B and Fig. 17C is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0156] FIG. 10A to FIG. 10E is a cross-sectional view illustrating a process performed before the bonding process.

[0157] Reference Fig. 10A , a first conductive layer 305 may be formed on the first substrate 301. Before forming the first conductive layer 305, a first protective layer 303 having an etching selectivity with respect to the first substrate 301 may be formed on the first substrate 301. In an implementation, the first substrate 301 may include silicon, and the first protective layer 303 may include nitride.

[0158] The first conductive layer 305 may include a conductive material having etching resistance with respect to an etching material when a subsequent etching process is performed to remove the first protective layer 303. In an implementation, the first conductive layer 305 may include silicon.

[0159] Subsequently, the first material layer 311 and the second material layer 313 may be alternately stacked on the first conductive layer 305. In an embodiment, the first material layer 311 may be an insulating material for an interlayer insulating layer such as silicon oxide, and the second material layer 313 may be a sacrificial material having an etching selectivity relative to the first material layer 311 such as silicon nitride. In another embodiment, the first material layer 311 may be an insulating material for an interlayer insulating layer, and the second material layer 313 may be a conductive material for a word line and a lower selection line. Hereinafter, for ease of description, the manufacturing process will be described mainly based on an embodiment in which the first material layer 311 is made of an insulating material for an interlayer insulating layer and the second material layer 313 is made of a sacrificial material. However, embodiments of the present disclosure are not limited thereto.

[0160] Subsequently, a hole 320 may be formed to penetrate the first material layer 311 and the second material layer 313. The hole 320 may penetrate the first conductive layer 305 and the first protective layer 303, and extend to the inside of the first substrate 301. The hole 320 may be formed by performing an etching process from the first material layer 311, which is the farthest from the first substrate 301 among the first material layer 311 and the second material layer 313, toward the first substrate 301. Therefore, the hole 320 may have a cone shape. As the hole 320 becomes farther from the first substrate 301, the width of the hole 320 becomes wider.

[0161] Subsequently, a first blocking insulating layer 321, a data storage layer 323, and a tunnel insulating layer 325 may be sequentially stacked on the surface of the hole 320. The data storage layer 323 may be made of a material that enables storage of data and has an etching selectivity with respect to the first blocking insulating layer 321 and the tunnel insulating layer 325. In an embodiment, the first blocking insulating layer 321 may include oxide, the data storage layer 323 may include silicon nitride, and the tunnel insulating layer 325 may include silicon oxide.

[0162] Subsequently, the central area of ​​the hole 320 may be filled with a channel structure 330 and a doped semiconductor pattern 335, wherein the channel structure 330 may include a channel layer 331 and a core insulating layer 333. The channel layer 331 may extend along the surface of the tunnel insulating layer 325 and may include a semiconductor material. In an embodiment, the channel layer may include silicon. The core insulating layer 333 and the doped semiconductor pattern 335 may fill the central area of ​​the hole 320 opened by the channel layer 331. After a portion of the hole 320 is filled with the core insulating layer 333, the doped semiconductor pattern 335 may be disposed on the core insulating layer 333. The channel structure 330 filling the central area of ​​the hole 320 may have a cone shape. As the hole 320 becomes farther from the first substrate 301, the width of the channel structure 330 becomes wider.

[0163] Reference Fig. 10B , a first trench 340 may be formed to penetrate Figure 3A The first material layer 311 and the second material layer 313 are shown, wherein the first trench 340 may be defined by etching the first material layer 311 and the second material layer 313. When etching the first material layer 311 and the second material layer 313, the first conductive layer 305 may be used as an etching stop layer.

[0164] when Fig. 10A When the second material layer 313 shown in FIG. 1 is a sacrificial material, the conductive pattern 347 may be replaced by the first trench 340. Fig. 10A The second material layer 313 is shown as being replaced by the conductive pattern 347 Fig. 10A The process of the second material layer 313 shown includes removing the Fig. 10A The process of opening the gate region between the first material layers 311 by forming the second material layer 313 as shown in FIG. 1 , and the process of filling the gate region with the conductive pattern 347 .

[0165] Before filling the gate regions with the conductive patterns 347 , a second blocking insulating layer 341 may be formed along a surface of each gate region, wherein each conductive pattern 347 may fill a portion of the gate region opened by the second blocking insulating layer 341 .

[0166] The conductive patterns 347 may be formed of various conductive materials. In an implementation, each conductive pattern 347 may include a conductive metal barrier layer 343 and a metal layer 345 . Each conductive pattern 347 may surround a sidewall of the channel structure 330 between the first material layers 311 .

[0167] Reference Fig. 10C , may be filled with a gate isolation layer 351 which may be an insulating material Fig. 10B The first trench 340 is shown in FIG.

[0168] Subsequently, a second trench 353 may be formed to penetrate Fig. 10B In an implementation, the second trench 353 may penetrate through two conductive patterns. Fig. 10B Some of the conductive patterns 347 shown in FIG. 347A may be isolated into drain selection lines 347D by the second trenches 353. Other conductive patterns not penetrated by the second trenches 353 may be defined as word lines 347W.

[0169] Reference Fig. 10D , may be filled with a drain isolation layer 357 which may be formed of an insulating material Fig. 10C The second groove 353 is shown in FIG.

[0170] Subsequently, the first insulating layer 361 may be formed to extend to overlap the channel structure 330, the gate isolation layer 351, the drain isolation layer 357, and the interlayer insulating layer 311. Continuously, a bit line contact structure 363 may be formed to penetrate the first insulating layer 361. The bit line contact structure 363 may be electrically connected to the channel structure 330 and the doped semiconductor pattern 335.

[0171] Subsequently, a bit line 365 may be formed to contact the bit line contact structure 363. The bit line 365 may extend onto the first insulating layer 361. In an implementation, the bit line 365 may extend in the first direction D1.

[0172] Reference Fig. 10E The bonding structure may be formed on the bit line 365 and may include a first insulating structure 367 and a first conductive bonding pad 371 buried in the first insulating structure 367 .

[0173] Before forming the first conductive bonding pad 371, the first interconnect structure 369 may be formed to include a plurality of conductive patterns buried in the first insulating structure 367. Some conductive patterns of the first interconnect structure 369 may be electrically connected to the bit line 365. The first conductive bonding pad 371 may contact the first interconnect structure 369 and may be electrically connected to the bit line 365 via the first interconnect structure 369.

[0174] Fig.11 is a cross-sectional view illustrating a process of forming a peripheral circuit structure.

[0175] Reference Fig.11 , the process of forming the peripheral circuit structure 390 may include: a process of forming an isolation layer 383 in the second substrate 381 to separate the active area of ​​the second substrate 381; a process of forming transistors 385A and 385B in the active area separated by the source isolation layer 383; a process of forming a second interconnect structure 389 connected to the transistors 385A and 385B; and a process of forming a second conductive bonding pad 391 connected to the second interconnect structure 389.

[0176] Transistors 385A and 385B may include reference Figure 3A Some of transistors 385A and 385B (eg, 385B) may constitute a page buffer circuit.

[0177] The second substrate 381 including the transistors 385A and 385B may be covered by a second insulating structure 387. A second interconnect structure 389 and a second conductive bonding pad 391 may be buried in the second insulating structure 387.

[0178] The second interconnect structure 389 may include a plurality of conductive patterns, some of which may be connected to the transistor 385B of the page buffer circuit. The second conductive bonding pad 391 may be connected to the transistor 385B of the page buffer circuit via the second interconnect structure 389.

[0179] Fig.12 is a cross-sectional view illustrating a bonding process.

[0180] Reference Fig.12 , the peripheral circuit structure 390 may be aligned to face the first insulating structure 367 and the first conductive bonding pad 371 of the bonding structure.

[0181] Subsequently, the second insulating structure 387 and the second conductive bonding pad 391 of the peripheral circuit structure 390 may be bonded to the first insulating structure 367 and the first conductive bonding pad 371 of the bonding structure.

[0182] After the process of performing the bonding process, the process temperature may be limited to 450° C. or less, so that defects occurring in the first and second conductive bonding pads 371 and 391 due to high temperature may be reduced.

[0183] Fig.13 are cross-sectional views illustrating some processes performed after the bonding process.

[0184] Reference Fig.13 , you can remove Fig.12 The first substrate 301 shown in FIG. Fig.12 The first protective layer 303 shown protects the first conductive layer 305. Subsequently, the Fig.12 The first protective layer 303 shown in FIG. 1 is removed so that the first conductive layer 305 and the first blocking insulating layer 321 can be exposed.

[0185] Fig.14A and Fig. 14B yes Fig.13 An enlarged process cross-sectional view of region C shown in FIG.

[0186] Reference Fig.14A , a preliminary recessed region 403 may be formed between the first conductive layer 305 and the data storage layer 323 by selectively removing a portion of the first blocking insulating layer 321. The remaining first blocking insulating layer 321 may be disposed closer to the first conductive layer 305 than the conductive metal barrier layer 343 and the metal layer 345.

[0187] Reference Fig. 14B By selectively removing the data storage layer 323, a recessed region 405 may be defined between the first conductive layer 305 and the tunnel insulating layer 325. The remaining first blocking insulating layer 321 and the remaining data storage layer 323 may be disposed closer to the first conductive layer 305 than the conductive metal barrier layer 343 and the metal layer 345.

[0188] Fig.15A and Fig. 15B is a cross-sectional view illustrating subsequent processes continued after forming a recessed region.

[0189] Reference Fig.15A , a second conductive layer 411 may be formed along the surface of the first conductive layer 305 and the tunnel insulating layer 325, and the second conductive layer 411 may be filled Fig. 14B Recessed area 405 is shown.

[0190] The second conductive layer 411 may include at least one of silicon, metal silicide, and a conductive metal barrier, wherein the metal silicide may include tungsten silicide or nickel silicide, and the conductive metal barrier may include titanium and titanium nitride.

[0191] Reference Fig. 15B , a portion of the second conductive layer 411 may be removed to expose the tunnel insulating layer 325 and the first conductive layer 305. The second conductive layer 411 may be retained as Fig. 14B The recessed region 405 shown in FIG. 4 surrounds the sidewall of the tunnel insulating layer 325 .

[0192] Fig.16A and Fig. 16B is a process cross-sectional view illustrating a process of isolating an upper select line.

[0193] Reference Fig.16A , an uneven structure may be defined by a channel structure 330 that protrudes farther than the first conductive layer 305 in the third direction D3. A second protective layer 421 may be formed along the surface of the uneven structure, and the second protective layer 421 may be deposited under conditions that reduce step coverage. In an embodiment, the second protective layer 421 may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) having a step coverage that is more reduced than that of atomic layer deposition (ALD). The second protective layer 421 may include a material having an etching selectivity relative to the first conductive layer 305. In an embodiment, the second protective layer 421 may include an amorphous carbon layer (ACL) that may be deposited by plasma enhanced chemical vapor deposition (PE-CVD).

[0194] The second protective layer 421 deposited under the condition of reducing the step coverage may be formed relatively thicker on the convex portion of the uneven structure than on the concave portion of the uneven structure, may have an overhang structure, and may have side walls facing each other, and each first opening 423 is interposed between the side walls facing each other. As the overhang structure becomes farther from the first conductive layer 305, the width of each first opening 423 may be narrowed by the second protective layer 421.

[0195] Subsequently, by using a photolithography process, a mask pattern 431 may be formed on the second protective layer 421. The mask pattern 431 may be a photoresist pattern that may include a second opening 433.

[0196] The second opening 433 may overlap the gate isolation layer 351 and the drain isolation layer 357 , respectively. The first opening 423 overlapping the gate isolation layer 351 and the drain isolation layer 357 may be exposed through the second opening 433 .

[0197] The first conductive layer 305 located at the periphery of the channel structure 330 may be blocked by the second protection layer 421 having an overhang structure.

[0198] Reference Fig. 16B , can be achieved through Fig.16AThe first conductive layer 305 is etched by etching the first opening 423 exposed by the second opening 433 shown in FIG. 4 to form a third trench 441 penetrating the first conductive layer 305. An upper selection line may be defined by the third trench 441. In an embodiment, the upper selection line may be a source selection line 443. Each source selection line 443 may include a first conductive layer 305 separated by the third trench 441 and a second conductive layer 411 between the first conductive layer 305 and the tunnel insulating layer 325.

[0199] According to an embodiment of the present disclosure, the second conductive layer 411 is retained to surround the channel structure 330 between the tunnel insulating layer 325 and the first conductive layer 305, so that the retained width of the source selection line 443 between the tunnel insulating layer 325 and the third trench 441 can be widened. Therefore, in an embodiment of the present disclosure, a selection transistor with a gate all around (GAA) can be stably formed.

[0200] FIG. 17A to FIG. 17C An embodiment of a subsequent process continuing after forming the source selection line 443 is illustrated.

[0201] Reference Fig.17A , an upper insulating layer 451 may be formed to fill the third trench 441 and cover the source selection line 443 , the channel structure 330 , and the tunnel insulating layer 325 , wherein the upper insulating layer 451 may include oxide.

[0202] Reference Fig. 17B , a portion of the upper insulating layer 451 and a portion of the tunnel insulating layer 325 may be etched through an etching process such as an etch-back process, so that the channel layer 331 of the channel structure 330 may be exposed.

[0203] The upper insulating layer 451 may remain in the third trench 441 , and may remain to cover the source selection line 443 .

[0204] Reference Fig. 17C , a doped semiconductor layer 455 of a common source layer may be formed on the exposed region of the channel layer 331 .

[0205] Fig.18A , Fig.18B , Fig.18C , Fig.18D , Fig.18E , Fig.18F , Figure 18G , Fig.18H , Fig.18I , Fig.18J , Figure 18K , Figure 18L , Figure 18M and Fig.18N is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0206] Reference Fig.18A , as referenced Fig. 10A As described above, a first protective layer 503 and a first conductive layer 505 may be formed on the first substrate 501. Fig. 10A As described, the first material layers 511 and the second material layers 513 may be alternately stacked on the first conductive layer 505 to form a stacked structure 510 .

[0207] Subsequently, a hole 520 may be formed, which penetrates the first material layer 511 , the second material layer 513 , the first conductive layer 505 , and the first protective layer 503 , and extends to the inside of the first substrate 501 .

[0208] Reference Fig.18B The first blocking insulating layer 521, the data storage layer 523 and the tunnel insulating layer 525 may be sequentially stacked on Fig.18A On the surface of the hole 520 shown in , each of the first blocking insulating layer 521 , the data storage layer 523 , and the tunnel insulating layer 525 may extend not only along the sidewall and bottom surface of the hole 520 , but also along the top surface of the stack structure 510 .

[0209] The data storage layer 523 may be made of a material that enables storage of data and has an etching selectivity with respect to the first blocking insulating layer 521 and the tunnel insulating layer 525, and the first blocking insulating layer 521 and the tunnel insulating layer 525 may be made of a material that enables storage of data and has an etching selectivity with respect to the first blocking insulating layer 521 and the tunnel insulating layer 525. Fig. 10A Made of described material.

[0210] Subsequently, the preliminary trench structure 530P may be filled Fig.18A The preliminary channel structure 530P may include a channel layer 531 and a core insulating layer 533. The channel layer 531 may be formed as a semiconductor layer and may extend along the surface of the tunnel insulating layer 525. In an embodiment, the channel layer 531 may include silicon. The core insulating layer 533 may be disposed on the channel layer 531 and may be filled with a Fig.18A The core insulating layer 533 may be formed so that Fig.18A The height of the upper opening of the hole 520 shown in FIG.

[0211] After forming the core insulating layer 533, the upper end of the hole opened by the core insulating layer 533 may be filled with the doped semiconductor layer 539. The doped semiconductor layer 539 may include a vertical portion 539A filling the upper end of the hole and a horizontal portion 539B extending from the vertical portion 539A parallel to the top surface of the stack structure 510.

[0212] Reference Fig.18C, a first trench 540 may be formed, wherein the first trench 540 may penetrate Fig.18B The doped semiconductor layer 539, the channel layer 531, the tunnel insulating layer 525, the data storage layer 523, the first blocking insulating layer 521, the first material layer 511 and the second material layer 513 are shown in FIG. Therefore, a preliminary gate stack structure 510P and a channel structure 530 may be defined.

[0213] The channel structure 530 may include a pillar portion PP penetrating the preliminary gate stacked structure 510P, wherein the pillar portion PP of the channel structure 530 may include a core insulating layer 533 and a channel layer 531 penetrating the preliminary gate stacked structure 510P.

[0214] Fig.18B The doped semiconductor layer 539 shown in FIG. 5 may be isolated into a common source layer 539S by a first trench 540 .

[0215] Reference Fig.18D , as referenced Fig. 10B As described, the second material layer 513 can be replaced by a conductive pattern 547, wherein at least one conductive pattern of the conductive pattern 547 adjacent to the common source layer 539S can be used as a source selection line, and the other conductive patterns can be used as word lines. Fig. 10B As described, before forming the conductive pattern 547 , the second blocking insulating layer 541 may be formed.

[0216] Reference Fig.18E , can be filled with gate isolation layer 551 Fig.18D The first trench 540 is shown in FIG. The gate isolation layer 551 may be formed of an insulating material.

[0217] Subsequently, a bonding structure may be formed, which may cover the gate isolation layer 551 and the common source layer 539S. The bonding structure may be configured with a first insulating structure 561.

[0218] Reference Fig.18F , a peripheral circuit structure 590 may be provided, and the peripheral circuit structure 590 may include transistors 585A and 585B, an interconnection structure 589 connected to the transistors 585A and 585B, and a second insulating structure 587. The transistors 585A and 585B may be formed in an active region of the second substrate 581 separated by the isolation layer 583. The transistors 585A and 585B and the interconnection structure 589 may be buried in the second insulating structure 587, and the second insulating structure 587 may include two or more insulating layers.

[0219] Subsequently, the peripheral circuit structure 590 may be aligned such that the peripheral circuit structure 590 faces the first insulation structure 561. Subsequently, the second insulation structure 587 of the peripheral circuit structure 590 may be bonded to the first insulation structure 561.

[0220] Reference Figure 18G , can be removed sequentially Fig.18F The first substrate 501 and the first protective layer 503 shown in FIG. 5 may expose the first conductive layer 505 and the first blocking insulating layer 521 .

[0221] Reference Fig.18H , can be referenced by using Fig.14A and Fig. 14B The described process is used to remove a portion of the first blocking insulating layer 521 and a portion of the data storage layer 523. Therefore, a recessed region 605 may be defined between the first conductive layer 505 and the tunnel insulating layer 525.

[0222] Reference Fig.18I , can be referenced by using Fig.15A and Fig. 15B The process described will fill Fig.18H The second conductive layer 611 of the recessed region 605 shown in FIG. 5 is formed to surround the sidewall of the tunnel insulating layer 625 between the first conductive layer 505 and the tunnel insulating layer 525 .

[0223] Reference Fig.18J , can be referenced by using Fig.16A and Fig. 16B The process of isolating the upper selection line described above is used to form a second trench 641 that penetrates the first conductive layer 505. The upper selection line may be defined by the second trench 641. In an embodiment, the upper selection line may be a drain selection line 643. Each drain selection line 643 may include a first conductive layer 505 separated by the second trench 641 and a second conductive layer 611 between the first conductive layer 505 and the tunnel insulating layer 525.

[0224] According to an embodiment of the present disclosure, the second conductive layer 611 remains to surround the channel structure 530 between the tunnel insulating layer 525 and the first conductive layer 505 , so that a selection transistor having a gate all around (GAA) structure can be stably formed.

[0225] Reference Figure 18K , the first upper insulating layer 651 may be formed to fill the second trench 641, and may be formed to cover the drain selection line 643, the channel structure 530, and the tunnel insulating layer 525. The first upper insulating layer 651 may include an oxide. The surface of the first upper insulating layer 651 may be planarized by a process such as chemical mechanical polishing (CMP).

[0226] Reference Figure 18L , the first contact hole 660 may be formed to penetrate a portion of the first upper insulating layer 651 overlapping the gate isolation layer 551, the gate isolation layer 551, the first insulating structure 561, and the second insulating structure 587. The first contact hole 660 may be formed to expose a conductive pattern of the interconnection structure 589, and may expose a conductive pattern of the interconnection structure 589 connected to a transistor (e.g., 585B) of the page buffer circuit.

[0227] Subsequently, a first via contact structure 665 may be formed, which may fill the first contact hole 660 and may include a conductive metal barrier layer 661 extending along a surface of the first contact hole 660 and a metal layer 663 filling a central region of the first contact hole 660 opened by the conductive metal barrier layer 661 .

[0228] Reference Figure 18M , the second upper insulating layer 667 may be formed on the first upper insulating layer 651 , and may extend to cover the first via contact structure 665 .

[0229] Subsequently, contact holes 670A and 670B may be formed, and the contact holes 670A and 670B may penetrate at least one of the first upper insulating layer 651 and the second upper insulating layer 667 , and may include the second contact hole 670A and the third contact hole 670B.

[0230] The second contact hole 670A may penetrate the second upper insulating layer 667 to expose the first via contact structure 665. The third contact hole 670B may penetrate the tunnel insulating layer 525 to expose the channel layer 531 in addition to the first upper insulating layer 651 and the second upper insulating layer 667.

[0231] Reference Fig.18N , can be achieved by filling the Figure 18M 670A and the third contact hole 670B shown in , to form a second through-hole contact structure 675A and a bit line contact structure 675B. In an embodiment, the process of forming the second through-hole contact structure 675A and the bit line contact structure 675B may include: a process of forming a conductive metal barrier layer 671 along a surface of each of the second contact hole 670A and the third contact hole 670B; and a process of filling a central area of ​​each of the second contact hole 670A and the third contact hole 670B opened by the conductive metal barrier layer 617 with a metal layer 673.

[0232] The second via contact structure 675A may fill Figure 18M The second contact hole 670A shown in FIG. 1 is in contact with the first through-hole contact structure 665. The bit line contact structure 675B may be filled with Figure 18MThe third contact hole 670B shown in FIG. 5A may contact the channel layer 531 of the channel structure 530 .

[0233] Then, you can execute the following Figure 8B Subsequent processes for forming bit lines are described.

[0234] Fig.19 is a block diagram illustrating a configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0235] Reference Fig.19 , the memory system 1100 may include a memory device 1120 and a memory controller 1110 .

[0236] The memory device 1120 may include a channel structure, a blocking insulating layer, and a tunnel insulating layer. The channel structure may include a first pillar portion and a second pillar portion extending from the first pillar portion. The blocking insulating layer may surround the sidewall of the first pillar portion, the data storage layer is between the blocking insulating layer and the first pillar portion, the selection line overlaps with the end of the data storage layer and the end of the blocking insulating layer facing the extension direction of the second pillar portion, and the selection line surrounds the sidewall of the second pillar portion. The tunnel insulating layer may be disposed between the first pillar portion and the data storage layer, and the tunnel insulating layer extends between the selection line and the second pillar portion.

[0237] The memory device 1120 may be a multi-chip package configured with a plurality of flash memory chips.

[0238] The memory controller 1110 may control the memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 may be used as an operation memory of the CPU 1112, the CPU 1112 may perform an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 may include a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 may detect and correct errors included in data read from the memory device 1120. The memory interface 1115 may be interfaced with the memory device 1120. The memory controller 1110 may also include a read-only memory (ROM) for storing code data, etc., which is interfaced with the host.

[0239] Fig. 20 is a block diagram illustrating a configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0240] Reference Fig. 20, the computing system 1200 may include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0241] The memory system 1210 may be configured with a memory device 1212 and a memory controller 1211. The memory device 1212 may include a channel structure, a blocking insulating layer, and a tunnel insulating layer. The channel structure may include a first pillar portion and a second pillar portion extending from the first pillar portion. The blocking insulating layer may surround the sidewall of the first pillar portion, the data storage layer is between the blocking insulating layer and the first pillar portion, the selection line overlaps with the end of the data storage layer facing the extension direction of the second pillar portion and the end of the blocking insulating layer, and the selection line surrounds the sidewall of the second pillar portion. The tunnel insulating layer may be disposed between the first pillar portion and the data storage layer, and the tunnel insulating layer extends between the selection line and the second pillar portion.

[0242] In an embodiment, the present disclosure may provide a semiconductor device having a wafer bonding structure, comprising a selection line, a blocking insulating layer, a data storage layer and a tunnel insulating layer, wherein the selection line comprises a first conductive pattern and a second conductive pattern, wherein the first conductive pattern surrounds the tunnel insulating layer, and wherein the second conductive pattern overlaps with an end portion of the blocking insulating layer and an end portion of the data storage layer, and the second conductive pattern is inserted between the first conductive pattern and the tunnel insulating layer.

[0243] According to the present disclosure, a selection line having a gate all around (GAA) structure can be formed. Therefore, the operation characteristics of a semiconductor memory device can be improved.

[0244] CROSS-REFERENCE TO RELATED APPLICATIONS

[0245] This application claims the priority of Korean Patent Application No. 10-2020-0134645 filed on October 16, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, the semiconductor memory device include: a first conductive bonding pad; a peripheral circuit structure including a second conductive bonding pad bonded to the first conductive bonding pad; a channel structure disposed above the peripheral circuit structure with the first conductive bonding pad and the second conductive bonding pad interposed between the channel structure and the peripheral circuit structure, the channel structure comprising a first column portion and a second column portion extending from the first column portion in a direction away from the first column portion; a blocking insulating layer surrounding a sidewall of the first pillar portion of the channel structure; a data storage layer disposed between the first pillar portion of the channel structure and the blocking insulating layer; a conductive pattern, the conductive pattern contacting an end portion of the blocking insulating layer and an end portion of the data storage layer, the conductive pattern surrounding a sidewall of the second pillar portion of the channel structure; as well as a tunnel insulating layer disposed between the first pillar portion of the channel structure and the data storage layer, The second pillar portion of the channel structure protrudes further than the conductive pattern in a direction in which the second pillar portion extends from the first pillar portion.

2. The semiconductor memory device according to claim 1, in, The conductive pattern has a bottom portion disposed at substantially the same height as the end portion of the blocking insulating layer and the end portion of the data storage layer.

3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device further comprises: include: An upper insulating layer directly covers a surface of the conductive pattern opposite to the peripheral circuit structure.

4. The semiconductor memory device according to claim 3, in, The upper insulating layer includes oxide.

5. The semiconductor memory device according to claim 1, further comprising: include: a plurality of interlayer insulating layers and a plurality of word lines, the plurality of interlayer insulating layers and the plurality of word lines being alternately stacked in a direction from the peripheral circuit structure toward the conductive pattern, the plurality of interlayer insulating layers and the plurality of word lines surrounding the first pillar portion of the channel structure, The blocking insulating layer, the data storage layer, and the tunnel insulating layer are interposed between the first pillar portion and each of the plurality of interlayer insulating layers and the plurality of word lines.

6. The semiconductor memory device according to claim 5, in, The conductive pattern is thicker than each of the plurality of word lines.

7. The semiconductor memory device according to claim 1, in, The blocking insulating layer and the data storage layer are not disposed between the second pillar portion of the channel structure and the conductive pattern.

8. A semiconductor memory device, the semiconductor memory device include: a first conductive bonding pad; a peripheral circuit structure including a second conductive bonding pad bonded to the first conductive bonding pad; a channel structure disposed above the peripheral circuit structure with the first conductive bonding pad and the second conductive bonding pad interposed between the channel structure and the peripheral circuit structure, the channel structure comprising a first column portion and a second column portion extending from the first column portion in a direction away from the first column portion; a blocking insulating layer surrounding a sidewall of the first pillar portion of the channel structure; a data storage layer disposed between the first pillar portion of the channel structure and the blocking insulating layer; a tunnel insulating layer, the tunnel insulating layer being disposed between the first pillar portion of the channel structure and the data storage layer; an upper insulating layer, the upper insulating layer surrounding the first side wall of the second column portion; as well as a conductive pattern, the conductive pattern contacting an end portion of the blocking insulating layer and an end portion of the data storage layer, the conductive pattern surrounding a second sidewall of the second pillar portion, the second sidewall being disposed between the first sidewall and the first pillar portion, Wherein, the upper insulating layer directly covers the surface of the conductive pattern opposite to the peripheral circuit structure.

9. The semiconductor memory device according to claim 8, in, The upper insulating layer includes oxide.

10. The semiconductor memory device according to claim 8, in, The conductive pattern has a bottom portion disposed at substantially the same height as the end portion of the blocking insulating layer and the end portion of the data storage layer.

11. The semiconductor memory device according to claim 8, wherein the semiconductor memory device further comprises: include: a plurality of interlayer insulating layers and a plurality of word lines, the plurality of interlayer insulating layers and the plurality of word lines being alternately stacked in a direction from the peripheral circuit structure toward the conductive pattern, the plurality of interlayer insulating layers and the plurality of word lines surrounding the first pillar portion of the channel structure, The blocking insulating layer, the data storage layer, and the tunnel insulating layer are interposed between the first pillar portion and each of the plurality of interlayer insulating layers and the plurality of word lines.

12. The semiconductor memory device according to claim 11, in, The conductive pattern is thicker than each of the plurality of word lines.

13. The semiconductor memory device according to claim 8, in, The blocking insulating layer and the data storage layer are not disposed between the second pillar portion of the channel structure and the conductive pattern.

14. A semiconductor memory device, the semiconductor memory device include: Peripheral circuit structure; a first stacked structure and a second stacked structure, the first stacked structure and the second stacked structure being spaced apart from the peripheral circuit structure in a vertical direction, the first stacked structure and the second stacked structure being spaced apart from each other by a trench; a channel structure including a first column portion and a second column portion, the first column portion passing through each of the first stacked structure and the second stacked structure, the second column portion extending from the first column portion and protruding further than each of the first stacked structure and the second stacked structure in a direction away from the first column portion; a blocking insulating layer between each of the first stacked structure and the second stacked structure and the first pillar portion of the channel structure; a data storage layer disposed between the first pillar portion of the channel structure and the blocking insulating layer; a tunnel insulating layer, the tunnel insulating layer being disposed between the first pillar portion of the channel structure and the data storage layer; a conductive pattern, the conductive pattern contacting an end portion of the blocking insulating layer and an end portion of the data storage layer, the conductive pattern surrounding a sidewall of the second pillar portion of the channel structure; an upper insulating layer, the upper insulating layer covering the conductive pattern and the channel structure; as well as A through-hole contact structure passes through the upper insulating layer and is aligned with the trench in the vertical direction.

15. The semiconductor memory device according to claim 14, in, The conductive pattern has a bottom portion disposed at substantially the same height as the end portion of the blocking insulating layer and the end portion of the data storage layer.

16. The semiconductor memory device according to claim 14, in, The upper insulating layer directly contacts a surface of the conductive pattern opposite to the peripheral circuit structure.

17. The semiconductor memory device according to claim 14, in, The upper insulating layer includes oxide.

18. The semiconductor memory device according to claim 14, in, Each of the first stacked structure and the second stacked structure includes a plurality of interlayer insulating layers and a plurality of word lines alternately stacked in the vertical direction, the plurality of interlayer insulating layers and the plurality of word lines surrounding the first pillar portion of the channel structure.

19. The semiconductor memory device according to claim 18, in, The conductive pattern is thicker than each of the plurality of word lines.

20. The semiconductor memory device according to claim 14, in, The blocking insulating layer and the data storage layer are not disposed between the second pillar portion of the channel structure and the conductive pattern.

21. A method for manufacturing a semiconductor memory device, the method The following steps are involved: forming a structure including a first conductive layer over a substrate, a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked over the first conductive layer, a hole penetrating the plurality of interlayer insulating layers, the plurality of conductive patterns, and the first conductive layer and extending into the substrate, a channel structure in the hole, a multilayer stack extending along an outer surface of each of the channel structures, and a first conductive bonding pad over the first conductive layer, with the channel structure interposed between the first conductive bonding pad and the first conductive layer; bonding the first conductive bonding pad to a second conductive bonding pad of a peripheral circuit structure; after bonding the first conductive bond pad to the second conductive bond pad of the peripheral circuit structure, removing the substrate to expose the first conductive layer and the multilayer stack; removing a portion of the multilayer stack to form a recessed region between the first conductive layer and the channel structure; as well as A second conductive layer is formed to fill the recessed area.

22. The method according to claim 21, in, The channel structure includes a first channel structure and a second channel structure that are adjacent to each other. wherein the plurality of conductive patterns include a plurality of word lines and selection groups above the first conductive layer, and The plurality of word lines are interposed between the first conductive layer and the selection group.

23. The method according to claim 22, in, The first conductive layer is thicker than each of the plurality of word lines.

24. The method according to claim 22, in, The selection group includes a first drain selection line surrounding the first channel structure and a second drain selection line surrounding the second channel structure, wherein the first drain selection line and the second drain selection line are separated from each other by a trench between the first drain selection line and the second drain selection line, and Each of the plurality of word lines surrounds the first channel structure and the second channel structure.

25. The method according to claim 21, in, Each of the holes has a width that becomes wider as each of the holes becomes farther away from the substrate.

26. The method according to claim 21, in, A smaller number of material layers in the multi-layer stack remain between the second conductive layer and each of the channel structures than between the plurality of conductive patterns and each of the channel structures.

27. The method according to claim 21, in, The multi-layer stack includes a blocking insulating layer on a surface of each of the holes, a data storage layer on a surface of the blocking insulating layer, and a tunnel insulating layer on a surface of the data storage layer.

28. The method according to claim 27, in, The step of removing a portion of the multi-layer stack includes removing a portion of the blocking insulating layer and a portion of the data storage layer to expose the tunnel insulating layer, and Wherein, the recessed area is formed between the first conductive layer and the tunnel insulating layer.

29. The method according to claim 21, further comprising: The following steps are involved: An upper insulating layer is formed to directly cover the first conductive layer and the second conductive layer.

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