Semiconductor memory device

Abstract

The invention relates to a semiconductor memory device. The semiconductor memory device includes a gate stack, a hole penetrating the gate stack, and a channel structure. The aperture has an undercut region defined on a sidewall thereof. The channel structure covers a portion of the undercut region and opens another portion of the undercut region.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to an electronic device, and more particularly to a semiconductor memory device. Background Art

[0002] As is well known, semiconductor memory devices have become ubiquitous and therefore, the demand for semiconductor memory devices continues to increase.

[0003] A semiconductor memory device may include memory cells for storing data. In order to obtain a semiconductor memory device having a large capacity, a technology for a three-dimensional semiconductor memory device including memory cells arranged three-dimensionally has been developed. Summary of the invention

[0004] According to an embodiment, a semiconductor memory device may include: a gate stack, the gate stack including a first sub-stack, a second sub-stack and a third sub-stack, the first sub-stack to the third sub-stack being stacked on top of each other in a first direction; and a cell plug, the cell plug extending in the first direction and penetrating the first sub-stack, the second sub-stack and the third sub-stack, wherein the cell plug includes a first region penetrating the first sub-stack, a second region penetrating the second sub-stack, and a third region penetrating the third sub-stack, each of the first region, the second region and the third region having a top end and a bottom end, each of the top end and the bottom end having a corresponding area, wherein the area of ​​the top end of the first region of the cell plug is greater than the area of ​​the bottom end of the second region of the cell plug, and wherein the top end of the second region of the cell plug has an area greater than the area of ​​the bottom end of the third region.

[0005] According to an embodiment, a semiconductor memory device may include: a gate stack comprising a plurality of conductive layers spaced apart and stacked on each other in a first direction; a hole extending in the first direction and penetrating the plurality of conductive layers; a channel structure comprising a first channel column and a second channel column extending in the first direction, the channel structure being located in the hole and spaced apart from each other in a second direction, the second direction being located in a plane substantially parallel to the plurality of conductive layers; and a memory layer being located between the gate stack and each of the first channel column and the second channel column, wherein a curved portion defining an undercut region is formed on a sidewall of the hole, wherein the undercut region comprises a first portion in the second direction and a second portion in a third direction intersecting the second direction in the plane, and wherein the channel structure covers the first portion of the undercut region and opens the second portion of the undercut region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A and Figure 1B is a perspective view of a semiconductor memory device according to an embodiment of the present disclosure;

[0007] Figure 2 is a circuit diagram showing a memory cell array according to an embodiment of the present disclosure;

[0008] Figure 3A , Figure 3B , Figure 3C and Figure 3D is a vertical cross-sectional view showing a first structure and a second structure of a semiconductor memory device according to an embodiment of the present disclosure;

[0009] Figure 4 is a perspective view of a semiconductor memory device according to an embodiment of the present disclosure;

[0010] Figure 5A and Figure 5B is a vertical cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure;

[0011] Fig. 6A and Figure 6B is a diagram showing a portion of a semiconductor memory device according to an embodiment of the present disclosure;

[0012] Fig. 7A , Figure 7B and Figure 7C is a vertical cross-sectional view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure;

[0013] Fig. 8A and Figure 8Bis a perspective view showing steps of a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure;

[0014] Fig. 9 It is shown along Figure 8B A vertical cross-sectional view of a portion of the internal structure taken along the minor axis of the bore shown;

[0015] Fig.10 is a vertical cross-sectional view showing a semiconductor memory device according to a comparative example; and

[0016] Fig.11 is a block diagram illustrating an electronic system including a semiconductor memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] The specific structure and function description disclosed herein are only shown for the purpose of describing the embodiments according to the conception of the present disclosure. The embodiments according to the conception of the present disclosure can be modified in various forms and replaced with other equivalent embodiments. Therefore, the present disclosure should not be interpreted as being limited to the embodiments set forth herein.

[0018] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and the order or number of components is not limited by these terms.

[0019] Embodiments provide a semiconductor memory device capable of improving operation reliability.

[0020] Figure 1A and Figure 1B is a perspective view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0021] Reference Figure 1A and Figure 1B , the semiconductor memory device may include a first structure ST1, a second structure ST2, and a doped semiconductor structure DPS located between the first structure ST1 and the second structure ST2. The first structure ST1 may include a cell array structure CAS and a bit line array structure BAS. The second structure ST2 may include a peripheral circuit structure PS.

[0022] The bit line array structure BAS may include a plurality of bit lines BL.

[0023] The cell array structure CAS may be located between the bit line array structure BAS and the doped semiconductor structure DPS, and may include a memory block ( Figure 1A). The memory block may include a plurality of memory cell strings electrically connected to the bit line array structure BAS and the doped semiconductor structure DPS. Each memory cell string may include a channel structure CH extending from the doped semiconductor structure DPS toward a bit line BL corresponding thereto. (See Figure 3A , Figure 3B , Figure 3C or Figure 3D ).

[0024] The doped semiconductor structure DPS may include at least one of an n-type impurity and a p-type impurity, and may be used as at least one of a common source region and a well region. The doped semiconductor structure DPS may include a first conductive type doped region containing n-type impurities as majority carriers. The doped semiconductor structure DPS may also include a second conductive type doped region containing p-type impurities as majority carriers. The first conductive type doped region may be set as a common source region, and the second conductive type doped region may be set as a well region.

[0025] The peripheral circuit structure PS may be configured to perform three operations: 1) a program operation for storing data in a memory cell; 2) a read operation for outputting data stored in a memory cell; and 3) an erase operation for erasing data stored in a memory cell. The peripheral circuit structure PS may include an input / output circuit, a control circuit, a voltage generating circuit, a row decoder, a column decoder, and a page buffer. More specifically, the peripheral circuit structure PS may include a plurality of transistors, capacitors, resistors, and the like.

[0026] The peripheral circuit structure PS may include a region overlapping / under the doped semiconductor structure DPS, the cell array structure CAS, and the bit line array structure BAS. The peripheral circuit structure PS may include a region overlapping / under the doped semiconductor structure DPS, the cell array structure CAS, and the bit line array structure BAS. Figure 1A As shown, the doped semiconductor structure DPS is vertically adjacent to the doped semiconductor structure DPS, or can be as shown Figure 1B Shown vertically adjacent to the bit line array structure BAS.

[0027] The cell array structure CAS may be connected to the peripheral circuit structure PS through a plurality of selection lines, a plurality of word lines, a bit line array structure BAS, and a doped semiconductor structure DPS. Figure 1A and Figure 1B Although not shown in the drawings, each of the first structure ST1 and the second structure ST2 may include at least one of a plurality of interconnections, a plurality of contacts, and a plurality of conductive bonding pads for electrical connection.

[0028] The cell array structure CAS may include a three-dimensional cell array structure including memory cells arranged in three dimensions.

[0029] Figure 2 is a circuit diagram showing a memory cell array according to an embodiment of the present disclosure.

[0030] Reference Figure 2 , the memory cell array may include a plurality of memory cell strings CS. Each of the memory cell strings CS may include at least one source selection transistor SST, a plurality of memory cell transistors MC (hereinafter referred to as memory cells MC), and at least one drain selection transistor DST. The plurality of memory cells MC may be connected in series between the source selection transistor SST and the drain selection transistor DST. The source selection transistor SST, the plurality of memory cells MC, and the drain selection transistor DST of each memory cell string CS may be connected in series with each other through a channel structure CH. (See Figure 3A , Figure 3B , Figure 3C or Figure 3D . )

[0031] The channel structure CH may be used as a channel region of the memory cell string CS and include a semiconductor layer. The channel structure CH may be connected to the common source region CSR and the bit line BL. The common source region CSR may be formed in the doped semiconductor structure DPS. A voltage may be applied to the common source region CSR to discharge the channel region potential of the memory cell string CS. A voltage may be applied to the bit line BL to precharge the channel region of the memory cell string CS.

[0032] The gate electrode GE of the source select transistor SST, the plurality of memory cells MC, and the drain select transistor DST may form a gate stack together. The gate stack may include a source select line SSL set as the gate electrode of the source select transistor SST, a plurality of word lines WL set as the plurality of gate electrodes of the plurality of memory cells MC, and a drain select line DSL set as the gate electrode of the drain select transistor DST.

[0033] The plurality of memory cell strings CS may be divided into a plurality of cell string groups. Figure 2 1 and are named CS1 and CS2. Each of the cell string groups may include at least two memory cell strings divided from the same cell plug CPL. (See Figure 3A , Figure 3B , Figure 3C or Figure 3D . ) According to an embodiment, each of the cell string groups may include a first memory cell string CS1 and a second memory cell string CS2.

[0034] Both the first memory cell string CS1 and the second memory cell string CS2 may be coupled to a common source region CSR. The first memory cell string CS1 and the second memory cell string CS2 may be individually controlled by gate electrodes GE electrically and physically separated from each other or by bit lines BL also electrically and physically separated from each other. According to an embodiment, the first memory cell string CS1 and the second memory cell string CS2 may be coupled to the same gate electrode GE and may be coupled to first and second bit lines BL1 and BL2, respectively.

[0035] Figure 3A , Figure 3B , Figure 3C and Figure 3D 2 is a vertical cross-sectional view showing a first structure ST1 and a second structure ST2 of a semiconductor memory device according to an embodiment of the present disclosure.

[0036] Reference FIG. 3A to FIG. 3D , the first structure ST1 may include the above reference Figure 1A and Figure 1B The cell array structure CAS and the bit line BL described above may include a gate stack 60 and a cell plug CPL. The gate stack 60 may be disposed between the doped semiconductor structure DPS and the bit line BL. The cell plug CPL may penetrate the gate stack 60.

[0037] The gate stack 60 may include a plurality of interlayer insulating layers 61 and a plurality of conductive layers 63 alternately stacked with each other in a direction orthogonal to the bit line BL, and the doped semiconductor structure DPS "faces" the bit line BL through the plurality of interlayer insulating layers 61 and the plurality of conductive layers 63. The plurality of conductive layers 63 may form Figure 2 Shown are a source select line SSL, a drain select line DSL and a plurality of word lines WL.

[0038] The cell plug CPL may include a channel structure CH and a memory layer ML within the gate stack 60. Some regions of the memory layer ML may be used as Figure 2 The data storage area of ​​the plurality of memory cells MC shown in FIG. Other areas can be used as Figure 2 Shown are a drain select transistor DST and a source select transistor SST.

[0039] As mentioned above Figure 2 As described, the cell plug CPL may be divided into two or more separate memory cell strings CS. According to an embodiment, the channel structure CH of the cell plug CPL may include a first channel pillar CHP1 and a second channel pillar CHP2 spaced apart from each other. The first channel pillar CHP1 may be used as a channel region of the first memory cell string CS1. The second channel pillar CHP2 may be used as a channel region of the second memory cell string CS2.

[0040] The channel structure CH may further include a capping pattern CAP1 or CAP2 serving as a junction. The capping pattern CAP1 or CAP2 may form an end portion of the channel structure CH toward the bit line BL. According to an embodiment, the channel structure CH may include a first capping pattern CAP1 and a second capping pattern CAP2 spaced apart from each other. The first capping pattern CAP1 may contact the first channel pillar CHP1, and the second capping pattern CAP2 may contact the second channel pillar CHP2. Each of the first capping pattern CAP1 and the second capping pattern CAP2 may include a doped semiconductor layer including at least one of a p-type impurity and an n-type impurity. According to an embodiment, each of the first capping pattern CAP1 and the second capping pattern CAP2 may include an n-type doped semiconductor layer including an n-type impurity as a majority carrier.

[0041] The first structure ST1 may further include a first insulating structure 69 covering the gate stack 60. The first insulating structure 69 may include a plurality of insulating layers. The bit line BL may be buried in the first insulating structure 69. The bit line BL may be coupled to the channel structure CH of the cell plug CPL. According to an embodiment, the bit line BL may be coupled to the channel structure CH through a bit line contact 67A in the first insulating structure 69.

[0042] FIG. 3A to FIG. 3D is a vertical cross-sectional view taken along a first bit line BL1 coupled to a first channel pillar CHP1 of a first memory cell string CS1. FIG. 3A to FIG. 3D Although not shown, similar to the first bit line BL1, the semiconductor memory device may further include a second bit line BL2 coupled to the second channel pillar CHP2 of the second memory cell string CS2.

[0043] Each of the first channel pillar CHP1 and the second channel pillar CHP2 may include a source side end facing a direction opposite to the bit line BL. The source side end of the first channel pillar CHP1 and the source side end of the second channel pillar CHP2 may be connected to each other through a connection pattern CNP near the doped semiconductor structure DPS. The insulating pillar IP may cover the connection pattern CNP. The first channel pillar CHP1 and the second channel pillar CHP2 may be spaced apart from each other, and the insulating pillar IP is located between the first channel pillar CHP1 and the second channel pillar CHP2. The first channel pillar CHP1, the second channel pillar CHP2 and the connection pattern CNP may include a channel layer together. Each of the first channel pillar CHP1 and the second channel pillar CHP2 may include a portion connected to the doped semiconductor structure DPS.

[0044] Reference Figure 3A, each of the first channel pillar CHP1 and the second channel pillar CHP2 may penetrate the memory layer ML and include an end contacting the doped semiconductor structure DPS. The doped semiconductor structure DPS may include at least one of n-type impurities and p-type impurities. According to an embodiment, an end of each of the first channel pillar CHP1 and the second channel pillar CHP2 may contact a common source region of the doped semiconductor structure DPS including n-type impurities as majority carriers.

[0045] Reference Figure 3B , the doped semiconductor structure DPS may be coupled to a "side" portion of each of the first channel pillar CHP1 and the second channel pillar CHP2. The doped semiconductor structure DPS may include a first semiconductor layer L1 and a second semiconductor layer L2. The second semiconductor layer L2 may be located between the first semiconductor layer L1 and the gate stack 60. The doped semiconductor structure DPS may also include a third semiconductor layer L3 located between the second semiconductor layer L2 and the gate stack 60. In some embodiments, the third semiconductor layer L3 may not be formed.

[0046] Each of the first to third semiconductor layers L1 to L3 may include at least one of an n-type impurity and a p-type impurity. According to an embodiment, each of the first to third semiconductor layers L1 to L3 may include an n-type impurity as a majority carrier. According to another embodiment, the first semiconductor layer L1 may include a p-type impurity as a majority carrier, and each of the second and third semiconductor layers L2 and L3 may include an n-type impurity as a majority carrier.

[0047] The second semiconductor layer L2 may penetrate the side portion of the memory layer ML, thereby contacting the side portion of each of the first channel pillar CHP1 and the second channel pillar CHP2. Therefore, the memory layer ML may be divided into a cell side pattern ML_C and a dummy pattern ML_D. The cell side pattern ML_C may be located between each of the first channel pillar CHP1 and the second channel pillar CHP2 and the gate stack 60. The dummy pattern ML_D may be located between the cell plug CPL and the first semiconductor layer L1.

[0048] Reference Figure 3C , each of the first channel pillar CHP1 and the second channel pillar CHP2 may include a portion extending upward so that the portion protrudes toward and into the doped semiconductor structure DPS more than the memory layer ML. The protruding portion of each of the first channel pillar CHP1 and the second channel pillar CHP2 may contact the doped semiconductor structure DPS. The doped semiconductor structure DPS may include at least one of an n-type impurity and a p-type impurity.

[0049] Reference Figure 3D, the semiconductor layer 50 may be located between the doped semiconductor structure DPS and the gate stack 60. The semiconductor layer 50 may include a semiconductor material such as silicon or germanium. The semiconductor layer 50 may include a single crystal semiconductor material or a polycrystalline semiconductor material. The semiconductor layer 50 may include an undoped semiconductor material or a doped semiconductor material including at least one of an n-type impurity and a p-type impurity.

[0050] The memory layer ML, the first channel pillar CHP1, and the second channel pillar CHP2 may extend into and through the semiconductor layer 50. The first channel pillar CHP1 and the second channel pillar CHP2, instead of the memory layer ML, may extend into and contact the doped semiconductor structure DPS. The doped semiconductor structure DPS may include at least one of n-type impurities and p-type impurities.

[0051] Reference FIG. 3A to FIG. 3D , the second structure ST2 may include a semiconductor substrate 71, a peripheral circuit structure PS, a second insulating structure 79, and a plurality of interconnections 77A.

[0052] The semiconductor substrate 71 may include an active region 71A divided by an isolation layer (not shown). The peripheral circuit structure PS may include one or more transistors. The gate insulating layer 73 and the gate electrode 75 of the transistor may be stacked on the active region 71A of the semiconductor substrate 71. The source / drain junction 71J of the transistor may be formed in the active region 71A at both ends of the gate electrode 75. The plurality of interconnects 77A may include sub-interconnects respectively coupled to the gate electrode 75 and the source / drain junction 71J.

[0053] The semiconductor substrate 71 and the peripheral circuit structure PS may be covered by the second insulating structure 79. A plurality of interconnections 77A may be arranged in the second insulating structure 79.

[0054] Reference Figure 3A and Figure 3B , a process of forming the doped semiconductor structure DPS and a process of forming the first structure ST1 may be performed on the second structure ST2 .

[0055] Reference Figure 3C and Figure 3D, the process of forming the first structure ST1 and the process of forming the second structure ST2 may be performed separately. The first structure ST1 may also include a first contact 67B and a first conductive bonding pad BP1 located in the first insulating structure 69. The second structure ST2 may also include a second contact 77B and a second conductive bonding pad BP2 located in the second insulating structure 79. The first conductive bonding pad BP1 of the first structure ST1 and the second conductive bonding pad BP2 of the second structure ST2 may be coupled to each other through a bonding process. The doped semiconductor structure DPS may be provided after the bonding process.

[0056] The first conductive bonding pad BP1 may be electrically coupled to any one of the bit line BL and the conductive layer 63 through the first contact 67B. The second conductive bonding pad BP2 may be electrically coupled to any one of the elements forming the peripheral circuit structure PS through the second contact 77B. Figure 3C and Figure 3D As shown, the first contact 67B, the first conductive bonding pad BP1, the second conductive bonding pad BP2 and the second contact 77B may be used to electrically connect the bit line BL and the structure as shown in FIG. Figure 1A or Figure 1B The peripheral circuit structure shown is the transistor of the page buffer PS.

[0057] Figure 4 , Figure 5A , Figure 5B , Fig. 6A and Figure 6B Together, embodiments of a semiconductor memory device are shown.

[0058] Figure 4 is a perspective view of a semiconductor memory device according to an embodiment of the present disclosure.

[0059] Reference Figure 4 , a hole 115 may penetrate the gate stack 110 . A cell plug CPL may be formed in the hole 115 .

[0060] The gate stack 110 may include a plurality of conductive layers 113A, 113B, and 113C spaced apart from each other and stacked on each other in the first direction DR1. The gate stack 110 may also include a plurality of interlayer insulating layers 111A, 111B, and 111C positioned alternately with the plurality of conductive layers 113A, 113B, and 113C in the first direction DR1. Each of the plurality of conductive layers 113A, 113B, and 113C and the plurality of interlayer insulating layers 111A, 111B, and 111C may extend in the form of a plate. Figure 4In the illustrated embodiment, each of the conductive layers 113A, 113B, and 113C and each of the interlayer insulating layers 111A, 111B, and 111C may be located in different XY planes. The first direction DR1 may be parallel to a Z axis that is orthogonal to the X axis and the Y axis that together define the XY plane.

[0061] Each of the conductive layers 113A, 113B, and 113C can be used as Figure 2 One of the multiple word lines WL shown. Each of the multiple conductive layers 113A, 113B and 113C may include at least one of a doped semiconductor layer and a metal layer. The doped semiconductor layer may include a doped silicon layer. The metal layer may include tungsten, copper, molybdenum, etc. Each of the multiple conductive layers 113A, 113B and 113C may also include a conductive metal nitride layer, such as titanium nitride, tantalum nitride, etc. Each of the multiple interlayer insulating layers 111A, 111B and 111C may include a silicon oxide layer.

[0062] The hole 115 may extend in the first direction DR1 to penetrate the plurality of conductive layers 113A, 113B, and 113C and penetrate the plurality of interlayer insulating layers 111A, 111B, and 111C. The hole 115 may have an elliptical horizontal cross-sectional shape so that it has different widths in the second direction DR2 and the third direction DR3. Therefore, the elliptical hole 115 may have a major axis in the second direction DR2 and a minor axis in the third direction DR3. The second direction DR2 may be an X-axis direction and the third direction DR3 may be a Y-axis direction.

[0063] The cell plug CPL may include a memory layer 120, a channel structure 131, and an insulating column 135. Each of the cell plug CPL and the insulating column 135 may have an elliptical horizontal cross section. The channel structure 131 may include a first channel column 131A and a second channel column 131B. The insulating column 135 may be located between the first channel column 131A and the second channel column 131B. The first channel column 131A and the second channel column 131B may be spaced apart from each other in the second direction DR2 on the XY plane by the elliptical insulating column 135. Each of the first channel column 131A and the second channel column 131B may have a crescent-shaped horizontal cross section. The memory layer 120 may include a first memory portion 120A between the first channel column 131A and the gate stack 110 and a second memory portion 120B between the second channel column 131B and the gate stack 110. The memory layer 120 may also include a connecting portion 120C.

[0064] The connection portion 120C may couple the first memory portion 120A and the second memory portion 120B to each other and be located between the insulating pillar 135 and the gate stack 110. Figure 4 Not shown, but the connection portion 120C of the memory layer 120 may be removed. The insulating pillar 135 may extend between the first memory portion 120A and the second memory portion 120B of the memory layer 120 and may contact the gate stack 110 .

[0065] The first channel pillar 131A and the second channel pillar 131B may each serve as a channel region of a memory cell string corresponding thereto.The first channel pillar 131A and the second channel pillar 131B may each be made of a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof.

[0066] The insulating pillar 135 may include an insulating material such as silicon oxide.

[0067] Figure 5A and Figure 5B is a vertical cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure. Figure 5A It is along Figure 4 A vertical cross-sectional view of the semiconductor memory device taken along line II'. Figure 5B It is shown along Figure 4 A cross-sectional view of the semiconductor memory device taken along line II-II'.

[0068] Reference Figure 5A and Figure 5B , the plurality of interlayer insulating layers 111A, 111B, and 111C and the plurality of conductive layers 113A, 113B, and 113C of the gate stack 110 may be divided into sub-stacks, three of which are shown in the drawings as being vertically stacked on top of each other in the first direction DR1. Thus, by aligning and connecting the shorter openings or holes that penetrate each of the sub-stacks, an elongated hole 115 may be made.

[0069] According to an embodiment, the plurality of interlayer insulating layers 111A, 111B, and 111C and the plurality of conductive layers 113A, 113B, and 113C may be divided into a first sub-stack 110A, a second sub-stack 110B, and a third sub-stack 110C stacked on top of each other in the first direction DR1. The plurality of interlayer insulating layers 111A, 111B, and 111C may include a first interlayer insulating layer 111A of the first sub-stack 110A, a second interlayer insulating layer 111B of the second sub-stack 110B, and a third interlayer insulating layer 111C of the third sub-stack 110C. The plurality of conductive layers 113A, 113B, and 113C may include a first conductive layer 113A of the first sub-stack 110A, a second conductive layer 113B of the second sub-stack 110B, and a third conductive layer 113C of the third sub-stack 110C.

[0070] The cell plug CPL and the hole 115 may extend in the first direction DR1 to penetrate the first sub-stack 110A to the third sub-stack 110C. The cell plug CPL may include a first region P1 penetrating the first sub-stack 110A, a second region P2 penetrating the second sub-stack 110B, and a third region P3 penetrating the third sub-stack 110C. The hole 115 may include a first opening 115A penetrating the first sub-stack 110A, a second opening 115B penetrating the second sub-stack 110B, and a third opening 115C penetrating the third sub-stack 110C. The first region P1 of the cell plug CPL may be located in the first opening 115A of the hole 115. The second region P2 of the cell plug CPL may be located in the second opening 115B of the hole 115. The third region P3 of the cell plug CPL may be located in the third opening 115C of the hole 115.

[0071] From the plan view, Figure 4 As can be seen, each of the cell plug CPL and the hole 115 may extend horizontally to a first width in the second direction DR2. The cell plug CPL and the hole 115 may also extend horizontally to a second width in a third direction DR3 that is orthogonal to the first direction DR1 and the second direction DR2. In an embodiment, the first width extension in the second direction DR2 may be greater than the second width extension in the third direction DR3.

[0072] Different channel pillars 131A and 131B of the channel structure 131 may form different memory cell strings. According to an embodiment, the first channel pillar 131A may be used as a channel region that connects a plurality of memory cells of the first memory cell string CS1 in series with each other, and the second channel pillar 131B may be used as a channel region that connects a plurality of memory cells of the second memory cell string CS2 in series with each other.

[0073] Each of the memory portions 120A and 120B may include a blocking insulating layer 121 extending along the sidewall of the hole 115, a data storage layer 123 extending along the inner wall of the blocking insulating layer 121, and a tunnel insulating layer 125 extending along the inner wall of the data storage layer 123. The blocking insulating layer 121 may include an insulating material capable of blocking charges. The tunnel insulating layer 125 may include an insulating material capable of enabling charge tunneling. The blocking insulating layer 121 may include an insulating layer having a dielectric constant greater than that of the tunnel insulating layer 125.

[0074] The data storage layer 123 may include a material capable of storing data changed by using Fowler-Nordheim tunneling. According to an embodiment, the data storage layer 123 may include a charge trapping insulating layer or an insulating layer containing conductive nanodots. The charge trapping insulating layer may include a silicon nitride layer. However, the present invention is not limited thereto. The data storage layer 123 may include a material layer capable of storing information based on another operating principle other than Fowler-Nordheim tunneling. According to an embodiment, the data storage layer 123 may include a phase change material layer, a ferroelectric layer, etc. In this embodiment, the channel structure 131 may be replaced by an electrode structure including columnar electrodes separated from each other.

[0075] The blocking insulating layer 121, the data storage layer 123, and the tunnel insulating layer 125 of the memory layer 120 may form a first memory portion 120A between the first channel pillar 131A and the gate stack 110. The blocking insulating layer 121, the data storage layer 123, and the tunnel insulating layer 125 of the memory layer 120 may form a second memory portion 120B between the second channel pillar 131B and the gate stack 110. Figure 4 , Figure 5A and Figure 5B Each of the first to third conductive layers 113A to 113C may include a first region 113AR1 corresponding to a first side region AR1 of the gate stack 110 , a second region 113AR2 corresponding to a second side region AR2 of the gate stack 110 , and a third region 113AR3 corresponding to a middle region AR3 of the gate stack 110 .

[0076] The first side region AR1 and the first region 113AR1 may extend along the outer surface of the first channel pillar 131A. The second side region AR2 and the second region 113AR2 may extend along the outer surface of the second channel pillar 131B. The middle region AR3 may be located between the first side region AR1 and the second side region AR2, and the third region 113AR3 may be located between the first region 113AR1 and the second region 113AR2.

[0077] The first region 113AR1 may contact the first memory portion 120A of the memory layer 120 and control the operation of the first channel pillar 131A. The second region 113AR2 may contact the second memory portion 120B of the memory layer 120 and control the operation of the second channel pillar 131B. The third region 113AR3 may couple the first region 113AR1 and the second region 113AR2 and extend along a portion of the sidewall of the hole 115 opened by the channel structure 131. The third region 113AR3 may surround the insulating pillar 135 without interposing the channel structure 131. At least one of the blocking insulating layer 121, the data storage layer 123, and the tunnel insulating layer 125 of the memory layer 120 may extend between the insulating pillar 135 and the third region 113AR3 of each of the first to third conductive layers 113A to 113C.

[0078] The first to third regions 113AR1 to 113AR3 of each of the first to third conductive layers 113A to 113C may extend around the hole 115. The first memory cell of the first memory cell string CS1 may be formed between the first channel pillar 131A and the first region 113AR1 of each of the first to third conductive layers 113A to 113C. The second memory cell of the second memory cell string CS2 may be formed between the second channel pillar 131B and the second region 113AR2 of each of the first to third conductive layers 113A to 113C.

[0079] A curved portion defining an undercut region UC1 or UC2 may be formed on the sidewall of the hole 115. The undercut region UC1 or UC2 may include a first portion A11 or A21 in the second direction DR2 and a second portion A12 or A22 in the third direction DR3. The undercut region UC1 or UC2 may be located at a level where a boundary between sub-stacks is located, or at a level where the openings are connected. According to an embodiment, the first undercut region UC1 may be located at a first level LV1 where a boundary between the first sub-stack 110A and the second sub-stack 110B is located, and the second undercut region UC2 may be located at a second level LV2 where a boundary between the second sub-stack 110B and the third sub-stack 110C is located.

[0080] The channel structure 131 may extend in the first direction DR1 to cover the first portion A11 or A21 of the undercut region UC1 or UC2, so that a plurality of memory cells stacked in the first direction DR1 may be connected in series with each other. In other words, each of the first channel pillar 131A and the second channel pillar 131B may extend from the first region P1 to the third region P3 of the cell plug CPL while covering the first portion A11 or A21 of the undercut region UC1 or UC2, so that a plurality of memory cells of the memory cell string CS1 or CS2 corresponding thereto may be connected in series with each other.

[0081] The second portion A12 or A22 of the undercut region UC1 or UC2 may be opened by the channel structure 131. As a result, interference between memory cell strings that are individually controlled in the cell plug CPL may be reduced. According to an embodiment, the first channel pillar 131A and the second channel pillar 131B may open the second portion A12 or A22 of the undercut region UC1 or UC2 to reduce interference between the first memory cell string CS1 and the second memory cell string CS2.

[0082] The second portion A12 or A22 of the undercut region UC1 or UC2 may have a width controlled within a range of 20 nm or less. Therefore, the phenomenon that the thickness of the channel layer of the channel structure 131 formed on the sidewall of the hole 115 to form the cell plug CPL is locally excessively increased in the undercut region UC1 or UC2 may be improved. Therefore, when the channel layer is etched to form the channel structure 131 of the cell plug CPL, the second portion A12 or A22 of the undercut region UC1 or UC2 may be opened without excessively etching the channel layer. As a result, the thickness loss of each of the first channel pillar 131A and the second channel pillar 131B of the channel structure 131 in the second direction DR2 may be reduced.

[0083] The undercut region UC1 or UC2 may be defined by the inner diameter difference between the openings of the hole 115. According to an embodiment, the top of the first opening 115A may be connected to the bottom of the second opening 115B, and the inner diameter of the top of the first opening 115A may be greater than the inner diameter of the bottom of the second opening 115B. Similarly, the top of the second opening 115B may be connected to the bottom of the third opening 115C, and the inner diameter of the top of the second opening 115B may be greater than the inner diameter of the bottom of the third opening 115C. The above-mentioned inner diameter difference between the first opening 115A and the second opening 115B may cause the second sub-stack 110B to protrude toward the center of the hole 115 to cover a portion of the first opening 115A. As a result, the first undercut region UC1 may be defined. Similarly, the above-mentioned inner diameter difference between the second opening 115B and the third opening 115C may cause the third sub-stack 110C to protrude toward the center of the hole 115 to cover a portion of the second opening 115B. As a result, the second undercut region UC2 may be defined.

[0084] The first to third regions P1 to P3 of the cell plug CPL may have the same structure as the first to third openings 115A to 115C of the hole 115 .

[0085] Fig. 6A and Figure 6B is a diagram showing a portion of a semiconductor memory device according to an embodiment of the present disclosure. Fig. 6A and Figure 6B It is shown as Figure 5A and Figure 5B A plan view of the outline of the cell plug CPL is shown. Fig. 6A It is shown as Figure 5A and Figure 5B 1 and 2 are plan views of the first and second regions P1 and P2 of the cell plug CPL at a first height LV1. Figure 6B It is shown as Figure 5A and Figure 5B 1 and 2 are plan views of the second region P2 and the third region P3 of the cell plug CPL at the second height LV2.

[0086] Reference Figure 5A and Figure 5B as well as Fig. 6A and Figure 6B, an upper surface P1_T of a top end of a first region P1 of the cell plug CPL may be located at a first height LV1. Similarly, a lower surface P2_B of a bottom end of a second region P2 of the cell plug CPL may be located at the same first height LV1 and coupled to the upper surface P1_T of a top end of the first region P1. An upper surface P2_T of a top end of the second region P2 of the cell plug CPL may be located at a second height LV2. A lower surface P3_B of a bottom end of a third region P3 of the cell plug CPL may be located at the same second height LV2 and coupled to the upper surface P2_T of a top end of the second region P2. Each of the surfaces P1_T, P2_B, P2_T, and P3_B may have an elliptical horizontal cross-section.

[0087] In the cell plug CPL, an area of ​​an upper surface P1_T of the first region P1 may be greater than an area of ​​a lower surface P2_B of the second region P2. The upper surface P1_T of the first region P1 may protrude toward side portions (eg, DR2 and DR3) within a range R1 of 20 nm or less compared to the lower surface P2_B of the second region P2.

[0088] In the cell plug CPL, the area of ​​the upper surface P2_T of the second region P2 may be greater than that of the lower surface P3_B of the third region P3. The upper surface P2_T of the second region P2 may protrude more toward the side portions (eg, DR2 and DR3) than the lower surface P3_B of the third region P3 within a range R2 of 20 nm or less.

[0089] In order to control the range R1 or R2 of the cell plug CPL protruding to the side portion and the width of the undercut region (A11 or A21) to 20 nm or less, the sidewall slope θ2 of the second region P2 of the cell plug CPL may be set to be closer to 90° than each of the sidewall slope θ1 of the first region P1 and the sidewall slope θ3 of the third region P3. In other words, the sidewall slope of the second region P2 may be steeper than the sidewall slope of each of the first region P1 and the third region P3. The length of the second region P2 of the cell plug CPL in the first direction DR1 may be smaller than the length of each of the first region P1 and the third region P3 of the cell plug CPL in the first direction DR1.

[0090] The second sub-stack 110B surrounding the shorter second region P2 may have a height smaller than the height of each of the first sub-stack 110A surrounding the longer first region P1 and the third sub-stack 110C surrounding the longer third region P3 in the first direction DR1. According to an embodiment, the first sub-stack 110A may include a plurality of first interlayer insulating layers 111A and a plurality of first conductive layers 113A alternately stacked with each other in the first direction DR1. The second sub-stack 110B may include a second interlayer insulating layer 111B and a second conductive layer 113B stacked on top of each other. The second interlayer insulating layer 111B and the second conductive layer 113B may be less than the plurality of first interlayer insulating layers 111A and the plurality of conductive layers 113A. The third sub-stack 110C may include a plurality of third interlayer insulating layers 111C and a plurality of third conductive layers 113C stacked on top of each other. The third interlayer insulating layer 111C and the third conductive layer may be more than the second interlayer insulating layer 111B and the second conductive layer 113B.

[0091] like Figure 5A and Figure 5B As shown, the second interlayer insulating layer 111B of the second sub-stack 110B may be adjacent to the uppermost first conductive layer among the plurality of first conductive layers 113A in the first direction DR1, and the second conductive layer 113B of the second sub-stack 110B may be adjacent to the lowermost third interlayer insulating layer among the plurality of third interlayer insulating layers 111C in the first direction DR1. However, the present disclosure is not limited thereto. The stacked layers of each of the first to third sub-stacks 110A to 110C may be designed in various ways.

[0092] Fig. 7A , Figure 7B and Figure 7C is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0093] Fig. 7A , Figure 7B and Figure 7C is a vertical cross-sectional view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure. 7A to 7C It is along Figure 4 The vertical cross-sectional view of the semiconductor memory device taken along the line II' shown in FIG. Figure 5A and Figure 5B The description of some parts of the implementation method is the same as that of some parts.

[0094] Reference Fig. 7A ,and Figure 5A and Figure 5BSimilarly, the first sub-stack 110A may include a plurality of first interlayer insulating layers 111A and a plurality of first conductive layers 113A. The second sub-stack 110B may include a second interlayer insulating layer 111B and a second conductive layer 113B. The third sub-stack 110C may include a plurality of third interlayer insulating layers 111C and a plurality of third conductive layers 113C.

[0095] according to Fig. 7A In the illustrated embodiment, the second conductive layer 113B of the second sub-stack 110B may be vertically adjacent to but above the uppermost interlayer insulating layer of the first interlayer insulating layers 111A in the first direction DR1. The second interlayer insulating layer 111B of the second sub-stack 110B may be vertically adjacent to but below the lowermost third conductive layer of the plurality of third conductive layers 113C in the first direction DR1.

[0096] The first undercut region UC1' may be defined by the second conductive layer 113B protruding more toward the side portion than the uppermost first interlayer insulating layer. The second undercut region UC2' may be defined by the lowermost third conductive layer protruding more toward the side portion than the second interlayer insulating layer 111B.

[0097] Reference Figure 7B and Figure 7C ,and Figure 5A and Figure 5B Similarly, each of the first and third sub-stacks 110A and 110C may include a plurality of interlayer insulating layers 111A or 111C and a plurality of conductive layers 113A or 113C alternately stacked in the first direction DR1. The second sub-stack 110B' or 110B" may include at least one interlayer insulating layer.

[0098] Reference Figure 7B , the second sub-stack 110B' may include a lower interlayer insulating layer 111B1 and an upper interlayer insulating layer 111B2 stacked on top of each other in the first direction DR1. The lower interlayer insulating layer 111B1 may be vertically adjacent to but above the uppermost conductive layer among the conductive layers 113A of the first sub-stack 110A in the first direction DR1. The upper interlayer insulating layer 111B2 may be adjacent to but below the lowermost conductive layer among the conductive layers 113C of the third sub-stack 110C in the first direction DR1.

[0099] The first undercut region UC1" may be defined by the lower interlayer insulating layer 111B1 protruding more toward the side portion than the conductive layer 113A of the first sub-stack 110A. The second undercut region UC2" may be defined by the conductive layer 113C of the third sub-stack 110C protruding more toward the side portion than the upper interlayer insulating layer 111B2.

[0100] Reference Figure 7C , the second sub-stack 110B" may include a single insulating layer or at least two insulating layers. The bottom surface 110B-1 of the second sub-stack 110B" may be vertically adjacent to but above the uppermost conductive layer of the conductive layers 113A of the first sub-stack 110A in the first direction DR1. The top surface 110B-2 of the second sub-stack 110B" may be vertically adjacent to but below the lowermost conductive layer of the conductive layers 113C of the third sub-stack 110C in the first direction DR1. The first undercut region UC11" and the second undercut region UC22" may be located at different heights within the insulating layer of the second sub-stack 110B".

[0101] Fig. 8A and Figure 8B is a perspective view showing steps of a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0102] Fig. 8A and Figure 8B A stack 210 including holes 219 is shown in both. Fig. 8A and Figure 8B 2 is a perspective view showing the stack 210 to facilitate identification of the structure located in the hole 219 .

[0103] Reference Fig. 8A , the stack 210 may be formed on a lower structure (not shown). According to an embodiment, the lower structure may include the Figure 3A According to another embodiment, the lower structure may include the second structure ST2, the first semiconductor layer L1, and a sacrificial layer between the first semiconductor layer L1 and the third semiconductor layer L3. The sacrificial layer may be formed in a subsequent process as follows: Figure 3B According to another embodiment, the lower structure may be a sacrificial substrate including a silicon wafer. All or part of the sacrificial substrate may be replaced by a Figure 3C or Figure 3D The doped semiconductor structure DPS shown is replaced. The remaining sacrificial substrate may correspond to Figure 3D The semiconductor layer 50 is shown.

[0104] According to the above-described various embodiments, a stack 210 may be formed on a lower structure. The stack 210 may include a plurality of first material layers 211A, 211B, and 211C and a plurality of second material layers 213A, 213B, and 213C alternately stacked with each other in a first direction DR1. Each of the plurality of first material layers 211A, 211B, and 211C and the plurality of second material layers 213A, 213B, and 213C may be in the form of a plate extending along a second direction DR2 and a third direction DR3 intersecting each other in a plane.

[0105] The plurality of second material layers 213A, 213B, and 213C may have a material having an etching selectivity relative to the plurality of first material layers 211A, 211B, and 211C. According to an embodiment, the plurality of first material layers 211A, 211B, and 211C may include an insulating material such as a silicon oxide layer and a silicon oxynitride layer, and the plurality of second material layers 213A, 213B, and 213C may include a sacrificial insulating material such as a silicon nitride layer. After forming the cell plug, the sacrificial insulating material may be replaced by a conductive material. The conductive material may include at least one of a doped semiconductor layer and a metal layer. When the conductive material includes a metal layer, the conductive metal nitride layer may be formed as a metal barrier layer. According to another embodiment, the plurality of first material layers 211A, 211B, and 211C may include a sacrificial material such as an undoped silicon layer, and the plurality of second material layers 213A, 213B, and 213C may include a conductive material such as a doped silicon layer. After forming the cell plug, the sacrificial material may be replaced by an insulating material such as a silicon oxide layer or a silicon oxynitride layer.

[0106] However, contrary to the above description, the plurality of first material layers 211A, 211B, and 211C may include an insulating material, and the plurality of second material layers 213A, 213B, and 213C may include a conductive material. According to an embodiment, the plurality of first material layers 211A, 211B, and 211C may include a silicon oxide layer, a silicon oxynitride layer, etc., and the plurality of second material layers 213A, 213B, and 213C may include at least one of a doped semiconductor layer and a metal layer. In addition to the metal layer, the plurality of second material layers 213A, 213B, and 213C may further include a conductive metal nitride layer.

[0107] The stack 210 may include a hole 219. The hole 219 may extend in the first direction DR1 so as to extend through the plurality of first material layers 211A, 211B, and 211C and the plurality of second material layers 213A, 213B, and 213C. The hole 219 may have an elliptical cross-section. The major axis 219_L of the ellipse may be along the second direction DR2, and the minor axis 219_S of the ellipse may be along the third direction DR3.

[0108] Forming the stack 210 including the hole 219 may include forming a first sub-stack 210A including a first opening 219A, forming a second sub-stack 210B including a second opening 219B on the first sub-stack 210A, and forming a third sub-stack 210C including a third opening 219C on the second sub-stack 210B.

[0109] The first sub-stack 210A may include a first group of first material layers 211A and a first group of second material layers 213A alternately stacked in a first direction DR1 of a plurality of first material layers 211A, 211B, and 211C and a plurality of second material layers 213A, 213B, and 213C. The first opening 219A may have an elliptical cross-section and extend in the first direction DR1 to extend through the first sub-stack 210A. Before forming the second sub-stack 210B, the inside of the first opening 219A may be filled with a first gap-filling layer (not shown).

[0110] The second sub-stack 210B may include a second group of first material layers 211B and a second group of second material layers 213B alternately stacked in a first direction DR1 of a plurality of first material layers 211A, 211B and 211C and a plurality of second material layers 213A, 213B and 213C. The second opening 219B may have an elliptical cross-section and extend in the first direction DR1 to penetrate the second sub-stack 210B. Before forming the third sub-stack 210C, the interior of the second opening 219B may be filled with a second gap filling layer (not shown). The stacking number of the first material layers 211B in the second group and the second material layers 213B in the second group may be less than the stacking number of the first material layers 211A in the first group and the second material layers 213A in the first group. Therefore, when forming the second opening 219B, the sidewall slope of the second opening 219B may be closer to 90° than the sidewall slope of the first opening 219A.

[0111] The third sub-stack 210C may include a third group of first material layers 211C and a third group of second material layers 213C alternately stacked in the first direction DR1 of a plurality of first material layers 211A, 211B, and 211C and a plurality of second material layers 213A, 213B, and 213C. The third opening 219C may have an elliptical cross-section and extend in the first direction DR1 to penetrate the third sub-stack 210C. The stacking number of the first material layers 211C in the third group and the second material layers 213C in the third group may be greater than the stacking number of the first material layers 211B in the second group and the second material layers 213B in the second group. Therefore, the sidewall slope of the third opening 219C may be less close to 90° than the sidewall slope of the second opening 219B.

[0112] After forming the third opening 219C, the first and second gap-filling layers may be removed through the third opening 219C to expose the first and second openings 219A and 219B. The first to third openings 219A to 219C may be coupled to each other to form a hole 219 .

[0113] After forming the hole 219, a memory layer 220 may be formed along the sidewall of the hole 219. The memory layer 220 may include Fig. 9 The blocking insulating layer 221, the data storage layer 223 and the tunnel insulating layer 225 are shown. The blocking insulating layer 221, the data storage layer 223 and the tunnel insulating layer 225 may include Figure 5A and Figure 5B Various materials exemplified in .

[0114] Reference Fig. 8A , a channel layer 231L may be formed in the hole 219. The channel layer 231L may be formed along an inner wall of the memory layer 220. The channel layer 231L may include silicon (Si), germanium (Ge), or a mixture thereof.

[0115] Because the hole 219 has an elliptical shape, the deposition amount of the channel layer 231L may be controlled so that the channel layer 231L may be deposited with different thicknesses in directions along which the major axis 219_L and the minor axis 219_S defined by the hole 219 extend. The channel layer 231L may have a first thickness D1 along the major axis 219_L of the hole 219 and a second thickness D2 along the minor axis 219_S of the hole 219. The deposition amount of the channel layer 231L may be controlled so that the first thickness D1 may be greater than the second thickness D2 (D1>D2).

[0116] Reference Figure 8B , by etching through the open central region 219CR of the hole 219 Fig. 8A As shown in the channel layer 231L, the channel layer 231L may be separated into a first channel pillar 231A and a second channel pillar 231B. The first channel pillar 231A and the second channel pillar 231B may be separated from each other in a second direction DR2 along which the long axis 219_L of the hole 219 extends.

[0117] Wet etching can be used to etch Fig. 8A During the wet etching process, the channel layer 231L may be etched to a thickness less than the first thickness D1. Also, the channel layer 231L may be etched to a thickness equal to or greater than the second thickness D2, as described above with reference to Fig. 8A described.

[0118] The channel layer may be etched to different amounts in the second direction DR2 corresponding to the long axis 219_L of the hole 219 and in the third direction DR3 corresponding to the short axis 219_S of the hole 219. This is because different lateral regions of the channel layer may be exposed by the etchant used for wet etching in the second direction DR2 and the third direction DR3. More specifically, during the wet etching process, the thickness loss of the channel layer in the second direction DR2 may be less than the thickness loss of the channel layer in the third direction DR3.

[0119] As mentioned above Fig. 8A As described above, since the first thickness D1 of the channel layer 231L is greater than the second thickness D2, even in reference Figure 8B During the described etching process, the channel layer 231L is etched to the second thickness D2, and portions of the channel layer 231L having the first thickness D1 may remain as the first channel pillar 231A and the second channel pillar 231B.

[0120] Fig. 9 It is shown along Figure 8B A vertical cross-sectional view of a portion of the internal structure of the hole 219 taken along the minor axis 219_S of the hole 219 is shown.

[0121] Reference Fig. 9 The hole 219 extending through the stack 210 may include a second opening 219B coupling the first opening 219A and the third opening 219C to each other. The second opening 219B may have a sidewall slope closer to 90° than that of each of the first opening 219A and the third opening 219C.

[0122] Fig.10 is a vertical cross-sectional view showing a semiconductor memory device according to a comparative example.

[0123] Fig.10 The hole 219' shown may have the same Fig. 8A and Figure 8B The elliptical cross-section of the hole 219 described is similar to the elliptical cross-section. Fig.10 is a cross-sectional view showing the internal structure of the hole 219 ′ taken along the minor axis of the hole 219 ′.

[0124] Reference Fig.10 The hole 219' may include a lower opening 219A' and an upper opening 219C'. The lower opening 219A' and the upper opening 219C' may be adjacent to each other in the first direction DR1 and may be directly connected to each other. The sidewall slope of each of the lower opening 219A' and the upper opening 219C' may be greater than Fig. 9 The second opening 219B shown is less close to 90°. For example, the lower opening 219A' can be Fig. 9The first opening 219A shown has the same sidewall slope, and the upper opening 219C' can be Fig. 9 The third openings 219C are shown to have the same sidewall slope.

[0125] Reference Fig. 9 and Fig.10 When the first opening 219A and the third opening 219C are connected to each other while interposing the second opening 219B whose sidewall slope is controlled to be relatively close to 90°, the width difference at the connection point between the openings can be reduced compared to when the first opening 219A and the third opening 219C are directly connected to each other without interposing the second opening 219B. More specifically, it is easier to control the width W1 or W2 of the undercut area A1 or A2 at the connection point between the first opening 219A to the third opening 219C to 20 nm or less than controlling the width W3 of the undercut area A3 at the connection point between the lower opening 219A' and the upper opening 219C'.

[0126] When the width W1 or W2 of the undercut region A1 or A2 is controlled to be 20 nm or less, the thickness of the channel layer 231L can be prevented from increasing during deposition. Fig. 8A The channel layer 231L shown in FIG. 1 is partially excessively enlarged in the undercut region A1 or A2. Figure 8B As described, when the channel layer is etched, a portion of the channel layer overlapping the short axis 219_S of the hole 219 may be stably removed.

[0127] When the width W3 of the undercut region A3 increases to a range exceeding 20 nm, even if a portion of the channel layer is etched to expose the memory layer 220, another portion of the channel layer may remain in the undercut region A3 at a region overlapping the short axis of the hole 219'. This may be defined as a residual channel layer 231R. The residual channel layer 231R may cause interference between the first channel pillar and the second channel pillar.

[0128] According to the embodiments of the present disclosure, it is easier to control the width W1 or W2 of the undercut region A1 or A2 to 20 nm or less. Figure 8B As shown, the first channel pillar 231A and the second channel pillar 231B may be stably separated from each other in the hole 219 , thereby reducing the generation of the residual channel layer 231R.

[0129] In the formation Figure 8B After the first and second channel pillars 231A and 231B are shown, a subsequent process of filling the central region 219CR of the hole 219 with an insulating pillar may be performed.

[0130] Based on Figure 5A and Figure 5BThe structures corresponding to the undercut regions UC1 and UC2 shown in FIG. Fig. 8A , Figure 8B and Fig. 9 The first to third sub-stacks 210A to 210C or stacks 210 and first to third openings 219A to 219C are shown. However, the embodiments of the present disclosure are not limited thereto. According to another embodiment, Fig. 8A and Figure 8B The stacking quantity and type of the material layers of the first to third sub-stacks 210A to 210C shown may be based on Fig. 7A The undercut areas UC1' and UC2' shown, Figure 7B The undercut areas UC1" and UC2" shown or Figure 7C The undercut areas UC11" and UC22" shown vary.

[0131] Fig.11 is a block diagram illustrating an electronic system 1000 including a semiconductor memory device according to an embodiment of the present disclosure.

[0132] Reference Fig.11 The electronic system 1000 may be a computing system, a medical device, a communication device, a wearable device, a memory system, etc. The electronic system 1000 may include a host 1100 and a storage device 1200 .

[0133] The host 1100 may store data in the storage device 1200, or may read the stored data from the storage device 1200 based on an interface. The interface may include at least one of a double data rate (DDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, a peripheral component interconnect (PCI) interface, a PCI-Express (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial ATA interface, a parallel ATA interface, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics interface (IDE), a firewire interface, a universal flash memory (UFS) interface, and a non-volatile memory express (NVMe) interface.

[0134] The storage device 1200 may include a memory controller 1210 and a semiconductor memory device 1220. According to an embodiment, the storage device 1200 may be a storage medium such as a solid state drive (SSD), a universal serial bus (USB) memory, or the like.

[0135] The memory controller 1210 may store data in the semiconductor memory device 1220 in response to the control of the host 1100 , or may read data stored in the semiconductor memory device 1220 .

[0136] The semiconductor memory device 1220 may include a single memory chip or a plurality of memory chips. The semiconductor memory device 1220 may store data or output stored data in response to the control of the memory controller 1210.

[0137] The semiconductor memory device 1220 may be a nonvolatile memory device. The semiconductor memory device 1220 may include the semiconductor memory device described above. Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B and Figure 7C The gate stack and the cell plug described. According to an embodiment, the semiconductor memory device 1220 may include a channel structure extending in a first direction along a hole that penetrates the gate stack. The channel structure may include a first channel column and a second channel column spaced apart from each other in a second direction that intersects the longitudinal direction of the hole. A portion of the sidewall of the hole at a position corresponding to between the first channel column and the second channel column may be opened by the channel structure.

[0138] According to an embodiment of the present disclosure, defects occurring during a process of separating channel pillars from each other in a hole may be reduced to improve operational reliability of a semiconductor memory device.

[0139] CROSS-REFERENCE TO RELATED APPLICATIONS

[0140] This application claims the priority of Korean Patent Application No. 10-2023-0075512 filed in the Korean Intellectual Property Office on June 13, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: a gate stack, the gate stack comprising a first sub-stack, a second sub-stack, and a third sub-stack, the first to third sub-stacks being stacked on top of each other in a first direction; as well as a cell plug extending in the first direction and penetrating the first sub-stack, the second sub-stack, and the third sub-stack, The unit plug includes a first region penetrating the first sub-stack, a second region penetrating the second sub-stack, and a third region penetrating the third sub-stack, each of the first region, the second region, and the third region has a top end and a bottom end, each of the top end and the bottom end has a corresponding area, wherein the area of ​​the top end of the first region of the unit plug is greater than the area of ​​the bottom end of the second region of the unit plug, and The top end of the second region of the cell plug has an area larger than an area of ​​the bottom end of the third region.

2. The semiconductor memory device according to claim 1, wherein A length of the second region of the cell plug in the first direction is smaller than a length of each of the first region and the third region of the cell plug in the first direction.

3. The semiconductor memory device according to claim 1, wherein: A sidewall slope of the second region of the cell plug is steeper than a sidewall slope of each of the first region and the third region of the cell plug.

4. The semiconductor memory device according to claim 1, wherein: The first sub-stack includes a plurality of first conductive layers and a plurality of first interlayer insulating layers alternately stacked with each other in the first direction, wherein the second sub-stack includes a second conductive layer and a second interlayer insulating layer stacked in the first direction, and The third sub-stack includes a plurality of third conductive layers and a plurality of third interlayer insulating layers alternately stacked with each other in the first direction.

5. The semiconductor memory device according to claim 4, wherein: The second interlayer insulating layer of the second sub-stack and an uppermost first conductive layer of the plurality of first conductive layers are adjacent to each other in the first direction, and The second conductive layer of the second sub-stack and the lowermost third interlayer insulating layer of the plurality of third interlayer insulating layers are adjacent to each other in the first direction.

6. The semiconductor memory device according to claim 4, wherein: The second conductive layer of the second sub-stack and an uppermost first interlayer insulating layer of the plurality of first interlayer insulating layers are adjacent to each other in the first direction, and The second interlayer insulating layer of the second sub-stack and the lowermost third conductive layer of the plurality of third conductive layers are adjacent to each other in the first direction.

7. The semiconductor memory device according to claim 1, wherein: Each of the first sub-stack and the third sub-stack includes a plurality of conductive layers and a plurality of interlayer insulating layers alternately stacked with each other in the first direction, and The second sub-stack includes an interlayer insulating layer adjacent to the conductive layer of each of the first sub-stack and the third sub-stack.

8. The semiconductor memory device according to claim 1, wherein: A height of the second sub-stack in the first direction is smaller than a height of each of the first sub-stack and the third sub-stack in the first direction.

9. The semiconductor memory device according to claim 1, wherein: The first region of the cell plug protrudes toward a side portion by 20 nm or less than the second region of the cell plug.

10. The semiconductor memory device according to claim 1, wherein The second region of the cell plug protrudes toward the side portion by 20 nm or less than the third region.

11. The semiconductor memory device according to claim 1, wherein: The cell plug has a first width in a second direction and a second width in a third direction, the second direction and the third direction being orthogonal, and Wherein, the first width is greater than the second width.

12. The semiconductor memory device according to claim 1, wherein: The unit plug comprises: a channel structure including a first channel pillar and a second channel pillar extending from the first region to the third region; and a memory layer between the gate stack and each of the first channel pillar and the second channel pillar, and Wherein, the first channel pillar and the second channel pillar are spaced apart from each other.

13. A semiconductor memory device, comprising: a gate stack comprising a plurality of conductive layers spaced apart in a first direction and stacked on top of each other; a hole extending in the first direction and penetrating the plurality of conductive layers; a channel structure, the channel structure comprising a first channel pillar and a second channel pillar extending in the first direction, the channel structure being located in the hole and spaced apart from each other in a second direction, the second direction being located in a plane parallel to the plurality of conductive layers; as well as a memory layer between the gate stack and each of the first channel pillar and the second channel pillar, wherein a curved portion defining an undercut region is formed on the side wall of the hole, wherein the undercut region comprises a first portion in the second direction and a second portion in a third direction intersecting the second direction in the plane, and The channel structure covers the first portion of the undercut region and opens the second portion of the undercut region.

14. The semiconductor memory device according to claim 13, wherein: The second portion of the undercut region has a width of 20 nm or less.

15. The semiconductor memory device according to claim 13, wherein: The hole extends to a first width in the second direction and to a second width in the third direction, and Wherein, the first width is greater than the second width.

16. The semiconductor memory device according to claim 13, wherein: In the plane, the hole has an elliptical horizontal cross-section with a major axis aligned with the second direction.

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