FSM-based clock switching of asynchronous clocks

Abstract

Aspects of the present disclosure provide an apparatus. In one example, an apparatus (20) includes a clock switching circuit (22) coupled with an oscillator (273) and one or more circuit units (230, 240, 250, 260). The clock switching circuit is configured to receive a set of frequency signals (282, 283, 284) from the oscillator, provide an uplink master clock signal (281) and an enable signal (285, 286) to the one or more circuit units, the enable signal being determined in synchronization with the uplink master clock signal, and receive the set of frequency signals (282, 283, 284) from the oscillator. A clock frequency request is received from the one or more circuit units or clock management circuitry, the uplink master clock signal is provided based on a first signal of the set of frequency signals, and in accordance with the clock frequency request, the uplink master clock signal is transmitted to the one or more circuit units or clock management circuitry. It is determined whether to continue providing the uplink master clock signal based on the first signal or to provide the uplink master clock signal based on a second signal of the set of frequency signals.

Description

Background Art

[0001] A system on chip (SoC) or microcontroller unit (MCU) including a combination of a processor, a memory and other hardware components is an embedded system with a dedicated function. An embedded system can be a part of a computer or an electronic device (such as a chip or an electronic circuit board). An embedded system can include multiple circuit units, and the multiple circuit units can include various intellectual property rights (IPs). Circuit units are also referred to as IPs in this article. For example, designers of systems of application-specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs) logic integrate IPs as building blocks in embedded systems. IPs include multiple circuit elements, and the multiple circuit elements include a clock generator that provides a clock signal for synchronizing signals and operations within and across IPs of an embedded system. Summary of the invention

[0002] In some examples, a device includes a clock switching circuit coupled to an oscillator and one or more circuit units. The clock switching circuit is configured to receive a set of frequency signals from the oscillator, provide an uplink master clock signal and an enable signal to the one or more circuit units, the enable signal being determined in synchronization with the uplink master clock signal, receive a clock frequency request from the one or more circuit units or a clock management circuit, provide the uplink master clock signal based on a first signal in the set of frequency signals, and determine whether to continue to provide the uplink master clock signal based on the first signal or a second signal in the set of frequency signals according to the clock frequency request.

[0003] In some examples, a method includes receiving, by a clock management circuit, a clock frequency request from a circuit unit for a clock signal having a first frequency. The method also includes determining, by the clock management circuit based on the clock frequency request, to provide an uplink master clock signal based on a first clock frequency signal from a set of clock frequency signals, the first clock frequency signal having the first frequency. The method also includes receiving, by the clock management circuit, a second clock frequency request from a second circuit unit for a second clock signal having a second frequency. The method also includes determining, by the clock management circuit based on the second clock frequency request, in response to the second frequency being less than the first frequency, to continue providing the uplink master clock signal based on the first clock frequency signal. The method also includes determining, by the clock management circuit based on the second clock frequency request, in response to the second frequency being greater than the first frequency, to provide the uplink master clock signal based on a second clock frequency signal from the set of clock frequency signals, the second clock frequency signal having the second frequency. The method also includes providing the uplink master clock signal and an enable signal to the circuit unit and the second circuit unit, the enable signal being provided synchronously with the uplink master clock signal.

[0004] In some instances, a device includes a clock switching circuit and a finite state machine (FSM). The FSM is configured to provide a first control signal to the clock switching circuit to perform a state transition, the state transition determining to switch an uplink master clock signal from a first clock frequency signal to a second clock frequency signal or a third clock frequency signal, the first clock frequency signal having a faster clock frequency than the second clock frequency signal, and the third clock frequency signal having a slower clock frequency than the second clock frequency signal. The FSM is also configured to provide a second control signal to the clock switching circuit to provide a second clock frequency enable signal and a third clock frequency enable signal together with the uplink master clock signal, the second clock frequency enable signal and the third clock frequency enable signal being generated synchronously with the uplink master clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of a processing system according to various examples.

[0006] Figure 2 is a block diagram of a SoC or MCU with a clock switching circuit according to various examples.

[0007] Figure 3 is a diagram of signals used for clock switching according to various examples.

[0008] Figure 4 is a diagram of a clock switching circuit according to various examples.

[0009] Figure 5 is a diagram of a clock switching circuit according to various examples.

[0010] Figure 6 is a diagram of signals used for clock switching according to various examples.

[0011] Figure 7 is a diagram of a clock switching circuit according to various examples.

[0012] Figure 8 is a diagram showing a signal relationship between a signal transition and a glitch according to various examples.

[0013] Fig. 9 is a flow chart of a method for clock switching according to various examples.

[0014] Fig.10 is a state diagram suitable for implementation by a state machine according to various examples. DETAILED DESCRIPTION

[0015] Embedded systems such as SoCs and MCUs may include IPs that run at different clock frequencies. The clock frequency may be provided to the IP as a clock signal by different clock generators (also referred to herein as oscillators). Providing different clock frequencies by different oscillators reduces the power consumption of the SoC to meet certain power constraints. The same IP may also perform operations at different clock frequencies. However, there may be problems with exchanging signals across clock boundaries. For example, IPs running at different clock frequencies generated by different oscillators cannot interact in a synchronous manner. A clock switching scheme based on combinational logic for changing the clock frequency for the IP may introduce glitches in the clock signal, such as due to the wrong timing of switching according to the cycle between different clock frequencies. More complex clock switching schemes including synchronizers may also introduce delays due to the IP waiting for a certain period of time before switching the clock frequency (such as when switching from a lower clock frequency to a higher clock frequency, or when switching from a higher clock frequency to a lower clock frequency).

[0016] This specification provides an example of a scheme for switching the clock frequency of a clock signal provided to an IP to avoid signal timing glitches and reduce latency. The scheme includes a circuit, system, and method for performing clock switching between two or more clock frequencies from one or more corresponding oscillators. Therefore, the same output clock signal and one or more clock enable signals for generating and synchronizing an internal clock based on a received clock signal are provided to one or more IPs in the system. For example, by implementing an integrated clock gate (ICG), the IP can be enabled to generate an internal clock based on an output clock signal and a clock enable signal. The clock frequency of the output clock signal is determined by a finite state machine (FSM), which is coupled to a multiplexer to select a clock frequency from available clock frequencies provided by an oscillator. In order to mitigate the presence of glitches in the output clock signal provided to the IP, the clock frequency of the output clock signal provided to the IP based on the control of the FSM may not be the clock frequency requested by the IP, but can be switched to the clock frequency requested by the IP based on the clock enable signal provided by the IP based on the control of the FSM and received in synchronization with the output clock signal.

[0017] Figure 1 1 is a block diagram of a processing system 10 configured according to software, hardware, or both to perform clock switching according to various examples of the specification. The processing system 10 includes hardware components that can be coupled to or part of a chip or embedded system (such as a SoC or MCU in a device), including IPs that run at different clock frequencies. The processing system 10 can also execute computer programs or instructions to perform clock switching. For example, the processing system 10 includes a SoC or MCU (SoC / MCU) 20 having a clock switching circuit 22 that performs clock switching according to various examples of the specification. Figure 1 As shown, the processing system 10 also includes one or more processors 101 and one or more memories 102. The one or more processors 101 are coupled to the SoC / MCU 20 or include the SoC / MCU. In some examples, the processing system 10 may also include one or more transceivers 103 for establishing a connection. These components may be connected via a bus 105 or in any other suitable manner. Figure 1 , an example in which components are connected via bus 105 is shown.

[0018] The processor 101 is configured to read and execute computer-readable instructions. For example, the processor 101 is configured to call and execute instructions in a program stored in the memory 102, including the instruction 106. In some instances, the instruction 106 implements the FSM when it is executed. In response to the processor 101 providing data, the processor 101 drives or controls the transceiver 103 to perform data transmission. In response to the processor 101 receiving data, the processor 101 also drives or controls the transceiver 103 to perform reception. Therefore, the processor 101 can be regarded as a control center for performing transmission or reception of data, and the transceiver 103 is an executor for performing transmission and reception operations.

[0019] In some instances, memory 102 is coupled to processor 101 via bus 105 or input / output interface 107. In other instances, memory 102 is integrated with processor 101. Memory 102 is configured to store a variety of software programs and / or multiple sets of instructions, including instructions 106. Memory 102 may include one or more storage devices. For example, memory 102 includes high-speed random access memory and / or may include non-volatile memory, such as one or more disk storage devices, flash memory or another non-volatile solid-state storage device. Memory 102 may store an operating system, such as a real-time operating system (RTOS), ANDROID, IOS, WINDOWS or LINUX. Memory 102 may further store a network communication program. The network communication program may be used to communicate with one or more accessory devices, one or more user devices or one or more network devices. Memory 102 may further store a user interface program. The user interface program displays the content of the application through a graphical interface and receives data or operations performed by the user on the application through input controls (such as menus, dialog boxes or physical input devices (not shown)). The memory 102 is configured to store instructions 106 for executing various methods and processes provided according to various examples of this specification.

[0020] The transceiver 103 includes a transmitter and a receiver. The transceiver 103 is configured to transmit a signal provided by the processor 101. The transceiver 103 is also configured to receive a signal from another device or apparatus. The processing system 10 may also be provided with a wired network interface or a local area network (LAN) interface to support wired communication. The processing system 10 may also include a communication component for transmitting and receiving wireless communication signals.

[0021] The processing system 10 may further include an input / output interface 107 for implementing communication between the processing system 10 and one or more input / output devices (not shown). Examples of input / output devices include audio input / output devices, keyboard input devices, displays, etc. The input / output devices are configured to perform interaction between the processing system 10 and a user or an external environment. The input / output devices communicate with the processor 101 through a user interface.

[0022] Figure 2 2 is a block diagram of a SoC / MCU 20 with a clock switching circuit 22 according to various examples. The SoC / MCU 20 is configured to operate using a clock signal, which may have one of various different clock frequencies that may vary during operation. For example, the SoC / MCU 20 may be coupled to or part of a processing system 10 (such as a computer or electronic device). The SoC / MCU 20 includes a central processing unit (CPU) 210, which may be one of the IPs of the SoC / MCU 20. The CPU 210 is coupled to other IPs of the SoC / MCU 20 and is configured to control (e.g., through signaling) the operation of the other IPs. The SoC / MCU 20 may also include a power management circuit 220 for providing power and regulating power to the IPs and other components of the SoC / MCU 20. The IPs of the SoC / MCU 20 include a timer 230, an analog-to-digital converter (ADC) 240, a digital-to-analog converter (DAC) 250, and one or more peripheral interfaces 260. Examples of the peripheral interface 260 include a serial peripheral interface (SPI), a universal asynchronous receiver-transmitter (UART), and an inter-integrated circuit (I2C). At least some of the IPs and other components of the SoC / MCU 20 may be coupled to each other. For example, the timer 230 is coupled to the ADC 240, the DAC 250, and the one or more peripheral interfaces 260 and exchanges signals therewith. The ADC 240 and the DAC 250 may also be coupled to the one or more peripheral interfaces 260 and exchange signals therewith.

[0023] The SoC / MCU 20 also includes a clock management circuit 270 that provides a clock signal having a frequency selected from a set of available clock frequencies to the IPs of the SoC / MCU 20. For example, the clock management circuit 270 provides an uplink master clock signal (ULPCLK) 281 to one or more IPs, the one or more IPs including at least one of the timer 230, the ADC 240, the DAC 250, and the one or more peripheral interfaces 260. The ULPCLK 281 may have a selectable frequency, and the clock management circuit 270 includes a clock switching circuit 22 that switches the clock frequency of the ULPCLK 281 according to a request from the IP. The clock switching circuit 22 includes a clock frequency selection circuit 271 that selects the clock frequency of the ULPCLK 281 from a plurality of clock frequencies provided by a corresponding oscillator 273. The clock management circuit 270 also includes a FSM 272 coupled to the clock switching circuit 22. FSM 272 provides a control signal to clock frequency selection circuit 271 to switch the clock frequency of ULPCLK 281 to IP. Figure 2 The connections for providing ULPCLK 281 from the clock management circuit 270 to each of the timer 230, ADC 240, DAC 250, and one or more peripheral interfaces 260 are shown with corresponding arrows. Requests from the IP including the timer 230, ADC 240, DAC 250, and one or more peripheral interfaces 260 may be provided to the clock management circuit 270 via the same connection or other connections (not shown).

[0024] In at least some instances, the clock signal provided to the IP by the clock management circuit 270 has a frequency other than the frequency requested by the corresponding IP receiving the clock signal. For example, the first IP may request a clock signal at a first frequency, and the second IP may request a clock signal at a second frequency less than the first frequency. The clock management circuit 270 may provide a clock signal having a first frequency to both the first IP and the second IP. The clock management circuit 270 may also provide a clock enable signal to the first IP and the second IP. Based on the clock signal and the clock enable signal, the second IP may generate or otherwise generate an internal clock signal at a second frequency. In some embodiments, the second IP generates an internal clock signal through an ICG, which gates the clock signal according to the clock enable signal to provide an internal clock signal. In this way, both the first IP and the second IP may receive the same clock signal, but generate an internal clock signal at the frequency of their respective requests. This may facilitate interoperability between the first IP and the second IP, thereby alleviating at least some challenges that may be caused by the first IP and the second IP including components running at different clock frequencies such as those received asynchronously from different clock sources. For example, because both the first IP and the second IP receive the same clock signal (eg, ULPCLK) from the clock management circuit 270 , challenges in cross-border signaling between the first IP and the second IP may be alleviated and interoperability of the first IP and the second IP may be improved.

[0025] In one example, if Figure 2 As shown, ULPCLK 281 switches between clock signals having three different clock frequencies. The clock signals include a high clock frequency signal (SYSCLK) 282 having a high clock frequency, an intermediate clock frequency signal (MFCLK) 283 having an intermediate clock frequency, and a low clock frequency signal (LFCLK) 284 having a low clock frequency. In some examples, SYSCLK 282 has a clock frequency equal to approximately 20 megahertz (MHz), MFCLK 283 has a clock frequency equal to approximately 2MHz, and LFCLK 284 has a clock frequency equal to approximately 32 kilohertz (kHz). In other examples, instead of an oscillator, a clock divider (not shown) may be used to provide the clock frequency signals. For example, a clock divider may be used to divide SYSCLK 282 to provide MFCLK 283 and LFCLK 284 , but power consumption associated with providing MFCLK 283 and LFCLK 284 may be increased compared to providing MFCLK 283 and LFCLK 284 via dedicated oscillators.

[0026] The frequency signal is provided according to the frequency and power requirements of the processing system 10. The clock frequency selection circuit 271 selects between the input signals SYSCLK 282, MFCLK 283, and LFCLK 284 to be used as the basis of ULPCLK 281 when a request is received from the IP. For example, the clock frequency of ULPCLK 281 may be switched multiple times by the clock frequency selection circuit 271 in the order of multiple clock frequency requests from the IP. When requests for different frequencies are received, the FSM 272 arbitrates between the different frequencies to select one frequency to be used as the basis of ULPCLK 281. For example, in response to requests for clock signals at different frequencies from multiple IPs, the clock frequency selection circuit 271 selects the highest frequency request from the IP through the FSM 272, and provides one of the SYSCLK 282, MFCLK 283, or LFCLK 284 as ULPCLK 281, so that ULPCLK 281 has a frequency that satisfies the highest frequency request. The remaining plurality of IPs requesting a clock signal at a frequency lower than that of the ULPCLK 281 may generate an internal clock signal based on the ULPCLK 281 and the MFCLK enable signal (MFTICK) 285 or the LFCLK enable signal (LFTICK) 286 .

[0027] The clock switching circuit 22 provides MFTICK 285 and LFTICK 286 together with ULPCLK 281 from the clock frequency selection circuit 271 to indicate to the IP when to switch the internal clock frequency of the IP to the clock frequency of ULPCLK 281 . Figure 2 , coupling of ULPCLK 281, MFTICK 285, and LFTICK 286 from clock switching circuit 22 to each of timer 230, ADC 240, DAC 250, and one or more peripheral interfaces 260 (eg, collectively referred to as "IPs," or individually referred to as "an IP") is shown with corresponding arrows.

[0028] The clock switching circuit 22 performs clock switching to mitigate signal timing glitches and reduce latency at the IP. For example, in response to receiving a clock frequency request for the highest clock frequency from the IP, the clock switching circuit 22 may first select SYSCLK 282 at the clock frequency selection circuit 271 to provide as ULPCLK 281. The clock switching circuit 22 may then receive a request for other frequencies from the IP, and in response, may switch to providing ULPCLK 281 based on MFCLK 283 or LFCLK 284. In some instances, the clock switching circuit 22 may receive requests for both the highest clock frequency (e.g., SYSCLK 282) and one of MFCLK 283 or LFCLK 284. In response, the clock switching circuit 22 can provide ULPCLK 281 based on SYSCLK 282, and the IP requesting the clock frequency of MFCLK 283 or LFCLK 284 can internally generate or generate the clock frequency based on ULPCLK 281 (e.g., at the frequency of SYSCLK 282) and MFTICK 285 or LFTICK 286. For example, the receiving IP can gate ULPCLK 281 according to MFTICK 285 or LFTICK 286 to generate an internal MF clock signal or an internal LF clock signal, respectively. In some examples, the gating is performed by an ICG included in the receiving IP.

[0029] At each clock switch, the clock switching circuit 22 also synchronizes the MFTICK 285 and LFTICK 286 with the clock cycle of ULPCLK 281. The clock cycle is a repetitive time period of a signal transition between an asserted high value and a low value, and is determined by the clock frequency of the signal. For example, a higher clock frequency signal has a shorter clock cycle (e.g., time period). The clock switching circuit 22 synchronizes the MFTICK 285 and LFTICK 286 with the clock cycle of ULPCLK 281 by detecting and aligning the rising edges in the clock cycles of ULPCLK 281, MFTICK 285, and LFTICK 286 in a timely manner as described in the example below. In response to the IP receiving a ULPCLK 281 at a frequency other than the frequency requested by the IP, the IP is configured to generate an internal clock signal at the requested frequency according to the received ULPCLK 281 and the synchronized MFTICK 285 or LFTICK 286. Synchronizing the clock cycles of MFTICK 285 and LFTICK 286 with ULPCLK 281 mitigates signal timing glitches at the IP during clock switching. By first providing SYSCLK 282 as ULPCLK 281, the clock cycles of MFTICK 285 and LFTICK 286 can be synchronized faster than switching ULPCLK 281 to MFCLK 283 or LFCLK 284, thereby reducing the delay at the IP during clock switching.

[0030] Figure 3 2 is a diagram of a signal 300 for clock switching according to various examples. The signal 300 can be exchanged in the SoC / MCU 20 to perform clock switching for the IP as the clock switching circuit 22 controlled by the FSM 272. The signal 300 includes a SYSCLK 282 having a first clock period 302 corresponding to a first clock frequency (e.g., about 20 MHz), a LFCLK 284 having a second clock period 304 corresponding to a second clock frequency (e.g., about 32 kHz), and a MFCLK 283 having a third clock period 306 corresponding to a third clock frequency (e.g., about 2 MHz). The SYSCLK 282, the LFCLK 284, and the MFCLK 283 are provided to the clock switching circuit 22 by the corresponding oscillator 273. Figure 3Also shown in FIG. 28 is ULPCLK_MF and ULPCLK_LF. ULPCLK_MF has an average frequency approximately equal to the frequency of MFCLK 283 and represents an internally generated clock as may be generated by an ICG as described herein based on received ULPCLK 281 and MFTICK 285. ULPCLK_LF has an average frequency approximately equal to the frequency of LFCLK 284 and represents an internally generated clock as may be generated by an ICG as described herein based on received ULPCLK 281 and LFTICK 286. Figure 3 As shown, signal 300 is not shown to scale, nor do the exact frequency ratios between the various signals of signal 300 depicted in the waveform for purposes of the present disclosure.

[0031] Signal 300 includes a first request signal (LFCLK request) 308 for requesting LFCLK 284, a second request signal (SYSCLK request) 310 for requesting SYSCLK 282, and a third request signal (MFCLK request) 312 for requesting MFCLK 283. LFCLK request 308, SYSCLK request 310, and MFCLK request 312 may be provided to clock management circuit 270 by the same IP at different times or by different IPs to request clock signals at corresponding clock frequencies. In this regard, in instances with multiple separate IPs, multiple instances of LFCLK request 308, SYSCLK request 310, and MFCLK request 312 may be received. As described above, signal 300 also includes ULPCLK 281, LFTICK 286, and MFTICK 285. The clock frequency selection circuit 271 selects one of SYSCLK 282, LFCLK 284, or MFCLK 283 to be used as ULPCLK 281 according to a control signal provided by FSM 272. FSM 272 provides a control signal according to a state transition of FSM 272, which determines clock switching and controls the selection by the clock frequency selection circuit 271 of ULPCLK 281.

[0032] For example, Figure 3As shown, SYSCLK 282, LFCLK 284, and MFCLK 283 are provided to clock frequency selection circuit 271 by corresponding oscillators 273. In response to a request from IP or clock management circuit 270, LFCLK request 308 may be previously set and maintained to an asserted high value. Therefore, ULPCLK 281 is previously set to the clock frequency of LFCLK 284 having a second clock period 304. In response to a new request for MFCLK 283 or SYSCLK 282 by any IP or clock management circuit 270, clock switching circuit 22 switches ULPCLK 281 to SYSCLK 282 having a first clock period 302. The request for MFCLK 283 or SYSCLK 282 is indicated by setting MFCLK request 312 or SYSCLK request 310 to an asserted high value, respectively. After switching ULPCLK 281 to SYSCLK 282, clock switching circuit 22 synchronizes LFTICK 286 and MFTICK 285 with ULPCLK 281 according to the clock frequency of SYSCLK 282. Synchronizing the signals includes timely aligning the rising edges of different signals in different clock cycles. Figure 3 Specific illustration is shown in FIG. 2 , but the width of the clock cycle of LFTICK 286 and MFTICK 285 can match the width of the clock cycle of LFCLK 284 and MFCLK 283, respectively. If the new request received is for SYSCLK 282, no further action is taken. If the new request received is for MFCLK 283, then after first switching ULPCLK 281 from LFCLK 284 to SYSCLK 282, MFCLK request 312 is set to an asserted high value or maintained at an asserted high value, and SYSCLK request 310 is set to an asserted low value. In this case, ULPCLK 281 is then switched from SYSCLK 282 to MFCLK 283. MFTICK 285 is also set to an asserted high value. If ULPCLK 281 was previously set to MFCLK 283 and a request for SYSCLK 282 is received, similar steps may also be performed.

[0033] exist Figure 3In another example not shown in FIG, if ULPCLK 281 was previously set to MFCLK 283 and a new request for LFCLK 284 or SYSCLK 282 is received by any IP or clock management circuit 270, the clock switching circuit 22 switches ULPCLK 281 to SYSCLK 282. The request for LFCLK 284 or SYSCLK 282 is indicated by setting LFCLK request 308 or SYSCLK request 310 to an asserted high value, respectively. After switching ULPCLK 281 to SYSCLK 282, the clock switching circuit 22 synchronizes LFTICK 286 and MFTICK 285 with ULPCLK 281 according to the clock frequency of SYSCLK 282. If the new request received is for SYSCLK 282, no further action is taken. If the new request received is for LFCLK 284, then after first switching ULPCLK 281 from MFCLK 283 to SYSCLK 282, LFCLK request 308 is set to a high value asserted or maintained at a high value asserted, and SYSCLK request 310 is set to a low value asserted. In this case, ULPCLK 281 is then switched from SYSCLK 282 to LFCLK 284. LFTICK 286 is also set to a high value asserted, and MFTICK 285 is set to a low value asserted. For example, two IPs can request MFCLK 283 and LFCLK 284 independently. In this case, the highest request clock frequency is provided together with the clock frequency enable signal set for the lowest request clock frequency. Therefore, MFCLK request 312 is maintained at a high value asserted, and ULPCLK 281 is maintained, set to MFCLK 283 and is not switched to LFCLK 284. LFTICK 286 is also provided synchronously with MFCLK 283.

[0034] Switching ULPCLK 281 from LFCLK 284 to SYSCLK 282 and then to MFCLK 283, or from MFCLK 283 to SYSCLK 282 and then to LFCLK 284 allows the clock cycle of MFTICK 285 to be synchronized with the clock cycle of ULPCLK 281 faster than switching ULPCLK 281 directly from LFCLK 284 to MFCLK 283. Synchronizing MFTICK 285 and LFTICK 286 with ULPCLK 281 according to the clock frequency of SYSCLK 282 avoids signal timing glitches at the IP when performing clock switching. Switching ULPCLK 281 to SYSCLK 282 having a faster setup time than MFCLK 283 reduces the delay at the IP in the clock switch. For example, if SYSCLK 282 is equal to about 20 MHz, the setup time of SYSCLK 282 can be less than about 1 microsecond (us). If MFCLK 283 is equal to about 2 MHz, the setup time of MFCLK 283 may be equal to about 10 us. If LFCLK 284 is equal to about 32 kHz, the setup time of LFCLK 284 may be equal to about 1 millisecond (ms). Faster synchronization at the clock switching circuit 22 also reduces the delay at the IP when performing clock switching. For example, if ULPCLK 281 switches directly from LFCLK 284 to MFCLK 283, since the clock cycle of LFCLK 284 is longer than the clock cycle of SYSCLK 282, it may take longer to synchronize the clock cycle of MFTICK 285 with the clock cycle of ULPCLK 281. For example, the clock switching time from LFCLK 284 at about 32 kHz to MFCLK 283 at about 2 MHz or to SYSCLK 282 at about 20 MHz may be less than about 2 us. The state transition of the FSM 272 for controlling the clock frequency selection circuit 271 in the clock switching circuit 22 may take less than approximately 10 to 20 clock cycles of the signal 300 including the synchronization delay.

[0035] Figure 42 is a diagram of a clock frequency selection circuit 271 according to various examples. The clock frequency selection circuit 271 is configured to selectively provide ULPCLK 281 based on SYSCLK 282, LFCLK 284, or MFCLK 283 according to the state transition of FSM 272. The clock frequency selection circuit 271 may include a delay element 410 coupled to a first multiplexer 420 and an ICG 440 coupled to a second multiplexer 450, the first multiplexer is coupled to an AND gate 430, and the second multiplexer is also coupled to the AND gate 430. In some examples, components of the clock frequency selection circuit 271 may be part of the clock switching circuit 22.

[0036] although Figure 4 272 is not shown in the figure, but the clock frequency selection circuit can operate at least partially under the control of the FSM 272. For example, the FSM 272 can be configured at the clock management circuit 270 by software, hardware, or both to provide control signals to the clock frequency selection circuit 271. The control signals determine the state transition for selecting the ULPCLK 281 at the clock frequency selection circuit 271. The control signals include an intermediate clock frequency slow indication signal (slowismfclk) 471 provided to the first multiplexer 420, a clock frequency signal low value signal (frcclklow) 472 provided to the AND gate 430 and the ICG 440, and an uplink master clock frequency slow indication signal (ulpclkisslow) 473 provided to the second multiplexer 450. The values ​​of the control signals provided by the FSM 272 provide state transitions that determine the clock switching at the clock frequency selection circuit 271.

[0037] To mitigate signal timing glitches in clock switching, FSM 272 may control the timing of individual control signals for respective elements of clock frequency selection circuit 271 to provide a time delay between the control signals of at least one clock cycle of SYSCLK 282. For example, if the clock frequency of SYSCLK 282 is approximately 20 MHz, the control signals slowismfclk, frcclklow, and ulpclkisslow are separated by a time delay of approximately 50 nanoseconds (ns).

[0038] The FSM 272 provides slowismfclk 471 to the first multiplexer 420 to cause the first multiplexer 420 to provide a slow clock frequency signal (slowclk) 481 as one of the MFCLK 283 or a delayed representation of the LFCLK (delayed LFCLK) 482 provided by the delay element 410. For example, slowismfclk 471 is set to an asserted high value to cause the first multiplexer 420 to provide slowclk 481 as the MFCLK 283, or to an asserted low value to cause the first multiplexer 420 to provide a delayed LFCLK 482 as the slowclk 481. The delayed LFCLK 482 is provided by the delay element 410, which may be any suitable circuit element that causes a controllable or programmable delay that delays the LFCLK 284 by one or more clock cycles of the SYSCLK 282. For example, if the clock frequency of SYSCLK 282 is about 20 MHz, LFCLK 284 may be delayed by about 140 ns. FSM 272 provides frcclklow 472 to AND gate 430 to provide slowclk_frc 474 based on slowclk 481 and frcclklow 472. In some examples, frcclklow 472 is provided to the inverting input of AND gate 430, or an inverter (not shown) is placed in series between FSM 272 and AND gate 430 to invert the value of frcclklow 472 after being output by FSM 272 and before being received by AND gate 430. In response to slowclk 481 having an asserted value and frcclklow 472 having a deasserted value, AND gate 430 provides slowclk_frc 474 as the asserted value. Similarly, in response to slowclk 481 having a deasserted value or frcclklow 472 having an asserted value, AND gate 430 provides slowclk_frc 474 having a deasserted value. FSM 272 also provides frcclklow 472 to ICG 440 so that ICG 440 gates SYSCLK 282 according to frcclklow 472, thereby providing SYSCLK 282 as a system clock frequency signal low value indication signal (sysclkfrclow) 483 to second multiplexer 450. In some examples, frcclklow 472 is provided to an inverting gate input of ICG 440, or an inverter (not shown) is placed in series between FSM 272 and ICG 440 to invert the value of frcclklow 472 after being output by FSM 272 and before being received by ICG 440.Thus, in response to frcclklow 472 having an asserted low value, ICG 440 provides SYSCLK 282 as sysclkfrclow 483. FSM 272 provides ulpclkisslow 473 to second multiplexer 450 to cause second multiplexer 450 to provide ULPCLK 281 as one of slowclk_frc 474 or sysclkfrclow 483. For example, in response to ulpclkisslow 473 having an asserted high value, ULPCLK 281 is set to the value of slowclk_frc 474. Similarly, in response to ulpclkisslow 473 having a deasserted value, ULPCLK 281 is set to the value of sysclkfrclow 483.

[0039] In one example, as referenced Figure 2 As shown and described, the FSM 272 controls the oscillator 273, which provides the SYSCLK 282, to turn off after switching the ULPCLK 281 from the SYSCLK 282 to the MFCLK 283 or the LFCLK 284 and synchronizing the LFTICK 286 and the MFTICK 285 with the ULPCLK 281, thereby saving power in the SoC / MCU 20. The FSM 272 also controls the oscillator 273 to turn on in response to receiving a clock switching request such as switching the ULPCLK 281 from the LFCLK 284 to the MFCLK 283 or from the MFCLK 283 to the LFCLK 284.

[0040] Figure 5 is a diagram of a clock switching circuit 500 according to various examples. The clock switching circuit 500 (which may be part of the clock switching circuit 22) is configured to provide MFTICK 285 in synchronization with the clock cycle of ULPCLK 281 according to the clock frequency of SYSCLK 282. The clock switching circuit 500 may include a rising edge detection circuit 501 coupled to the FSM 272. The rising edge detection circuit 501 includes a first delay element 502, a second delay element 504 coupled to the first delay element 502, and an AND gate 505 coupled to the second delay element 504. Although Figure 52, but in various examples, any suitable non-zero number of first delay elements 502 may be included in the rising edge detection circuit 501. In some examples, the first delay element 502 and the second delay element 504 may be flip-flops or latches. The clock switching circuit 500 may further include a counter 507 coupled to the FSM 272, an AND gate 508 coupled to the FSM 272 and the counter 507, and an OR gate 509 coupled to the AND gate 508 and the FSM 272.

[0041] The rising edge detection circuit 501 is configured to detect a rising edge of the MFCLK 283 and in response provide a MFCLK rising edge indication signal (MFEDGE) 513. In at least some examples, the MFEDGE 513 can be used to provide the MFTICK 285 in a synchronized manner with the SYSCLK 282. The first delay element 502 and the second delay element 504 of the rising edge detection circuit 501 provide the MFCLK 283 synchronized with the SYSCLK 282 based on detecting the rising edge of the MFCLK 283. The AND gate 505 provides the MFEDGE 513 to the FSM 272 based on the MFCLK 283 as provided by the first delay element 502 and the inverted representation of the MFCLK 283 as provided by the second delay element 504. The FSM 272 provides the MFEDGE 513 and the SYSCLK 282 as data and clock inputs, respectively, to the counter 507. The counter 507 is configured to provide the MFTICK_RAW to the AND gate 508. In some examples, counter 507 is programmable to provide MFTICK_RAW a programmed number of clock cycles of SYSCLK 282 after the time a rising edge is detected in MFEDGE 513. This provides MFTICK_RAW in synchronization with SYSCLK 282. The number of clock cycles of counter 507 may be proportional to the ratio of the clock frequency of SYSCLK 282 to the clock frequency of MFCLK 283. For example, if the clock frequency of SYSCLK 282 is equal to approximately 20 MHz and the clock frequency of MFCLK 283 is equal to approximately 2 MHz, the number of clock cycles may be equal to approximately 10.

[0042] The FSM 272 provides a MFCLK select signal (MF_SEL) 514 and a SYSCLK select signal (SYS_SEL) 515, which can be used to provide the MFTICK 285. The MF_SEL 514 is provided to an AND gate 508. In some examples, the MF_SEL 514 is provided to the inverting input of the AND gate 508, or an inverter (not shown) is placed in series between the FSM 272 and the AND gate 508 to invert the value of the MF_SEL 514 after being output by the FSM 272 and before being received by the AND gate 508. The SYS_SEL 515 and the output of the AND gate 508 are provided to an OR gate 509. In some examples, SYS_SEL 515 is provided to the inverting input of OR gate 509, or an inverter (not shown) is placed in series between FSM 272 and OR gate 509 to invert the value of SYS_SEL 515 after being output by FSM 272 and before being received by OR gate 509. OR gate 509 provides MFTICK 285 based on performing an OR logic operation between SYS_SEL 515 (or an inverted representation of SYS_SEL 515) and the output of AND gate 508.

[0043] Figure 6 is a diagram of a signal 600 for clock switching according to various examples. Signal 600 includes signals that can be exchanged in clock switching circuit 500 to perform clock switching for IP. In at least some examples, Figure 6 The signals shown in 600 include signals that can be used to provide MFTICK 285. Signal 600 includes SYSCLK 282, MFCLK 283, MFEDGE 513, MFTICK counter signal (MFTICKCNT) 601 of counter 507, MFTICK 285, and ULPCLK 281 (in Figure 6 As shown in FIG. 6A , the SYSCLK 282 is switched from MFCLK 283 to SYSCLK 282. As described above, the signal 600 also includes ULPCLK_MF. When describing the signal 600, reference may be made to the components in the various prior art figures of this specification, such as components that may provide or receive the described signals.

[0044] As described above, the rising edge detection circuit 501 provides the MFEDGE 513 after detecting that the MFCLK 283 is asserted high 603. The rising edge detection circuit 501 may also align the MFEDGE 513 to start simultaneously with the SYSCLK falling edge 604. The rising edge detection circuit 501 provides the MFEDGE 513 to the FSM 272, which provides the MFEDGE 513 to the counter 507. In response to detecting that the MFEDGE 513 is asserted high 605, the counter 507 begins to be set to count down for a programmed time period. For example, the countdown time period may be approximately equal to 9 clock cycles of the SYSCLK 282. The 9 clock cycles of the countdown time period are based on the ratio of the SYSCLK 282 and the MFCLK 283 being 20 MHz and 2 MHz, respectively, and taking into account approximately two clock cycles for additional clock switching delays in the clock switching circuit 500. More generally, the countdown can be programmed to start at a value of XY, where X is an integer representation of the ratio of the frequencies between SYSCLK 282 and MFCLK 283, and Y is an estimated number of clock cycles used for synchronization in clock switching circuit 500. In response to the value of MFTICKCNT 601 being asserted (e.g., "1"), MFTICK 285 is asserted. The assertion of MFTICK 285 enables the ICG of the receiving IP to synchronize the ULPCLK 281 and MFTICK 285 (each as Figure 6 In response to the value of MFTICKCNT 601 reaching 0, MFTICK 285 is deasserted. Based on ULPCLK 281 and MFTICK 285, MFCLK_TICK 602 may be provided. For example, the receiving IP may clock ULPCLK 281 according to MFTICK 285 (e.g., through an ICG as described above) to provide MFCLK_TICK 602 having an average frequency approximately equal to the average frequency of MFCLK 283.

[0045] Figure 72 is a diagram of a clock switching circuit 700 according to various examples. The clock switching circuit 700 (which may be part of the clock switching circuit 22) is configured to provide the LFTICK 286 in synchronization with the clock cycle of the ULPCLK 281 according to the clock frequency of the SYSCLK 282. Because the clock frequency of the LFCLK 284 (e.g., about 32 kHz) may be substantially slower than the clock frequency of the SYSCLK 282 (e.g., about 20 MHz), when the ULPCLK 281 is not switched to the SYSCLK 282 in the clock switching circuit 700 within the countdown period of the clock cycle of the SYSCLK 282, the LFTICK 286 may be provided in synchronization with the ULPCLK 281. The clock switching circuit 700 may delay or force the LFTICK 286 to an asserted high or low value based on edge detection of the LFCLK 284 to avoid signal timing glitches that may be caused by signal transitions of the ULPCLK 281 and LFTICK 286 based on the LFCLK 284 .

[0046] In some examples, the clock switching circuit 700 includes each of the following: Figure 7 The clock switching circuit 700 further includes a delay element 702, a delay element 704, an AND gate 706, an AND gate 708, an OR gate 709, an AND gate 720, and a multiplexer 714 coupled as shown. Figure 7 Delay element 722, delay element 724, delay element 726, delay element 728, and inverter 730 are shown coupled. Figure 7 Two delay elements 722 and two delay elements 726 are shown in FIG. 1 , but in various examples, any suitable number of delay elements 722 and delay elements 726 may be selected, provided that the same number of delay elements is selected for both delay elements 722 and delay elements 726 .

[0047] Delay elements 702 and 704 and AND gate 706 are configured to detect the rising edge of delayed LFCLK 482 and provide a LFCLK rising edge indication signal (lfclkrise) 710. Delay element 702 provides a LFCLK asserted high value indication signal (lfclkishigh) 711, and delay element 704 provides an inverted delayed LFCLK asserted high value indication signal (~lfclkishigh_dly) 712 to AND gate 706. Based on lfclkishigh 711 and ~lfclkishigh_dly 712, AND gate 703 provides lfclkrise 710. The first delay element 702 and the second delay element 704 provide lfclkishigh 711 and ~lfclkishigh_dly 712 based on LFCLK 284 and ULPCLK 281.

[0048] If both lfclkishigh 711 and -lfclkishigh_dly 712 have asserted high values, then AND gate 706 provides lfclkrise 710 having an asserted high value. AND gate 708 provides an output LFCLK rising edge indication signal (lfclkout) 715 based on lfclkrise 710 and an LFTICK asserted low value indication signal (frclkticklow) 713, which may be provided by FSM 272. In some examples, frclkticklow 713 is provided to the inverting input of AND gate 708, or an inverter (not shown) is placed in series between FSM 272 and AND gate 708 to invert the value of frclkticklow 713 after being output by FSM 272 and before being received by AND gate 708. Thus, if lfclkrise 710 has an asserted high value and frclkticklow 713 has an asserted low value, then AND gate 708 provides lfclkout 715 having an asserted high value. OR gate 709 provides a first low clock frequency enable signal (ticklf_ulp) 717 synchronized with the clock cycle of ULPCLK 281 based on lfclkout 715 and LFTICK asserted high value indication signal (frclktickhigh) 716, which may be provided by FSM 272. If lfclkout 715 or frclktickhigh 716 has an asserted high value, then OR gate 705 provides ticklf_ulp 717 having an asserted high value. Multiplexer 714 provides LFTICK 286 based on ticklf_ulp 717 and a second low clock frequency enable signal (ticklf_sys) 718 synchronized with the clock cycle of SYSCLK 282. Uplink master clock frequency slow indication signal (ulpclkisslow) 719 is provided to multiplexer 714 as by FSM 272 to cause multiplexer 714 to select ticklf_ulp 717 or ticklf_sys 718 to provide LFTICK 286. For example, in response to ulpclkisslow 719 having an asserted high value, multiplexer 714 provides LFTICK 286 with the value of ticklf_ulp 717.

[0049] AND gate 720 is based on the above reference Figure 5The ticklf_sys 718 is provided by performing an AND logic operation between the described MFTICK_RAW, the signal indicating that ~lfclk_vec is equal to 2'b00, the signal indicating that ~lfclk_vec is equal to 2'b10, and the signal indicating that ~lfclkvecdly_reg is equal to 2'b10. In some instances, the signal indicating that ~lfclk_vec is equal to 2'b00 is determined based on a logic operation of not {(not lfclk_vec[1]) and (not lfclk_vec[0])}. The logic operation can be performed by any suitable software or hardware implementation (not shown). In some instances, the signal indicating that ~lfclk_vec is equal to 2'b10 is determined based on a logic operation of not {lfclk_vec[1] and (not lfclk_vec[0])}. The logic operation can be performed by any suitable software or hardware implementation (not shown). In some examples, the signal indicating that ~lfclkvecdly_reg is equal to 2'b10 is determined based on a logic operation of not {lfclkvecdly_reg[1] and (not lfclkvecdly_reg[0])}. The logic operation can be performed by any suitable software or hardware implementation (not shown). In some examples, delay element 722 is clocked by an inverted representation of SYSCLK 282, such as provided by inverter 730, to provide lfclk_vec[1] based on delayed LFCLK 482. Delay element 724 provides lfclkvecdly_reg[1] based on lfclk_vec[1] and is clocked based on SYSCLK 282. Delay element 726 is clocked by an inverted representation of SYSCLK 282 to provide lfclk_vec[1] based on a further delay (such as Figure 4 The delayed LFCLK 482 provided by the delay element 410 in FIG. 7 provides lfclk_vec[0]. The delay element 728 provides lfclkvecdly_reg[0] based on lfclk_vec[0] and clocking according to the SYSCLK 282.

[0050] Figure 8 800 is a diagram illustrating a signal relationship between a signal transition and a glitch according to various examples. When switching ULPCLK 281 from LFCLK 284 to SYSCLK 282, the signal transition may include a rising edge of LFCLK 284 that may cause a timing glitch at the IP. For example, in response to both the received ULPCLK 281 and LFTICK 286 having asserted high values, a glitch 805 may occur at the IP. Figure 8As shown, ULPCLK 281 may transition to an asserted high value with LFCLK 284 before switching ULPCLK 281 to SYSCLK 282. The rising edge of ULPCLK 281 may occur before LFCLK 284 is synchronized with SYSCLK 282 to provide synchronized LFCLK (synchronized LFCLK / synched LFCLK) 808. For example, synchronized LFCLK 808 may transition to an asserted high value after one or more clock cycles of SYSCLK 282 starting from LFCLK 284. Because ULPCLK 281 transitions with LFCLK 284 instead of synchronized LFCLK 808, FSM 272 forces LFTICK 286 to transition to an asserted low value after ULPCLK 281 transitions to an asserted high value. This may cause the IP to receive both ULPCLK 281 and LFTICK 286 at asserted high values ​​simultaneously, thereby causing a glitch 805 .

[0051] To avoid glitches, the FSM 272 is configured to provide the LFTICK 286 in a manner that does not cause glitches 805 at the IP. The timing of providing the LFTICK 286 is based on predicting the rising edge of the LFCLK 284. The FSM 272 can be configured to provide the LFTICK 286 according to four cases of the signal relationship 800 based on the signal values ​​of the LFCLK 284 and the delayed LFCLK 482. The delayed LFCLK 482 can be delayed by more than about two clock cycles of the SYSCLK 282, such as about 140ns by the delay element 410, to predict the transition time of the synchronized LFCLK 808.

[0052] The four conditions monitored by the FSM 272 and logic (e.g., AND gate 720) of the clock switching circuit 700 include a first condition 810 detected when both the LFCLK 284 and the delayed LFCLK 482 are at asserted low values ​​811 and 812, respectively. In this case, no current transitions are predicted in the synchronized LFCLK 808, and the LFTICK 286 can be provided to the IP by the clock frequency selection circuit 271 along with the ULPCLK 281 without causing glitches. The second condition 820 is when the asserted low value 821 of the LFCLK 284 is detected along with the asserted high value 822 of the delayed LFCLK 482. In this case, there is no current rising edge in the LFCLK 284 to cause a glitch, and the LFTICK 286 can also be provided to the IP by the clock frequency selection circuit 271 along with the ULPCLK 281.

[0053] In the third case 830, when a rising edge or asserted high value 831 of LFCLK 284 is detected with an asserted low value 832 of delayed LFCLK 482, an upcoming transition or rising edge for synchronized LFCLK 808 is predicted. In this case, a glitch 805 may occur when LFTICK 286 is provided to the IP along with ULPCLK 281. To avoid the glitch, FSM 272 does not provide LFTICK 286 to the IP at this time. For example, FSM 272 is configured to delay providing LFTICK 286 to the IP within at least one or two clock cycles of SYSCLK 282. Delaying the provision of LFTICK 286 can avoid receiving both ULPCLK 281 and LFTICK 286 at the asserted high value at the IP at the same time. In other examples, when the third case 830 occurs, the FSM 272 forces the LFTICK 286 to transition to an asserted low value before the ULPCLK 281 transitions to an asserted high value, which avoids causing a glitch 805 at the IP.

[0054] The fourth case is when both the LFCLK 284 and the delayed LFCLK 482 are detected at asserted high values ​​841 and 842, respectively. This indicates that the rising edge of the synchronized LFCLK 808 has previously occurred and the current condition for a glitch is not detected at the IP. In this case, the LFTICK 286 can also be provided by the clock frequency selection circuit 271 together with the ULPCLK 281 without causing a glitch. Table 1 describes four cases for configuring the FSM 272 to provide the LFTICK 286 in a manner that does not cause a glitch in the clock signal at the IP. The FSM 272 can determine to provide the LFTICK 286 at the output of the multiplexer 714 in the clock switching circuit 700.

[0055] Table 1

[0056]

[0057] Fig. 99 is a flow chart of a method 900 for clock switching according to various examples. The method 900 may be performed by the clock switching circuit 22 to switch the clock frequency of the ULPCLK 281 according to the clock frequency request from the IP, and synchronize the MFTICK 285 and the LFTICK 286 with the clock cycle of the ULPCLK 281. At step 910, a clock frequency request is received from the IP by the clock management circuit 270. For example, a clock frequency request is received from any IP of the SoC / MCU 20 to request a clock frequency of one of the SYSCLK 282, MFCLK 283, or LFCLK 284. At step 920, the clock management circuit 270 determines to switch the ULPCLK 281 from the LFCLK 284 to the MFCLK 283, or from the MFCLK 283 to the LFCLK 284 based on the clock frequency request. At step 930, ULPCLK 281 is switched to SYSCLK 282, which is the fastest clock frequency supported by SoC / MCU 20. For example, ULPCLK 281 is switched from LFCLK 284 to SYSCLK 282 by clock switching circuit 400, regardless of the requested clock frequency. At step 940, MFTICK 285 and LFTICK 286 are synchronized with the clock cycle of SYSCLK 282. Synchronization is performed by aligning the rising edges of MFTICK 285 and LFTICK 286 according to the timing of the clock cycle or the rising edge of SYSCLK 282. For example, MFTICK 285 is synchronized with the clock cycle of SYSCLK 282 by clock switching circuit 500, and LFTICK 286 is synchronized with the clock cycle of SYSCLK 282 by clock switching circuit 700. At step 950, ULPCLK 281 is switched from SYSCLK 282 to MFCLK 283 or LFCLK 284 according to the clock frequency request from the IP. At step 960, the synchronized MFTICK 285 and LFTICK 286 are provided to the IP together with ULPCLK 281.

[0058] Fig.10 1000 is a state diagram suitable for implementation by a state machine according to various examples. In some examples, the state machine is FSM 272. The state machine can operate and transition between states based at least in part on the signals and relationships shown in state diagram 1000. Based on these transitions, the state machine can control clock selection circuits (such as clock frequency selection circuit 271) to provide one or more clock signals to other circuits. For example, the state machine can receive a request from various IPs as described herein, which can be a request for a clock signal with a frequency of SYSCLK 282, LFCLK 284, or MFCLK 283. Fig.10 As shown, the request from the IP to receive a clock signal having a frequency of SYSCLK 282 is represented as sysclkreq_sync, and the request from the IP to receive a clock signal having a frequency of MFCLK 283 is represented as mfclkreq_sync. The tilde (~) before the variable name represents a logical negation function. Therefore, the ~ before the variable name indicates that the variable has a deasserted value, such as a value of logical zero.

[0059] like Fig.10 As shown, each state of the state diagram 1000 corresponds to a control signal provided by the state machine. Fig.10 In the , the control signal is shown as an 8-bit control signal, indexed sequentially from bit 0 to bit 7 in the right-to-left direction. However, in various embodiments, the control signal may include a greater number of bits, at least some of which correspond to functions not described herein. The state machine may provide at least some of the bits of the control signal to various components of the clock selection circuit so that the clock selection circuit provides a clock signal to the IP. As shown in Table 2 below, the bits of the control signal uniquely correspond to the various control signals described herein.

[0060] Table 2

[0061]

[0062]

[0063] In state 1002, the state machine controls the clock selection circuit to provide a clock signal, such as ULPCLK 281, whose frequency is approximately equal to the frequency of SYSCLK 282. State 1002 can be a reset state of the state machine, so that the state machine starts running in state 1002 and progresses to other states of the state machine through state transitions. In response to receiving sysclkreq_sync and mfclkreq_sync, each with a deasserted value (e.g., ~sysclkreq_sync and ~mfclkreq_sync), the state machine transitions to state 1004.

[0064] In state 1004, the state machine implements a delay. For example, state 1004 can be a wait state in which the state machine allows the clock selection circuit time to process or perform other actions or functions outside the scope of the present disclosure. Although shown as a single state, in some instances, state 1004 can instead be implemented as multiple progressive states. In response to ~sysclkreq_sync and ~mfclkreq_sync and a slow fall, the state machine transitions to state 1012. As used herein, a slow fall refers to a falling edge detection in slowclk 481. In response to sysclkreq_sync or mfclkreq_sync, the state machine transitions to state 1032, and then transitions to state 1002 after a programmed wait time.

[0065] In state 1012, the state machine asserts frcclklow and transitions to state 1014. In state 1014, the state machine maintains the asserted value of frcclklow, asserts ulpclkisslow, asserts frclftickhigh, and transitions to state 1016. In state 1016, the state machine maintains the asserted values ​​of ulpclkisslow and frclftickhigh, and deasserts frcclklow. In response to mfclkfall, the state machine transitions to state 1018. As used herein, mfclkfall refers to falling edge detection in MFCLK 283.

[0066] In state 1018, the state machine controls the clock selection circuit to provide a clock signal having a frequency approximately equal to the frequency of LFCLK 284. In addition, the state machine maintains the asserted values ​​of ulpclkisslow and frclftickhigh, and also asserts frcmfticklow. In some examples, the state machine remains in state 1018 until sysclkreq_sync or mfclkreq_sync is received. In response to sysclkreq_sync or mfclkreq_sync, the state machine transitions to state 1022.

[0067] In state 1022, the state machine implements a delay. For example, state 1022 can be a wait state in which the state machine allows the clock selection circuit time to process or perform other actions or functions outside the scope of the present disclosure. In response to the binary value of lfclk_vec being 2'b10 (e.g., the decimal value is 2), the state machine transitions to state 1024. In response to the binary value of lfclk_vec not being 2'b10 (e.g., the decimal value is not 2), the state machine transitions to state 1026.

[0068] In state 1024, the state machine implements a delay. For example, state 1024 can be a wait state in which the state machine allows the clock selection circuit time to process or perform other actions or functions outside the scope of the present disclosure. In response to the binary value of lfclk_vec being 2'b11 (e.g., a decimal value of 3), the state machine transitions to state 1026.

[0069] In state 1026 , the state machine maintains the asserted values ​​of frcmfticklow and ulpclkisslow, deasserts frclftickhigh, asserts frclfticklow, asserts frcclklow, and transitions to state 1028 .

[0070] In state 1028 , the state machine maintains the asserted values ​​of frcmfticklow, frclfticklow, and frcclklow, deasserts ulpclkisslow, asserts slowismfclk, and transitions to state 1030 .

[0071] In state 1030, the state machine maintains the asserted values ​​of frcmfticklow and slowismfclk, deasserts frclfticklow, and deasserts frcclklow. In response to receiving mfgood_sync, the state machine transitions to state 1002. As used herein, mfgood_sync indicates that one of the oscillators 273 providing MFCLK 283 is operating in a normal state.

[0072] Returning to state 1002 , the state machine maintains slowismfclk in the asserted state and deasserts frcmfticklow. In response to ˜sysclkreq_sync and mfclkreq_sync, the state machine transitions to state 1040 .

[0073] In state 1040, the state machine maintains the asserted value of slowismfclk and implements a delay. For example, state 1040 can be a wait state in which the state machine allows time for the clock selection circuit to process or perform other actions or functions outside the scope of the present disclosure. In response to ~sysclkreq_sync and ~mfclkreq_sync or sysclkreq_sync and mfclkreq_sync, the state machine transitions to state 1002. In response to ~sysclkreq_sync and mfclkreq_sync and lfclk_vec having a binary value of 2'b01 (e.g., a decimal value of 1), the state machine transitions to state 1042.

[0074] In state 1042, the state machine maintains the asserted value of slowismfclk and implements a delay. For example, state 1042 can be a wait state in which the state machine allows the clock selection circuit time to process or perform other actions or functions outside the scope of the present disclosure. In response to mfclkrise, the state machine transitions to state 1044. As used herein, mfclkrise represents a rising edge detection in MFCLK 283.

[0075] In state 1044, the state machine maintains the asserted value of slowismfclk, asserts frclfticklow, asserts frcmftickhigh, asserts frcclklow, and transitions to state 1046. In state 1046, the state machine maintains the asserted values ​​of slowismfclk, frclfticklow, frcmftickhigh, and frcclklow, and asserts ulpclkisslow. In response to mfclkfall, the state machine transitions to state 1048.

[0076] In state 1048, the state machine controls the clock selection circuit to provide a clock signal having a frequency approximately equal to the frequency of MFCLK 283. In addition, the state machine maintains the asserted values ​​of slowismfclk, frclfticklow, and ulpclkisslow, and deasserts frclfticklow and frcclklow. In some examples, the state machine remains in state 1048 until sysclkreq_sync or ~mfclkreq_sync is received. In response to sysclkreq_sync or ~mfclkreq_sync, the state machine transitions to state 1052.

[0077] In state 1052, the state machine implements a delay. For example, state 1052 can be a wait state in which the state machine allows the clock selection circuit time to process or perform other actions or functions outside the scope of the present disclosure. In response to mfclkfall, lfclk_vec having a binary value other than 2'b10 (e.g., a decimal value of 2), and lfclkdly_reg having a value other than 2'b10 (e.g., a decimal value of 2), the state machine transitions to state 1054.

[0078] In state 1054, the state machine implements a delay. For example, state 1054 can be a wait state in which the state machine allows the clock selection circuit time to process or perform other actions or functions outside the scope of the present disclosure. In response to lfclk_vec having a binary value of 2'b10 (e.g., a decimal value of 2) or lfclkdly_reg having a value of 2'b10 (e.g., a decimal value of 2), the state machine transitions to state 1056.

[0079] In state 1056, the state machine implements a delay. For example, state 1056 can be a wait state in which the state machine allows the clock selection circuit time to process or perform other actions or functions outside the scope of the present disclosure. In response to mfclkrise, the state machine transitions to state 1058.

[0080] In state 1058, the state machine implements a delay. For example, state 1058 can be a wait state in which the state machine allows the clock selection circuit time to process or perform other actions or functions outside the scope of the present disclosure. In response to mfclkrise, the state machine transitions to state 1060.

[0081] Returning to state 1054 , in response to mfclkrise, lfclk_vec having a binary value other than 2′b10 (eg, a decimal value of 2), and lfclkdly_reg having a value other than 2′b10 (eg, a decimal value of 2), the state machine transitions to state 1060 .

[0082] In state 1060, the state machine implements a delay. For example, state 1060 may be a wait state in which the state machine allows the clock selection circuit time to process or perform other actions or functions outside the scope of the present disclosure. In response to the binary value of MFTICKCNT 601 being 4'b0100 (e.g., a decimal value of 8) as maintained and provided by counter 507, the state machine transitions to state 1062.

[0083] In state 1062, the state machine maintains frcmtickhigh, slowismfclk, and ulpclkisslow with asserted values, asserts frclfticklow, asserts frcclklow, and transitions to state 1064. In state 1064, the state machine maintains frcmfticklow, slowismfclk, and frcclklow with asserted values, deasserts ulpclkisslow, and transitions to state 1066. In state 1066, the state machine maintains frmcmftickhigh and slowismfclk with asserted values, deasserts frclfticklow and frcclklow, and transitions to state 1002.

[0084] According to the above described state and transition operation to provide Fig.10 The state machine of the control signals shown and described herein provides a clock signal to the requesting device (such as the IP described herein). Under the control of the state machine, the clock signal provided by the clock selection circuit can be at a certain frequency, which is the highest frequency among the frequencies requested by the IP. The clock selection circuit can further provide an enable signal, such as MFTICK 285 and LFTICK 286, to the requesting IP. The requesting IP can receive the clock signal provided under the control of the state machine, and by further clocking the clock signal according to the enable signal (e.g., by the ICG as described above), the IP generates a lower frequency clock signal. However, because these lower frequency clock signals are generated by each requesting IP from the same clock signal provided under the control of the state machine, at least some challenges related to exchanging signals across clock boundaries are alleviated.

[0085] The term "coupled" is used throughout this specification. The term may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then in a first instance, device A is coupled to device B, or in a second instance, if the intermediate component C does not significantly change the functional relationship between device A and device B, then device A is coupled to device B through an intermediate component C, so that device B is controlled by device A through a control signal provided by device A.

[0086] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of hardware components and interconnection of the device, or a combination thereof.

[0087] Circuits or devices described herein as including certain components may instead be adapted to be coupled with those components used to form the described circuit systems or devices. For example, a structure described as including one or more circuit elements (e.g., flip-flops, latches, gates, multiplexers, counters, etc.) and / or one or more sources (e.g., voltage and / or current sources) may instead include circuit elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled with at least some of the circuit elements and / or sources to form the described structure during or after manufacture, e.g., by an end user and / or a third party.

[0088] Although certain components may be described herein as having a particular process technology, these components may be interchangeable with components of other process technologies. The circuits described herein may be reconfigured to include the replaced components to provide functionality at least partially similar to that available prior to component replacement.

[0089] Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. The described examples may be modified, and other examples are possible, within the scope of the claims.

Claims

1. A device comprising: A clock switching circuit is coupled to the oscillator and the one or more circuit units, wherein the clock switching circuit is configured to: receiving a set of frequency signals from the oscillator; providing an uplink master clock signal and an enable signal to the one or more circuit units, wherein the enable signal is determined synchronously with the uplink master clock signal; receiving a clock frequency request from the one or more circuit units or the clock management circuit; providing the uplink master clock signal based on a first signal in the set of frequency signals; and According to the clock frequency request, it is determined whether to continue to provide the uplink master clock signal based on the first signal or based on a second signal in the set of frequency signals.

2. The apparatus of claim 1 , further comprising a finite state machine (FSM) coupled to the clock switching circuit and configured to provide a control signal for controlling the clock switching circuit to provide the uplink master clock signal.

3. The apparatus of claim 2, wherein the clock switching circuit comprises a clock frequency selection circuit configured to select the uplink master clock signal from the set of frequency signals according to the control signal.

4. The device according to claim 3, wherein the set of frequency signals includes a low clock frequency signal, a medium clock frequency signal and a high clock frequency signal, and the clock frequency selection circuit includes: a delay element having a delay element input configured to receive the low clock frequency signal and a delay element output configured to provide a delayed low clock frequency signal; a first multiplexer having a first multiplexer first input, a first multiplexer second input, and a first multiplexer output, the first multiplexer input being configured to receive an intermediate clock frequency signal, the first multiplexer second input being coupled to the delay element output, and the first multiplexer output being configured to provide a slow clock frequency signal as one of the intermediate clock frequency signal or the delayed low clock frequency signal according to an intermediate clock frequency slow indication signal included in the control signal; an AND gate having an AND gate output, a first AND gate input, and a second AND gate input, the first AND gate input being coupled to the first multiplexer output, the second AND gate input being configured to receive an inversion of a clock frequency signal low value indication signal included in the control signal, and the AND gate output being configured to provide an uplink master clock multiplexer signal; an integrated clock gate (ICG), the ICG having an ICG data input, an ICG control input, and an ICG output, the ICG data input being configured to receive the high clock frequency signal, the ICG control input being configured to receive the clock frequency signal low value indication signal, and a first ICG output being configured to provide a system clock frequency signal low value indication signal; as well as a second multiplexer, the second multiplexer having a second multiplexer first input, a second multiplexer second input and a second multiplexer output, the second multiplexer first input being coupled to the AND gate output, the second multiplexer second input being coupled to the ICG output, and the second multiplexer output being configured to provide the uplink master clock signal based on the uplink master clock multiplexer signal, the system clock frequency signal low value indication signal and the uplink master clock frequency slow indication signal included in the control signal.

5. The device according to claim 3, wherein the clock switching circuit is configured to provide the second enable signal in synchronization with a clock cycle of the high clock frequency signal based on the intermediate clock frequency selection signal and the high clock frequency selection signal included in the control signal.

6. The device of claim 5 , wherein the clock switching circuit further comprises a rising edge detection circuit, the rising edge detection circuit being coupled to the FSM and configured to detect a rising edge of the intermediate clock frequency signal, the second enable signal being provided by the clock switching circuit based on the detected rising edge of the intermediate clock frequency signal, the rising edge detection circuit comprising: a delay element having a first delay element output configured to provide the intermediate clock frequency signal synchronized with the high clock frequency signal based on detecting the rising edge; as well as An AND gate is coupled to the delay element, the AND gate having a first AND gate output and a second AND gate output, the first AND gate output being configured to provide an intermediate clock frequency signal rising edge indication signal to the FSM, the second AND gate output being configured to allow the delay element to provide the high clock frequency signal, the intermediate clock frequency signal rising edge indication signal being sent based on detecting the rising edge of the intermediate clock frequency signal.

7. The apparatus of claim 6, wherein the clock switching circuit further comprises: a digital counter coupled to the FSM, the digital counter having a first digital counter output, the first digital counter output being configured to provide a second enable original signal within a certain number of clock cycles of the high clock frequency signal after receiving a rising edge indication signal of the intermediate clock frequency signal; a second AND gate having a second AND gate first input, a second AND gate second input, and a second AND gate output, the second AND gate first input being coupled to the FSM and configured to receive an inversion of the intermediate clock frequency selection signal included in the control signal, and the second AND gate second input being coupled to the digital counter output; and An OR gate having an OR gate first input, an OR gate second input and an OR gate output, wherein the OR gate first input is coupled to the FSM and configured to receive a high clock frequency signal selection signal from the control signal, a second OR gate second input is coupled to the second AND gate output, and the OR gate output is configured to provide the intermediate clock frequency selection signal.

8. The apparatus of claim 7, wherein the number of clock cycles of the high clock frequency signal is proportional to a ratio of a first clock frequency of the high clock frequency signal to a second clock frequency of the intermediate clock frequency signal.

9. The apparatus of claim 1 , wherein the set of frequency signals includes a low clock frequency signal, a medium clock frequency signal, and a high clock frequency signal, and wherein the clock switching circuit further comprises: a delay element having a first delay element output configured to provide a low clock frequency signal high value indication signal and a second delay element output configured to provide a delayed low clock frequency signal high value indication signal; a first AND gate, the first AND gate being coupled to the delay element, the first AND gate having a first AND gate output, the first AND gate output being configured to provide a low clock frequency rising edge indication signal based on the low clock frequency signal high value indication signal and the delayed low clock frequency signal high value indication signal; a second AND gate, the second AND gate being coupled to the first AND gate, the second AND gate having a second AND gate output, the second AND gate output being configured to provide an output low clock frequency signal rising edge indication signal based on an inversion of the low clock frequency signal rising edge indication signal and a low clock frequency signal low value indication signal; an OR gate coupled to the second AND gate and configured to receive a third enable signal high value indication signal, the OR gate having an OR gate output, the OR gate output configured to provide a low clock frequency synchronized with the uplink master clock signal; as well as a multiplexer coupled to the OR gate, the multiplexer having a multiplexer output configured to provide the low clock frequency enable signal based on the low clock frequency synchronized with a clock cycle of the uplink master clock signal, the low clock frequency synchronized with a clock cycle of the high clock frequency signal, and an uplink master clock signal low value indication signal.

10. A method comprising: receiving, by the clock management circuit, a clock frequency request from the circuit unit for a clock signal having a first frequency; Determining, by the clock management circuit based on the clock frequency request, to provide an uplink master clock signal based on a first clock frequency signal from a group of clock frequency signals, the first clock frequency signal having the first frequency; receiving, by the clock management circuit, from a second circuit unit, a second clock frequency request for a second clock signal having a second frequency; In response to the second frequency being less than the first frequency, determining by the clock management circuit based on the second clock frequency request to continue providing the uplink master clock signal based on the first clock frequency signal; In response to the second frequency being greater than the first frequency, determining by the clock management circuit based on the second clock frequency request to provide the uplink master clock signal based on a second clock frequency signal from the set of clock frequency signals, the second clock frequency signal having the second frequency; as well as The uplink master clock signal and an enable signal are provided to the circuit unit and the second circuit unit, and the enable signal is provided in synchronization with the uplink master clock signal.

11. The method according to claim 10, comprising: In response to the second frequency being greater than the first frequency, generating, by the circuit unit, a first internal clock signal having the first frequency based on the uplink master clock signal and the enable signal; as well as In response to the second frequency being less than the first frequency, a second internal clock signal having the second frequency is generated by the second circuit unit based on the uplink master clock signal and the enable signal.

12. The method according to claim 10, comprising: receiving, by the clock management circuit, a third clock frequency request for a third clock signal having a third frequency from a third circuit unit; In response to the third frequency being less than the first frequency and the second clock frequency, determining by the clock management circuit to continue to provide the uplink master clock signal based on a higher frequency from the first clock frequency signal and the second clock frequency signal; In response to the third frequency being greater than the first frequency and the second frequency, determining by the clock management circuit based on the third clock frequency request to provide the uplink master clock signal based on a third clock frequency signal from the set of clock frequency signals, the third clock frequency signal having the third frequency; as well as The uplink master clock signal, an enable signal and a second enable signal are provided to the circuit unit, the second circuit unit and the second circuit unit, and the enable signal and the second enable signal are provided in synchronization with the uplink master clock signal.

13. The method according to claim 12, wherein the first frequency is greater than the second frequency and the third frequency, the method comprising: generating, by the second circuit unit, a second internal clock signal having the second frequency based on the uplink master clock signal and the enable signal; as well as A third internal clock signal having the third frequency is generated by the third circuit unit based on the uplink master clock signal and the second enable signal.

14. The method according to claim 12, wherein the third frequency is greater than the first frequency and the second frequency, the method comprising: generating, by a first circuit unit, a first internal clock signal having the first frequency based on the uplink master clock signal and the enable signal; as well as A second internal clock signal having the second frequency is generated by the second circuit unit based on the uplink master clock signal and the second enable signal.

15. The method according to claim 10, comprising: providing each frequency signal in the set of clock frequency signals by a corresponding oscillator, wherein the set of clock frequency signals includes a third clock frequency signal having a third frequency greater than the first frequency and the second frequency; as well as In response to the third frequency being greater than the first frequency requested by the first circuit unit and the second frequency requested by the second circuit unit, an oscillator of the oscillators that provides the third clock frequency signal is disabled.

16. The method of claim 10, further comprising disabling an oscillator providing the first clock frequency signal in response to providing the uplink master clock signal based on the second clock frequency signal.

17. An apparatus comprising: clock switching circuit; and A finite state machine (FSM), the FSM being configured to: providing a first control signal to the clock switching circuit for state transition, the state transition determining to switch the uplink master clock signal from a first clock frequency signal to a second clock frequency signal or a third clock frequency signal, the first clock frequency signal having a faster clock frequency than the second clock frequency signal, and the third clock frequency signal having a slower clock frequency than the second clock frequency signal; and A second control signal is provided to the clock switching circuit to provide a second clock frequency enable signal and a third clock frequency enable signal together with the uplink master clock signal, the second clock frequency enable signal and the third clock frequency enable signal being generated synchronously with the uplink master clock signal.

18. The apparatus of claim 17, wherein the FSM is configured to: Providing a second slow clock frequency indication signal to the clock switching circuit, wherein the second slow clock frequency indication signal enables the clock switching circuit to provide a slow clock frequency signal according to the delayed third clock frequency signal or the second clock frequency signal; providing a clock frequency signal low value indication signal to the clock switching circuit to determine an uplink master clock multiplexer signal using the slow clock frequency signal, the clock frequency signal low value indication signal causing the clock switching circuit to provide a system clock frequency signal low value indication signal based on the high clock frequency signal; providing an uplink master clock frequency slow indication signal to the clock switching circuit, the uplink master clock frequency slow indication signal causing the clock switching circuit to provide an output clock frequency signal based on the uplink master clock multiplexer signal and the system clock frequency signal low value indication signal; and The uplink master clock multiplexer signal is provided to the clock switching circuit, causing the clock switching circuit to provide the uplink master clock signal based on the output clock frequency signal and the high clock frequency signal.

19. The apparatus of claim 17, wherein the FSM is configured to provide an uplink master clock frequency slow indication signal to the clock switching circuit, the uplink master clock frequency slow indication signal causing the clock switching circuit to provide the third clock frequency enable signal as one of a first third clock frequency enable signal synchronized with a clock cycle of the uplink master clock signal and a second third clock frequency enable signal synchronized with a clock cycle of the high clock frequency signal.

20. The apparatus of claim 17, wherein the FSM is configured to: providing a second clock frequency selection signal to the clock switching circuit, the second clock frequency selection signal causing the clock switching circuit to select the second clock frequency signal; and A high clock frequency selection signal is provided to the clock switching circuit, and the high clock frequency selection signal causes the clock switching circuit to select the second clock frequency signal.

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