Dual drive doherty power amplifiers and related systems and methods

Abstract

The invention provides a Doherty amplifier based on dual drive. The Doherty amplifier comprises a first power amplifier and a second power amplifier connected with the first power amplifier in parallel. The first power amplifier is configured to receive a first portion of a signal having a first phase, and the second power amplifier is configured to receive a second portion of a signal having a second phase having a phase difference from the first phase. At least one of the first power amplifier or the second power amplifier includes a dual drive power amplifier core.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent claims the benefit of U.S. Provisional Patent Application No. 63 / 319,930, entitled “DUAL-DRIVE DOHERTY POWER AMPLIFIER AND RELATED SYSTEMS AND METHODS,” filed on March 15, 2022. The entire contents of each of the prior applications listed above are incorporated herein by reference. Background Art 1. Technical Field

[0003] The present disclosure relates generally to power amplifier architectures, and more particularly to a Doherty load modulation power combining network in combination with a primary / auxiliary power amplifier core using a dual drive configuration to increase achievable communication modulation efficiency.

[0004] 2. Description of related prior art

[0005] Doherty amplifiers have been around for decades. In recent years, there has been a resurgence of the Doherty amplifier. For example, modern communication systems use Doherty amplifiers in base stations based on massive multiple-input multiple-output (mMIMO). In fact, modern communication systems use complex signal modulation schemes such as OFDM (Orthogonal Frequency Division Multiplexing) with high peak-to-average power ratio (PAPR), and the probability of a power amplifier operating at its peak power with maximum efficiency is very low. The property of the Doherty amplifier to exhibit multiple efficiency peaks at various lower power levels makes it an attractive choice to increase the average efficiency of modern transmitters. The Doherty amplifier can achieve this by using a technique called "dynamic load modulation", in which the load seen by the main amplifier varies as a function of the power level in order to improve efficiency at lower power levels. Summary of the invention

[0006] The following is a non-exhaustive list of some aspects of the present technology. These and other aspects are described in the following disclosure.

[0007] Some aspects include a dual-drive based Doherty amplifier comprising: a power divider, a first power amplifier coupled to a first output of the power divider, and a second power amplifier coupled to a second output of the power divider and connected in parallel with the first power amplifier; wherein the second power amplifier receives a second output signal of a phase difference from a first output signal of the first output from a second output having a phase difference, wherein at least one of the first power amplifier or the second power amplifier includes a dual-drive power amplifier core.

[0008] Some aspects include a dual-drive based Doherty amplifier comprising: a first power amplifier, and a second power amplifier connected in parallel with the first power amplifier; wherein the first power amplifier is configured to receive a first portion of a signal having a first phase, and wherein the second power amplifier receives a second portion of a signal having a second phase having a phase difference from the first phase, and wherein at least one of the first power amplifier or the second power amplifier includes a dual-drive power amplifier core.

[0009] Some aspects include a method of amplifying power using a dual-drive based Doherty amplifier including a dual-drive power amplifier core. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects of the present technology will be better understood when the present application is read in light of the following drawings, in which like numbers represent similar or identical elements:

[0011] Figure 1 A block diagram of a Doherty load modulation power combining network according to various embodiments of the present disclosure is shown;

[0012] Figure 2 shows a schematic diagram of a dual-drive power amplifier (PA) core according to various embodiments of the present disclosure;

[0013] Figure 3 A coupled transmission line pair is shown that enables passive generation of a signal αVin+ from Vin+ and passive generation of a signal αVin from Vin- according to various embodiments of the present disclosure;

[0014] Figure 4 The use of various embodiments according to the present disclosure is shown Figure 2 Dual drive core Figure 1 Detailed schematic diagram of the Doherty load modulation power combining network;

[0015] Figure 5 The present invention shows various embodiments of the present invention. Figure 1 Block diagram of the in-phase and quadrature (IQ) networks of the Doherty load modulation power combining network;

[0016] Figure 6 The present invention shows various embodiments of the present invention. Figure 1 Block diagram of the IQ network of the Doherty load modulation power combining network;

[0017] Figure 7 An example block diagram of a power amplifier utilizing a dual drive core according to various embodiments of the present disclosure is shown;

[0018] Fig. 8AA graph showing the input impedance of a dual-drive power amplifier according to various embodiments of the present disclosure;

[0019] Figure 8B shows the input impedance of a dual-drive power amplifier core according to various embodiments of the present disclosure; and

[0020] Fig. 9 The method for deriving the Figure 2 Schematic diagram of the small signal dual-drive transistor model of the dual-drive power amplifier (PA) core input impedance.

[0021] Although the present technology is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. The drawings may not be drawn to scale. However, it should be understood that the drawings and their detailed description are not intended to limit the present technology to the particular form disclosed, but rather, the present invention is intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the present technology as defined by the appended claims. DETAILED DESCRIPTION

[0022] In order to alleviate the problems described herein, the inventors had to invent solutions and, in some cases, just as importantly, recognize problems that were overlooked (or not yet foreseen) by others in the fields of wireless communications, Doherty amplifiers, and power amplifiers. Indeed, the inventors wish to emphasize the difficulty of recognizing these emerging problems, which will become more apparent in the future if industry trends continue as the inventors anticipate. Furthermore, because multiple problems are solved, it should be understood that some embodiments are problem specific, and not all embodiments solve every problem of the conventional systems described herein or provide every benefit described herein. That is, improvements that solve various permutations of these problems are described below.

[0023] Due to the low breakdown voltage of the device and limited f max Traditional power amplifiers ("PA's") have limited efficiency, output power, and gain due to factors such as the use of complex modulation schemes (e.g., QAMs / OFDM) and poor quality of chip passive components, as well as limited voltage swings. Furthermore, while the use of complex modulation schemes (e.g., QAMs / OFDM) are spectrally efficient, they have the combined cost of reduced peak-to-average power ratio ("PAPR"). This results in PAs typically operating far from their most efficient peak output power, which in turn greatly reduces their average modulation efficiency.

[0024] To improve efficiency under power back-off (PBO) and modulation, designers have used complex design techniques such as load modulation (Doherty and out-phasing PAs). But these techniques sacrifice gain, linearity, and peak efficiency because they lose the power combining / phase shifter network. Harmonic tuned PAs improve peak efficiency but at the expense of linearity and bandwidth due to harmonic termination. While the dual-drive topology improves the peak efficiency and linearity achievable in the PA core by out-phasing the coupled gate and source, thereby increasing the total swing, it does not improve efficiency under power back-off conditions.

[0025] The disclosed technology relates to a new power amplifier (PA) architecture to significantly improve the achievable communication modulation efficiency. To achieve this, the systems and methods of the present disclosure use a combination of a Doherty load modulation power combining network and a main / auxiliary PA core utilizing a dual-drive configuration, as described in U.S. Patent No. 11,469,726, entitled “High-efficiency dual-drive power amplifier for high-reliability applications,” filed on March 3, 2022, and incorporated herein by reference. The dual-drive input coupling network supports driving the gate and source terminals of the differential pair out of phase while properly DC biasing the two terminals. The coupling network ensures that the source and drain of the transistor swing in phase, thereby artificially reducing the transistor knee voltage to increase the total output voltage swing. The enhanced voltage swing improves PA peak output power, linearity, and efficiency. In addition, due to the coupling with the source, the input impedance of the dual-drive PA core is greatly reduced, minimizing the required impedance transformation ratio and supporting broadband and low-loss matching networks.

[0026] The Doherty power combining network supports power combining for high power applications, as well as active load modulation with enhanced power back-off (PBO) efficiency. The combination of the Doherty network and dual-drive PA core supports high PBO efficiency peaks for efficient communication under modulation, high gain due to low matching losses in the input / interstage network, and broadband operation due to minimal impedance transformation required.

[0027] In addition, due to the low breakdown voltage and limited f maxTraditional power amplifiers (PAs) have limited efficiency, output power, and gain due to the use of complex modulation schemes such as QAMs / OFDM, poor quality of chip passive components, and limited voltage swing. In addition, complex modulation schemes such as QAMs / OFDM are used to improve spectral efficiency at the expense of increasing peak-to-average power ratio (PAPR). This results in PAs operating on average far from their most efficient peak output power, which greatly reduces the average modulation efficiency. To improve efficiency under PBO and modulation, designers have used complex design techniques such as load modulation (Doherty and out-phasing PAs). However, these techniques sacrifice gain, linearity, and peak efficiency due to losses in the power combining / phase shifter networks. Harmonic tuning PAs improve peak efficiency but at the expense of linearity and bandwidth due to harmonic termination. The dual-drive topology increases the total swing by coupling the gate and source out of phase, thereby improving the peak efficiency and linearity achievable by the PA core. However, it does not improve efficiency under power back-off conditions.

[0028] To overcome these challenges, the disclosed systems and methods propose a new PA architecture that employs Doherty power in combination with a main / auxiliary PA core utilizing a dual-drive configuration. The Doherty PA architecture can support PBO efficiency enhancement through effective load modulation. However, the Doherty PA architecture may suffer from limited peak efficiency due to the limited gain and loss of the power combining / IQ power distribution network, and the disclosed technology uses a dual-drive PA core of the main / auxiliary PA to alleviate these problems.

[0029] According to some embodiments of the disclosed technology, a dual-drive PA core for a primary / auxiliary PA helps alleviate these problems. The dual-drive active core feeds the input signal into the source and gate of the PA in an out-of-phase manner through a multi-feed coupling network. The dual-drive PA core uses a differential pair consisting of M1 and M2 and a multi-feed network to couple the gate of M1 to the source of M2 and the gate of M2 to the source of M1 while ensuring proper DC bias points: the gate is a non-zero DC voltage and the source is DC grounded. The coupling network causes the source of the transistor to swing in phase with its drain, thereby reducing the effective voltage inflection point and enhancing the output swing, which in turn improves the linearity, output power, and power added efficiency of the dual-drive PA core compared to traditional common source (CS) and common source and common gate.

[0030] Therefore, according to aspects of the present disclosure, the increased peak efficiency due to the dual-drive PA core for main / auxiliary can compensate for the reduced peak efficiency due to the Doherty power combining network, while still maintaining the PBO efficiency improvement, greatly increasing the average efficiency achievable under modulation. In addition, because the dual-drive topology combines common-gate and common-source amplifiers, the input impedance of the PA core is greatly reduced. This minimizes the impedance transformation required for the matching network that interfaces with the dual-drive core input, extends the achievable bandwidth of the Doherty PA, and minimizes the losses within the matching network. The reduction in matching network losses increases the overall gain of the PA, further improving the peak efficiency, thereby improving the modulation efficiency achievable by the Doherty PA. The outstanding performance makes the PA architecture an efficient topology for commercial applications.

[0031] Figure 1 FIG. 1 is a block diagram of a Doherty load modulation power combining network 100 according to various embodiments of the present disclosure. In various embodiments, the Doherty load modulation power combining network 100 may include a Doherty power amplifier architecture. Figure 1 A specific Doherty power amplifier architecture is shown in FIG. 1 , but those skilled in the art in possession of the present disclosure will recognize that other circuits that can be classified as Doherty power amplifiers are contemplated and fall within the scope of the present disclosure. The Doherty power amplifier architecture may include a driver 102 that includes a driver input 102a and a driver output 102b. The driver input 102a may receive an input signal RF in In various embodiments, driver 102 may include a dual-drive power amplifier core, discussed in further detail below.

[0032] In various embodiments, the driver output 102b can provide a driver output signal to an in-phase and quadrature (IQ) network 104. The IQ network 104 may include a power divider and a phase shifter. The power divider can distribute the driver output signal to a main signal line and an auxiliary signal line. The phase shifter can be coupled to the auxiliary signal line and can shift the signal on the auxiliary signal line (e.g., a line that provides a signal to an auxiliary power amplifier). Although a power splitter that divides the signal into two paths is shown, other splitter configurations (e.g., 3-way, 4-way, or other configurations that are obvious to those skilled in the art) are also contemplated. In some embodiments, the phase shifter can produce an orthogonal (90 degree) phase shift. However, other phase shifts are also contemplated. The phase shifter can include an orthogonal hybrid coupler, a Lange coupler, a polyphase filter quadrature splitter, a Schiffman phase shifter, a branch line coupler, a power splitter with a delay line, or any other phase shifter that is obvious to those skilled in the art having the present disclosure. In various embodiments, the phase shifter outputs to the auxiliary power amplifier input 108a, while the main power amplifier input 106a does not include a phase shifter and receives a portion of the driver output signal without a phase shift.

[0033] As mentioned, the IQ network 104 is coupled to the main power amplifier input 106a of the main power amplifier 106. The main power amplifier 106 may include a main power amplifier output 106b. The main power amplifier 106 may be biased in class AB. However, other classes are also contemplated. In various embodiments, the main power amplifier 106 may include a dual-drive power amplifier core, discussed in further detail below. The IQ network 104 is also coupled to the auxiliary power amplifier input 108a of the auxiliary power amplifier 108. The auxiliary power amplifier 108 may include an auxiliary power amplifier output 108b. The auxiliary power amplifier 108 may be biased in class C. The biasing scheme means that at low input drive levels, the main power amplifier 106 is turned on and the auxiliary power amplifier 108 is turned off. As the input level increases, the drive level of the main power amplifier 106 also increases, and when the output power is approximately one-quarter of the maximum value of the main power amplifier, the auxiliary power amplifier 108 begins to conduct current. In various embodiments, the auxiliary power amplifier 108 may include a dual-drive power amplifier core, discussed in further detail below.

[0034] In various embodiments, the main power amplifier output 106b can be coupled to a second phase shifter 110 (e.g., an impedance converter) that shifts the phase of the main power amplifier output signal to match the phase of the auxiliary power amplifier output signal from the auxiliary power amplifier output 108b. Thus, in various embodiments, to match the 90 degree phase shift of the auxiliary power amplifier 108, the phase shifter 110 can include a quarter wavelength impedance converter. The signals from the phase shifter 110 and the auxiliary power amplifier output 108b can be combined at the output matching network 112 and output as the output signal RF out Provided to load Z L Although in Figure 1 A particular Doherty load modulation power combining network 100 is shown in FIG. 1 , but those skilled in the art having possession of the present disclosure will recognize that other Doherty power amplifiers including other components and configurations may be contemplated and still fall within the scope of the present disclosure.

[0035] Figure 2 is a schematic diagram of a dual-drive power amplifier (PA) core 200 according to an embodiment of the present disclosure, which may be provided as Figure 1 The Doherty load modulates at least one of the main power amplifier 106 or the auxiliary power amplifier 108 of the power combining network 100. In some embodiments, the driver 102 may also include a dual-drive power amplifier core 200. The dual-drive power amplifier core 200 may utilize a transistor differential pair including a first transistor M1202 and a second transistor M2204 having a dual-drive coupling network 206. The dual-drive coupling network 206 may include transmission line sections T1208, T2210, T3212, and T4214, wherein T1208 and T2210 are electromagnetically coupled, and T3212 and T4214 are electromagnetically coupled. The dual-drive coupling network 206 may apply a first portion of a balanced input signal Vin- through T4214 to drive the gate of M1202, while coupling a version of Vin- through T3212 to drive the source terminal of M2204. At the same time, a second portion of the balanced input signal Vin+, Vin+, can be applied via T2210 to drive the gate of M2204, while a version of Vin+ is coupled via T1208 to drive the source terminal of M1202. The embodiments disclosed herein also allow for providing correct DC bias points, such as a non-zero DC voltage at the gate and a DC ground at the source. Using this PA topology, the sources of transistors 202 and 204 can swing in phase with their drains, allowing for an extension of the voltage knee / output swing, which can increase output power linearly and increase power efficiency while using low supply voltages.

[0036] Figure 3 Yes, it can be provided Figure 22 is a diagram of a coupling network 300 of a dual-drive coupling network 206, which includes a pair of transmission line-based couplers T1208 and T2210, T3212, and T4214, where T1208 is coupled to T2210 (S 302) and T3212 is coupled to T4214 (S 304). Although each of T1208, T2210, T3212, and T4214 (in isolation) can be considered an independent transmission line, the proximity of T1208 to T2210 allows electromagnetic coupling therebetween, so that T1208 and T2210 can form a first transmission line-based coupler. Similarly, T3212 and T4214 can form a second transmission line-based coupler. Couplings 302 and 304 are capable of passively generating signals αVin+ and αVin- from Vin+ and Vin-, respectively. In some embodiments, the coupling network 300 may introduce inductive reactance source degradation, which may reduce the overall device power gain. In some embodiments, the inductive reactance can be reduced by selecting a transmission line geometry that has an even mode impedance Z 0e and odd mode impedance Z 0o provides a reasonably low value while maintaining the desired coupling coefficient α. According to certain embodiments of the present disclosure, the coupling coefficient α may be set by the transmission line geometry.

[0037] In some embodiments of the present disclosure, the coupling coefficient α may be set in a range between about 0.1 and about 0.9. In another embodiment, the coupling coefficient α may be set in a range between about 0.2 and about 0.8. In yet another embodiment, the coupling coefficient α may be set in a range between about 0.3 and about 0.7. In yet another embodiment, the coupling coefficient α may be set in a range between about 0.4 and about 0.6. In yet another embodiment, the coupling coefficient α may be set in a range between about 0.3 and about 0.4.

[0038] As referenced above Figure 2 and Figure 3 As discussed, the dual-drive power amplifier core 200 may include a first transistor M1 202 having at least three terminals, including an M1 gate terminal, an M1 drain terminal, and an M1 source terminal. The dual-drive power amplifier core 200 may include a second transistor M2 204 having at least three terminals, including an M2 gate terminal, an M2 drain terminal, and an M2 source terminal.

[0039] The dual drive power amplifier core 200 may include a first transmission line coupler including a first transmission line section T1 208 having a first end and a second end, wherein the first end is grounded and the second end is connected to the M1 source terminal.

[0040] The dual drive power amplifier core 200 may include a first transmission line coupler including a second transmission line portion T2210 having a first end and a second end, wherein the first end may be configured to receive one or more of a core first input signal and / or a first bias voltage. The second end of the second transmission line portion T2210 may be connected to the M2 gate terminal and may be capacitively coupled to the M1 drain terminal. As described above, the first transmission line portion T1208 may be electromagnetically coupled to the second transmission line portion T2210.

[0041] The dual-drive power amplifier core 200 may include a second transmission line coupler including a third transmission line portion T3212 having a first end and a second end, wherein the first end is grounded and the second end may be connected to the M2 source terminal.

[0042] The dual drive power amplifier core 200 may include a fourth transmission line portion T4214 having a first end and a second end, wherein the first end may be configured to receive one or more of a core second input signal and / or a first bias voltage. The second end of the fourth transmission line portion T4214 may be connected to the M1 gate terminal, and in some implementations, may be capacitively coupled to the M2 drain terminal. As described above, the third transmission line portion T3212 may be electromagnetically coupled to the fourth transmission line portion T4214.

[0043] Figure 4 A Doherty load modulation power combining network 400 is shown, which includes Figure 1 The Doherty load modulation power combining network 100 is used in power amplifiers and drivers Figure 2 For example, the driver 102 may include the dual-drive power amplifier core 200, the main power amplifier 106 may include the dual-drive power amplifier core 200, and the auxiliary power amplifier 108 may include the dual-drive power amplifier core 200. Figure 4 In the example shown, the main power amplifier 106 and the auxiliary power amplifier 108 can include a matching network 402 and a matching network 404. The driver 102 can include a matching network 406 and a matching network 408.

[0044] Figure 5 It is shown that various embodiments according to the present disclosure can provide Figure 1104. As described above, the IQ network 500 may include a power splitter 502 and a phase shifter 504. The power splitter 502 may split a driver output signal or other input signal, and the phase shifter 504 may shift a signal on a line to which it is coupled (e.g., a line providing a signal to the auxiliary power amplifier 108). Although illustrated as a power splitter 502 that splits a signal into two lines, other splitter configurations are illustrated (e.g., 3-way, 4-way, or other configurations that are obvious to those skilled in the art). In some embodiments, the phase shifter 504 may produce a quadrature (90 degree) phase shift. However, other phase shifts may also be considered. The phase shifter 504 may include an orthogonal hybrid coupler, a Lange coupler, a polyphase filter quadrature splitter, a Scheffman phase shifter, a branch line coupler, a power splitter with a delay line, or any other phase shifter that is obvious to those skilled in the art having the present disclosure. In various embodiments, a phase shifter is located on the auxiliary power amplifier input 108a, while the main power amplifier input 106a does not include a phase shifter. Figure 6 Shown as Figure 1 An IQ network 600 of another embodiment of the IQ network 104 is shown.

[0045] Figure 7 is a block diagram of an example power amplifier 700 that may utilize the dual-drive power amplifier core 200 (described above) according to various embodiments of the present disclosure. Various arrangements may be configured to utilize the dual-drive power amplifier core 200 without departing from the scope of the present disclosure. Figure 7 A practical example of how other stages (e.g., input matching network 702, driver 704, interstage matching network 706, and / or output network 708) may be used for dual-drive power amplifier core 200 is depicted. Power amplifier 700 may be used as at least one of main power amplifier 106 or auxiliary power amplifier 108.

[0046] Fig. 8A Graph 800a showing the input impedance of a dual drive power amplifier, Figure 8B The value of α is 0.3. Figure 2 800b is a graph of the input impedance of the dual-drive power amplifier core 200. One of the advantages of the dual-drive based Doherty PA is the reduced input impedance of the transistors because the device gate impedance is in parallel with its low source impedance, which can also be designed through source coupling α, thereby simplifying the design of broadband and low loss inter-stage matching networks without the need for de-Qing resistors. Fig. 9 A small signal dual-drive transistor model 900 is shown for deriving input impedance, which includes a dual-drive coupling network and inductor degeneration. The input impedance of the dual-drive power amplifier core 200 can be expressed using the following equation:

[0047]

[0048]

[0049]

[0050]

[0051]

[0052]

[0053]

[0054]

[0055]

[0056]

[0057]

[0058]

[0059] Among them, R p is a parallel representation of the degenerated gate resistance caused by the added source inductance of the dual drive coupling network. The real part of the input impedance Z in Will be The input impedance is determined by the term since it is the smallest term. Furthermore, the input impedance becomes a design choice and can be easily adjusted by varying the coupling between source and gate.

[0060] Thus, a system and method for providing a dual-drive Doherty power amplifier has been described. A Doherty power combination of a main / auxiliary PA core using a dual-drive configuration is employed. Conventional Doherty PA architectures can support PBO efficiency enhancement through active load modulation. However, due to the limited gain and loss of the power combination / IQ power distribution network, the peak efficiency of the conventional Doherty PA architecture is limited. Dual-drive PA cores for main / auxiliary PAs help alleviate these problems. The increased peak efficiency due to the dual-drive PA cores for main / auxiliary can compensate for the reduced peak efficiency due to the Doherty power combination network while still maintaining the improved PBO efficiency, greatly increasing the average efficiency achievable under modulation. In addition, since the dual-drive topology combines common-gate and common-source amplifiers, the input impedance of the PA core is greatly reduced. This minimizes the impedance transformation required for the matching network of the dual-drive core input interface, extends the achievable bandwidth of the Doherty PA, and minimizes the losses within the matching network. The reduction in matching network losses increases the overall gain of the PA, further improving the peak efficiency, thereby improving the modulation efficiency achievable by the Doherty PA. The superior performance perfectly positions the PA architecture as a highly efficient topology for commercial applications such as wireless communications, radar, satellite communications, and other applications that will be apparent to those skilled in the art in possession of this disclosure.

[0061] In the block diagram, the components shown are depicted as discrete functional blocks, but the embodiments are not limited to systems in which the functions described herein are organized as shown. The functions provided by each component may be provided by software or hardware modules that are organized differently from the present description, for example, such software or hardware may be mixed, combined, copied, decomposed, distributed (for example, within a data center or geographically), or otherwise organized differently. The functions described herein may be provided by one or more processors of one or more computers that execute code stored on a tangible, non-transitory machine-readable medium. In some cases, although the singular term "medium" is used, the instructions may be distributed on different storage devices associated with different computing devices, for example, each computing device has a different subset of instructions, which is consistent with the use of the singular term "medium" herein. In some cases, a third-party content delivery network may host some or all of the information transmitted over the network, in which case, to the extent that the information (e.g., content) is considered to be provided or otherwise provided, the information may be provided by sending instructions to retrieve the information from the content delivery network.

[0062] The reader should understand that this application describes several independently useful technologies. Instead of separating these technologies into multiple independent patent applications, the applicant grouped these technologies into a single file because their related themes contribute to the economy in the application process. However, the different advantages and aspects of these technologies should not be lumped together. In some cases, the embodiments solve all the defects mentioned here, but it should be understood that these technologies are independently useful, and some embodiments only solve a subset of these problems or provide other unmentioned benefits, which are obvious to those skilled in the art who read this disclosure. Due to cost constraints, some of the technologies disclosed herein may not be claimed for protection at present, but may be claimed in later applications, such as continued applications or by amending the present claims. Similarly, due to space limitations, the abstract and overview of the invention section of this document should not be regarded as a comprehensive list containing all these technologies or all aspects of these technologies.

[0063] It should be understood that the description and the drawings are not intended to limit the present technology to the specific form disclosed, on the contrary, the present invention is intended to cover all modifications, equivalents and substitutes that fall within the spirit and scope of the present technology defined by the appended claims. In view of this description, further modifications and alternative embodiments of various aspects of the present technology will be obvious to those skilled in the art. Therefore, the description and the drawings are interpreted as illustrative only, and are intended to teach those skilled in the art to implement the general way of the present technology. It should be understood that the forms of the present technology shown and described here will be regarded as examples of embodiments. Elements and materials can replace those shown and described here, parts and processes can be reversed or omitted, and certain features of the present technology can be used independently, all of which are obvious to those skilled in the art who benefit from the description of the present technology. Without departing from the spirit and scope of the present technology described in the appended claims, changes can be made to the elements described here. The titles used here are only for organizational purposes and are not meant to limit the scope of the description.

[0064] As used throughout this application, the word "may" is used in a permissive sense (i.e., meaning that it is possible), rather than in a mandatory sense (i.e., meaning that it must be). The words "include" and "comprises" and the like mean including, but not limited to. As used throughout this application, the singular forms "a", "an" and "the" include plural referents unless the context clearly indicates otherwise. Thus, for example, references to "an element" include combinations of two or more elements, although other terms and phrases, such as "one or more", are used for one or more elements. Unless otherwise indicated, the term "or" is non-exclusive, i.e., includes "and" and "or" terms describing conditional relationships, such as, "in response to X, Y", "based on X, Y", "if X, Y", "when X, Y", etc., including causal relationships, where the antecedent is a necessary causal condition, the antecedent is a sufficient causal condition, or the antecedent is a causal condition that contributes to the result, for example, "state X occurs when condition Y is obtained" is equivalent to "X only occurs when Y" and "X occurs on the basis of Y and Z". This conditional relationship is not limited to results immediately after the antecedent condition is obtained, because some results may be delayed, and in the conditional statement, the antecedent conditions are related to their results, for example, the antecedent conditions are related to the probability of the result occurring. Unless otherwise specified, a statement in which multiple attributes or functions are mapped to multiple objects (e.g., one or more processors perform steps A, B, C, and D) includes all of these attributes or functions being mapped to all of these objects, and subsets of attributes or functions being mapped to subsets of attributes or functions (e.g., all processors perform steps AD, and processor 1 performs step A, processor 2 performs step B and part of step C, and processor 3 performs step C and part of step D). Similarly, references to a "computer system" that performs step A and a "computer system" that performs step B may include the same computing device within a computer system that performs both steps or different computing devices within a computer system that performs steps A and B. In addition, unless otherwise specified, a statement that a value or action is "based on" another condition or value includes both the case where the condition or value is the only factor and the case where the condition or value is one of multiple factors. Unless otherwise stated, a statement that "each" instance of a certain set has certain properties should not be read as excluding the case where certain identical or similar members of the larger set do not have that property, i.e., each does not necessarily mean every. Limitations on the order of steps should not be read as claims unless expressly stated, for example, using explicit language such as "after performing X, performing Y", as opposed to statements that might be improperly construed to imply an order limitation, such as "perform X on item, perform Y on item X", which is used for the purpose of making the claim more readable rather than to prescribe an order.Statements referring to "at least Z of A, B, and C," etc. (e.g., "at least Z of A, B, or C") refer to at least Z of the listed categories (A, B, and C), and do not require at least Z elements in each category. Unless otherwise stated, it will be apparent from the discussion that it should be understood that throughout the discussion of this specification, terms such as "processing," "computing," "determining," etc., are used to refer to the actions or processes of a specific device, such as a special purpose computer or similar special purpose electronic processing / computing device. Features described with reference to geometric configurations, such as "parallel," "perpendicular / orthogonal," "square," "cylindrical," etc., should be interpreted as including items that substantially embody the properties of the geometric configurations, for example, "parallel" surfaces include substantially parallel surfaces. Reference is made to the ranges in the specification to determine the permissible ranges of deviations from the Platonic ideal for these geometric configurations, and if such ranges are not stated, reference is made to industry norms in the field of use, and if such ranges are not defined, reference is made to industry norms in the field of manufacture of the specified features, and if such ranges are not defined, features that substantially embody the geometric configurations should be interpreted as including those features that are within 15% of the defined properties of the geometric configurations. The terms "first", "second", "third", "given", etc., if used in the claims, are used to distinguish or identify, not to indicate order or numerical limitation. As is the case in ordinary usage in the art, data structures and formats described with reference to uses that are obvious to humans need not be presented in a human-understandable format to constitute the described data structures or formats, for example, text need not be presented or even encoded in Unicode or ASCII to constitute text; images, maps, and data visualizations need not be displayed or decoded to constitute images, maps, and data visualizations, respectively; speech, music, and other audio need not be emitted through speakers or decoded to constitute speech, music, or other audio, respectively. Computer-implemented instructions, commands, etc. are not limited to executable code, and may be implemented in the form of data that causes the function to be invoked, such as in the form of arguments to a function or API call. In the case where custom noun phrases (and other coined terms) are used in the claims and lack a self-explanatory structure, the definition of such phrases may be recited in the claims themselves, in which case the use of such custom noun phrases should not be construed as imparting additional limitations by inspection of the specification or external evidence.

[0065] In this patent, any U.S. patent, U.S. patent application, or other material (e.g., article) is incorporated by reference into this patent, and the text of these materials is incorporated by reference only to the extent that there is no conflict between these materials and the statements and drawings set forth in this patent. In the event of such a conflict, the text of this document controls, and the terms in this document should not be given a narrower interpretation due to the way those terms are used in other materials incorporated by reference.

[0066] The present technology will be better understood with reference to the following examples:

[0067] 1. A dual-drive based Doherty amplifier, comprising: a power divider; a first power amplifier coupled to a first output of the power divider; and a second power amplifier coupled to a second output of the power divider and connected in parallel with the first power amplifier, wherein the second power amplifier receives a phase second output signal of a first output signal from the first output from a second output having a phase difference, wherein at least one of the first power amplifier or the second power amplifier comprises a dual-drive power amplifier core.

[0068] 2. A dual-drive based Doherty amplifier according to embodiment 1, wherein the dual-drive power amplifier core comprises: a transistor differential pair, each transistor having a gate terminal, a drain terminal and a source terminal; and a multi-feed coupling network, configured to: drive the dual-drive power amplifier core out of phase at the gate terminal and the source terminal by allowing the transistor differential pair to be driven out of phase at the gate terminal and the source terminal; and allow the source terminal and the drain terminal to swing in phase.

[0069] 3. A dual-drive based Doherty amplifier according to any one of embodiments 1-2, wherein the dual-drive power amplifier core comprises: a core first output terminal Vout+, configured to be connected to the drain terminal of the first transistor; a core second output terminal Vout-, configured to be connected to the drain terminal of the second transistor; and a transmission line coupler, the first transmission line coupler comprising a transmission line portion having a first end configured to receive a core first input signal Vin+, the second transmission line coupler comprising a transmission line portion having a first end configured to receive a core first input signal Vin-, wherein the core first output terminal and the core second output terminal are configured to output an amplified differential signal corresponding to the difference between the core first input signal Vin+ and the core second input signal Vin-.

[0070] 4. A dual-drive based Doherty amplifier according to embodiment 3, wherein the dual-drive power amplifier core comprises: a first transistor comprising a first transistor M1 having an M1 gate terminal, a drain terminal comprising an M1 drain terminal and an M1 source terminal; and a second transistor comprising a second transistor M2 having an M2 gate terminal, a drain terminal comprising an M2 drain terminal, and an M2 source terminal, wherein the first transmission line coupler further comprises a first transmission line portion T1 having a first end and a second end, wherein the first end is grounded and the second end is connected to the M1 source terminal, wherein the transmission line portion having a first end configured to receive a first input signal Vin+ of the core comprises a second transmission line portion of the first transmission line coupler. The invention relates to a transmission line segment T2, wherein the second transmission line segment T2 further has a second end connected to the M2 gate terminal and coupled to the M1 drain terminal, wherein the first transmission line segment T1 is electromagnetically coupled to the second transmission line segment T2, wherein the second transmission line coupler further includes a third transmission line segment T3 having a first end and a second end, wherein the first end is grounded and the second end is connected to the M2 source terminal, wherein the transmission line segment having a first end configured to receive the core first input signal Vin- comprises a fourth transmission line segment T4, wherein the fourth transmission line segment T4 further has a second end connected to the M1 gate terminal and coupled to the M2 drain terminal, and wherein the third transmission line segment T3 is electromagnetically coupled to the fourth transmission line segment T4.

[0071] 5. The dual-drive based Doherty amplifier according to any one of embodiments 1-4 further comprises: a driver comprising a driver input and a driver output, wherein the driver output is coupled to the input of the power divider.

[0072] 6. The dual-drive based Doherty amplifier of embodiment 5, wherein the driver comprises a second dual-drive power amplifier core.

[0073] 7. The dual-drive based Doherty amplifier according to any one of embodiments 1-6, wherein the dual-drive power amplifier core improves broadband operation of the dual-drive based Doherty amplifier due to a reduction in input impedance at the dual-drive power amplifier core.

[0074] 8. According to the dual-drive based Doherty amplifier of any one of embodiments 1-7, the first power amplifier is a class AB amplifier, and the second power amplifier is a class C amplifier.

[0075] 9. The dual-drive based Doherty amplifier according to any one of embodiments 1-8, further comprising an impedance converter coupled to a power amplifier output of the first power amplifier.

[0076] 10. The dual-drive based Doherty amplifier according to embodiment 9, further comprising an output matching network coupled to the impedance converter and a power amplifier output of the second power amplifier, wherein an output matching network output is provided to a load.

[0077] 11. A dual-drive based Doherty amplifier, comprising: a first power amplifier; and a second power amplifier connected in parallel with the first power amplifier, wherein the first power amplifier is configured to receive a first portion of a signal having a first phase, and wherein the second power amplifier receives a second portion of a signal having a second phase having a phase difference from the first phase, and wherein at least one of the first power amplifier or the second power amplifier includes a dual-drive power amplifier core.

[0078] 12. A dual-drive based Doherty amplifier according to embodiment 11, wherein the dual-drive power amplifier core comprises: a transistor differential pair, each transistor having a gate terminal, a drain terminal and a source terminal; and a multi-feed coupling network, configured to: drive the dual-drive power amplifier core out of phase at the gate terminal and the source terminal by allowing the transistor differential pair to be driven out of phase at the gate terminal and the source terminal; and allow the source terminal and the drain terminal to swing in phase.

[0079] 13. A dual-drive based Doherty amplifier according to embodiment 12, wherein the multi-feed coupling network: couples the input signal from the gate terminal of the first transistor of the transistor differential pair to the source terminal of the second transistor of the transistor differential pair; and the gate terminal of the second transistor to the source terminal of the first transistor; while providing a non-zero DC voltage to the gate terminal and a DC ground to the source terminal.

[0080] 14. The dual-drive based Doherty amplifier according to any one of embodiments 11-13 further comprises: an in-phase quadrature (IQ) network, wherein the IQ network comprises a power divider configured to receive an input signal and divide the input signal into a first part of the signal and a second part of the signal.

[0081] 15. The dual-drive based Doherty amplifier according to any one of embodiments 11-14, further comprising: a driver comprising a driver input and a driver output, wherein the driver output is coupled to the input of the power divider.

[0082] 16. The dual-drive based Doherty amplifier of embodiment 15, wherein the driver comprises a second dual-drive power amplifier core.

[0083] 17. The dual-drive based Doherty amplifier of any one of embodiments 11-16, wherein the dual-drive power amplifier core improves broadband operation of the dual-drive based Doherty amplifier due to a reduction in input impedance at the dual-drive power amplifier core.

[0084] 18. The dual-drive based Doherty amplifier according to any one of embodiments 11-17, wherein the first power amplifier is a class AB amplifier and the second power amplifier is a class C amplifier.

[0085] 19. The dual-drive based Doherty amplifier of any one of embodiments 11-18, further comprising an impedance converter coupled to a power amplifier output of the first power amplifier.

[0086] 20. The dual-drive based Doherty amplifier according to embodiment 19, further comprising an output matching network coupled to the impedance converter and a power amplifier output of the second power amplifier, wherein an output matching network output is provided to a load.

Claims

1. A dual-drive Doherty amplifier, characterized in that: include: Power divider; a first power amplifier coupled to a first output of the power divider; as well as a second power amplifier coupled to a second output of the power divider and connected in parallel with the first power amplifier, Wherein the second power amplifier receives a phase second output signal of the first output signal from the first output from the second output having a phase difference, wherein at least one of the first power amplifier or the second power amplifier includes a dual drive power amplifier core.

2. The dual-drive based Doherty amplifier according to claim 1, characterized in that: The dual-drive power amplifier core comprises: a differential pair of transistors, each transistor having a gate terminal, a drain terminal, and a source terminal; as well as A multi-feed coupling network, wherein the multi-feed coupling network is configured as: driving the dual drive power amplifier core out of phase at the gate terminals and the source terminals by allowing the differential pair of transistors to be driven out of phase at the gate terminals and the source terminals; The source terminal and the drain terminal are allowed to swing in phase.

3. The dual-drive based Doherty amplifier according to claim 1, characterized in that: The dual-drive power amplifier core comprises: a core first output terminal Vout+, the core first output terminal Vout+ being configured to be connected to a drain terminal of the first transistor; a core second output terminal Vout-, the core second output terminal Vout- being configured to be connected to a drain terminal of the second transistor; as well as a transmission line coupler, the first transmission line coupler comprising a transmission line portion having a first end configured to receive a core first input signal Vin+, the second transmission line coupler comprising a transmission line portion having a first end configured to receive a core first input signal Vin-, The first core output terminal and the second core output terminal are configured to output an amplified differential signal corresponding to the difference between the first core input signal Vin+ and the second core input signal Vin-.

4. The dual-drive based Doherty amplifier according to claim 3, characterized in that: The dual-drive power amplifier core comprises: the first transistor, the first transistor comprising a first transistor M1 having an M1 gate terminal, a drain terminal comprising an M1 drain terminal and an M1 source terminal; as well as the second transistor, the second transistor comprising a second transistor M2 having an M2 gate terminal, a drain terminal including an M2 drain terminal, and an M2 source terminal, wherein the first transmission line coupler further comprises a first transmission line section T1 having a first end and a second end, wherein the first end is grounded and the second end is connected to the M1 source terminal, wherein the transmission line portion having a first end configured to receive a core first input signal Vin+ comprises a second transmission line portion T2 of the first transmission line coupler, wherein the second transmission line portion T2 further has a second end connected to the M2 gate terminal and coupled to the M1 drain terminal, The first transmission line portion T1 is electromagnetically coupled to the second transmission line portion T2. wherein the second transmission line coupler further comprises a third transmission line section T3 having a first end and a second end, wherein the first end is grounded and the second end is connected to the M2 source terminal, wherein the transmission line portion having the first end configured to receive the core first input signal Vin- comprises a fourth transmission line portion T4, wherein the fourth transmission line portion T4 further has a second end connected to the M1 gate terminal and coupled to the M2 drain terminal, and The third transmission line portion T3 is electromagnetically coupled to the fourth transmission line portion T4.

5. The dual-drive based Doherty amplifier according to claim 1, characterized in that: Further including: A driver includes a driver input and a driver output, wherein the driver output is coupled to the input of the power divider.

6. The dual-drive based Doherty amplifier according to claim 5, characterized in that: The driver includes a second dual-drive power amplifier core.

7. The dual-drive based Doherty amplifier according to claim 1, characterized in that: The dual-drive power amplifier core improves broadband operation of a dual-drive based Doherty amplifier due to the reduction of input impedance at the dual-drive power amplifier core.

8. The dual-drive based Doherty amplifier according to claim 1, characterized in that: The first power amplifier is a class AB amplifier, and the second power amplifier is a class C amplifier.

9. The dual-drive based Doherty amplifier according to claim 1, characterized in that: Also included is an impedance converter coupled to a power amplifier output of the first power amplifier.

10. The dual-drive based Doherty amplifier according to claim 9, characterized in that: Further comprising an output matching network coupled to the impedance converter and a power amplifier output of the second power amplifier, wherein an output matching network output is provided to a load.

11. A dual-drive Doherty amplifier, characterized in that: include: a first power amplifier; and a second power amplifier connected in parallel with the first power amplifier, wherein the first power amplifier is configured to receive a first portion of a signal having a first phase, and wherein the second power amplifier receives a second portion of a signal having a second phase having a phase difference from the first phase, and wherein at least one of the first power amplifier or the second power amplifier comprises a dual drive power amplifier core.

12. The dual-drive based Doherty amplifier according to claim 11, characterized in that: The dual-drive power amplifier core comprises: a differential pair of transistors, each transistor having a gate terminal, a drain terminal, and a source terminal; as well as The multi-feed coupling network is configured as: driving the dual drive power amplifier core out of phase at the gate terminals and the source terminals by allowing the differential pair of transistors to be driven out of phase at the gate terminals and the source terminals; as well as The source terminal and the drain terminal are allowed to swing in phase.

13. The dual-drive based Doherty amplifier according to claim 12, characterized in that: The multi-feed coupling network: coupling an input signal from the gate terminal of a first transistor of the transistor differential pair to the source terminal of a second transistor of the transistor differential pair; and The gate terminal of the second transistor is connected to the source terminal of the first transistor; a non-zero DC voltage is provided to the gate terminal, and a DC ground is provided to the source terminal.

14. The dual-drive based Doherty amplifier according to claim 11, characterized in that: Further including: An in-phase quadrature (IQ) network, wherein the IQ network comprises a power splitter configured to receive an input signal and split the input signal into the first portion of the signal and the second portion of the signal.

15. The dual-drive based Doherty amplifier according to claim 14, characterized in that: Further including: A driver includes a driver input and a driver output, wherein the driver output is coupled to the input of the power divider.

16. The dual-drive based Doherty amplifier according to claim 15, characterized in that: in, The driver includes a second dual-drive power amplifier core.

17. The dual-drive based Doherty amplifier according to claim 11, characterized in that: The dual-drive power amplifier core improves broadband operation of a dual-drive based Doherty amplifier due to the reduction of input impedance at the dual-drive power amplifier core.

18. The dual-drive based Doherty amplifier according to claim 11, characterized in that: The first power amplifier is a class AB amplifier, and the second power amplifier is a class C amplifier.

19. The dual-drive based Doherty amplifier according to claim 11, characterized in that: Further comprising an impedance converter coupled to a power amplifier output of the first power amplifier.

20. The dual-drive based Doherty amplifier according to claim 19, characterized in that: Further comprising an output matching network coupled to the impedance converter and a power amplifier output of the second power amplifier, wherein an output matching network output is provided to a load.

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