A reliability testing method for semiconductor laser chip

Abstract

The present invention discloses a reliability test method for semiconductor laser chips, and relates to the field of laser chips. The method comprises: selecting multiple test chips from the same batch of laser chips; testing the power of multiple test chips as the current changes at different test temperatures to determine the high temperature aging condition and the high power aging condition; selecting multiple high temperature aging chips and multiple high power aging chips from the same batch of laser chips; performing high temperature aging on multiple high temperature aging chips under the high temperature aging condition, and counting the number of high temperature failures; performing high power aging on multiple high power aging chips under the high power aging condition, and counting the number of high power failures; judging the main factors affecting the reliability of the laser chips from the same batch according to the number of high temperature failures and the number of high power failures. The reliability test method for conductor laser chips provided by the present invention can judge the main factors affecting the reliability of laser chips from the same batch.

Description

Technical Field

[0001] The present invention relates to the field of laser chips, and in particular to a reliability testing method for semiconductor laser chips. Background Art

[0002] Reliability is an important factor in the manufacture of semiconductor laser chips. The level of reliability largely determines the service life and scope of application of the laser chip.

[0003] At present, the market only has means to evaluate the reliability of semiconductor laser chips, but lacks methods to judge the main factors affecting reliability, resulting in the inability to provide optimization basis for the mass production process of laser chips. Summary of the invention

[0004] The purpose of the present invention is to provide a reliability testing method for semiconductor laser chips, which can determine the main factors affecting the reliability of laser chips in the same batch, and can provide an optimization basis for the production process to improve the quality of batch laser chips.

[0005] The embodiment of the present invention provides a technical solution:

[0006] A reliability testing method for a semiconductor laser chip, comprising:

[0007] Selecting a plurality of test chips from the same batch of laser chips;

[0008] Testing the power of a plurality of test chips as the current changes at a plurality of different test temperatures;

[0009] According to the power test results, determine the high temperature aging conditions and high power aging conditions;

[0010] Selecting a plurality of high-temperature aged chips and a plurality of high-power aged chips from the same batch of laser chips;

[0011] Performing high temperature aging for a set time on the plurality of high temperature aging chips under the high temperature aging conditions, and counting the number of high temperature failures in the plurality of high temperature aging chips after the aging is completed;

[0012] Performing high-power aging for the set time period on the plurality of high-power aging chips under the high-power aging condition, and counting the number of high-power failures in the plurality of high-power aging chips after the aging is completed;

[0013] According to the number of high-temperature failures and the number of high-power failures, main factors affecting the reliability of laser chips in the same batch are determined.

[0014] In an optional embodiment, the step of respectively testing the power of a plurality of test chips as the current changes at a plurality of different test temperatures comprises:

[0015] Setting a plurality of incremental test temperatures, wherein the difference between two adjacent test temperatures is the same, and the highest test temperature is 3 to 4 times the operating temperature of the laser chip;

[0016] Gradually increasing currents are loaded onto the multiple test chips at the multiple test temperatures, and the powers of the multiple test chips are monitored respectively, wherein the maximum value of the current loaded onto the multiple test chips is 2 to 3 times the operating current of the laser chip.

[0017] In an optional implementation manner, the step of determining the high temperature aging condition and the high power aging condition according to the power test result includes:

[0018] Drawing a power-current relationship diagram of a plurality of the test chips to obtain a plurality of thermal reversal currents at the test temperatures;

[0019] Selecting the one with the highest test temperature corresponding to the multiple thermal reversal currents and the corresponding test temperature as the high temperature aging condition;

[0020] The one with the highest power corresponding to the multiple thermal reversal currents and the corresponding test temperature are selected as the high-power aging condition.

[0021] In an optional embodiment, the number of the plurality of high-temperature aged chips is consistent with the number of the plurality of high-power aged chips, and the step of determining the main factors affecting the reliability of the laser chips in the same batch according to the number of high-temperature failures and the number of high-power failures includes:

[0022] If the number of high-temperature failures is greater than the number of high-power failures, it is determined that the epitaxial quality is the main factor affecting the reliability of the laser chips in the same batch;

[0023] If the number of high-power failures is greater than the number of high-temperature failures, it is determined that the cavity surface process is the main factor affecting the reliability of the laser chips in the same batch.

[0024] In an optional embodiment, the step of selecting a plurality of test chips from the same batch of laser chips includes:

[0025] Selecting a plurality of the test chips on the same wafer;

[0026] The step of selecting the same number of high-temperature aged chips and high-power aged chips from the same batch of laser chips comprises:

[0027] Selecting a first preset number of the high-temperature aging chips and the high-power aging chips respectively on the wafer to which the plurality of test chips belong;

[0028] A second preset number of the high-temperature aging chips and the high-power aging chips are respectively selected from wafers of a different tape-out batch from the wafers to which the plurality of test chips belong.

[0029] In an optional embodiment, after the step of performing high-power aging for the set duration on the plurality of high-power aging chips under the high-power aging condition and counting the number of high-power failures in the plurality of high-power aging chips after aging, the method further includes:

[0030] The Arrhenius model applied to the laser chips of the same batch is modified according to the number of high-temperature failures and the number of high-power failures.

[0031] In an optional embodiment, the step of correcting the Arrhenius model applied to the laser chips of the same batch according to the number of high-temperature failures and the number of high-power failures includes:

[0032] If the number of high-power failures is greater than the number of high-temperature failures, a power pressure factor is added to the Arrhenius model applied to the laser chips of the same batch to obtain a new Arrhenius model:

[0033] ;

[0034] If the number of high-temperature failures is greater than the number of high-power failures, the power pressure factor is removed from the Arrhenius model applied to the laser chips of the same batch to obtain a new Arrhenius model:

[0035] .

[0036] In an optional embodiment, before the step of selecting a plurality of high-temperature aged chips and a plurality of high-power aged chips from the same batch of laser chips, the method further includes:

[0037] The reliability of the high temperature aging condition and / or the high power aging condition is verified according to an Arrhenius model.

[0038] In an optional embodiment, the step of verifying the reliability of the high temperature aging condition according to the Arrhenius model includes:

[0039] According to the Arrhenius model, the high temperature acceleration factor corresponding to the high temperature aging condition is calculated;

[0040] Selecting the same number of multiple high-temperature verification chips and multiple normal aging chips from the same batch of laser chips;

[0041] Performing high-temperature aging on the plurality of high-temperature verification chips under the high-temperature aging conditions, and allowing the plurality of normal aging chips to operate normally under normal operating conditions;

[0042] If the failure number of the high temperature verification chip is equal to the failure number of the normal aging chip, and the ratio of the high temperature aging time to the normal operation time is equal to the high temperature acceleration factor, then the high temperature aging condition is determined to be reliable.

[0043] In an optional embodiment, the step of verifying the reliability of the high power aging condition according to the Arrhenius model includes:

[0044] Calculating a high-power acceleration factor corresponding to the high-power aging condition according to an Arrhenius model;

[0045] Selecting the same number of multiple high-power verification chips and multiple normal aging chips from the same batch of laser chips;

[0046] Performing high-power aging on the plurality of high-power verification chips under the high-power aging conditions, and allowing the plurality of normal aging chips to operate normally under normal working conditions;

[0047] If the number of failures of the high-power verification chip is equal to the number of failures of the normal aging chip, and the ratio of the high-power aging duration to the normal operation duration is equal to the high-power acceleration factor, then the high-power aging condition is determined to be reliable.

[0048] Compared with the prior art, the reliability test method of the semiconductor laser chip provided by the present invention determines the high temperature aging condition and the high power aging condition, and performs high temperature aging on part of the laser chips in the same batch under the high temperature aging condition, and performs high power aging on another part under the high power aging condition, and finally determines the main factors affecting the reliability of the laser chips in the same batch according to the comparison of the laser chips that fail under the two aging treatments, determines the problems existing in the laser chips in the same batch, and provides an optimization basis for the production process of the corresponding model of batch laser chips to improve the quality. Therefore, the beneficial effects of the reliability test method of the semiconductor laser chip provided by the present invention include: being able to judge the main factors affecting the reliability of the laser chips in the same batch, and being able to provide an optimization basis for the production process to improve the quality of the batch laser chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative work.

[0050] Figure 1 A flowchart of a reliability testing method for a semiconductor laser chip provided by an embodiment of the present invention;

[0051] Figure 2 for Figure 1 A sub-step flow chart of step S102;

[0052] Figure 3 for Figure 1 A sub-step flow chart of step S103;

[0053] Figure 4 for Figure 3 A power-current relationship diagram of a plurality of the test chips drawn in sub-step S1031;

[0054] Figure 5 for Figure 1 A sub-step flow chart of step S104;

[0055] Figure 6 for Figure 1 Another sub-step flow chart of step S104;

[0056] Figure 7 for Figure 1 A sub-step flow chart of step S108;

[0057] Figure 8 for Figure 1 Another sub-step flow chart of step S108 in FIG. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0059] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0060] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0061] In the description of the present invention, it should be understood that the terms "upper", "lower", "inside", "outside", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use, or are directions or positional relationships commonly understood by those skilled in the art. These directions or positional relationships are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0062] Furthermore, the terms “first”, “second”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0063] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms such as "setting" and "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0064] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings.

[0065] Example

[0066] See also Figure 1 , Figure 1 The figure shows a flowchart of a reliability test method for semiconductor laser chips provided in this embodiment. The method is used to determine the main factors affecting the reliability of laser chips of the same model in the same batch, which may specifically include:

[0067] Step S101 , selecting a plurality of test chips from the same batch of laser chips.

[0068] It can be understood that the reliability testing method for semiconductor laser chips provided in this embodiment is aimed at laser chips of the same batch, which refers to batch products produced by the same process. Laser chips of the same batch can come from wafers of different tape-out batches.

[0069] Preferably, in this embodiment, multiple test chips are selected from the same wafer.

[0070] Step S102 , testing the power of multiple test chips as the current changes at multiple different test temperatures.

[0071] Please refer to Figure 2 , Figure 2 The figure shows a sub-step flow chart of step S102. Step S102 may include the following sub-steps:

[0072] Sub-step S1021, setting a plurality of increasing test temperatures.

[0073] The difference between two adjacent test temperatures is the same, and the highest test temperature is 3 to 4 times the operating temperature of the laser chip.

[0074] In this embodiment, four test temperatures are set, namely 25° C., 45° C., 65° C. and 85° C., that is, the difference between two adjacent test temperatures is 20° C.

[0075] Sub-step S1022 , loading gradually increasing currents on the multiple test chips at multiple test temperatures, and monitoring the power of the multiple test chips respectively.

[0076] The maximum value of the current loaded on the multiple test chips is 2 to 3 times the working current of the laser chip. In this embodiment, the maximum value of the loaded current is 3.3A.

[0077] Please continue reading Figure 1 The reliability testing method of the semiconductor laser chip provided in this embodiment may further include:

[0078] Step S103, determining high temperature aging conditions and high power aging conditions according to the power test result.

[0079] Please refer to Figure 3 , Figure 3 The figure shows a sub-step flow chart of step S103. Step S103 may include the following sub-steps:

[0080] Sub-step S1031 , drawing a power-current relationship diagram of multiple test chips to obtain thermal inversion currents at multiple test temperatures.

[0081] Please refer to Figure 4 , Figure 4The figure shows the power-current relationship diagram of multiple test chips drawn in sub-step S1031 in this embodiment.

[0082] It can be understood that the thermal reversal current refers to the current corresponding to when the power changes from a gradually increasing trend to a decreasing trend as the current increases at a specific temperature.

[0083] Depend on Figure 4 It can be seen that when the test temperature is 25°C, when the loaded current reaches the maximum value of 3.3A, thermal reversal still does not occur; when the test temperature is 45°C, there is a thermal reversal current of 3A; when the test temperature is 65°C, there is a thermal reversal current of 2.6A; when the test temperature is 85°C, there is a thermal reversal current of 2A.

[0084] Sub-step S1032, selecting the one with the highest corresponding test temperature among the multiple thermal reversal currents and its corresponding test temperature as the high temperature aging condition.

[0085] In this embodiment, 2A and its corresponding 85° C. are selected from 2A, 2.6A and 3A, that is, the high temperature aging condition is a temperature of 85° C. and a current of 2A.

[0086] Sub-step S1033, selecting the one with the highest power corresponding to the multiple thermal reversal currents and its corresponding test temperature as the high-power aging condition.

[0087] In this embodiment, 3A and its corresponding 45° C. are selected from 2A, 2.6A and 3A, that is, the high-power aging condition is a temperature of 45° C. and a current of 3A.

[0088] Please continue reading Figure 1 The reliability testing method of the semiconductor laser chip provided in this embodiment may further include:

[0089] Step S104 , verifying the reliability of the high temperature aging condition and / or the high power aging condition according to the Arrhenius model.

[0090] Please refer to Figure 5 , Figure 5 The figure shows a sub-step flow chart of step S104. Step S104 may include the following sub-steps:

[0091] Sub-step S1041, calculating the high temperature acceleration factor corresponding to the high temperature aging condition according to the Arrhenius model.

[0092] The temperature of 85°C and the current of 2A corresponding to the high temperature aging condition are brought into the Arrhenius model to calculate the high temperature acceleration factor. It can be understood that the high temperature acceleration factor refers to the ratio of the failure time of the laser chip under high temperature aging conditions to the failure time under normal working conditions.

[0093] Sub-step S1042 , selecting a plurality of high-temperature verification chips and a plurality of normal aging chips of the same number from the same batch of laser chips.

[0094] In this embodiment, high temperature verification chips and normal aging chips are selected from a wafer to which multiple test chips belong. In this embodiment, the number of high temperature verification chips and normal aging chips is 32.

[0095] Sub-step S1043, performing high-temperature aging on a plurality of high-temperature verification chips under high-temperature aging conditions, and allowing a plurality of normal aging chips to operate normally under normal operating conditions.

[0096] At a temperature of 85°C, multiple high-temperature verification chips were loaded with a current of 2A and operated for 168 hours, while multiple normal aging chips were operated at the operating temperature and operating current for 168 hours.

[0097] Sub-step S1044, if the failure number of the high temperature verification chip is equal to the failure number of the normal aging chip, and the ratio of the high temperature aging time to the normal operation time is equal to the high temperature acceleration factor, it is determined that the high temperature aging condition is reliable.

[0098] For example, if the high temperature acceleration factor is 2, the number of failures of 32 high temperature verification chips when running for 84 hours is the same as the number of failures of 32 normal aging chips when running for 168 hours, then the high temperature aging condition is determined to be accurate and reliable. If they are not equal, steps S101 to S103 can be repeated, and multiple test temperatures and maximum current values ​​can be reset to re-determine the high temperature aging condition and perform verification.

[0099] It should be noted that in actual applications, the ratio of the high-temperature aging time to the normal operation time in sub-step S1044 does not necessarily need to be completely equal to the high-temperature acceleration factor. A certain error is allowed, and the larger the high-temperature acceleration factor, the larger the allowable error.

[0100] Please refer to Figure 6 , Figure 6 The figure shows another sub-step flow chart of step S104. Step S104 may also include the following sub-steps:

[0101] Sub-step S1045, calculating the high-power acceleration factor corresponding to the high-power aging condition according to the Arrhenius model.

[0102] Similarly, the temperature of 45°C and the current of 3A corresponding to the high-power aging condition are brought into the Arrhenius model to calculate the high-power acceleration factor. The high-power acceleration factor refers to the ratio of the failure time of the laser chip under high-power aging conditions to the failure time under normal working conditions.

[0103] Sub-step S1046, selecting the same number of multiple high-power verification chips and multiple normal aging chips from the same batch of laser chips.

[0104] Similarly, in this embodiment, high-power verification chips and normal aging chips are selected from the wafer to which the plurality of test chips belong. In this embodiment, the number of high-power verification chips and normal aging chips is 32.

[0105] Sub-step S1047, performing high-power aging on the multiple high-power verification chips under high-power aging conditions, and making the multiple normal aging chips operate normally under normal working conditions.

[0106] At a temperature of 45°C, multiple high-power verification chips were loaded with a current of 3A and operated for 168 hours, while multiple normal aging chips were operated at the operating temperature and operating current for 168 hours.

[0107] Sub-step S1048, if the failure number of the high-power verification chip is equal to the failure number of the normal aging chip, and the ratio of the high-power aging time to the normal operation time is equal to the high-power acceleration factor, then it is determined that the high-power aging condition is reliable.

[0108] For example, if the high-power acceleration factor is 2, and the number of failures of 32 high-power verification chips when running for 84 hours is the same as the number of failures of 32 normal aging chips when running for 168 hours, then the high-power aging condition is determined to be accurate and reliable. If they are not equal, steps S101 to S103 can be repeated, and multiple test temperatures and maximum current values ​​can be reset to re-determine the high-power aging condition and perform verification.

[0109] Similarly, in actual applications, the ratio of the high-power aging duration to the normal operation duration in sub-step S1048 does not necessarily need to be completely equal to the high-power acceleration factor. A certain error is allowed, and the larger the high-power acceleration factor, the larger the allowable error.

[0110] Please continue reading Figure 1 The reliability testing method of the semiconductor laser chip provided in this embodiment may further include:

[0111] Step S105 , selecting a plurality of high-temperature aged chips and a plurality of high-power aged chips from the same batch of laser chips.

[0112] In this embodiment, the number of the multiple high-temperature aging chips is the same as the number of the multiple high-power aging chips. Specifically, a first preset number of high-temperature aging chips and high-power aging chips are selected from the wafers to which the multiple test chips belong. A second preset number of high-temperature aging chips and high-power aging chips are selected from wafers of different tape-out batches from the wafers to which the multiple test chips belong.

[0113] It can be understood that the sum of the first preset number of high temperature aging chips and the second preset number of high temperature aging chips is the number of all high temperature aging chips; the sum of the first preset number of high power aging chips and the second preset number of high power aging chips is the number of all high power aging chips.

[0114] In this embodiment, the first preset number and the second preset number are both 16. In other embodiments, multiple high temperature aging chips and high power aging chips can be selected from wafers of different tape-out batches, and it is only necessary to ensure that the number of all high temperature aging chips is equal to the number of all high power aging chips.

[0115] Step S106, performing high temperature aging for a set time period on the plurality of high temperature aging chips under high temperature aging conditions, and counting the number of high temperature failures in the plurality of high temperature aging chips after the aging is completed.

[0116] In this embodiment, the duration is set to 2000 hours. That is, at a temperature of 85° C., a current of 2A is loaded on multiple high-temperature aging chips for 2000 hours. After the aging is completed, the number of failures in the multiple high-temperature aging chips is counted to obtain the high-temperature failure number.

[0117] Step S107 , performing high-power aging for a set time period on the multiple high-power aging chips under high-power aging conditions, and counting the number of high-power failures in the multiple high-power aging chips after the aging is completed.

[0118] In this embodiment, a plurality of high-power aged chips are loaded with a current of 3A and run for 2000 hours at a temperature of 45° C. After the aging is completed, the number of failures in the plurality of high-power aged chips is counted to obtain the number of high-power failures.

[0119] Step S108 , judging the main factors affecting the reliability of laser chips in the same batch according to the number of high-temperature failures and the number of high-power failures.

[0120] See also Figure 7 Since the number of the multiple high-temperature aging chips selected in this embodiment is consistent with the number of the multiple high-power aging chips, step S108 may include the following sub-steps:

[0121] Sub-step S1081 , if the number of high-temperature failures is greater than the number of high-power failures, it is determined that the epitaxial quality is the main factor affecting the reliability of the laser chips in the same batch.

[0122] When aging under high-temperature aging conditions, the junction temperature of multiple high-temperature aging chips will reach 3 to 4 times that of normal use conditions, which puts a greater test on the materials of high-temperature aging chips. When the number of high-temperature failures is greater than the number of high-power failures, the problems with epitaxial quality can be quickly screened out, indicating that the reliability of laser chips in the same batch is mainly affected by the epitaxial quality.

[0123] After determining that epitaxial quality is the main factor affecting the reliability of laser chips in the same batch, the epitaxial layer growth process can be optimized in a targeted manner to improve the epitaxial quality, thereby improving the quality of batch laser chips.

[0124] Sub-step S1082: If the number of high-power failures is greater than the number of high-temperature failures, it is determined that the cavity surface process is the main factor affecting the reliability of the laser chips in the same batch.

[0125] When aging is performed under high-power aging conditions, the cavity surface output power of multiple high-power aged chips will exceed twice that of normal working conditions, which puts a greater test on the cavity surface process of high-power aged chips. When the number of high-power failures is greater than the number of high-temperature failures, the problems with the cavity surface process can be screened out more quickly, indicating that the reliability of laser chips in the same batch is mainly affected by the cavity surface process.

[0126] Similarly, after determining that the cavity surface process is the main factor affecting the reliability of the laser chips in the same batch, the cavity surface process can be optimized in a targeted manner to improve the quality of batch laser chips.

[0127] In another embodiment, in step S105, the number of the selected multiple high temperature aging chips and the number of the selected multiple high power aging chips may be different. In this case, please refer to Figure 8 , step S108 may further include the following sub-steps:

[0128] Sub-step S1083, calculating the ratio of the number of high temperature failures to all the high temperature aged chips to obtain a high temperature failure ratio.

[0129] Sub-step S1084, calculating the ratio of the number of high-power failures to all the high-power aged chips to obtain a high-power failure ratio.

[0130] Sub-step S1085 , if the high temperature failure ratio is greater than the high power failure ratio, it is determined that the epitaxial quality is the main factor affecting the reliability of the laser chips in the same batch.

[0131] Sub-step S1086: if the high-power failure ratio is greater than the high-temperature failure ratio, it is determined that the cavity surface process is the main factor affecting the reliability of the laser chips in the same batch.

[0132] Please continue reading Figure 1 The reliability testing method of the semiconductor laser chip provided in this embodiment may further include:

[0133] Step S109 , correcting the Arrhenius model applied to the laser chips of the same batch according to the number of high-temperature failures and the number of high-power failures.

[0134] In this embodiment, step S109 may include the following sub-steps:

[0135] If the number of high-temperature failures is greater than the number of high-power failures, the power pressure factor is removed from the Arrhenius model applied to the laser chips of the same batch to obtain a new Arrhenius model:

[0136] .

[0137] In the case where it is determined that the reliability of laser chips in the same batch is mainly affected by the epitaxial quality, the power stress factor can be eliminated from the Arrhenius model used to evaluate aging conditions to improve the accuracy of the model.

[0138] in the formula , , They are the junction temperature, operating current and operating power under rated operating conditions, , , is the junction temperature, current and power under the corresponding accelerated test conditions, is the Boltzmann constant. is the activation energy of the chip, m and n are the pressure factors of current and power respectively. These three specific values ​​need to be obtained through experiments to obtain the parameter values ​​of the corresponding products.

[0139] In this case, the life t is calculated as:

[0140] .

[0141] A is an unknown constant. We can take the logarithm of both sides of the equation and get:

[0142] .

[0143] Select 2 or more groups of aging conditions with the same current and different temperatures for aging. Since the current is the same, It can also be regarded as a constant. The formula can be regarded as a linear equation of temperature and life span. A linear fit can be performed and the slope is , because, Ea can be obtained. Then select more than 2 groups of aging conditions with the same temperature and different currents for aging to obtain the m value.

[0144] In this embodiment, step S109 may further include the following sub-steps:

[0145] If the number of high-power failures is greater than the number of high-temperature failures, the power pressure factor is added to the Arrhenius model applied to the laser chips of the same batch to obtain a new Arrhenius model:

[0146] .

[0147] When it is determined that the reliability of laser chips in the same batch is mainly affected by the cavity surface process, the power pressure factor is added to the Arrhenius model used to evaluate aging conditions to obtain a new power-related model, thereby improving the accuracy of the model.

[0148] In this case, it can be deduced that:

[0149] .

[0150] Select four or more aging conditions with different currents and temperatures for aging, and solve the four-variable linear equation system according to the results to obtain the values ​​of m, n, Ea and A.

[0151] In summary, the reliability test method for semiconductor laser chips provided in this embodiment can determine the main factors affecting the reliability of laser chips in the same batch, and can provide an optimization basis for the production process to improve the quality of batch laser chips. In addition, the Arrhenius model used to evaluate aging conditions can be optimized to improve the accuracy of its evaluation results.

[0152] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A reliability testing method for a semiconductor laser chip, characterized in that: include: Selecting a plurality of test chips from the same batch of laser chips; Testing the power of a plurality of test chips as the current changes at a plurality of different test temperatures; According to the power test results, determine the high temperature aging conditions and high power aging conditions; Selecting a plurality of high-temperature aged chips and a plurality of high-power aged chips from the same batch of laser chips; Performing high temperature aging for a set time on the plurality of high temperature aging chips under the high temperature aging conditions, and counting the number of high temperature failures in the plurality of high temperature aging chips after the aging is completed; Performing high-power aging for the set time period on the plurality of high-power aging chips under the high-power aging condition, and counting the number of high-power failures in the plurality of high-power aging chips after the aging is completed; According to the number of high-temperature failures and the number of high-power failures, determine the main factors affecting the reliability of laser chips in the same batch; The step of determining the main factors affecting the reliability of laser chips in the same batch according to the number of high-temperature failures and the number of high-power failures includes: In the case where the number of the plurality of high-temperature aged chips is the same as the number of the plurality of high-power aged chips, if the number of high-temperature failures is greater than the number of high-power failures, it is determined that the epitaxial quality is the main factor affecting the reliability of the laser chips in the same batch; If the number of high-power failures is greater than the number of high-temperature failures, it is determined that the cavity surface process is the main factor affecting the reliability of the laser chips in the same batch.

2. The reliability testing method of a semiconductor laser chip according to claim 1, characterized in that: The step of determining the main factors affecting the reliability of laser chips in the same batch according to the number of high-temperature failures and the number of high-power failures further includes: When the number of the plurality of high-temperature aged chips is different from the number of the plurality of high-power aged chips, calculating the ratio of the number of high-temperature failures to all the high-temperature aged chips to obtain a high-temperature failure ratio; Calculating the ratio of the number of high-power failures to all the high-power aged chips to obtain a high-power failure ratio; If the high temperature failure ratio is greater than the high power failure ratio, it is determined that the epitaxial quality is the main factor affecting the reliability of the laser chips in the same batch; If the high-power failure ratio is greater than the high-temperature failure ratio, it is determined that the cavity surface process is the main factor affecting the reliability of the laser chips in the same batch.

3. The reliability testing method of a semiconductor laser chip according to claim 1, characterized in that: The step of respectively testing the power of a plurality of test chips as the current changes at a plurality of different test temperatures comprises: Setting a plurality of incremental test temperatures, wherein the difference between two adjacent test temperatures is the same, and the highest test temperature is 3 to 4 times the operating temperature of the laser chip; Gradually increasing currents are loaded onto the multiple test chips at the multiple test temperatures, and the powers of the multiple test chips are monitored respectively, wherein the maximum value of the current loaded onto the multiple test chips is 2 to 3 times the operating current of the laser chip.

4. The reliability testing method of a semiconductor laser chip according to claim 1, characterized in that: The step of determining the high temperature aging condition and the high power aging condition according to the power test result comprises: Drawing a power-current relationship diagram of a plurality of the test chips to obtain a plurality of thermal reversal currents at the test temperatures; Selecting the one with the highest test temperature corresponding to the multiple thermal reversal currents and the corresponding test temperature as the high temperature aging condition; The one with the highest power corresponding to the multiple thermal reversal currents and the corresponding test temperature are selected as the high-power aging condition.

5. The reliability testing method of a semiconductor laser chip according to claim 1, characterized in that: The step of selecting a plurality of test chips from the same batch of laser chips comprises: Selecting a plurality of the test chips on the same wafer; The step of selecting the same number of high-temperature aged chips and high-power aged chips from the same batch of laser chips comprises: Selecting a first preset number of the high-temperature aging chips and the high-power aging chips respectively on the wafer to which the plurality of test chips belong; A second preset number of the high-temperature aging chips and the high-power aging chips are respectively selected from wafers of a different tape-out batch from the wafers to which the plurality of test chips belong.

6. The reliability testing method of a semiconductor laser chip according to claim 1, characterized in that: After the step of performing high-power aging for the set time period on the plurality of high-power aging chips under the high-power aging condition and counting the number of high-power failures in the plurality of high-power aging chips after aging, the method further includes: The Arrhenius model applied to the laser chips of the same batch is modified according to the number of high-temperature failures and the number of high-power failures.

7. The reliability testing method of a semiconductor laser chip according to claim 6, characterized in that: The step of correcting the Arrhenius model applied to the laser chips of the same batch according to the number of high-temperature failures and the number of high-power failures comprises: If the number of high-temperature failures is greater than the number of high-power failures, the power pressure factor is removed from the Arrhenius model applied to the laser chips of the same batch to obtain a new Arrhenius model: ； If the number of high-power failures is greater than the number of high-temperature failures, a power pressure factor is added to the Arrhenius model applied to the laser chips of the same batch to obtain a new Arrhenius model: ； in, is the junction temperature under rated operating conditions, is the operating current under rated operating conditions, is the operating power under rated operating conditions, is the junction temperature under the corresponding accelerated test conditions, is the current under the corresponding accelerated test condition, is the power under the corresponding accelerated test conditions, is the Boltzmann constant, is the activation energy of the laser chip, m is the pressure factor of the current, and n is the pressure factor of the power.

8. The reliability testing method of a semiconductor laser chip according to claim 1, characterized in that: Before the step of selecting a plurality of high-temperature aged chips and a plurality of high-power aged chips from the same batch of laser chips, the method further comprises: The reliability of the high temperature aging condition and / or the high power aging condition is verified according to an Arrhenius model.

9. The reliability testing method of a semiconductor laser chip according to claim 8, characterized in that: The step of verifying the reliability of the high temperature aging condition according to the Arrhenius model comprises: According to the Arrhenius model, the high temperature acceleration factor corresponding to the high temperature aging condition is calculated; Selecting the same number of multiple high-temperature verification chips and multiple normal aging chips from the same batch of laser chips; Performing high-temperature aging on the plurality of high-temperature verification chips under the high-temperature aging conditions, and allowing the plurality of normal aging chips to operate normally under normal operating conditions; If the failure number of the high temperature verification chip is equal to the failure number of the normal aging chip, and the ratio of the high temperature aging time to the normal operation time is equal to the high temperature acceleration factor, then the high temperature aging condition is determined to be reliable.

10. The reliability testing method of a semiconductor laser chip according to claim 8, characterized in that: The step of verifying the reliability of the high power aging condition according to the Arrhenius model comprises: Calculating a high-power acceleration factor corresponding to the high-power aging condition according to an Arrhenius model; Selecting the same number of multiple high-power verification chips and multiple normal aging chips from the same batch of laser chips; Performing high-power aging on the plurality of high-power verification chips under the high-power aging conditions, and allowing the plurality of normal aging chips to operate normally under normal working conditions; If the number of failures of the high-power verification chip is equal to the number of failures of the normal aging chip, and the ratio of the high-power aging duration to the normal operation duration is equal to the high-power acceleration factor, then the high-power aging condition is determined to be reliable.

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