Semiconductor structure, preparation method, photon chip and optical computing equipment

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method, a photon chip and optical computing equipment. The semiconductor structure comprises: a substrate; a first semiconductor device layer over the substrate, the first semiconductor device layer including an active device and a first waveguide optically interconnected with the active device; the metal interconnection structure is located above the first semiconductor device layer, and the active device is electrically connected with the metal interconnection structure; the second semiconductor device layer is positioned above the metal interconnection structure and comprises a grating coupler and a second waveguide which is optically interconnected with the grating coupler; an optical interconnection structure through which the first waveguide and the second waveguide are optically interconnected; the first end of the electric connection structure is electrically connected with the metal interconnection structure, and the second end of the electric connection structure is used for being electrically connected with an external circuit. According to the technical scheme provided by the embodiment of the invention, the coupling efficiency of the grating coupler can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a preparation method, a photonic chip and an optical computing device. Background Art

[0002] Photonic chips, also known as photonic integrated circuits (PICs) and photonic integrated chips, refer to chips that use photons to process and transmit information. Currently, photonic chips are optically coupled to external optical fibers through couplers (e.g., planar couplers and grating couplers). Among them, planar couplers are also called grating couplers, which use the grating diffraction effect to couple light into photonic chips.

[0003] However, currently, the light coupling efficiency of grating couplers is low. Summary of the invention

[0004] In view of the above problems, the present application is proposed to provide a semiconductor structure, a preparation method, a photonic chip and an optical computing device that solve the above problems or at least partially solve the above problems.

[0005] Therefore, in one embodiment of the present application, a semiconductor structure is provided, comprising:

[0006] substrate;

[0007] a first semiconductor device layer located above the substrate, the first semiconductor device layer comprising an active device and a first waveguide optically interconnected with the active device;

[0008] a metal interconnect structure located above the first semiconductor device layer, the active device being electrically connected to the metal interconnect structure;

[0009] a second semiconductor device layer located above the metal interconnect structure, the second semiconductor device layer comprising a grating coupler and a second waveguide optically interconnected with the grating coupler;

[0010] an optical interconnection structure, wherein the first waveguide and the second waveguide are optically interconnected through the optical interconnection structure;

[0011] An electrical connection structure, a first end of the electrical connection structure is electrically connected to the metal interconnection structure, and a second end of the electrical connection structure is used to be electrically connected to an external circuit.

[0012] Optionally, the grating coupler includes a grating structure; and the semiconductor structure further includes:

[0013] A first dielectric layer is covered on the second semiconductor device layer, wherein the first dielectric layer is provided with an opening used as a light passage, and the opening is located above the grating structure.

[0014] Optionally, the electrical connection structure passes through the first dielectric layer and is arranged away from the grating coupler and the second waveguide.

[0015] Optionally, the semiconductor structure further includes:

[0016] A second dielectric layer covering the first semiconductor device layer, wherein the metal interconnect structure is wrapped in the second dielectric layer;

[0017] The optical interconnection structure penetrates the second dielectric layer and is arranged away from the metal interconnection structure.

[0018] Optionally, the active device is electrically connected to the metal interconnection structure through an electrical contact hole located in the second dielectric layer.

[0019] Optionally, the material of the second semiconductor device layer is a single crystal semiconductor material.

[0020] Optionally, the active device includes an optical modulator and / or a photodetector.

[0021] Optionally, the metal interconnect structure includes multiple metal interconnect layers and conductive vias connecting adjacent metal interconnect layers.

[0022] In another embodiment of the present application, a semiconductor manufacturing method is provided, comprising:

[0023] providing a first substrate;

[0024] forming a first semiconductor device layer on the first substrate, the first semiconductor device layer comprising an active device and a first waveguide optically interconnected with the active device;

[0025] forming a metal interconnect structure and an optical interconnect structure above the first semiconductor device layer, wherein the active device is electrically connected to the metal interconnect structure;

[0026] forming a second semiconductor device layer over the metal interconnection structure and the optical interconnection structure, the second semiconductor device layer comprising a grating coupler and a second waveguide optically interconnected with the grating coupler, the first waveguide and the second waveguide optically interconnected through the optical interconnection structure;

[0027] An electrical connection structure is formed, wherein a first end of the electrical connection structure is electrically connected to the metal interconnection structure, and a second end of the electrical connection structure is used to be electrically connected to an external circuit.

[0028] Optionally, the grating coupler includes a grating structure; the method further includes:

[0029] forming a first dielectric layer for covering the second semiconductor device layer;

[0030] An opening serving as a light passage is provided on the first medium layer, and the opening is located above the grating structure.

[0031] Optionally, forming an electrical connection structure includes:

[0032] Etching a region of the first dielectric layer that avoids the grating coupler and the second waveguide to form a first through hole in the first dielectric layer;

[0033] A metal material is deposited in the first through hole to obtain an electrical connection structure that penetrates the first dielectric layer.

[0034] Optionally, a metal interconnect structure and an optical interconnect structure are formed above the first semiconductor device layer, comprising:

[0035] forming a second dielectric layer and a metal interconnect structure above the first semiconductor device layer, wherein the metal interconnect structure is wrapped in the second dielectric layer;

[0036] Etching a region of the second dielectric layer that avoids the metal interconnect structure to form a second through hole in the second dielectric layer;

[0037] Depositing a semiconductor material in the second through hole to obtain a first optical interconnect structure penetrating the second dielectric layer;

[0038] Wherein, the optical interconnection structure includes the first optical interconnection structure.

[0039] Optionally, forming a second semiconductor device layer above the metal interconnect structure and the optical interconnect structure includes:

[0040] Providing a second substrate, wherein the second substrate comprises a first semiconductor layer and a third dielectric layer formed on a surface of the first semiconductor layer;

[0041] Bonding the surface of the third dielectric layer to the surface of the second dielectric layer through a bonding process;

[0042] The first semiconductor layer is etched to obtain a second semiconductor device layer.

[0043] Optionally, the above method further includes:

[0044] forming a fourth dielectric layer covering the second semiconductor device layer;

[0045] Sequentially etching the fourth dielectric layer and the third dielectric layer to form a third through hole;

[0046] Depositing a semiconductor material in the third through hole to obtain a second optical interconnection structure;

[0047] One end of the second optical interconnection structure is in contact with and connected to the first optical interconnection structure, and the other end of the second optical interconnection structure is in contact with and connected to the second waveguide. The optical interconnection structure includes the first optical interconnection structure and the second optical interconnection structure.

[0048] In another embodiment of the present application, a photonic chip is provided, comprising any of the semiconductor structures described above.

[0049] In another embodiment of the present application, an optical computing device is provided, including: the above-mentioned photonic chip.

[0050] In the technical solution provided in the embodiment of the present application, the active device is located below the metal interconnection structure, and the grating coupler is located above the metal interconnection structure. This can prevent the metal material remaining in the preparation process of the metal interconnection structure from affecting the coupling efficiency of the grating coupler, which is equivalent to improving the coupling efficiency of the grating coupler. In addition, in the technical solution provided in the embodiment of the present application, the layered design of the grating coupler and the active device helps to further shrink the size of the active device, provide space for the future development of photonic chips, and is also beneficial to reduce the optical signal interference between the two. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 1 is a cross-sectional view of an existing semiconductor structure;

[0053] Figure 2 A cross-sectional view of a semiconductor structure provided in one embodiment of the present application;

[0054] Figure 3 A schematic diagram of a preparation method according to an embodiment of the present application;

[0055] Figure 4 A cross-sectional view of a first semiconductor structure provided in one embodiment of the present application;

[0056] Figure 5 A cross-sectional view of a second semiconductor structure provided in one embodiment of the present application;

[0057] Figure 6 A cross-sectional view of a third semiconductor structure provided in one embodiment of the present application;

[0058] Figure 7A cross-sectional view of a fourth semiconductor structure provided in an embodiment of the present application;

[0059] Figure 8a A cross-sectional view of a fifth semiconductor structure provided in one embodiment of the present application;

[0060] Figure 8b A cross-sectional view of a sixth semiconductor structure provided in an embodiment of the present application;

[0061] Figure 8c A cross-sectional view of a seventh semiconductor structure provided in one embodiment of the present application;

[0062] Figure 8d A cross-sectional view of an eighth semiconductor structure provided in one embodiment of the present application;

[0063] Figure 8e A cross-sectional view of a ninth semiconductor structure provided in an embodiment of the present application;

[0064] Fig. 9 A cross-sectional view of a tenth semiconductor structure provided according to an embodiment of the present application.

[0065] Fig.10 A cross-sectional view of an eleventh semiconductor structure provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0066] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below according to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0067] In addition, some of the processes described in the specification, claims and the above-mentioned figures of the present application include multiple operations that appear in a specific order, and these operations may not be executed in the order in which they appear in this article or may be executed in parallel. The serial numbers of the operations, such as 201, 202, etc., are only used to distinguish between different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit the "first" and "second" to be different types.

[0068] First, the vocabulary involved in the embodiments of the present application is explained. It can be understood that this explanation is for a clearer understanding of the embodiments of the present application, and does not necessarily constitute a limitation on the embodiments of the present application.

[0069] Optical devices refer to devices that can process, manipulate, transmit and / or detect optical signals, such as waveguides, couplers, modulators, detectors, etc.

[0070] Active devices refer to devices that require energy (such as power). The device can be an optical device, such as a modulator, a detector, etc.

[0071] A grating coupler is a device that uses the diffraction effect of a grating to couple light.

[0072] A modulator (also known as an optical modulator) is used to modulate an optical signal, that is, to change certain characteristics of an optical signal, such as light intensity, phase or frequency.

[0073] Detectors (also known as photodetectors) are used to convert optical signals into electrical signals.

[0074] Optical interconnection: refers to the method of transmitting data through optical signals, such as laser signals.

[0075] Figure 1 FIG. 1 is a cross-sectional schematic diagram of an existing semiconductor structure. Figure 1 As shown, the semiconductor structure includes: a substrate 10, a dielectric layer 11 covering the substrate 10, a semiconductor device layer 12 formed on the dielectric layer 11, and a dielectric layer 13 covering the semiconductor device layer 12, wherein a metal interconnection structure 14 is provided in the dielectric layer 13.

[0076] The semiconductor device layer 12 includes a waveguide 121, a grating coupler 122 and an active device 123. The grating coupler 122 is optically interconnected with the waveguide 121 (not shown), and the waveguide 121 is optically interconnected with the active device 123 (not shown).

[0077] The active device 123 is electrically connected to the metal interconnect structure 14 through an electrical contact 15 .

[0078] The metal interconnection structure 14 includes a plurality of metal interconnection layers 141 and conductive vias 142 connecting adjacent metal interconnection layers, wherein each metal interconnection layer 141 includes metal interconnection wires.

[0079] In order to facilitate the light to enter / exit the grating coupler 122, an opening 16 as a light passage is provided in the dielectric layer 13. Exemplarily, the opening 16 can be used for inserting an external optical fiber.

[0080] like Figure 1As shown, the grating coupler 122 is located below the metal interconnect structure 14. During the process, the optical path is easily contaminated by light-absorbing materials such as metal, resulting in low coupling efficiency of the grating coupler; the manufacturing process of the optical path generally requires multiple steps of opening the dielectric layer, and the process complexity is high; the grating coupler 122 and the optical path occupy a large area, which affects the further size reduction of the photonic chip in the future.

[0081] In order to solve or partially solve the above-mentioned technical problems, an embodiment of the present application provides a new semiconductor structure, in which the grating coupler is moved above the metal interconnection structure. This can prevent the metal material remaining from the preparation process of the metal interconnection structure from affecting the coupling efficiency of the grating coupler. In addition, moving the grating coupler above the metal interconnection structure will help to further shrink the size of active devices, provide space for the future development of photonic chips, and help reduce the interference of optical signals between the grating coupler and the active devices.

[0082] Figure 2 FIG. 1 is a cross-sectional schematic diagram of a semiconductor structure provided by an embodiment of the present application. Figure 2 As shown, the semiconductor structure includes:

[0083] A substrate 20; a first semiconductor device layer 21 located above the substrate 20, the first semiconductor device layer 21 comprising an active device 211 and a first waveguide 212 optically interconnected with the active device 211; a metal interconnection structure 22 located above the first semiconductor device layer 21, the active device 211 being electrically connected to the metal interconnection structure 22; a second semiconductor device layer 23 located above the metal interconnection structure 22, the second semiconductor device layer 23 comprising a grating coupler 231 and a second waveguide 232 optically interconnected with the grating coupler 231; an optical interconnection structure 24, the first waveguide 212 and the second waveguide 232 being optically interconnected through the optical interconnection structure 24; and an electrical connection structure 25, a first end of the electrical connection structure 25 being electrically connected to the metal interconnection structure 22, and a second end of the electrical connection structure 25 being used for electrical connection to an external circuit.

[0084] The substrate 20 is a semiconductor substrate, such as a silicon substrate or a germanium substrate.

[0085] In some embodiments, in order to prevent the substrate from affecting the functions of the devices in the first semiconductor device layer 21, the substrate 20 and the first semiconductor device layer 21 are isolated by a dielectric. Figure 2 As shown, the semiconductor structure may further include a dielectric layer 26, which is located between the substrate 20 and the first semiconductor device layer 21 and is used to isolate the substrate 20 from the first semiconductor device layer 21. Exemplarily, the material of the dielectric layer 26 is silicon dioxide.

[0086] The first semiconductor device layer 21 may include one or more active devices 211 and one or more first waveguides 212. An active device 211 may be optically interconnected with one or more second waveguides 212, and the specific design may be determined according to the required circuit function, which is not specifically limited in this application.

[0087] The material of the first semiconductor device layer (i.e., the material of the active device 211 and the first waveguide 212) is a semiconductor material, such as silicon, germanium, etc. In some embodiments, in order to ensure the performance of the waveguide and the active device, the material of the first semiconductor device layer is a single crystal semiconductor material, such as single crystal silicon, single crystal germanium, etc.

[0088] The active device 211 may include but is not limited to: a modulator and a detector.

[0089] The metal interconnect structure 22 is used to realize electrical connection between active devices in the first semiconductor device layer 21, thereby forming a circuit.

[0090] Exemplarily, the metal interconnect structure 22 is a single-layer structure, that is, the metal interconnect structure 22 includes only one metal interconnect layer.

[0091] For example, Figure 2 As shown, the metal interconnect structure 22 is a multi-layer structure, that is, the metal interconnect structure 22 includes a multi-layer metal interconnect layer 221 and a conductive via 222 connecting adjacent metal interconnect layers. The material of the metal interconnect structure 22 can be, for example, a metal material such as copper, silver or gold, which is not specifically limited in the embodiment of the present application.

[0092] In an optional implementation, the metal interconnect structure 22 is isolated from the first semiconductor device layer 21 by a dielectric.

[0093] For example, Figure 2 As shown, the semiconductor structure may further include a dielectric layer 27 (i.e., the second dielectric layer mentioned above), the dielectric layer 27 covers the first semiconductor device layer 21, and the metal interconnection structure 22 is wrapped inside the dielectric layer 27. In the metal interconnection structure 22, adjacent metal interconnection layers are isolated by the dielectric layer 27, and different metal interconnection lines in the same metal interconnection layer are isolated by the dielectric layer 27. The material of the dielectric layer 27 may be, for example, silicon dioxide.

[0094] In an optional embodiment, if Figure 2 As shown, the metal interconnect structure 22 and the first semiconductor device layer 21 are isolated by the dielectric layer 27 .

[0095] In order to realize the circuit, such as Figure 2As shown, the active device 211 is electrically connected to the metal interconnect structure 22 through an electrical contact hole 28. The electrical contact hole 28 is located in the second dielectric layer.

[0096] like Figure 2 As shown, the second semiconductor device layer 23 is located above the metal interconnection structure 22 , and the first semiconductor device layer 21 is located below the metal interconnection structure 22 .

[0097] The number of the grating couplers 231 in the second semiconductor device layer 23 can be one or more, and the number of the second waveguides 232 can be one or more, which is not specifically limited in the embodiment of the present application.

[0098] For example, Figure 2 As shown, the grating coupler 231 includes a grating structure 2311 and a waveguide structure (not shown). The grating structure is provided with a plurality of parallel grating grooves, and the direction of the grating grooves is orthogonal to the propagation direction of light in the waveguide structure.

[0099] The material of the second semiconductor device layer (i.e., the material of the grating coupler 231 and the second waveguide 232) is a semiconductor material, such as silicon, germanium, etc. In some embodiments, in order to ensure the performance of the waveguide and the grating coupler, the material of the second semiconductor device layer is a single crystal semiconductor material, such as single crystal silicon, single crystal germanium, etc.

[0100] In some embodiments, the second semiconductor device layer 23 and the metal interconnect structure 22 are isolated from each other.

[0101] Exemplarily, the second semiconductor device layer 23 and the metal interconnect structure 22 are isolated by a dielectric, for example, by the dielectric layer 27 mentioned above.

[0102] In some embodiments, Figure 2 As shown, the optical interconnection structure 24 penetrates the dielectric layer 27 and avoids (i.e., avoids) the metal interconnection structure 22. One end of the optical interconnection structure 24 is connected to the first waveguide 212, and the other end is connected to the second waveguide 232, thereby realizing the optical interconnection between the first waveguide 212 and the second waveguide 232.

[0103] The optical interconnect structure 24 is a waveguide structure, and the number of the optical interconnect structure 24 can be one or more, which is not specifically limited in the present embodiment. The optical interconnect structure 24 can be made of semiconductor material, such as silicon, germanium and other materials.

[0104] Exemplarily, the length direction of the optical interconnect structure 24 or the propagation direction of light in the optical interconnect structure 24 is perpendicular to the surface of the substrate 20 .

[0105] In some embodiments, the electrical connection structure 25 may be multiple, and different electrical connection structures 25 may be electrically connected to different metal interconnection layers to provide a level (e.g., a high level or a low level) for the metal interconnection layer. That is, a first end of the electrical connection structure 25 is electrically connected to the metal interconnection structure 22, and a second end of the electrical connection structure 25 is electrically connected to an external circuit. Exemplarily, the external circuit may be used to provide a level.

[0106] It should be noted that the area occupied by the electrical connection structure 25 is much smaller than the area occupied by the metal interconnection layer. Therefore, the preparation process of the electrical connection structure 25 leaves less metal material near the grating coupler.

[0107] In some embodiments, Figure 2 As shown, the semiconductor structure may further include a dielectric layer 29 (i.e., the first dielectric layer mentioned above) covering the second semiconductor device layer 23. The electrical connection structure 25 may penetrate the dielectric layer 29 and avoid the grating coupler 231 and the second waveguide 232. The second end of the electrical connection structure 25 is exposed for electrical connection with an external circuit.

[0108] In the technical solution provided in the embodiment of the present application, the active device is located below the metal interconnection structure, and the grating coupler is located above the metal interconnection structure. This can prevent the metal material remaining in the preparation process of the metal interconnection structure from affecting the coupling efficiency of the grating coupler. In addition, in the technical solution provided in the embodiment of the present application, the layered design of the grating coupler and the active device helps to further shrink the size of the active device, provide space for the future development of photonic chips, and is also beneficial to reduce the optical signal interference between the two.

[0109] In order to improve the coupling efficiency of the grating coupler, such as Figure 2 As shown, the dielectric layer 29 is provided with an opening 16 used as a light passage, and the opening 16 is located above the grating structure 2311 .

[0110] In this way, the light entering the grating coupler directly reaches the grating coupler through the opening 16, and the light output by the grating coupler directly reaches the external optical fiber through the opening 16, which can improve the light coupling efficiency.

[0111] In the embodiment of the present application, since the opening position of the optical path is located above the metal interconnection layer, it is possible to avoid contamination of the optical path by metal and other light-absorbing materials remaining in the preparation process of the metal interconnection layer, thereby avoiding the impact on the coupling efficiency; and the area occupied by the electrical connection structure is much smaller than the area occupied by the metal interconnection layer. Therefore, the preparation process of the electrical connection structure leaves very little metal material near the grating coupler, which has little impact on the coupling efficiency.

[0112] The following will be combined Figure 3A method for preparing the above semiconductor structure is introduced. Figure 3 As shown, the method comprises the following steps:

[0113] 301. Provide a first substrate.

[0114] Among them, the first substrate can be called a first substrate wafer.

[0115] In some embodiments, the first substrate may be a semiconductor substrate, and the material of the semiconductor substrate may be any semiconductor material, such as silicon, germanium, etc., which is not specifically limited in the embodiments of the present application. Exemplarily, the first substrate is a silicon substrate.

[0116] In other embodiments, Figure 4 As shown, the first substrate is a silicon-on-insulator (SOI) substrate, which includes a silicon substrate 41 (or bottom silicon), a top silicon layer 43, and a silicon dioxide buried oxide layer 42 located between the top silicon layer 43 and the silicon substrate 41. The top silicon layer 43 is single crystal silicon.

[0117] 302. Form a first semiconductor device layer above the first substrate.

[0118] The first semiconductor device layer includes an active device and a first waveguide optically interconnected with the active device.

[0119] In some embodiments, when the first substrate is a semiconductor substrate, a dielectric layer (or insulating layer) may be first deposited on the semiconductor substrate, and then a semiconductor layer may be deposited on the dielectric layer, and the semiconductor layer may be etched to obtain a first semiconductor device layer.

[0120] In other embodiments, Figure 5 As shown, when the first substrate is an SOI substrate, the top silicon 43 in the SOI substrate is etched to obtain a first semiconductor device layer 51 , and the first semiconductor device layer 51 includes an active device 511 and a first waveguide 512 .

[0121] 303. Form a metal interconnection structure and an optical interconnection structure above the first semiconductor device layer.

[0122] Wherein, the active device is electrically connected to the metal interconnection structure.

[0123] The first semiconductor device layer and the metal interconnection layer structure are isolated by a dielectric.

[0124] In some embodiments, Figure 6As shown, a dielectric layer 61 (also referred to as the second dielectric layer above) and a metal interconnection structure 62 are formed above the first semiconductor device layer 51. The metal interconnection structure 62 is coated inside the dielectric layer 61. The metal interconnection structure 62 is electrically connected to the active device 511 through the electrical contact hole 63.

[0125] For example, Figure 6 As shown, the electrical contact hole 63 is located in the dielectric layer 61 .

[0126] It should be noted that the formation of the dielectric layer 61 , the metal interconnect structure 62 and the electrical contact hole 63 involves multiple dielectric layer depositions, multiple metal layer depositions, multiple dielectric layer etchings and multiple metal layer etchings.

[0127] Exemplarily, a dielectric layer a is deposited on the first semiconductor device layer 51, and the dielectric layer a is etched to form a contact hole in the dielectric layer a; a metal material is deposited to form a first metal layer on the etched dielectric layer a and fill the contact hole with metal material (the contact hole filled with metal material is called an electrical contact hole); the first metal layer is patterned to obtain a first metal interconnection layer; a dielectric layer b for covering the first metal interconnection layer is deposited, and the dielectric layer b is etched to form a through hole in the dielectric layer b; a metal material is deposited to form a second metal layer on the etched dielectric layer b and fill the through hole with metal material; the second metal layer is patterned to obtain a second metal interconnection layer; if the second metal interconnection layer is the top metal interconnection layer (or the last metal interconnection layer), a dielectric layer can be deposited again on the second metal interconnection layer to cover the second metal interconnection layer; if the second metal interconnection layer is not the top metal interconnection layer, other metal interconnection layers can also be prepared according to the same steps as above.

[0128] After forming the metal interconnect structure, the Figure 6 The semiconductor structure shown.

[0129] like Figure 7 As shown, after forming the first optical interconnection structure 71, the following is obtained: Figure 7 The semiconductor structure shown in the figure, wherein one end of the first optical interconnection structure 71 is connected to the first waveguide 512, and the other end is exposed. The above optical interconnection structure includes the first optical interconnection structure 71.

[0130] Exemplarily, the first optical interconnection structure penetrates the metal interconnection structure.

[0131] Exemplarily, the first optical interconnection structure runs through each metal interconnection layer in the metal interconnection structure.

[0132] For example, Figure 7 As shown, the first optical interconnect structure 71 is located in the dielectric layer 61 .

[0133] For example, Figure 7 As shown, the first optical interconnection structure 71 penetrates the dielectric layer 61 .

[0134] In an optional embodiment, the area of ​​the dielectric layer 61 avoiding the metal interconnection structure 62 can be etched to form a through hole (i.e., the second through hole mentioned above) in the dielectric layer 61, and a semiconductor material, such as a silicon material, is deposited in the through hole to obtain a first optical interconnection structure 71 that penetrates the dielectric layer 61.

[0135] 304. Form a second semiconductor device layer above the metal interconnect structure.

[0136] The second semiconductor device layer includes a grating coupler and a second waveguide optically interconnected with the grating coupler, and the first waveguide and the second waveguide are optically interconnected via the optical interconnection structure.

[0137] Wherein, the metal interconnect structure and the second semiconductor device layer are isolated by a dielectric.

[0138] In some embodiments, Figure 8a As shown, a semiconductor layer is formed on the dielectric layer 61 by depositing a semiconductor material, and the semiconductor layer is patterned (i.e., etched) to obtain a second semiconductor device layer 81. The first semiconductor device layer 81 includes a grating coupler 811 and a second waveguide 812. The second waveguide 812 is optically interconnected with the first waveguide 512 through a first optical interconnection structure 71.

[0139] In other embodiments, Figure 8b to Figure 8c As shown, a second substrate is provided, the second substrate includes a semiconductor layer 82 and a dielectric layer 83 formed on the surface of the semiconductor layer 82; the surface of the dielectric layer 83 is bonded to the surface of the dielectric layer 61 through a bonding process; and the second semiconductor device layer 81 can be formed by etching the semiconductor layer 82. Bonding is a technology that uses van der Waals forces, molecular forces, or even atomic forces between material surfaces to achieve bonding. The second substrate can be called a second substrate wafer.

[0140] like Figure 8b As shown, a second substrate is provided, the second substrate includes a semiconductor layer 82 and a dielectric layer 83 formed on the surface of the semiconductor layer 82; through a bonding process, the surface of the dielectric layer 83 is bonded to the surface of the dielectric layer 61. Before bonding, the surfaces of the dielectric layer 83 and the dielectric layer 61 can be cleaned.

[0141] In practical applications, the thickness of the semiconductor layer 82 in the second substrate is relatively large. In an optional embodiment, before etching or patterning the semiconductor layer 82 to form the second semiconductor device layer 81, the semiconductor layer 82 is thinned, for example, by grinding. Subsequently, the thinned semiconductor layer 82 is etched to form the second semiconductor device layer 81 (e.g., Figure 8c shown).

[0142] In practical applications, by depositing semiconductor materials (i.e. Figure 8a The semiconductor layer obtained by the corresponding embodiment is usually a polycrystalline semiconductor material layer, and it is difficult to form a single crystal semiconductor material layer. By adopting the bonding solution provided in the embodiment of the present application, it is easy to obtain a single crystal semiconductor material layer for preparing the second semiconductor device layer. In this way, the performance of the waveguide and grating coupler in the second semiconductor device layer can be effectively ensured.

[0143] Figure 8c In the semiconductor structure shown, the second waveguide 811 in the second semiconductor device layer 81 is not optically interconnected with the optical interconnect structure 71 .

[0144] In order to realize the optical interconnection between the optical interconnection structure 71 and the second waveguide 811, the following steps may be adopted:

[0145] like Figure 8d As shown, a dielectric layer 84 (ie, the fourth dielectric layer mentioned above) is deposited on the second semiconductor device layer 81; Figure 8e As shown, the dielectric layer 84 and the dielectric layer 83 are etched to form a through hole (i.e., the third through hole mentioned above), and a semiconductor material, such as a silicon material, is deposited in the through hole to form a second optical interconnection structure 85 in the through hole. One end of the second optical interconnection structure 85 is in contact with and connected to the first optical interconnection structure 71, and the other end is in contact with and connected to the second waveguide 811, that is, one end of the second optical interconnection structure 85 is optically interconnected with the first optical interconnection structure 71, and the other end is optically interconnected with the second waveguide 811.

[0146] The optical interconnection structure includes a first optical interconnection structure 71 and a second optical interconnection structure 85 .

[0147] 305. Form an electrical connection structure.

[0148] like Fig. 9 As shown, a first end of the electrical connection structure 91 is electrically connected to the metal interconnection structure 62, and a second end of the electrical connection structure 91 is used to be electrically connected to an external circuit.

[0149] In some embodiments, after obtaining the second semiconductor device layer, a first dielectric layer can be formed to cover the second semiconductor device layer; an area in the first dielectric layer that avoids the grating coupler and the second waveguide is etched to form a first through hole in the first dielectric layer; and a metal material is deposited in the first through hole to obtain an electrical connection structure that penetrates the first dielectric layer and avoids the grating coupler and the second waveguide.

[0150] For example, when obtaining Figure 8a After the semiconductor structure shown in the figure is formed, a dielectric layer (not shown) for covering the second semiconductor device layer 81 is formed, and a through hole (that is, the first through hole mentioned above) is formed by etching the dielectric layer and the dielectric layer 61, and a metal material is deposited in the through hole to obtain an electrical connection structure that penetrates the dielectric layer and avoids the grating coupler and the second waveguide. In this embodiment, the dielectric layer for covering the second semiconductor device layer 81 is also the first dielectric layer mentioned above.

[0151] For example, when obtaining Figure 8e After the semiconductor structure shown in Fig. 9 As shown, a dielectric layer 91 is formed to cover the dielectric layer 84; the dielectric layer 91, the dielectric layer 84, the dielectric layer 83 and the dielectric layer 61 are sequentially etched to form a through hole (i.e., the first through hole mentioned above); a metal material is deposited in the through hole to obtain an electrical connection structure 92 that sequentially penetrates the dielectric layer 91, the dielectric layer 84, the dielectric layer 83 and avoids the arrangement of the grating coupler and the second waveguide. In this embodiment, the dielectric layer 91 and the dielectric layer 84 are combined to form the first dielectric layer mentioned above.

[0152] In the technical solution provided in the embodiment of the present application, the active device is located below the metal interconnection structure, and the grating coupler is located above the metal interconnection structure. This can prevent the metal material remaining in the preparation process of the metal interconnection structure from affecting the coupling efficiency of the grating coupler. In addition, in the technical solution provided in the embodiment of the present application, the layered design of the grating coupler and the active device helps to further shrink the size of the active device, provide space for the future development of photonic chips, and is also beneficial to reduce the optical signal interference between the two.

[0153] In some embodiments, the above method may further include:

[0154] 306. Open an opening on the first dielectric layer for light passage.

[0155] The opening is located above the grating structure, for example, directly above it.

[0156] like Fig.10 As shown, the opening 100 may be formed by etching the dielectric layer 91 or etching the dielectric layer 91 and the dielectric layer 84 .

[0157] Exemplarily, different grating couplers correspond to different openings, and the openings corresponding to different grating couplers are located above the grating structure of the grating coupler.

[0158] Optionally, the materials of the dielectric layers in the embodiment of the present application may be the same, for example, all of them are silicon dioxide materials. The deposited semiconductor material may be silicon material, and the materials of the first semiconductor device layer and the second semiconductor device layer may be single crystal silicon material.

[0159] The technical solution provided in the embodiment of the present application has stronger integration, separates the active device and the optical interaction system, and reduces their mutual influence; the grating coupler is moved upward, the optical path manufacturing process is simple, and the metal layer preparation process will not affect the optical coupling efficiency; more grating couplers can be placed above the metal interconnect layer, which also adds more space for the substrate below and more space for accommodating active devices; the separation of the grating coupler can continue to miniaturize the size of active devices, etc., providing space for the future development of photonic chips.

[0160] The embodiment of the present application also provides a photonic chip. The photonic chip may include the semiconductor structure involved in the above embodiments. Exemplarily, the photonic chip may be a photonic computing chip, and exemplary, the photonic computing chip is a photonic computing chip based on a neural network. The photonic chip in the embodiment of the present application may be a silicon photonic chip.

[0161] The embodiment of the present application further provides an optical computing device, which may include the photonic chip involved in the above embodiment.

[0162] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application is described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents; and these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application. In addition, if two or more features, systems, products, materials and / or methods described herein do not contradict each other, any combination of these features, systems, products, materials and / or methods is included within the scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: substrate; a first semiconductor device layer located above the substrate, the first semiconductor device layer comprising an active device and a first waveguide optically interconnected with the active device; a metal interconnect structure located above the first semiconductor device layer, the active device being electrically connected to the metal interconnect structure; a second semiconductor device layer located above the metal interconnect structure, the second semiconductor device layer comprising a grating coupler and a second waveguide optically interconnected with the grating coupler; an optical interconnection structure, wherein the first waveguide and the second waveguide are optically interconnected through the optical interconnection structure; An electrical connection structure, a first end of the electrical connection structure is electrically connected to the metal interconnection structure, and a second end of the electrical connection structure is used to be electrically connected to an external circuit.

2. The semiconductor structure according to claim 1, characterized in that: The grating coupler comprises a grating structure; the semiconductor structure further comprises: A first dielectric layer is covered on the second semiconductor device layer, wherein the first dielectric layer is provided with an opening used as a light passage, and the opening is located above the grating structure.

3. The semiconductor structure according to claim 2, characterized in that: The electrical connection structure penetrates the first dielectric layer and is arranged away from the grating coupler and the second waveguide.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: Also includes: A second dielectric layer covering the first semiconductor device layer, wherein the metal interconnect structure is wrapped in the second dielectric layer; The optical interconnection structure penetrates the second dielectric layer and is arranged away from the metal interconnection structure.

5. The semiconductor structure according to claim 4, characterized in that: The active device is electrically connected to the metal interconnection structure through an electrical contact hole located in the second dielectric layer.

6. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The material of the second semiconductor device layer is a single crystal semiconductor material.

7. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The active devices include light modulators and / or light detectors.

8. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The metal interconnection structure includes multiple metal interconnection layers and conductive vias connecting adjacent metal interconnection layers.

9. A method for preparing a semiconductor, characterized in that: include: providing a first substrate; forming a first semiconductor device layer on the first substrate, the first semiconductor device layer comprising an active device and a first waveguide optically interconnected with the active device; forming a metal interconnect structure and an optical interconnect structure above the first semiconductor device layer, wherein the active device is electrically connected to the metal interconnect structure; forming a second semiconductor device layer over the metal interconnection structure and the optical interconnection structure, the second semiconductor device layer comprising a grating coupler and a second waveguide optically interconnected with the grating coupler, the first waveguide and the second waveguide optically interconnected through the optical interconnection structure; An electrical connection structure is formed, wherein a first end of the electrical connection structure is electrically connected to the metal interconnection structure, and a second end of the electrical connection structure is used to be electrically connected to an external circuit.

10. The method according to claim 9, characterized in that The grating coupler comprises a grating structure; the method further comprises: forming a first dielectric layer for covering the second semiconductor device layer; An opening serving as a light passage is provided on the first medium layer, and the opening is located above the grating structure.

11. The method according to claim 10, characterized in that An electrical connection structure is formed, comprising: Etching a region of the first dielectric layer that avoids the grating coupler and the second waveguide to form a first through hole in the first dielectric layer; A metal material is deposited in the first through hole to obtain an electrical connection structure that penetrates the first dielectric layer.

12. The method according to any one of claims 9 to 11, characterized in that A metal interconnect structure and an optical interconnect structure are formed above the first semiconductor device layer, comprising: forming a second dielectric layer and a metal interconnect structure above the first semiconductor device layer, wherein the metal interconnect structure is wrapped in the second dielectric layer; Etching a region of the second dielectric layer that avoids the metal interconnect structure to form a second through hole in the second dielectric layer; Depositing a semiconductor material in the second through hole to obtain a first optical interconnect structure penetrating the second dielectric layer; Wherein, the optical interconnection structure includes the first optical interconnection structure.

13. The method according to claim 12, characterized in that Forming a second semiconductor device layer above the metal interconnect structure and the optical interconnect structure, comprising: Providing a second substrate, wherein the second substrate comprises a first semiconductor layer and a third dielectric layer formed on a surface of the first semiconductor layer; Bonding the surface of the third dielectric layer to the surface of the second dielectric layer through a bonding process; The first semiconductor layer is etched to obtain a second semiconductor device layer.

14. The method according to claim 13, characterized in that Also includes: forming a fourth dielectric layer covering the second semiconductor device layer; Sequentially etching the fourth dielectric layer and the third dielectric layer to form a third through hole; Depositing a semiconductor material in the third through hole to obtain a second optical interconnection structure; One end of the second optical interconnection structure is in contact with and connected to the first optical interconnection structure, and the other end of the second optical interconnection structure is in contact with and connected to the second waveguide. The optical interconnection structure includes the first optical interconnection structure and the second optical interconnection structure.

15. A photonic chip, characterized in that: The semiconductor structure comprises the semiconductor structure as claimed in any one of claims 1 to 8.

16. An optical computing device, characterized in that include: The photonic chip as described in claim 15 above.

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