CNN-oriented signed approximate multiply-add calculation unit based on error mutual compensation

Abstract

The invention discloses a CNN-oriented signed approximate multiply-add calculation unit based on error mutual compensation, and belongs to the technical field of calculation, reckoning or counting. The approximate multiplication and addition calculation unit comprises a sign bit processing module, a sub multiplier module and a partial accumulation module. And the symbol processing module performs XOR operation on the symbol bits of the two input operands to obtain the symbol bit of a calculation result. The sub-multiplier module multiplies the numerical value part of the operand to obtain a partial product; wherein a precise multiplier is used when the numeric high order is multiplied by the numeric high order, and an approximate multiplier is used in other cases. The partial accumulation module uses an accurate adder at a high position and uses an approximate adder at a low position. And meanwhile, when the approximate multiplier and the approximate adder are designed, errors of the approximate multiplier and the approximate adder are mutually compensated, so that the energy efficiency of the circuit is improved, the influence of approximate calculation on the precision of the neural network is reduced, and the requirement of the neural network on calculation precision is met.

Description

Technical Field

[0001] The present invention relates to engineering technologies such as approximate computing, energy-efficient computing circuits, neural networks, and particularly discloses a signed approximate multiplication-addition computing unit based on error mutual compensation for a convolutional neural network and an implementation method thereof, belonging to the technical field of computing, inference or counting. Background Art

[0002] In recent decades, with the advancement of chip manufacturing technology, the performance of processors has been greatly improved. However, the rise of application fields such as big data and artificial intelligence, as well as the emergence of application scenarios such as embedded and the Internet of Things, have put forward higher requirements for low-power and high-efficiency computing units. At the same time, artificial intelligence applications such as image classification and speech recognition have a certain degree of fault tolerance, and it is not always necessary to perform precise calculations when processing data. Therefore, approximate calculations that sacrifice some calculation accuracy to obtain higher energy efficiency are becoming increasingly important.

[0003] The most successful type of artificial neural network is the Convolutional Neural Network (CNN), which is a multi-layer artificial neural network. Each layer of the network performs multiplication and summation operations on the output of the previous layer of the network to generate the input of the next layer of the network. The network structure can be divided into convolutional layer, pooling layer, activation layer, fully connected layer and loss layer. The main calculation of CNN comes from the convolution operation in a large number of convolutional layers, so a large number of multiplication and addition operations are required. The core of the neural network accelerator is the computing unit, which is used to perform operations such as convolution, matrix multiplication, and activation function in the neural network. There is a multiplier and accumulation unit (MAC) in each computing unit. The performance improvement of a single multiplier can significantly improve the performance of the entire accelerator. Therefore, it is necessary to design an approximate multiplication and addition computing unit for convolutional neural networks.

[0004] CNN itself is tolerant to some smaller errors, and the output of the convolutional layer will accumulate a large number of multiplication results. Therefore, as long as the variance of the error is small, the accumulated error will converge to the average value, which will not affect the extraction of abstract features. In order to minimize the error variance, the simplest method is to obtain a uniformly distributed error, but this method has too high requirements for the approximate solution. It only needs to meet the requirement of obtaining a unified error expectation for the same input distribution. At the same time, it is also required that the positive and negative errors are as symmetrical as possible to offset each other. In addition, the relative error also needs to be as small as possible, that is, the smaller the calculation result, the higher the accuracy. Combined with the above requirements, it is only necessary to calculate the relative error distribution of the approximate calculation unit. When it is close to the normal distribution, the results of the multiplication and addition calculations will compensate each other, thereby improving the accuracy of network recognition.

[0005] Due to the rapid development of circuit scale at this stage, traditional manual design methods can no longer meet the collaborative design requirements of ultra-large-scale integrated circuits. Therefore, in recent years, a variety of circuit design methods based on automatic logic synthesis have emerged, such as Cartesian genetic algorithm and Boolean matrix decomposition. In Boolean matrix decomposition design, since the input matrix can be decomposed into several sub-circuits to reduce the number of inputs and reduce time complexity, it is more suitable for designing large-scale approximate circuits such as multipliers. However, when designing approximate circuits, existing Boolean matrix decomposition considers accuracy and ignores energy efficiency. For approximate adders, their structure is relatively simple, so it is easy to obtain approximate adders with errors biased in a specific direction through Cartesian genetic algorithms; when using Boolean matrix decomposition to generate approximate adders, since it is necessary to generate compressor circuits and decompressor circuits and then combine them, for small-scale adders, it may lead to hardware complexity, and the actual circuit performance is not as expected. Therefore, Boolean matrix decomposition is not suitable for the design of approximate adders. In addition, for an approximate multiplication-addition calculation unit that includes multiplication and addition operations, the error of the approximate multiplier will be further accumulated and / or amplified after the approximate addition operation, which will eventually affect the accuracy of the approximate multiplication-addition operation. Therefore, it is necessary to comprehensively consider the approximate multiplication error and the approximate addition error when designing the circuit.

[0006] In summary, the present invention aims to propose a high-energy-efficiency approximate multiplication-addition computing unit for convolutional neural networks to overcome the above-mentioned defects. Summary of the invention

[0007] The purpose of the present invention is to address the deficiencies of the above-mentioned background technology and provide a signed approximate multiplication and addition calculation unit based on error mutual compensation for convolutional neural networks. Under the constraint of a criterion function that considers the trade-off between accuracy and performance, Boolean matrix decomposition is used to design an approximate multiplier, and then a Cartesian genetic algorithm is used to design an approximate adder based on the error characteristics of the approximate multiplier, so that the error of the approximate multiplier and the error of the approximate adder compensate each other. While providing high energy efficiency and occupying less hardware resources, the impact of the error caused by approximate calculation on the accuracy of the neural network is reduced, the technical problem of limited power consumption of hardware deployment at the edge of the neural network is solved, and the purpose of the invention of balancing the accuracy and energy efficiency of computing hardware is achieved.

[0008] The present invention adopts the following technical solutions to achieve the above-mentioned invention object:

[0009] A signed approximate multiplication and addition calculation unit based on error mutual compensation for CNN includes: a sign bit processing module, a sub-multiplier module and a partial accumulation and addition module; the sign bit processing module is used to obtain the sign bit of the multiplication and addition calculation result according to the sign bits of two fixed-point signed operands input; the sub-multiplier module includes: an accurate multiplier for performing an accurate multiplication operation on the numerical high bits of the two operands, an approximate multiplier for performing an approximate multiplication operation on the numerical high bits of one operand and the numerical low bits of another operand, and an approximate multiplier for performing an approximate multiplication operation on the numerical low bits of the two operands, and the approximate multiplier is passed under the constraint of a metric function that considers the trade-off between accuracy and performance. Acquired by Boolean matrix decomposition; a partial accumulation module, including: an accurate adder for performing accurate addition operation on the numerical high bits of the partial products output by each multiplier in the sub-multiplier module, an approximate adder for performing approximate addition operation on the numerical low bits of the partial products output by each multiplier in the sub-multiplier module, the accumulation result of the accurate adder and the accumulation result of the approximate adder are spliced ​​into the numerical part of the multiplication and addition calculation, the sign bit of the multiplication and addition calculation result and the numerical part of the multiplication and addition calculation are combined to obtain the final result of the approximate multiplication and addition calculation, the approximate adder is generated by a Cartesian genetic algorithm, and the fitness function of the Cartesian genetic algorithm includes mathematical terms that are complementary to the error distribution of the approximate adder and the error distribution of the approximate multiplier.

[0010] As a further optimization scheme for a signed approximate multiplication-addition calculation unit based on error mutual compensation for CNN, a sign bit processing module obtains the sign bit of the multiplication-addition calculation result according to the sign bits of the two input fixed-point signed operands. Specifically, the two input fixed-point signed operands are encoded, and the encoding of each fixed-point signed operand includes: a sign bit, a high bit of the value, and a low bit of the value, and an XOR operation is performed on the sign bits of the two input operands.

[0011] As a further optimization scheme for a signed approximate multiplication-addition computing unit based on error mutual compensation for CNN, a metric function considering the trade-off between accuracy and performance includes: a mathematical term measuring the size of the approximate multiplication operation error and a mathematical term measuring the energy efficiency of the approximate multiplication circuit.

[0012] As a further optimization scheme for the signed approximate multiplication-addition computing unit based on error mutual compensation for CNN, the fitness function of the Cartesian genetic algorithm also includes mathematical terms that measure the size of the approximate addition operation error and mathematical terms that measure the energy efficiency of the approximate addition circuit.

[0013] As a further optimization scheme for the signed approximate multiplication-addition computing unit based on error mutual compensation for CNN, the metric function considering the trade-off between accuracy and performance is Where n is the number of multiplication operations, Y iis the exact result of the i-th multiplication operation, Y i ′ is the approximate result of the i-th multiplication operation, FET_num1 is the number of transistors in the approximate multiplier circuit, α and β are the weights of the approximate multiplication operation error and the energy efficiency of the approximate multiplication circuit, respectively, and α+β=1.

[0014] As a further optimization scheme for the signed approximate multiplication and addition unit based on error mutual compensation for CNN, the fitness function of the Cartesian genetic algorithm is: Where m is the number of addition operations, Z j is the exact result of the jth addition operation, Z j ′ is the approximate result of the j-th addition operation, FET_num2 is the number of transistors in the approximate adder circuit, D is the expected error distribution of the approximate adder, a, b and c are the weights of the approximate addition operation error size, the approximate adder circuit energy efficiency and the approximate adder error distribution, respectively, and a+b+c=1.

[0015] As a further optimization scheme for a signed approximate multiplication-addition calculation unit based on mutual error compensation for CNN, the partial accumulation-addition module also includes: a shift circuit for performing a shift operation on the partial products output by each multiplier in the sub-multiplier module.

[0016] As a further optimization scheme for the signed approximate multiplication-addition computing unit based on error mutual compensation for CNN,

[0017] When the calculation bit width of the two fixed-point signed operands is 2N, all multipliers in the sub-multiplier module and all adders in the partial accumulation and addition module participate in the operation, 2N is the complete input operand bit width of the approximate multiplication and addition calculation unit, 4≤N≤8;

[0018] When performing an exact multiplication operation on two fixed-point signed input operands with a computing bit width of N-1, the exact multiplier that performs an exact multiplication operation on the high bits of the values ​​of the two operands participates in the operation, and all approximate multipliers and some accumulation-addition modules do not participate in the operation;

[0019] When an approximate multiplication operation is performed on two fixed-point signed input operands both having a computing bit width of N, the approximate multiplier that performs an approximate multiplication operation on the numerical low bits of the two operands participates in the operation, and the precise multiplier, the remaining approximate multipliers, and some accumulation-addition modules do not participate in the operation;

[0020] When the bit widths of two fixed-point signed operands are N and N-1 respectively, an approximate multiplier that performs an approximate multiplication operation on the high bit of the value of one operand and the low bit of the value of the other operand participates in the operation, and the precise multiplier, the remaining approximate multipliers and some accumulation and addition modules do not participate in the operation.

[0021] The present invention provides a method for implementing a signed approximate multiplication-addition computing unit based on error mutual compensation for a convolutional neural network, comprising the following steps:

[0022] Step 1, split the two input fixed-point operands into a sign bit, a high bit of a value, and a low bit of a value respectively;

[0023] Step 2, performing an XOR operation on the sign bits of the two input operands to obtain the sign bit of the multiplication and addition calculation result;

[0024] Step 3, sending the encoded high-order and low-order values ​​of the two input operands to the sub-multiplier module, so that they are multiplied to obtain four partial products respectively, and using an exact multiplier when the high-order value is multiplied by the high-order value, and using an approximate multiplier in other cases;

[0025] Step 4, send the four partial products to the partial accumulation and addition module for accumulation, use the precise adder for the high position and the approximate adder for the low position, and make the errors of the approximate adder and the approximate multiplier compensate each other to obtain the numerical part of the multiplication and addition calculation result, and get the final calculation result after combining with the sign bit.

[0026] The present invention adopts the above technical solution and has the following beneficial effects:

[0027] (1) The present invention provides a signed approximate multiplication and addition calculation unit based on error mutual compensation for a convolutional neural network. An approximate multiplier is generated by using Boolean matrix decomposition, and then an approximate adder is generated by using a Cartesian genetic algorithm according to the error characteristics of the approximate multiplier. The overall errors of the two approximate calculation circuits are close to a normal distribution, so that positive and negative errors compensate for each other and reduce the influence of approximate calculation on the accuracy of the neural network.

[0028] (2) The present invention uses an automatic logic synthesis method in the design of approximate circuits. In the Boolean matrix decomposition design of the approximate multiplier, the mean square error and the number of transistors are comprehensively considered to select an approximate multiplier circuit with a good compromise between accuracy and energy efficiency from the candidate approximate multiplier circuits. In the design of the approximate adder, the fitness function that considers the complementary factors of the approximate adder error and the approximate multiplier error distribution is used to evaluate the approximate adder circuit automatically generated by the Cartesian genetic algorithm. Finally, an approximate adder circuit that can compensate for the approximate adder error and has a good compromise between accuracy and energy efficiency is obtained, thereby ensuring that the designed approximate multiplication and addition circuit achieves a good balance between accuracy and energy efficiency. At the same time, the efficiency of circuit design is greatly improved compared with manual design. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the overall architecture of a signed approximate multiplication-addition computing unit based on error mutual compensation for a convolutional neural network proposed by the present invention.

[0030] Figure 2 is a flowchart of using Boolean matrix decomposition to generate approximate multipliers in the sub-multiplier module.

[0031] Figure 3 It is a schematic diagram of Boolean matrix decomposition to generate a compressor matrix, a decompressor matrix and a final approximate Boolean matrix.

[0032] Figure 4 It is a flowchart of using Cartesian genetic algorithm to generate the approximate adder in the partial accumulation and addition module.

[0033] Figure 5 This is the circuit diagram of the approximate adder in the partial accumulation-add module generated using the Cartesian genetic algorithm. DETAILED DESCRIPTION

[0034] The technical solution of the invention is described in detail below with reference to the accompanying drawings.

[0035] like Figure 1 As shown, the present invention proposes a signed approximate multiplication and addition calculation unit based on error mutual compensation for convolutional neural networks, which is used to calculate the multiplication and addition operations of signed numbers in neural networks. The approximate multiplication and addition calculation unit includes: a sign bit processing module, a sub-multiplier module and a partial accumulation and addition module.

[0036] The sign processing module is used to obtain the sign bit of the multiplication and addition calculation result according to the sign bits of the two input fixed-point signed operands, specifically including encoding operation and XOR operation. First, the two input fixed-point signed operands are encoded, specifically: when the input fixed-point signed operand is a positive number, it remains unchanged; when the input fixed-point signed operand is a negative number, its sign bit remains unchanged, the value bit is inverted and added by one, but the carry is discarded, so as to keep the bit width unchanged; the encoded input operand is divided into three parts: the sign bit, the high value bit and the low value bit; for example, if the input fixed-point signed operand is the decimal number 127 represented by 8-bit binary complement, that is, 01111111, it remains unchanged; if the input fixed-point signed operand is the decimal number -1 represented by 8-bit binary complement, that is, 11111111, its sign bit remains unchanged, the value bits 1111111 are inverted to obtain 0000000, and then 1 is added to obtain 0000001, that is, the value bits represent the absolute value of the input operand. When the input operand is 8 bits, the highest bit is the sign bit, the high bit of the value is the following 3 bits, and the remaining 4 bits are the low bits of the value. Then, the sign bits of the two input operands are XORed to obtain the sign bit of the approximate multiplication and addition calculation result, that is, when the signs of the two input operands are the same, the multiplication and addition result is a positive number and the sign bit is 0; when the signs of the two input operands are different, the multiplication and addition result is a negative number and the sign bit is 1.

[0037] The sub-multiplier module is used to perform multiplication operations on the numerical high bits and numerical low bits of two operands respectively, perform precise multiplication operations on the numerical high bits of the two operands, perform approximate multiplication operations on the numerical high bits of one operand and the numerical low bits of the other operand, and perform approximate multiplication operations on the numerical low bits of the two operands. For example: when the input operand is 8 bits, the 4 multipliers in the sub-multiplier module perform calculations simultaneously, namely, a 4×4 multiplier, a 3×3 multiplier, and two 4×3 multipliers, of which the 3×3 multiplier is a precise multiplier, and the remaining multipliers are approximate multipliers generated by Boolean matrix decomposition.

[0038] The process of generating approximate multipliers by Boolean matrix decomposition is as follows Figure 2 As shown, first, the compressor matrix B and decompressor matrix C are decomposed into the original input Boolean matrix M, and the final approximate Boolean matrix A, M≈B⊙C, where ⊙ represents Boolean matrix multiplication. The process of Boolean matrix decomposition to obtain each matrix is ​​as follows Figure 3As shown, when the compressor matrix B and the decompressor matrix C perform Boolean matrix multiplication, the accumulated result of the multiplication is calculated using logic or; then, the compressor matrix B and the decompressor matrix C are converted into operation circuits respectively using a logic synthesis tool, and the converted operation circuits are combined to obtain a candidate approximate multiplication circuit; then, the mean square error is used as the error measurement function, the number of transistors is used as an indicator of circuit area and power consumption, and the error measurement function is combined with the indicators of circuit area and power consumption as a measurement standard function S, and an approximate multiplier circuit with a better compromise between accuracy and energy efficiency is selected from the candidate approximate multiplication circuits. The calculation formula of the measurement standard function S is as follows:

[0039]

[0040] Where n is the number of multiplication operations, Y i is the exact result of the i-th multiplication operation, Y i ′ is the approximate result of the i-th multiplication operation, FET_num1 is the number of transistors in the approximate multiplier circuit, α and β are the weights of the error size and circuit energy efficiency, respectively, and α+β=1.

[0041] By designing the approximate adder in the sub-multiplier module, the high-bit multiplication is calculated accurately, and the low-bit multiplication is calculated approximately, so that a good compromise can be achieved between the calculation accuracy and hardware energy efficiency. In addition, when calculating the multiplication of input operands with a smaller bit width, each multiplier in the sub-multiplier module can be calculated independently and in parallel. For example, when calculating 3-bit data multiplied by 3-bit data, a 3×3 accurate multiplier can be used for calculation, and the multiplication result can be obtained directly without generating partial products, so there is no need to call the partial accumulation and addition module.

[0042] The partial accumulation module is used to perform accumulation operations on the partial products generated by the sub-multiplier module, obtain the numerical part of the multiplication and addition calculation, combine the numerical part of the multiplication and addition calculation with the sign bit of the approximate multiplication and addition calculation result, and obtain the final result of the approximate multiplication and addition calculation. The accumulation operation on the partial products generated by the sub-multiplier module is specifically: performing an accurate addition operation on the numerical high bits of the partial products, and performing an approximate addition operation on the numerical low bits of the partial products. The approximate adder for performing an approximate addition operation on the numerical low bits of the partial products is generated using a Cartesian genetic algorithm based on the error characteristics of the approximate multiplier in the sub-multiplier module, so that the error of the approximate multiplication and the error of the approximate adder compensate each other.

[0043] The Cartesian genetic algorithm represents the adder circuit as a two-dimensional programmable node combination, where the nodes are basic logic gates, such as AND gates, OR gates, NOT gates, and XOR gates. The offspring population is generated through the inheritance and mutation of the nodes. Each individual in the offspring population represents an approximate adder circuit design scheme, and the best individual is selected according to the fitness function. The calculation formula of the fitness function F is as follows:

[0044]

[0045] Where m is the number of addition operations, Z j is the exact result of the jth addition operation, Z j ′ is the approximate result of the j-th addition operation, FET_num2 is the number of transistors in the approximate adder circuit; D is the expected error distribution of the approximate adder, which is complementary to the error distribution of the approximate multiplier, that is, the errors of the approximate multiplier and the approximate adder are superimposed and approach a normal distribution with a mathematical expectation of 0, so that the positive and negative errors cancel each other out; a, b and c are the error size, circuit energy efficiency and the weight of the error distribution, respectively, and a+b+c=1.

[0046] The bit width and precision of the approximate multiplication and addition calculation unit are reconfigurable. Assuming that the complete input operand bit width of the approximate multiplication and addition calculation unit is 2N, 4≤N≤8, when calculating the input operand with a bit width of 2N, all multipliers in the sub-multiplier module and all adders in the partial accumulation and addition module participate in the operation. When calculating input operands with a bit width of N or N-1, the four multipliers in the sub-multiplier module can perform multiplication operations in parallel and directly output the multiplication results without passing through the partial accumulation and addition module, which specifically includes the following three situations: In the first situation, when the multiplication of two input operands with a bit width of N-1 is accurately calculated, the precise multiplier corresponding to the multiplication of the high-order values ​​is used, and all approximate multipliers and the partial accumulation and addition module do not participate in the operation; In the second situation, when the multiplication of two input operands with a bit width of N is approximate, the approximate multiplier for multiplying the low-order values ​​of the two operands is used, and the precise multiplier, the remaining approximate multipliers and the partial accumulation and addition module do not participate in the operation; In the third situation, when the bit widths of the two input operands are N and N-1 respectively, two approximate multipliers for multiplying the low-order values ​​by the high-order values ​​are used, and the precise multiplier, the remaining approximate multipliers and the partial accumulation and addition module do not participate in the operation.

[0047] The partial accumulation and addition module includes a shift circuit, an approximate adder, and an exact adder. Assuming that both input operands are 8 bits, the partial product obtained by multiplying the high bit of the value by the high bit of the value is 6 bits, which needs to be shifted left by 8 bits; the partial product obtained by multiplying the low bit of the value by the low bit of the value is 8 bits, which does not require left shifting, so the two partial products have no overlapping parts and can be combined and recorded as PP1; the two partial products obtained by multiplying the high bit of the value by the low bit of the value are 7 bits, which need to be shifted left by 4 bits. The two partial products overlap with each other, so they need to be accumulated first to obtain PP2. Then PP1 and PP2 are accumulated to obtain the numerical part of the approximate multiplication and addition calculation result. In the addition tree, an exact adder is used for the high bit, and an approximate adder is used for the low bit. The approximate adder is generated using a Cartesian genetic algorithm based on the error characteristics of the approximate multiplier in the sub-multiplier module, so that the errors of the two compensate for each other. In order to meet the requirements of energy consumption and accuracy at the same time, when PP1 and PP2 are accumulated, the lower 8 bits use an approximate adder designed by a Cartesian genetic algorithm. The flow chart of the Cartesian algorithm is shown as follows. Figure 4 As shown, the circuit schematic diagram of the approximate adder is as follows Figure 5 As shown. The 9th to 15th bits use a precise adder. The numerical part of the multiplication and addition calculation result can be obtained by adding PP1 and PP2, and the final approximate multiplication and addition calculation result can be obtained by combining it with the sign bit. The sign bit of the calculation result indicates whether it is positive or negative. When the sign bit is 0, it indicates a positive number, and when the sign bit is 1, it indicates a negative number; the numerical bit uses binary to represent the absolute value of the calculation result.

[0048] The present invention is not limited to the above-mentioned optimal implementation mode. Under the inspiration of the present invention, anyone can derive other various forms of high-efficiency approximate multiplication-addition computing units for convolutional neural networks and implementation methods thereof, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims

1. A signed approximate multiplication-addition computing unit based on error mutual compensation for CNN, It is characterized in that include: A sign bit processing module, used for obtaining the sign bit of the multiplication and addition calculation result according to the sign bits of the two input fixed-point signed operands; A sub-multiplier module, comprising: an exact multiplier for performing an exact multiplication operation on the numerical high bits of two operands, an approximate multiplier for performing an approximate multiplication operation on the numerical high bits of one operand and the numerical low bits of another operand, and an approximate multiplier for performing an approximate multiplication operation on the numerical low bits of the two operands, wherein the approximate multiplier is obtained by Boolean matrix decomposition under the constraint of a metric function considering a trade-off between accuracy and performance; and, The partial accumulation and addition module comprises: an accurate adder for performing accurate addition operation on the numerical high bits of the partial products output by each multiplier in the sub-multiplier module, and an approximate adder for performing approximate addition operation on the numerical low bits of the partial products output by each multiplier in the sub-multiplier module, the accumulation result of the accurate adder and the accumulation result of the approximate adder are spliced ​​into the numerical part of the multiplication and addition calculation, the sign bit of the multiplication and addition calculation result and the numerical part of the multiplication and addition calculation are combined to obtain the final result of the approximate multiplication and addition calculation, the approximate adder is generated by a Cartesian genetic algorithm, and the fitness function of the Cartesian genetic algorithm includes mathematical terms that complement the error distribution of the approximate adder and the error distribution of the approximate multiplier.

2. According to claim 1, a signed approximate multiplication and addition computing unit based on error mutual compensation for CNN, It is characterized in that The sign bit processing module obtains the sign bit of the multiplication and addition calculation result according to the sign bits of the two input fixed-point signed operands, specifically: the two input fixed-point signed operands are encoded, and the encoding of each fixed-point signed operand includes: a sign bit, a high bit of the value and a low bit of the value, and an exclusive OR operation is performed on the sign bits of the two input operands.

3. According to claim 2, a signed approximate multiplication and addition computing unit based on error mutual compensation for CNN, It is characterized in that The metric function considering the trade-off between accuracy and performance includes: a mathematical term measuring the magnitude of the approximate multiplication operation error and a mathematical term measuring the energy efficiency of the approximate multiplication circuit.

4. According to claim 3, a signed approximate multiplication and addition computing unit based on error mutual compensation for CNN, It is characterized in that The fitness function of the Cartesian genetic algorithm also includes a mathematical term for measuring the size of the approximate addition operation error and a mathematical term for measuring the energy efficiency of the approximate addition circuit.

5. According to claim 3, a signed approximate multiplication and addition computing unit based on error mutual compensation for CNN, It is characterized in that The criterion function considering the trade-off between accuracy and performance is: Where n is the number of multiplication operations, Y i is the exact result of the i-th multiplication operation, Y i ′ is the approximate result of the i-th multiplication operation, FET_num1 is the number of transistors in the approximate multiplier circuit, α and β are the weights of the approximate multiplication operation error and the energy efficiency of the approximate multiplication circuit, respectively, and α+β=1.

6. According to claim 4, a signed approximate multiplication and addition computing unit based on error mutual compensation for CNN, It is characterized in that The fitness function of the Cartesian genetic algorithm is Where m is the number of addition operations, Z j is the exact result of the jth addition operation, Z j ′ is the approximate result of the j-th addition operation, FET_num2 is the number of transistors in the approximate adder circuit, D is the expected error distribution of the approximate adder, a, b and c are the weights of the approximate addition operation error size, the approximate adder circuit energy efficiency and the approximate adder error distribution, respectively, and a+b+c=1.

7. A signed approximate multiplication-addition computing unit based on error mutual compensation for CNN according to any one of claims 1 to 6, It is characterized in that The partial accumulation and addition module also includes a shift circuit for performing a shift operation on the partial products output by each multiplier in the sub-multiplier module.

8. A signed approximate multiplication-addition computing unit based on error mutual compensation for CNN according to any one of claims 1 to 6, It is characterized in that When the calculation bit widths of the two fixed-point signed operands are both 2N, all multipliers in the sub-multiplier module and all adders in the partial accumulation-addition module participate in the operation, 2N is the complete input operand bit width of the approximate multiplication-addition calculation unit, 4≤N≤8; When performing an exact multiplication operation on two fixed-point signed input operands with a computing bit width of N-1, the exact multiplier that performs an exact multiplication operation on the high bits of the values ​​of the two operands participates in the operation, and all approximate multipliers and some accumulation-addition modules do not participate in the operation; When an approximate multiplication operation is performed on two fixed-point signed input operands both having a computing bit width of N, the approximate multiplier that performs an approximate multiplication operation on the numerical low bits of the two operands participates in the operation, and the precise multiplier, the remaining approximate multipliers, and some accumulation-addition modules do not participate in the operation; When the bit widths of two fixed-point signed operands are N and N-1 respectively, an approximate multiplier that performs an approximate multiplication operation on the high bit of the value of one operand and the low bit of the value of the other operand participates in the operation, and the precise multiplier, the remaining approximate multipliers and some accumulation and addition modules do not participate in the operation.

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