Storage address generation method, storage control method and storage address generation device

Abstract

The invention provides a memory address generation method, a memory control method and a memory address generation device. The generation method comprises the following steps: obtaining a data memory address based on an address signal from a bus of the SOC system by utilizing a memory controller in the SOC system, and correspondingly storing data from the bus into a data memory unit according to an access sequence from the lowest bit to the highest bit of the data memory address; and based on the mode of the storage controller, obtaining the ECC memory address, and correspondingly storing the obtained ECC check codes into the ECC storage unit according to the access sequence from the highest bit to the lowest bit of the ECC memory address. Therefore, the problem of common cause failure of the address line can be avoided, and the function safety protection effect is improved.

Description

Technical Field

[0001] The present application relates to the field of storage control technology, and in particular to a method for generating a memory address, a storage control method and a generating device. Background Art

[0002] The system memory subsystem inside the existing vehicle SOC chip needs to have functional safety protection. Usually, when the data is stored in the data memory, the corresponding ECC check code is stored in the ECC memory. When the processor reads the data in the data memory, the storage controller reads the data and ECC check code in the data memory and ECC memory at the same time to perform ECC check.

[0003] At present, the address of the data memory is obtained based on the address signal of the bus, and the address of the ECC memory is obtained by logical processing based on the address of the data memory. However, the present application finds that once the address lines of the data memory and the ECC memory have a common cause failure problem, since the ECC check code stored in the ECC memory is obtained based on the data in the data memory, it is very likely that the storage controller matches the data read from the data memory and the ECC check code stored in the ECC memory, but since the data and the ECC check code are taken from the wrong address, this still does not meet the requirements of functional safety protection and the erroneous data cannot be identified and corrected in time. Summary of the invention

[0004] In view of the above technical problems existing in the prior art, this application is proposed. This application aims to provide a method for generating a memory address, a storage control method and a generating device, which can avoid the problem of common cause failure of address lines and improve the effect of functional safety protection.

[0005] According to a first scheme of the present application, a method for generating a memory address is provided, wherein the memory address includes a data memory address and an ECC memory address, and the generating method includes: utilizing a memory controller in a SOC system to obtain a data memory address based on an address signal from a bus of the SOC system, and storing the data from the bus in a data storage unit in an access order from the lowest bit to the highest bit of the data storage address; based on a mode of the memory controller, obtaining the ECC memory address, and storing the obtained ECC check code in an ECC storage unit in an access order from the highest bit to the lowest bit of the ECC memory address.

[0006] According to a second scheme of the present application, a storage control method based on a SOC system is provided, the storage control method comprising: using a storage controller in the SOC system, obtaining a data storage address based on an address signal from a bus of the SOC system, and storing the data from the bus in a data storage unit in an access order from the lowest bit to the highest bit of the data storage address; obtaining an ECC memory address based on a mode in which the storage controller is located, and storing the obtained ECC check code in an ECC storage unit in an access order from the highest bit to the lowest bit of the ECC memory address; reading target data from the data storage unit in an access order from the lowest bit to the highest bit of the data storage address, and generating a second ECC check code based on the read target data; reading a first ECC check code from the ECC storage unit in an access order from the highest bit to the lowest bit of the ECC memory address, and judging whether the data has an error by comparing the second ECC check code with the first ECC check code.

[0007] According to a third scheme of the present application, a device for generating a memory address is provided, wherein the memory address includes a data memory address and an ECC memory address, and the generating device includes a memory controller, wherein the memory controller includes a first address decoding module, a second address decoding module, and a second inverter, and the memory controller is configured as follows: using the first address decoding module, obtaining a data memory address based on an address signal from a bus of the SOC system, and storing the data from the bus in a data storage unit in an access order from the lowest bit to the highest bit of the data storage address; using the second address decoding module, obtaining the ECC memory address according to a mode of the memory controller, and using the second inverter, and storing the obtained ECC check code in an ECC storage unit in an access order from the highest bit to the lowest bit of the ECC memory address.

[0008] According to a fourth solution of the present application, a SOC chip is provided, the SOC chip comprising a memory controller, the memory controller being configured to execute the memory address generation method described in each embodiment of the present application.

[0009] Compared with the prior art, the beneficial effects of the embodiments of the present application are: The memory address generation method provided by the embodiment of the present application uses a memory controller to obtain a data memory address based on an address signal, and the data memory address is used as a physical address of a data storage unit, and the data from the bus is stored in the data storage unit in an access order from the lowest bit to the highest bit of the data storage address. In addition, the ECC memory address is obtained by using the memory controller, and the obtained ECC check code is stored in the ECC storage unit in an access order from the highest bit to the lowest bit of the ECC memory address.

[0010] Storing the ECC check code in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address is equivalent to inverting the ECC memory address. In this way, by controlling the generation stage of the physical address lines of the data storage unit and the ECC storage unit, the ECC check code is stored in the ECC storage unit corresponding to the inverted ECC memory address, which can effectively avoid the common cause failure problem of the address line.

[0011] Moreover, when accessing the ECC storage unit, the storage controller reads the ECC check code in the access order from high to low. By comparing the data read from the data storage unit and the ECC check code read from the ECC storage unit, it can accurately determine whether there are errors in the data stored in the data storage unit, thereby timely identifying the erroneous data and improving the effect of functional safety protection.

[0012] In addition, based on the generation method of the present application, the ECC memory address is inverted for ECC check code storage, which enables the storage controller to switch freely between ECC enabled mode and ECC disabled mode without the need for additional processing steps due to switching between the two modes, increasing the processing complexity.

[0013] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above description and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar parts in different views. Similar reference numerals with letter suffixes or different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments by way of example and not by way of limitation, and together with the description and claims, are used to illustrate the disclosed embodiments. Such embodiments are illustrative and exemplary and are not intended to be exhaustive or exclusive embodiments of the present method, apparatus, system, or non-transitory computer-readable medium having instructions for implementing the method.

[0015] Figure 1 A flowchart of a method for generating a memory address according to an embodiment of the present application is shown.

[0016] Figure 2 A flow chart of a storage control method based on a SOC system according to an embodiment of the present application is shown.

[0017] Figure 3 A schematic structural diagram of a device for generating a memory address according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the technical solution of the present application, the present application is described in detail below in conjunction with the accompanying drawings and specific implementation examples. The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific implementation examples, but are not intended to limit the present application.

[0019] The words "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish. The words "include" or "comprises" and similar words used in this application mean that the elements before the word include the elements listed after the word, and do not exclude the possibility of covering other elements. In this application, the arrows shown in the figures of each step are only examples of the execution order, not limitations. The technical solution of this application is not limited to the execution order described in the embodiments. The various steps in the execution order can be combined, decomposed, or the order can be changed, as long as the logical relationship of the execution content is not affected.

[0020] All terms (including technical terms or scientific terms) used in this application have the same meaning as those understood by ordinary technicians in the field to which this application belongs, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined here. Techniques and equipment known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the techniques and equipment should be considered as part of the specification.

[0021] Figure 1 A flowchart of a method for generating a memory address according to an embodiment of the present application is shown, as shown in step S101-step S102. The arrows shown in the various steps in the figure are merely examples of the execution order, not limitations. The technical solution of the present application is not limited to the execution order described in the embodiments. The various steps in the execution order can be combined for execution, can be decomposed for execution, and can be swapped in order, as long as the logical relationship of the execution content is not affected.

[0022] In this embodiment, the memory address includes a data memory address and an ECC memory address. The data memory address refers to a physical address used to access actual data in the memory. In a computer system, a data memory (such as RAM) receives an address signal through an address bus to determine the data memory address to be read or written. The ECC memory can be used to store additional ECC check codes, which are used to detect and correct errors in the storage process.

[0023] When using ECC memory, the ECC check code is usually stored together with the data bit, and the logical address space of the ECC memory is expanded to include the check bit information. The ECC memory address can be obtained through logical processing based on the data memory address, thereby realizing the data error detection and correction function. When performing read and write operations, the control logic calculates the corresponding ECC memory address based on the data memory address, thereby ensuring that the data and ECC check code can be correctly accessed and updated.

[0024] However, the present application has found that according to the traditional method of generating physical address lines, there may be a common cause failure problem. The so-called common cause failure can be understood as when accessing the address signal of the bus, due to a flip in a certain bit (for example, accessing from 0 to 1), an erroneous memory address is calculated based on the address signal, and since the ECC memory address is obtained through logical processing based on the data memory address, the ECC memory address also has errors. Then, the present application has found that in the case of a common cause failure problem, since the ECC memory address is obtained through logical processing based on the data memory address, there may be a situation where the data read from the data storage unit still matches the ECC check code read from the ECC storage unit, but since the matching data and the ECC check code may be read from the wrong address, this still does not meet the requirements of functional safety protection, and this will result in the inability to promptly discover the originally erroneous data and correct it in a timely manner.

[0025] The embodiment provided in the present application can solve the above problem. In step S101, a storage controller in a SOC system is used to obtain a data storage address based on an address signal from a bus of the SOC system, and the data from the bus is stored in a data storage unit in an access order from the lowest bit to the highest bit of the data storage address.

[0026] Among them, System on Chip (SoC) refers to the integration of multiple hardware components on a single chip, such as central processing unit (CPU), memory controller, graphics processing unit (GPU), etc., to realize a complete computing system. SOC can contain a die, or multiple identical or different wafers.

[0027] In data storage, the storage controller is a key component responsible for managing and controlling the read and write operations of data on storage media (such as RAM, hard disk, SSD, etc.), such as internal random access memory (Internal RAM, IRAM). The storage controller can be integrated inside the chip as part of the SoC and is responsible for managing the interaction with storage devices (such as RAM, flash memory, etc.).

[0028] Specifically, the storage controller receives read and write requests from the CPU through the bus of the SOC system. The bus may contain corresponding parity check codes and ECC check codes. The storage controller first performs end-to-end check and error correction on the bus, generates an address signal for accessing the memory based on the bus signal after the check and error correction, and calculates the data memory address based on the address signal. For example, the common AXI (Advanced eXtensible Interface) and AHB (Advanced High-performance Bus) buses support burst transmission, and can calculate the physical address of each access to the data memory based on the first address and burst length.

[0029] As an example, the address signal is usually a virtual address or a logical address. The storage controller performs address decoding based on the address signal to determine the range of the address signal and the target storage area. For example, a decoder can be used to separate the address signal into high bits and low bits to determine the memory block to be accessed. In a system using virtual memory, the storage controller needs to convert the virtual address into a physical address by looking up the page table. For example, the corresponding physical page frame number can be found according to the page number in the virtual address. The physical page frame number can be combined with the offset in the virtual address to generate the final physical address. The calculated physical address is sent to the memory or peripheral through the address bus to indicate the data memory address to be read or written.

[0030] This is only an example and does not constitute a limitation on the specific solution.

[0031] The storage controller obtains the data storage address based on the address signal of the bus, performs corresponding read and write operations according to the calculated data storage address, and writes data to the data storage unit of the specified address or reads data from the data storage unit in the access order from the lowest bit to the highest bit of the data storage address.

[0032] In step S102, based on the mode of the storage controller, the ECC memory address is obtained, and the obtained ECC check code is stored in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address. In some other embodiments of the present application, the storage controller supports enabling ECC mode and disabling ECC mode. Enabling ECC mode means that the system or storage device will use error detection and correction code technology to ensure the integrity and reliability of the data when storing and transmitting data. Disabling ECC mode means that during the data storage and transmission process, no form of error detection and correction code is used, and the data will be stored and transmitted in the form of original data.

[0033] Among them, when the storage controller is in ECC-enabled mode, the CPU inside the SOC system can only access the space of the data memory address, and the ECC memory address is obtained by logical processing based on the data memory address. When the storage controller is in ECC-disabled mode, the ECC storage unit can be used as a data storage unit, and the ECC memory address is obtained based on the bus of the SOC system.

[0034] When the storage controller is in the ECC-enabled mode, the data based on the bus is logically processed to obtain the ECC check code. Specifically, the appropriate ECC type can be selected as needed, such as parity check, Hamming code, etc. Different ECC schemes have different error correction capabilities and complexities. The data (usually bytes or larger data blocks) for which the ECC needs to be calculated is divided into data blocks of fixed length, such as 8 bits, 16 bits or 32 bits. For the parity check type, the number of 1s in the data is calculated for each data block. If it is an odd number, a 1 is added as a parity check bit, and if it is an even number, a 0 is added; for the Hamming code, the data is subjected to specific position and logical operations to calculate the check bit, so as to detect and correct single bit errors. The calculated check bit is added to the end of the original data to form a complete ECC check code. For example, if the original data is 8 bits, the generated ECC check code may be 8 bits of data plus 4 bits of Hamming code check bits, a total of 12 bits.

[0035] This is only an illustrative description and does not constitute a limitation on the specific solution.

[0036] When the storage controller is in the ECC-disabled mode, the ECC check code is obtained based on the data of the bus, and the ECC check code can be generated and stored when the data is written, without relying on the working mode of the storage controller. Alternatively, in the system design, the bus may also include the ECC check code, and the data and other check codes can be transmitted through the bus at the same time. This is only used as an example and does not constitute a limitation on the specific solution.

[0037] In this embodiment, based on the mode of the storage controller, the ECC memory address is obtained, and the obtained ECC check code is stored in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address, so that the problem of common cause failure can be avoided. It can also be understood that the ECC memory address is inverted, and the ECC check code is stored in the ECC storage unit corresponding to the inverted ECC memory address, so that the common cause failure of the physical address line can be avoided, which is conducive to timely use of the ECC check code to correct the data, and improves the effect of functional safety protection.

[0038] For example, due to design reasons, the data storage unit corresponding to address 0 is prone to "stuck at 0" after aging. Since the ECC check code of data 0 is also 0, if the data and the ECC check code are stored in the same order, the ECC check cannot find the problem with the data. However, if the ECC check code is stored starting from the high bit of the address, and the ECC check code corresponding to the data stored at address 0 of the data memory is stored in the ECC storage unit corresponding to the highest bit of the ECC memory address, the ECC check can find data errors, thereby improving data security and integrity.

[0039] In some other embodiments of the present application, when the storage controller is in an ECC-enabled mode, the storage controller obtains an ECC memory address based on the data memory address (usually referred to as a physical address). The layout of the ECC storage unit is usually based on the data memory address, and for each data memory address, the ECC storage unit stores a check bit associated therewith. Specifically, the storage controller may obtain the physical address of the data memory from the request, and usually, the ECC data is stored in adjacent addresses or in specific increments. Therefore, the storage controller needs to know the address offset or mapping relationship of the ECC storage unit and calculate the ECC memory address using a specific algorithm or formula. For example, assuming that the original data memory address is A, the ECC memory address E may be calculated by the following formula: [E=A+\text{Offset}], where Offset is an offset defined according to the ECC implementation, and may be a constant related to the size of the ECC storage unit.

[0040] For example, assume that each storage unit (word) occupies 8 bytes and each word requires 2 bytes of ECC check bits: for a data memory address A, the ECC may be stored at A+8, for example, if the requested data memory address is 0×1000, then the corresponding ECC memory address may be 0×1008.

[0041] The above is only an exemplary description and does not constitute a limitation on the specific ECC check code generation method. For another example, assuming that each 64-bit data block corresponds to an 8-bit ECC check code, the storage controller can calculate the ECC memory address by the following formula: [\text{ECC Address}=\text{Data Address} / (\text{Data Block Size}+\text{ECCSize})], where (\text{Data Block Size}) is the size of the data block, and (\text{ECC Size}) is the size of the ECC code (for example, 64-bit data plus 8-bit ECC, a total of 72 bits).

[0042] When the storage controller is in the ECC-enabled mode, the storage controller obtains the ECC memory address based on the data memory address, and stores the ECC check code generated based on the data of the bus in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address. That is, in the ECC-enabled mode, the ECC check code is used to detect and correct single-bit and multi-bit errors in the data, thereby improving data integrity and stability. The storage controller obtains the ECC memory address based on the data memory address through logical processing, When ECC is enabled, the ECC check code generated based on the bus data is stored in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address, which can effectively avoid the problem of common cause failure, facilitate timely detection and correction of data, and improve data stability and integrity.

[0043] In some other embodiments of the present application, when the storage controller is in the ECC disabled mode, the storage controller obtains the ECC memory address based on the address signal of the bus, and stores the ECC check code from the bus in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address. For example, in the software development stage, the ECC disabled mode is required. At this time, the ECC memory address can be obtained based on the address signal of the bus, and the ECC check code is also stored in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address.

[0044] In this way, when the ECC mode is turned on, the ECC check code is also stored in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address. Therefore, in the ECC mode and the ECC-disabled mode, the ECC memory address reverse processing is transparent to the software. The ECC check code of the target data can be calculated by the storage controller in the ECC mode, and then configured to the non-ECC mode to read the ECC check code in the ECC storage unit, avoiding the storage controller from adding additional processing tasks and increasing the processing burden due to the switching of the ECC mode.

[0045] In some other embodiments of the present application, when the storage controller is in the ECC-enabled mode, the first circuit of the storage controller generating the data storage address cannot be reused with the second circuit generating the ECC storage address. That is, when the ECC mode is enabled, the storage controller obtains the data storage address through the first circuit based on the address signal of the bus through logical processing, and the original data is stored in the data storage unit in the access order from the lowest bit to the highest bit of the data storage address. Through the second circuit, the ECC storage address is obtained through logical processing based on the data storage address, and the ECC check code is stored in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC storage address. This process is separate and independent from the process of obtaining the data storage address through the first circuit, that is, the first circuit and the second circuit cannot be reused, so that the common cause failure problem can be effectively prevented to improve the effect of functional safety protection.

[0046] In some other embodiments of the present application, the storage controller is used to read data from the data storage unit in the access order from the lowest bit to the highest bit of the data storage address, and to read the ECC check code from the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address. That is to say, when the storage controller receives a read instruction from the bus, the storage controller accesses the data storage unit and the ECC storage unit in the opposite access order, that is, reads data from the data storage unit in the access order from the lowest bit to the highest bit of the data storage address, and reads the ECC check code from the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address. In this way, the correction of erroneous data can be achieved through ECC check, thereby improving the security and integrity of data security management.

[0047] Figure 2The flowchart of the storage control method based on the SOC system according to the embodiment of the present application is shown. In step S201, the storage controller in the SOC system is used to obtain the data storage address based on the address signal of the bus from the SOC system, and the data from the bus is stored in the data storage unit in the access order from the lowest bit to the highest bit of the data storage address. In step S202, based on the mode of the storage controller, the ECC memory address is obtained, and the obtained ECC check code is stored in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address; in step S203, the target data is read from the data storage unit in the access order from the lowest bit to the highest bit of the data storage address, and a second ECC check code is generated based on the read target data; in step S204, the first ECC check code is read from the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address, and the second ECC check code is compared with the first ECC check code to determine whether the data has an error. In this way, the problem of common cause failure of the physical address line can be avoided, and it can be accurately determined whether there are errors in the data stored in the data storage unit, so that the erroneous data can be identified in time, thereby improving the effect of functional safety protection.

[0048] In some other embodiments of the present application, Figure 3 , a device for generating a memory address is provided, the memory address includes a data memory address and an ECC memory address, the device includes a memory controller 301, the memory controller 301 includes a check module 308, a first address decoding module 302, a second address decoding module 303, a first inverter 304, a second inverter 306 and a gate 309. The check module 308 may be, for example, a bus error detection and correction module (Bus EDC), which ensures data integrity by monitoring and processing errors in the data transmission process of the system bus.

[0049] The storage controller 301 is configured to use the first address decoding module 302 to obtain the data storage address based on the address signal of the bus from the SOC system, and store the data from the bus in the data storage unit 305 in the access order from the lowest bit to the highest bit of the data storage address. The second address decoding module 303 is used to obtain the ECC memory address according to the mode of the storage controller 301, and the second inverter 306 is used to store the obtained ECC check code in the ECC storage unit 307 in the access order from the highest bit to the lowest bit of the ECC memory address. In this way, the problem of common cause failure of the address line can be avoided, and the effect of functional safety protection can be improved.

[0050] Specifically, the storage controller 301 responds to the first instruction to enable the ECC function, that is, ECC is enabled (ecc_en), then the selector 309 starts the second circuit 310, uses the second address decoding module 303 to obtain the ECC memory address based on the data memory address, and then uses the second inverter 306 to store the ECC check code generated based on the data of the bus in the ECC storage unit 307 in the access order from the highest bit to the lowest bit of the ECC memory address.

[0051] In some other embodiments, the storage controller 301 responds to the second instruction to turn off the ECC function, that is, turn off the ECC enable (ecc_en), then the selector 309 starts the first circuit 311, uses the first address decoding module 302 to obtain the ECC memory address based on the address signal of the bus, and then uses the first inverter 304 to store the ECC check code from the bus in the ECC storage unit 307 in the access order from the highest bit to the lowest bit of the ECC memory address. Among them, the first circuit 311 and the second circuit 310 are separated and run independently and cannot be reused, thereby avoiding the problem of common cause failure and improving the effect of functional safety protection.

[0052] The first address decoding module 302 and the second address decoding module 303 can convert the address signal from the bus into the physical address signal of the actual memory. This process involves parsing and mapping the address information on the bus to a specific storage location to ensure that the data can be correctly read and written to the predetermined memory location. In short, the address decoding module is responsible for converting high-level address requirements into addresses understood by the specific memory, thereby achieving accurate access to data.

[0053] The first inverter 304 and the second inverter 306 are basic logic gates, and their main function is to invert the level of the input signal. For example, when the input is logic high (1), the output is logic low (0); when the input is logic low (0), the output is logic high (1). By respectively setting the first inverter 304 and the second inverter 306 in the first circuit 311 and the second circuit 310, the ECC memory address can be inverted to achieve the ECC check code according to the access order from the highest bit to the lowest bit of the ECC memory address. Stored in the ECC storage unit 307.

[0054] In some other embodiments of the present application, a SOC chip is provided, the SOC chip includes a memory controller, and the memory controller is configured to execute the memory address generation method described in each embodiment of the present application.

[0055] It should be understood that in the present application, the processor can be a central processing unit (CPU), and the processor can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.

[0056] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct memory bus random access memory (Direct Rambus RAM, DR RAM).

[0057] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated in the processor.

[0058] It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0059] It should also be understood that the first, second, third, fourth and various numerical numbers involved in this document are only distinctions made for the convenience of description and are not intended to limit the scope of the present application.

[0060] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0061] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in a processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0062] In various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0063] Those skilled in the art will appreciate that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0064] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices, chips, electronic devices and storage media can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0065] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0066] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0067] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integration. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk), etc.

[0068] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for generating a memory address, characterized in that: The memory address includes a data memory address and an ECC memory address, and the generating method includes: Using a storage controller in the SOC system, obtaining a data storage address based on an address signal from a bus of the SOC system, and storing the data from the bus in a data storage unit in an access order from the lowest bit to the highest bit of the data storage address; Based on the mode of the storage controller, the ECC memory address is obtained, and the obtained ECC check code is stored in the ECC storage unit in an access order from the highest bit to the lowest bit of the ECC memory address.

2. The generation method according to claim 1, characterized in that: The storage controller supports an ECC-enabled mode and an ECC-disabled mode, and the generating method further includes: When the storage controller is in the ECC enabled mode, the storage controller obtains the ECC memory address based on the data storage address, and stores the ECC check code generated based on the data of the bus in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address.

3. The generation method according to claim 2, characterized in that: The generating method further comprises: When the storage controller is in the ECC disabled mode, the storage controller obtains the ECC memory address based on the address signal of the bus, and stores the ECC check code from the bus in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address.

4. The generation method according to claim 2, characterized in that: When the storage controller is in the ECC-enabled mode, a first circuit of the storage controller for generating the data memory address and a second circuit for generating the inverted ECC memory address cannot be reused.

5. The generation method according to claim 1, characterized in that: The generating method further comprises: The storage controller is used to read data from the data storage unit in an access order from the lowest bit to the highest bit of the data storage address, and the ECC check code is read from the ECC storage unit in an access order from the highest bit to the lowest bit of the ECC memory address.

6. A storage control method based on a SOC system, characterized in that: The storage control method comprises: Using a storage controller in the SOC system, obtaining a data storage address based on an address signal from a bus of the SOC system, and storing the data from the bus in a data storage unit in an access order from the lowest bit to the highest bit of the data storage address; Based on the mode of the storage controller, an ECC memory address is obtained, and the obtained ECC check code is stored in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address; Reading target data from the data storage unit in an access order from the lowest bit to the highest bit of the data storage address, and generating a second ECC check code based on the read target data; The first ECC check code is read from the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address, and whether the data has an error is determined by comparing the second ECC check code with the first ECC check code.

7. A device for generating a memory address, characterized in that: The memory address includes a data memory address and an ECC memory address, the generating device includes a memory controller, and the memory controller includes a first address decoding module, a second address decoding module and a second inverter, The storage controller is configured as follows: Using the first address decoding module, a data storage address is obtained based on an address signal from a bus of the SOC system, and the data from the bus is stored in the data storage unit in an access order from the lowest bit to the highest bit of the data storage address; The second address decoding module is used to obtain the ECC memory address according to the mode of the storage controller, and the second inverter is used to store the obtained ECC check code in the ECC storage unit in the access order from the highest bit to the lowest bit of the ECC memory address.

8. The generating device according to claim 7, characterized in that The storage controller is further configured to: In response to a first instruction to enable the ECC function, a second address decoding module is used to obtain an ECC memory address based on the data memory address, and then a second inverter is used to store the ECC check code generated based on the data of the bus in the ECC storage unit in an access order from the highest bit to the lowest bit of the ECC memory address.

9. The generating device according to claim 7, characterized in that: The storage controller further includes a first inverter, further configured as: In response to a second instruction to turn off the ECC function, a first address decoding module is used to obtain an ECC memory address based on the address signal of the bus, and then a first inverter is used to store the ECC check code from the bus into the ECC storage unit in an access order from the highest bit to the lowest bit of the ECC memory address.

10. A SOC chip, characterized in that: The SOC chip includes a memory controller, and the memory controller is configured to execute the method for generating a memory address according to any one of claims 1 to 4.

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