Verification method and verification device for storage controller

Abstract

The invention discloses a verification method and a verification device for a storage controller. The verification method comprises the following steps: executing a verification operation on the storage controller by using a verification component; during the set statistical time, multiple pieces of transaction information generated by interaction between the verification component and the storage controller in the verification operation are received from the verification component; based on the multiple pieces of transaction information, obtaining at least one performance index of the storage controller; and after the statistical time is over, outputting at least one performance index. According to the method disclosed by the embodiment of the invention, the performance indexes of the storage controller can be counted on the basis of the transaction information, so that the performance indexes of the performance analysis of the storage controller can be favorably counted, and the configuration of the storage controller can be better optimized on the basis of the performance statistical result.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a verification method and a verification device for a storage controller. Background Art

[0002] The external memory of CPU / GPU, such as the commonly used DDR (Double Data Rate Synchronous Dynamic Random Access Memory) / HBM (High Bandwidth Memory), is responsible for storing a large amount of data in the calculation process and the fast reading and writing operations of the received data, so its performance directly affects the computing power level of CPU / GPU. For memory devices such as DDR / HBM, it is necessary to design a storage controller module in the CPU / GPU chip to control the data reading and writing operations of the memory such as DDR / HBM. In addition to ensuring that the data in the memory such as DDR / HBM can be read and written correctly, the storage controller also needs to ensure that the performance of reading and writing data is as close to the theoretical bandwidth of the memory as possible. The theoretical bandwidth of the memory refers to the maximum bandwidth reached by the memory at the full data rate. In order to make the performance of reading and writing data as close to the theoretical bandwidth of the memory as possible, the storage controller needs to optimize the operation commands such as reading and writing so that the actual bandwidth of the memory can be as close to the theoretical bandwidth as possible.

[0003] As an important part of chip front-end design, chip verification requires comprehensive verification of chip functions to ensure the correctness of its functions. For the verification of storage controller modules used to control memories such as DDR / HBM, in addition to functional verification, performance verification is also required to verify whether its performance meets expectations. In the field of chip functional verification, Universal Verification Methodoy (UVM) can be used to quickly build a simulation verification platform and carry out verification work. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a verification method for a storage controller, comprising: using a verification component to perform a verification operation on the storage controller; during a set statistical time, receiving from the verification component a plurality of transaction information generated by the verification component interacting with the storage controller during the verification operation; based on the plurality of transaction information, obtaining at least one performance indicator of the storage controller; after the statistical time ends, outputting the at least one performance indicator.

[0005] For example, in the verification method provided by at least one embodiment of the present disclosure, for the multiple pieces of transaction information, the at least one performance indicator is counted based on the current transaction information and the previous piece of transaction information.

[0006] For example, in the verification method provided by at least one embodiment of the present disclosure, the at least one performance indicator is obtained based on the operation commands in the multiple pieces of transaction information.

[0007] For example, in the verification method provided by at least one embodiment of the present disclosure, the at least one performance indicator is obtained based on at least one of the following: the number of command conversions, the interval time of command conversions, the number of consecutive commands, the utilization rate of the storage block, the time of command execution, the proportion of time occupied by the command, and the number of storage block group conversions.

[0008] For example, in the verification method provided by at least one embodiment of the present disclosure, the at least one performance indicator includes at least one of the following: the number of conversions of read and write commands, the time interval for conversion of read and write commands, the number of consecutive read commands, the number of consecutive write commands, the number of consecutive read or write commands corresponding to the storage block, the utilization rate of the storage block, the time occupied by the refresh command, the proportion of the time occupied by the refresh command, and the bandwidth for reading or writing data.

[0009] For example, in the verification method provided by at least one embodiment of the present disclosure, the at least one performance indicator also includes a storage block group conversion number, and the storage block group conversion number is used to indicate the number of read or write operations between different storage block groups during a set statistical time period.

[0010] For example, in the verification method provided in at least one embodiment of the present disclosure, the at least one performance indicator is used to reconfigure parameters related to the storage controller.

[0011] For example, in the verification method provided in at least one embodiment of the present disclosure, the verification component is based on UVM and includes a monitor, a driver, and a scoreboard. The use of the verification component to perform a verification operation on the storage controller includes: the driver inputs a test signal to the storage controller; the monitor receives transaction information output for the test signal from the storage controller; the monitor inputs the transaction information into the scoreboard to verify the storage controller, wherein the transaction information is also transmitted from the monitor to a performance statistics module through a port of the verification component to obtain at least one performance indicator of the storage controller based on the transaction information.

[0012] At least one embodiment of the present disclosure further provides a verification device for a storage controller, comprising: a verification component, configured to perform a verification operation on the storage controller; a performance statistics module, configured to: during a set statistical time, receive from the verification component a plurality of transaction information generated by the verification component interacting with the storage controller during the verification operation, obtain at least one performance indicator of the storage controller based on the plurality of transaction information, and output the at least one performance indicator after the statistical time ends.

[0013] For example, in the verification device provided by at least one embodiment of the present disclosure, the performance statistics module is further configured to, for the multiple transaction information, store the current transaction information after statistics are calculated for the performance indicators of the current transaction information, wherein the at least one performance indicator is calculated based on the current transaction information and the last transaction information stored.

[0014] For example, in the verification device provided by at least one embodiment of the present disclosure, at least one performance indicator counted by the performance statistics module includes at least one of the following: the number of conversions of read and write commands, the time interval for conversion of read and write commands, the number of consecutive read commands, the number of consecutive write commands, the number of consecutive read or write commands corresponding to the storage block, the utilization rate of the storage block, the time occupied by the refresh command, the proportion of the time occupied by the refresh command, the number of conversions of the storage block group, and the bandwidth for reading or writing data.

[0015] For example, in the verification device provided in at least one embodiment of the present disclosure, the verification component is based on UVM and includes a monitor, a driver, and a scoreboard, the driver is configured to input a test signal to the storage controller; the monitor is configured to receive transaction information output for the test signal from the storage controller, and input the transaction information into the scoreboard to verify the storage controller; the performance statistics module is connected to the port of the verification component to obtain the multiple transaction information from the monitor.

[0016] For example, in the verification device provided by at least one embodiment of the present disclosure, the performance statistics module includes: a performance monitoring module, configured to obtain at least one performance indicator of the storage controller based on the multiple transaction information; an effective time determination module, configured to set the statistical time and determine whether the current time is within the statistical time; a clock counting module, configured to count the clock; and a reporting module, configured to output the at least one performance indicator.

[0017] At least one embodiment of the present disclosure further provides a verification device, including: at least one processor; at least one memory, wherein a computer program is stored in the at least one memory, and when the computer program is executed by the processor, the method according to at least one embodiment of the present disclosure is implemented.

[0018] At least one embodiment of the present disclosure further provides a computer-readable storage medium, wherein a computer program is stored. When the computer program is executed by a processor, the method according to at least one embodiment of the present disclosure is implemented.

[0019] At least one embodiment of the present disclosure further provides a computer program product, including a computer program / instruction, wherein when the computer program / instruction is executed by a processor, the method according to at least one embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0021] Figure 1 A schematic diagram showing a verification method for a storage controller according to at least one embodiment of the present disclosure is shown;

[0022] Figure 2 A schematic diagram of a verification device for a storage controller according to at least one embodiment of the present disclosure is shown;

[0023] Figure 3 Shows Figure 2 A schematic diagram of a performance statistics module in a verification device;

[0024] Figures 4 to 10 An example flow chart for performing statistics on an exemplary performance indicator is shown;

[0025] Fig.11 A schematic diagram of a verification device for a storage controller according to at least some embodiments of the present disclosure is shown;

[0026] Fig.12 A schematic diagram of a verification device according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0029] As mentioned above, the UVM method can be used to build a simulation verification platform for verification operations. For scenarios such as using DDR / HBM and other memories, the verification operations require not only functional correctness verification of the storage controller, but also performance verification. Performance verification mainly counts performance indicators such as read and write bandwidth. At present, the industry has not yet formed a set of universal verification methodologies and unified practices.

[0030] The inventors of the present disclosure note that the performance verification method of some embodiments includes:

[0031] Method 1: Evaluate performance by simulating waveforms;

[0032] Method 2: By adding a performance statistics module to the simulation verification platform, the performance is counted and the statistical results are printed.

[0033] The general process of evaluating performance through simulation waveforms in method 1 is: run a test case with a large amount of data for simulation, and the design engineer analyzes the generated waveform file. The design engineer needs to open the waveform file in the waveform viewer, drag the performance-related signals to the waveform display window, and then perform some logical operations on the signals, such as performing a logical "AND" on the Valid signal and the Clock signal, and then select a period of time to count the number of rising or falling edges of the signal during this period, so as to achieve the purpose of calculating performance.

[0034] The general process of evaluating performance through the performance statistics module in method 2 is as follows: the performance statistics module is generally connected to the monitor of the data transmission interface in the verification environment, receives data information from the monitor, accumulates the data according to bytes or bits, and records the start time and end time of the data validity, which can be recorded in ns (nanoseconds); when the data transmission is completed, the accumulated data value is divided by the data validity time to obtain the data bandwidth value as the performance value; finally, the bandwidth value is printed in the simulation log file for easy reference.

[0035] The method of evaluating performance through simulation waveforms in the above method 1 is cumbersome and the efficiency of performance analysis is low. If multiple performance indicators of multiple modules need to be calculated, it is very time-consuming; moreover, if performance indicators in multiple application scenarios need to be analyzed, the time required will increase exponentially. Although the method of evaluating performance through the performance statistics module in the above method 2 can intuitively obtain the bandwidth of read, write data and total data under different test stimuli, if the bandwidth statistics value fails to meet expectations or the bandwidth decreases in a certain period of time, it is difficult to analyze the cause through bandwidth statistics information.

[0036] For DDR / HBM memory chips, the read and write operations are relatively complex. If the performance is insufficient, the reasons may be multifaceted. It is difficult to analyze the reasons for the performance degradation only through bandwidth statistics. Considering that there are some common aspects in the operation of DDR / HBM memories, such as: refresh operations are required at intervals; when data needs to be read / written to a storage block (bank, or storage unit) address, an activation operation needs to be performed first; when a storage block is not used for a long time, a precharge operation is required; and there are timing requirements between different operation commands. For these types of memories, their storage controllers need to optimize the sending order and timing of these operation commands to achieve the required performance.

[0037] For a storage controller corresponding to a memory such as DDR / HBM, the present disclosure proposes a verification method for a storage controller chip, which includes a performance statistics method for counting one or more indicators that affect the performance, so as to locate the cause of insufficient performance more quickly.

[0038] The embodiments and examples of the present disclosure are described in detail below with reference to the accompanying drawings.

[0039] The present disclosure provides a verification method for a storage controller such as a DDR / HBM memory, including a performance statistics method for the storage controller. Figure 1A schematic diagram of a verification method 100 for a storage controller according to at least one embodiment of the present disclosure is shown.

[0040] like Figure 1 As shown, the method 100 includes steps S101 to S104:

[0041] Step S101: using a verification component to perform a verification operation on a storage controller;

[0042] Step S102: During a set statistical time period, receiving from the verification component a plurality of transaction information generated by the verification component interacting with the storage controller during a verification operation;

[0043] Step S103: acquiring at least one performance indicator of the storage controller based on the multiple pieces of transaction information;

[0044] Step S104: after the statistical time ends, output the at least one performance indicator.

[0045] Through the method of the embodiment of the present disclosure, at least one performance indicator of the storage controller can be obtained based on the transaction information during the verification period, so the implementation complexity is low, and the statistical performance indicator can better reflect the performance status of the storage controller.

[0046] For example, in one implementation, the verification method can be based on the UVM verification platform and can be implemented by writing in the SystemVerilog language. The performance statistics method can be used as an independent performance statistics module and hung on an existing verification environment.

[0047] Figure 2 A schematic diagram of a verification device (test system 200 ) for a storage controller according to at least one embodiment of the present disclosure is shown.

[0048] like Figure 2As shown, the test system 200 includes a test environment 210, which includes a performance statistics module 211, a scoreboard 212 and an agent component 213, and the agent component 213 interacts with a storage controller 220 (DUT) to be tested. Among them, the agent component 213 includes a monitor 213-1, a driver 213-2, a functional coverage analysis module 213-3 and a sequencer 213-4. The agent component 213 (including the monitor 213-1 and the driver 213-2) and the scoreboard 212 can be used to verify the DUT and can be called a verification component. During the verification or test process, the sequencer 213-4 sends test data to the driver 213-2, and the driver 213-2 sends a test signal to the storage controller 220 to be tested according to the test data. The monitor 213-1 receives the output signal from the storage controller 220 to be tested to convert it into transaction information, and sends the transaction information to the performance statistics module 211 and the scoreboard 212. The scoreboard 212 compares the information input from the monitor with the expected output (reference information) of the test signal to obtain information related to functional coverage, and the functional coverage analysis module 213-3 obtains and outputs the functional coverage based on the information related to functional coverage.

[0049] Performance statistics module 211 can be connected to monitor 213-1 in test environment 210 through the interface (port) of UVM verification platform. Monitor can capture the interface signal of memory (for example, DDR / HBM) and analyze interface information according to protocol, such as activation, precharge, refresh, read command, write command, read or write data information, etc. These information can be passed to performance statistics module 211 through the interface of UVM verification platform, and performance statistics module 211 can count and process these information, thereby deriving key information related to performance, and combining the information analysis of bandwidth to analyze the reason of insufficient or decreased performance.

[0050] Figure 3 Shows Figure 2 Schematic diagram of the performance statistics module 211 in the verification device. Figure 3 As shown, the functional modules inside the performance statistics module include: a performance monitoring module 211-1, an effective time determination module 211-2, a clock counting module 211-3, and a reporting module 211-4. The performance monitoring module 211-1 is configured to obtain at least one performance indicator of the storage controller based on multiple transaction information. The effective time determination module 211-2 is configured to set the statistical time and determine whether the current time is within the statistical time. The clock counting module 211-3 is configured to count the clock. The reporting module 211-4 is configured to output at least one performance indicator.

[0051] For example, the performance statistics module can be written based on the UVM standard, for example, it can inherit the uvm_ monitor, including a uvm_analysis_imp for connecting to the monitor of the memory (such as DDR / HBM VIP), and receiving the transaction information transmitted by the monitor. Among them, the performance monitoring module 211-1 is a task (task), which is mainly responsible for receiving the transaction information from the monitor, parsing and processing the information of the transaction, and performing the cumulative operation on the operation command required for statistics. The effective time determination module 211-2 (for example, implemented as is_active_window) as a function can set the number of clocks at the beginning and the number of clocks at the end of the performance statistics, so as to determine whether the current moment is within the effective statistical time. The clock counting module 211-3 (for example, implemented as Get_uclk_cycle) is also a function, which can count the simulation clock and return the number of clocks at the current moment. The reporting module 211-4 is a task, which is responsible for calculating the statistical performance indicators and printing out the results.

[0052] The modules / components / units used for verification and testing in the embodiments of the present disclosure may be implemented, for example, by a high-level abstract programming language, and there is no restriction on the choice of programming language.

[0053] According to at least one embodiment of the present disclosure, for example, for a DDR / HBM memory, when performing performance statistics on its storage controller, the performance statistics module can count at least one of the following information in addition to counting the bandwidth of read / write data:

[0054] 1. The number of conversions of read and write commands, for example, can be divided into two cases: the number of conversions from read commands to write commands and the number of conversions from write commands to read commands;

[0055] 2. The time interval for converting read and write commands, for example, can be divided into two situations: the time interval from a read command to a write command and the time interval from a write command to a read command;

[0056] 3. The number of consecutive read commands or consecutive write commands;

[0057] 4. the number of consecutive read or write commands corresponding to the storage block, and optionally, the utilization rate of each storage block;

[0058] 5. the time taken by the refresh command, and optionally, the proportion of the time taken;

[0059] 6. Number of storage block group conversions.

[0060] Figures 4 to 10 An example flow chart for performing statistics on exemplary performance indicators is shown. Figures 4 to 10 Describe the workflow of the performance statistics module in detail.

[0061] like Figure 4 As shown, in step S401, the performance statistics module first receives transaction information transmitted by the monitor. The transaction information may include activation, precharge, read, write, or refresh command information parsed by the monitor according to the bus protocol, and may also include read and write data information.

[0062] In step S402, the performance statistics module can determine whether the current time is within the statistical time, for example, it can call is_active_window to determine whether the current time is within the clock window corresponding to the statistical time. If the judgment result is yes, proceed to step S403, otherwise end.

[0063] In step S403, the performance statistics module can determine whether the operation commands of the current transaction and the previous transaction meet the statistical conditions. If the result of the determination is no, proceed to step S401. If the result of the determination is yes, proceed to step S404.

[0064] In step S404, the corresponding statistical counter performs a counting operation. For example, the corresponding statistical counter may be a counter that performs statistical counting on command information related to the performance indicator, such as a read / write command conversion times counter, a read / write command conversion time interval counter, a continuous read command counter or a continuous write command counter, a storage block usage times counter, a refresh command occupied time counter, etc.

[0065] Afterwards, in step S405, the current transaction can be saved for use when the next transaction is received, which is an optional step. In this way, when a new transaction is received, transaction information related to performance statistics can be obtained based on the current transaction information and the previous transaction information.

[0066] In step S406, it can be determined whether the report phase has been reached. If the result of the determination is no, the process proceeds to step S401, otherwise, if the report phase has been reached, that is, when the simulation reaches the report_phase, it indicates that the simulation has ended, the process proceeds to step S407.

[0067] In step S407, the reporting module is used to sort and process the values ​​of the statistical counters.

[0068] In step S408, the processed statistical values ​​are output to a log of the performance statistical report.

[0069] By using the above method to collect statistics on performance indicators, it is possible to assist in analyzing the causes of insufficient performance and provide guidance for design improvements. For example, the statistical performance indicators can be used to reconfigure parameters related to the storage controller. Figures 5 to 10 Describe in detail.

[0070] Figure 5 FIG. 1 is a schematic diagram showing a method for counting the number of read and write command conversions. Figure 5 As shown, the method includes steps S501-S507.

[0071] Step S501: receiving transaction information from a monitor;

[0072] Step S502: Determine whether it is within the statistical time; if the result of the determination is yes, proceed to step S503, otherwise end.

[0073] Step S503: Determine whether the current transaction is a read command and the previous transaction is a write command; if the result of the determination is no, proceed to step S501, otherwise proceed to step S504.

[0074] Step S504: the read-write conversion counter is incremented by 1;

[0075] Optionally, step S505 may also be performed: saving the current transaction for use when receiving the next transaction.

[0076] Next, proceed to step S506: determine whether the reporting stage has been reached. If the determination result is no, proceed to step S501, otherwise, proceed to step S507.

[0077] Step S507: directly print the value of the read-to-write conversion counter in the report task.

[0078] In the above method, counting the number of conversions from read commands to write commands is used as an example for explanation. It is understandable that this is only an example.

[0079] For the statistics of the conversion times of read and write commands, there are two types of conversions of read and write commands, one is the conversion of read to write commands, and the other is the conversion of write to read commands. When the statistical time window is valid, the statistical module can receive the transaction information sent from the monitor in real time and save the information of the previous transaction. If the current transaction information indicates that it is a read command, and the previous transaction is a write command, it means that a read-to-write conversion has been performed, and the statistical counter indicating the read-to-write operation is incremented by 1; similarly, if the current transaction information indicates that it is a write command, and the previous transaction is a read command, it means that a write-to-read conversion has been performed, and the statistical counter indicating the write-to-read operation is incremented by 1. When the simulation reaches the report phase (report_phase), the statistical counting results are printed to the corresponding log file.

[0080] By counting the number of read-write conversions, it is possible to determine whether the read-write conversions are frequent. If necessary, the number of read-write conversions at the entrance of the DDR / HBM storage controller can be combined to see the correspondence between the number of read-write conversions at the entrance and the number of read-write conversions obtained by statistics. The number of read-write conversions has a certain impact on the bandwidth. The time occupied by read-write conversions is longer than the time occupied by continuous reading or continuous writing, so if the number of read-write conversions is too high, it will affect the bandwidth. For example, the counted number of read-write conversions can be used to reconfigure the parameters related to the storage controller. For example, by counting the number of read-write conversions, it can help performance analysis and optimize the configuration (for example, adjusting or setting configuration parameters accordingly) or design of the storage controller.

[0081] Figure 6 FIG. 1 is a schematic diagram showing a method for counting the time intervals between read and write command conversions. Figure 6 As shown, the method includes steps S601-S608.

[0082] Step S601: receiving transaction information from a monitor;

[0083] Step S602: Determine whether it is within the statistical time; if the result of the determination is yes, proceed to step S603, otherwise end.

[0084] Step S603: Determine whether the current transaction is a read command and the previous transaction is a write command; if the result of the determination is no, proceed to step S601, otherwise proceed to step S604.

[0085] Step S604: Obtain the current clock number and put the difference between the current clock number and the clock number corresponding to the previous transaction into a queue;

[0086] Optionally, step S605 may also be performed: saving the current transaction and the obtained current clock number for use when receiving the next transaction.

[0087] Next, proceed to step S606: determine whether the reporting stage has been reached. If the determination result is no, proceed to step S601, otherwise, proceed to step S607.

[0088] Step S607: Determine at least one of the minimum value, the maximum value, and the average value in the queue.

[0089] Step S608: Print at least one of the minimum value, the maximum value, and the average value of the read-write conversion time interval.

[0090] In the above method, statistics on the time interval for converting a read command to a write command are used as an example for explanation. It is understandable that this is only an example.

[0091] For the conversion time interval of read and write commands, the time interval of read and write command conversion can be divided into two types, one is the command conversion time interval from read to write, and the other is the command conversion time interval from write to read. The time interval is counted using the number of clock cycles, and the number of clocks can be counted in real time by the clock counting module (for example, get_uclk_cycle). Every time the performance statistics module receives a read or write command, it records the number of clock cycles at that time. In this way, when the received transaction information is a read command and the previous transaction is a write command, it means that a read-write conversion has been performed. At this time, the number of clocks recorded by the last write command is subtracted from the number of clocks in the current clock counter to obtain the time interval of this read-write conversion. The queue data type of the read-write conversion time interval can be defined to record the time interval of each read-write conversion. Similarly, the time interval of each write-to-read conversion can also be recorded by referring to the read-to-write time interval method. The recorded read-write time interval information will be processed when the simulation reaches the report phase (report_phase). First, the queue of the read-write conversion time interval is circulated to find the maximum and minimum values. Secondly, the sum of all queue values ​​can be divided by the number of queues to obtain the average time interval. In this way, at least one of the minimum value, the maximum value and the average value of the read-write conversion time interval can be printed out in the log file of the performance statistics report.

[0092] For example, the statistical read-write conversion time interval can be used to reconfigure the parameters related to the storage controller. For example, the time interval of the read-write conversion can be used to find out the time occupied by the read-write conversion. The DDR / HBM protocol stipulates the minimum time interval allowed for the read-write conversion. If the statistical read-write conversion time is too large, it will inevitably affect the bandwidth. Therefore, by analyzing the read-write conversion time interval, the logic code or configuration register value of the DDR / HBM storage controller read-write conversion can be optimized (for example, the configuration parameters of the register are adjusted or set accordingly).

[0093] Figure 7 FIG. 2 is a schematic diagram showing a method for counting the number of consecutive read commands. Figure 7 As shown, the method includes steps S701-S710.

[0094] Step S701: receiving transaction information from a monitor;

[0095] Step S702: Determine whether it is within the statistical time; if the result of the determination is yes, proceed to step S703, otherwise end.

[0096] Step S703: Determine whether the current transaction is a read command; if the result of the determination is yes, proceed to step S704.

[0097] Step S704: the read command counter is incremented by 1;

[0098] Optionally, after step S704, step S705 may be performed: saving the current transaction for use when receiving the next transaction.

[0099] Next, proceed to step S706: determine whether the reporting stage has been reached. If the determination result is no, proceed to step S701, otherwise, proceed to step S707.

[0100] Step S707: Determine at least one of the minimum value, the maximum value, and the average value in the queue.

[0101] Step S708: Print at least one of the minimum value, the maximum value, and the average value of the read command counter.

[0102] If the judgment result in step S703 is no, proceed to step S709.

[0103] Step S709: Determine whether the current transaction is a write command; if the determination result is yes, proceed to step S710: put the value of the read command counter into the queue, then set the read command counter to 0, and proceed to step S706; otherwise, proceed to step S701.

[0104] For the above method, for the number of consecutive read commands or write commands sent: when the received transaction information is a read command, the read command counter starts counting until a transaction is a write command, the value of the read command counter is placed in a queue of a read command counter, and then the value of the read command counter is cleared. Similarly, when the received transaction information is a write command, the write command counter starts counting until a transaction is a read command, the value of the write command counter is placed in a queue of a write command counter, and then the value of the write command counter is cleared. In this way, the queues of the read counter and the write counter contain all the consecutive read times or consecutive write times. The recorded queues of the read / write counters are processed when the simulation reaches the reporting stage. First, the queues of the consecutive read / write counters are looped to find the maximum and minimum values. Secondly, the sum of all queue values ​​can be divided by the number of queues to get the average value of the consecutive read / write. The minimum, maximum and average values ​​of the consecutive read / write numbers can be printed in the log file of the performance statistics report.

[0105] For example, the counted continuous read / continuous write number can be used to reconfigure the parameters related to the storage controller. For example, through the statistics of the continuous read / continuous write number (or the continuous read / write number), it can be seen whether the number of continuous reads / continuous writes is more or less. Since the time occupied by the read-write conversion is longer than the time occupied by the continuous read or continuous write, if the number of continuous reads / writes is relatively small, it will have a certain impact on the bandwidth. By analyzing the number of continuous reads / writes, the logic code or configuration register value of the DDR / HBM storage controller read-write conversion can be optimized (for example, the configuration parameters of the register are adjusted or set accordingly).

[0106] Figure 8 FIG. 1 is a schematic diagram showing a method for counting the number of consecutive read or write commands corresponding to a storage block. Figure 8 As shown, the method includes steps S801-S810.

[0107] Step S801: receiving transaction information from a monitor;

[0108] Step S802: Determine whether it is within the statistical time; if the result of the determination is yes, proceed to step S703, otherwise end.

[0109] Step S803: Determine whether the current transaction is a read command or a write command without AP (automatic precharge); if the result of the determination is yes, proceed to step S806 and optionally, step S807.

[0110] Step S806: Obtain the storage block address value of the transaction, and increase the counter corresponding to the storage block by 1.

[0111] Step S807: Save the current transaction for use when receiving the next transaction;

[0112] Next, proceed to step S808: determine whether the reporting stage has been reached. If the determination result is no, proceed to step S801, otherwise, proceed to step S809.

[0113] Step S809: Determine at least one of the minimum value, the maximum value, and the average value in the queue corresponding to each storage block.

[0114] Step S810: Print at least one of the minimum value, the maximum value, and the average value of the number of consecutive read and write times corresponding to each storage block.

[0115] If the result of step S803 is no, proceed to step S804; if the result of step S804 is yes, proceed to step S805.

[0116] Step S804: Determine whether the current transaction is a precharge command or a read command or a write command with AP.

[0117] Step S805: obtain the storage block address value of the transaction, put the value of the counter corresponding to the storage block into the queue corresponding to the storage block, then set the counter corresponding to the storage block to 0, and proceed to step S801; otherwise, proceed directly to step S801.

[0118] In the above method, for the statistics of the number of read and write times when a certain storage block is activated: a certain storage block of the memory can only perform read and write operations after receiving the activation command operation, and when the storage block is no longer needed, the storage controller needs to send a precharge command. A statistical counter can be used to count the number of times a certain or each storage block receives a read and write command from receiving the activation command to receiving the precharge command. When the transaction received by the statistical module is a read command or a write command, the transaction information also includes a storage block value (for example, the address value of the storage block), and a counter array can be used to count the read and write commands corresponding to different storage blocks according to the storage block; when the received transaction is a precharge command, the value of the read and write counter corresponding to the storage block is placed in a queue divided by different storage blocks, and then the read and write counter is cleared. When the simulation proceeds to the report stage, the storage block queue stores the number of consecutive reads and writes each time the storage block is activated. After processing the queue, at least one of the minimum, maximum and average values ​​of the number of consecutive reads and writes when each storage block is activated can be obtained, and printed in the log file of the performance statistics report. In addition, in one implementation, the utilization rate of each storage block can also be counted. For example, the utilization rate of each storage block may be obtained based on the data in the queue counted using the above method, and printed in a log file of a performance statistics report.

[0119] For example, the statistical number of consecutive read and write times or storage block utilization when each storage block is activated can be used to reconfigure the parameters related to the storage controller. For example, by analyzing the statistical value of the consecutive read and write times or the statistical value of the storage block utilization when each storage block is activated, it can be determined whether the number of consecutive read and write times of the storage block when activated is too small. Because activation commands and precharge commands take up extra time, the same storage block should send as many read and write commands as possible when activated, and minimize the sending of activation and precharge commands. If the number of consecutive read and write times of the same storage block is too small, it will inevitably affect the bandwidth, and the corresponding logic code of the storage controller can be optimized or the configuration parameters involved in the storage controller can be adjusted.

[0120] Fig. 9 FIG. 1 is a schematic diagram showing a method for counting the time taken by refresh commands. Fig. 9 As shown, the method includes steps S901-S909.

[0121] Step S901: receiving transaction information from a monitor;

[0122] Step S902: Determine whether it is within the statistical time; if the result of the determination is yes, proceed to step S903, otherwise end.

[0123] Step S903: Determine whether the current transaction is a refresh command; if the result of the determination is yes, proceed to step S904.

[0124] Step S904: Get the current clock number and set the refresh start clock number to the clock number, and then proceed to step S901;

[0125] If the result of the judgment in step S903 is no, then step S905 is performed, and optionally, step S906 may also be performed.

[0126] Step S905: Obtain the current clock number, and put the difference between the obtained current clock number and the refresh start clock number into a queue.

[0127] Step S906: Save the current transaction for use when receiving the next transaction.

[0128] Next, proceed to step S907: determine whether the reporting stage has been reached. If the determination result is no, proceed to step S901, otherwise, proceed to step S908.

[0129] Step S908: sum up all the numbers in the queue to calculate the total number of refresh clocks; then divide it by the total number of simulation clocks to calculate the percentage.

[0130] Step S909: Print the total number of refresh clocks and the percentage of refresh time.

[0131] In the above method, the time occupied by the refresh command is counted as follows: when the received transaction information is a refresh-related command (for example, all_bank refresh or per_bank refresh), the performance statistics module records the current value of the clock counter; when the received transaction information is a non-refresh command, it indicates that the refresh operation is over, and the time occupied by the refresh can be obtained by subtracting the value of the clock counter at the start of the refresh from the value of the clock counter at this time. Before the end of the simulation, the values ​​of the number of clock cycles of all refresh times are accumulated to obtain the time occupied by all refreshes. When it comes to the reporting stage, the total number of clocks in the simulation time window and the number of clocks occupied by the refresh can be printed in the performance statistics log file, and the percentage of the number of refresh clocks to the total number of clocks can be calculated.

[0132] For example, the time or time ratio of the refresh command that is statistically taken can be used to reconfigure the parameters related to the storage controller. For example, by analyzing the time ratio of the refresh command, it can be determined whether the refresh time ratio is too large. If the ratio is too large, it means that the refresh command takes too long, which will have a certain impact on the data bandwidth. The refresh time interval and mechanism of the storage controller can be adjusted by adjusting or setting the configuration parameters of the storage controller accordingly, and the refresh time can be minimized while meeting the protocol requirements for the refresh timing.

[0133] In addition, for HBM type or similar memory devices, the number of bank group conversions may also be counted.

[0134] Fig.10 FIG. 1 is a schematic diagram showing a method for counting the number of storage block group conversions. Fig.10 As shown, the method includes steps S1001-S1008.

[0135] Step S1001: receiving transaction information from a monitor;

[0136] Step S1002: Determine whether it is within the statistical time; if the result of the determination is yes, proceed to step S1003, otherwise end.

[0137] Step S1003: Determine whether the current transaction is a read command or a write command; if the result of the determination is yes, proceed to step S1004; if the result of the determination is no, proceed to step S1001; otherwise, proceed to step S1005.

[0138] Step S1004: Determine whether the storage block group of the current transaction is different from the storage block group of the previous transaction.

[0139] Step S1005: the storage block group conversion counter is incremented by 1.

[0140] Optionally, after step S1005 , step S1006 may be performed: saving the current transaction for use when the next transaction is received.

[0141] Next, proceed to step S1007: determine whether the reporting stage has been reached. If the determination result is no, proceed to step S1001, otherwise, proceed to step S1008.

[0142] Step S1008: Print the value of the storage block group conversion counter.

[0143] Because the time interval between reading and writing different storage block groups of HBM storage devices is shorter than the time interval between reading and writing within the same storage block group, it is better to perform adjacent read and write operations between different storage block groups as much as possible to achieve better read and write performance. When the transaction information received by the performance statistics module is a read or write command, the transaction information also contains the value of the storage block group (for example, the address value). The address value of the current storage block group needs to be compared with the address value of the storage block group corresponding to the last received read and write command. If they are different, it means that the read and write operations are performed between different storage block groups, so the storage block group conversion counter can be increased by 1. Finally, the storage block group conversion counter is printed out in the report stage to the performance statistics log file.

[0144] For example, the statistical storage block group conversion times can be used to reconfigure parameters related to the storage controller. For example, by analyzing the value of the storage block group conversion times and combining the value of the total read and write times, the proportion of the storage block group conversion times to the total read and write times within the statistical time can be determined. If the proportion is too low, it will inevitably have a certain impact on the data bandwidth. The parameters related to the storage controller can be reconfigured, such as by adjusting the configuration of the address mapping or the logic code of the address mapping, to increase the storage block group conversion times as much as possible, thereby optimizing the performance bandwidth.

[0145] The format of the final printed performance report is a custom format. For example, based on the principle of simplicity and clarity, the printed information can include the name of the counter being counted and the value of the counter. Taking the conversion time interval of the read and write commands as a performance statistical indicator as an example, the printed result example is as follows:

[0146] Min Rd-->Wr turnaround clocks=7

[0147] Max Rd-->Wr turnaround clocks=129

[0148] Avg Rd-->Wr turnaround clocks=21

[0149] Min Wr-->Rd turnaround clocks=18

[0150] Max Wr-->Rd turnaround clocks=154

[0151] Avg Wr-->Rd turnaround clocks=28

[0152] Through the above information, it can be determined that the minimum time interval from read to write is 7 clock cycles, the maximum time interval is 129 clock cycles, and the average is 21 clock cycles; the minimum time interval from write to read is 18 clock cycles, the maximum time interval is 154 clock cycles, and the average is 28 clock cycles. First, analyze the minimum value of the read-write conversion interval. Generally, the read-write interval of the storage controller can be configured through the register. Check whether the minimum clock interval counted is equal to the value configured in the corresponding register. If it is not equal, it means that the design code cannot perform read-write conversion according to the value configured in the register, and the logic code of this function needs to be modified; if the minimum clock interval counted is equal to the configuration value of the register, it can also be checked whether the value of the register configuration is equal to the minimum read-write conversion time interval specified by the corresponding DDR / HBM device, otherwise it is necessary to set the value of the read-write conversion time interval register to be consistent with the minimum value specified by the device. Secondly, the maximum value of the read-write conversion interval can also be analyzed. If the maximum value of the read-write conversion interval is too large, it can be further analyzed in combination with the actual waveform to see whether the maximum value is reasonable and whether there is room for optimization in the design. In addition, the average value of the read-write conversion time interval can also be analyzed. The average value should be close to the minimum value. If it deviates greatly from the minimum value, it will also be one of the reasons for performance degradation. You can further combine the simulation waveform and the actual design code for analysis and then make modifications.

[0153] The embodiments of the present disclosure can solve the problem that the cause of insufficient performance or performance degradation cannot be quickly located in the performance verification of traditional DDR / HBM storage controllers. The present disclosure proposes to collect statistics on key information related to performance, and provides a statistical scheme and implementation method, and explains the impact of each statistical information on performance and the possible causes of performance degradation, thereby helping to speed up the location of the cause of performance degradation and make design improvements and optimizations.

[0154] At least some embodiments of the present disclosure also provide a verification device for a storage controller. Fig.11 A schematic diagram of a verification device for a storage controller according to at least some embodiments of the present disclosure is shown.

[0155] like Fig.11 As shown, a verification device 1100 for a storage controller according to at least some embodiments of the present disclosure includes: a verification component 1101 and a performance statistics module 1102. The verification component 1101 is configured to perform a verification operation on the storage controller, and the performance statistics module 1102 is configured to perform the following operations: during a set statistical time, receiving from the verification component 1101 multiple transaction information generated by the verification component 1101 interacting with the storage controller during the verification operation, obtaining at least one performance indicator of the storage controller based on the multiple transaction information, and outputting the at least one performance indicator after the statistical time ends.

[0156] For example, in one implementation, the performance statistics module 1102 is further configured to store the current transaction information after calculating performance indicators for the current transaction information for multiple transaction information, wherein at least one performance indicator is calculated based on the current transaction information and the last transaction information stored.

[0157] For example, in one implementation, at least one performance indicator counted by the performance statistics module 1102 includes at least one of the following: the number of conversions of read and write commands, the time interval for conversions of read and write commands, the number of consecutive read commands, the number of consecutive write commands, the number of read or write commands corresponding to the storage block, the utilization rate of the storage block, the time occupied by the refresh command, the proportion of the time occupied by the refresh command, the number of storage block group conversions, and the bandwidth for reading or writing data.

[0158] For example, in one implementation, the verification component 1101 is based on UVM and includes a monitor, a driver, and a scoreboard. The driver is configured to input a test signal to the storage controller; the monitor is configured to receive transaction information output for the test signal from the storage controller, and input the transaction information into the scoreboard to verify the storage controller. The performance statistics module 1102 is connected to the port of the verification component 1101 to obtain multiple transaction information from the monitor.

[0159] For example, in one implementation, the performance statistics module 1102 includes: a performance monitoring module, a valid time determination module, a clock counting module, and a reporting module.

[0160] The performance monitoring module is configured to obtain at least one performance indicator of the storage controller based on multiple transaction information; the effective time determination module is configured to set the statistical time and determine whether the current time is within the statistical time; the clock counting module is configured to count the clock; and the reporting module is configured to output at least one performance indicator.

[0161] At least some embodiments of the present disclosure further provide a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method according to any embodiment of the present disclosure is implemented.

[0162] At least some embodiments of the present disclosure further provide a computer program product, including a computer program / instruction, which implements the method according to any embodiment of the present disclosure when the computer program / instruction is executed by a processor.

[0163] At least some embodiments of the present disclosure further provide a verification device, the verification device comprising at least one processor and at least one memory. The at least one memory stores a computer program, and when the computer program is executed by the processor, the method according to any embodiment of the present disclosure is implemented.

[0164] For example, in one implementation, the verification device includes a verification apparatus for a storage controller according to any of the above embodiments.

[0165] Fig.12 A schematic diagram of a verification device according to at least one embodiment of the present disclosure is shown.

[0166] The verification devices in the embodiments of the present disclosure may include but are not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.12 The verification device 1000 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0167] For example, Fig.12 As shown, in some examples, the verification device 1200 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1201, which can be used to implement the verification device of any of the above embodiments, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1202 or the program loaded from the storage device 1208 to the random access memory (RAM) 1203. In the RAM 1203, various programs and data required for the operation of the computer system are also stored. The processing device 1201, the ROM 1202, and the RAM 1203 are connected to each other through a bus 1204. An input / output (I / O) interface 1205 is also connected to the bus 1204.

[0168] For example, the following components may be connected to the I / O interface 1205: an input device 1206 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1207 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1208 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1209 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1209 may allow the electronic device 1200 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. The drive 1210 is also connected to the I / O interface 1205 as needed. Removable media 1211, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 1210 as needed, so that the computer program read therefrom can be installed into the storage device 1208 as needed. Although Fig.12The verification device 1200 is shown as including various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0169] For example, the verification device 1200 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1209 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0170] For example, the verification device 1200 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0171] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be based on the protection scope of the attached claims and their equivalents.

Claims

1. A verification method for a storage controller, comprising: Performing a verification operation on the storage controller using a verification component; During a set statistical time, receiving from the verification component a plurality of transaction information generated by the verification component interacting with the storage controller during the verification operation; Based on the multiple pieces of transaction information, obtaining at least one performance indicator of the storage controller; After the statistical time ends, the at least one performance indicator is output.

2. The verification method according to claim 1, wherein: For the multiple pieces of transaction information, the at least one performance indicator is counted based on current transaction information and a previous piece of transaction information.

3. The verification method according to claim 1, wherein: The at least one performance indicator is obtained based on operation commands in the plurality of pieces of transaction information.

4. The verification method according to claim 3, wherein: The at least one performance indicator is obtained based on at least one of the following: The number of command conversions, the interval between command conversions, the number of consecutive commands, the utilization of storage blocks, the time for command execution, the proportion of time occupied by commands, and the number of storage block group conversions.

5. The verification method according to claim 3, wherein: The at least one performance indicator includes at least one of the following: The number of conversions of read and write commands, the time interval for conversions of read and write commands, the number of consecutive read commands, the number of consecutive write commands, the number of consecutive read or write commands corresponding to the storage block, the utilization of the storage block, the time occupied by the refresh command, the proportion of the time occupied by the refresh command, and the bandwidth for reading or writing data.

6. The verification method according to claim 5, wherein: The at least one performance indicator also includes the number of storage block group conversions, The storage block group conversion times are used to indicate the times of performing read or write operations between different storage block groups during a set statistical time period.

7. The verification method according to claim 1, wherein: The at least one performance indicator is used to reconfigure parameters related to the storage controller.

8. The verification method according to claim 1, wherein: The verification component is based on UVM and includes a monitor, a driver, a scoreboard, The using a verification component to perform a verification operation on the storage controller includes: Inputting a test signal from the driver to the storage controller; receiving, by the monitor, transaction information outputted from the storage controller in response to the test signal; The monitor inputs the transaction information into the scoreboard to verify the storage controller, The transaction information is also transmitted from the monitor to the performance statistics module through the port of the verification component to obtain at least one performance indicator of the storage controller based on the transaction information.

9. A verification device for a storage controller, comprising: A verification component configured to perform a verification operation on the storage controller; The performance statistics module is configured to: during a set statistical time, receive from the verification component a plurality of transaction information generated by the verification component interacting with the storage controller during the verification operation, obtain at least one performance indicator of the storage controller based on the plurality of transaction information, and output the at least one performance indicator after the statistical time ends.

10. The verification device according to claim 9, wherein: The performance statistics module is further configured to, for the plurality of pieces of transaction information, store the current transaction information after calculating the performance indicators for the current transaction information. The at least one performance indicator is counted based on the current transaction information and the last transaction information stored.

11. The verification device according to claim 9, wherein: The at least one performance indicator counted by the performance statistics module includes at least one of the following: The number of conversions of read and write commands, the time interval for conversions of read and write commands, the number of consecutive read commands, the number of consecutive write commands, the number of consecutive read or write commands corresponding to the storage block, the utilization of the storage block, the time occupied by the refresh command, the proportion of time occupied by the refresh command, the number of conversions of the storage block group, and the bandwidth for reading or writing data.

12. The verification device according to claim 9, wherein: The verification component is based on UVM and includes a monitor, a driver, a scoreboard, The driver is configured to input a test signal to the storage controller; The monitor is configured to receive transaction information outputted from the memory controller for the test signal, input the transaction information into the scoreboard to verify the memory controller, The performance statistics module is connected to the port of the verification component to obtain the multiple pieces of transaction information from the monitor.

13. The verification device according to claim 9, wherein: The performance statistics module includes: a performance monitoring module, configured to obtain at least one performance indicator of the storage controller based on the plurality of transaction information; An effective time determination module, configured to set the statistical time and determine whether the current time is within the statistical time; A clock counting module is configured to count clocks; A reporting module is configured to output the at least one performance indicator.

14. A verification device, comprising: at least one processor; At least one memory having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method according to any one of claims 1 to 8.

15. A computer-readable storage medium having a computer program stored therein, wherein the computer program, when executed by a processor, implements the method according to any one of claims 1 to 8.

16. A computer program product, comprising a computer program / instructions, which, when executed by a processor, implements the method according to any one of claims 1 to 8.

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