Verification method, device and system of isolation function

Abstract

The invention relates to the technical field of pre-silicon verification, and discloses an isolation function verification method, device and system, and the method comprises the steps: obtaining the hierarchical structure information of a power domain module in a to-be-tested chip; determining isolation definition information of the power domain module, and identifying an isolation signal type from the isolation definition information; determining a target internal port signal corresponding to the isolation signal type in the hierarchical structure information, and judging whether to perform mapping processing on the target internal port signal based on the signal mapping information according to the isolation signal type; and generating at least one assertion of a target isolation function verification signal according to the target isolation function verification signal represented by the judgment result, and performing isolation function verification on the power domain module based on the generated assertion. According to the technical scheme provided by one or more embodiments, the check assertion can be automatically and efficiently generated to verify the chip.

Description

Technical Field

[0001] The present application relates to the field of pre-silicon verification technology, and in particular to a verification method, device and system for an isolation function. Background Art

[0002] Pre-silicon verification is currently widely used in chip design. Pre-silicon verification can verify the chip through hardware simulation or software simulation.

[0003] In order to meet the requirements of the integrated circuit industry for chip power consumption, chip design has also become more complicated. In the pre-silicon verification stage, the verification of the isolation function is an important part of low-power design and verification. The verification process of the isolation function can ensure that the components that receive the output signals of the power-off area can work normally. The correctness of the isolation function usually directly affects the executability of the power domain design. In low-power verification, in addition to ensuring the correctness of the power domain division through power-on and power-off function verification, assertions are also required to ensure the functional correctness of the isolation signal.

[0004] At present, in the isolation function verification process, the generation of assertions mostly requires manual operation. The names of the isolated signals are manually screened out, and assertions are generated for the screened isolated signals one by one. In practical applications, if the isolated signal changes, due to the lag of manual operation, it is usually impossible to generate matching assertions in time, resulting in slow verification progress. In view of this, how to automatically and efficiently generate assertions for isolation function verification is an urgent problem to be solved. Summary of the invention

[0005] The present application provides a method, device and system for verifying an isolation function, which can automatically and efficiently generate assertions for verifying the isolation function.

[0006] In a first aspect, the present application provides a method for verifying an isolation function, the method being applied to a verification system for an isolation function, the system comprising a verification device and a chip to be tested; the verification device being communicatively connected to the chip to be tested, the chip to be tested comprising a power domain module for an isolation function to be verified, the method comprising: obtaining hierarchical information of the power domain module in the chip to be tested, the hierarchical information being at least used to characterize an internal port signal of the power domain module and signal mapping information of the power domain module in an upper-level module; determining isolation definition information of the power domain module, and identifying an isolation signal type from the isolation definition information; determining a target internal port signal corresponding to the isolation signal type in the hierarchical information, and judging whether to map the target internal port signal based on the signal mapping information according to the isolation signal type; generating at least one assertion of the target isolation function verification signal for a target isolation function verification signal characterized by a judgment result, and performing isolation function verification on the power domain module based on the generated assertion.

[0007] The technical solution provided by this embodiment of the present application can obtain the hierarchical information and isolation definition information of the power domain module for the power domain module of the isolation function to be verified in the chip to be tested. Among them, the hierarchical information can reflect the internal port signal of the power domain module in the chip to be tested and the signal mapping information between modules of different levels. After determining the isolation signal type based on the isolation definition information, it can be determined whether it is necessary to perform signal mapping processing on the target internal port signal corresponding to the isolation signal type, so as to ensure the correctness of the target isolation function verification signal. Subsequently, at least one assertion can be generated for the target isolation function verification signal, and the isolation function of the power domain module can be verified based on the generated assertion. It can be seen that the technical solution provided by this embodiment of the present application does not need to collect isolation signal information manually, but can automatically analyze the hierarchical information and isolation definition information to generate corresponding assertions. This process reduces human errors, and when the isolation signal changes, the hierarchical information and isolation definition information will also change accordingly. The assertion generated based on the changed hierarchical information and isolation definition information can also match the new isolation signal, thereby improving the efficiency and accuracy of assertion generation, thereby ensuring that the isolation function verification can proceed smoothly.

[0008] In one possible implementation, obtaining the hierarchical information of the power domain module in the chip under test includes: determining a first RTL file path of the power domain module, and determining a second RTL file path of the upper-level module; reading a first RTL file under the first RTL file path and a second RTL file under the second RTL file path; in the first RTL file, identifying a module identifier of the power domain module and obtaining an internal port signal of the power domain module; based on the module identifier, determining an instantiation location of the power domain module in the second RTL file, and obtaining, from the second RTL file, signal mapping information of the power domain module in the upper-level module.

[0009] The technical solution provided in this embodiment of the present application obtains hierarchical information, including the first RTL file path of the power domain module and the second RTL file path of the upper-level module, and reads the first RTL file and the second RTL file; by obtaining the module identifier of the power domain module, the instantiation position is located in the upper-level module, so as to accurately obtain the internal port signals and signal mapping information of the power domain module, thereby further improving the efficiency of the system.

[0010] In a possible implementation, in the first RTL file, identifying the module identifier of the power domain module includes: filtering out line information containing specified keywords in non-comment lines of the first RTL file, and removing formatting characters in the line information to obtain the module identifier of the power domain module.

[0011] The technical solution provided in this embodiment of the present application determines the module identification of the power domain module by screening out the row information containing the specified keywords, thereby improving the recognition accuracy of the module identification.

[0012] In one possible implementation, based on the module identifier, determining the instantiation position of the power domain module in the second RTL file includes: in the second RTL file, querying a target row with the module identifier as starting information; detecting whether the target row contains the instantiation identifier of the power domain module in the upper-level module, and if so, determining the position of the target row as the instantiation position of the power domain module; if not, querying the next target row with the module identifier as starting information.

[0013] The technical solution provided in this embodiment of the present application determines the instantiation position of the power domain module by querying the target row with the module identifier as the starting information, thereby improving the positioning accuracy of the instantiation position.

[0014] In a possible implementation, according to the instantiation position, obtaining the signal mapping information of the power domain module in the upper-level module from the second RTL file includes: starting from the instantiation position, searching the second RTL file for candidate rows containing the first specified symbol; from each of the candidate rows, reading the module internal port signals and module external signals having a mapping relationship, and converting the read module internal port signals and module external signals having a mapping relationship into signal mapping information in a specified data format.

[0015] The technical solution provided in this embodiment of the present application can obtain signal mapping information more quickly, conveniently and accurately by querying the candidate rows containing the first specified symbol, reading the module internal port signals and module external signals with the mapping relationship and converting them into signal mapping information in a specified data format.

[0016] In one possible implementation, determining the isolation definition information of the power domain module includes: reading the UPF file of the power domain module, and searching for a starting line containing a specified string in the non-comment lines of the UPF file, wherein the specified string is used to characterize the setting of the isolation definition information; starting from the starting line, detecting whether the end of each line carries a second specified symbol, and determining the ending line of the isolation definition information based on the detection result; and extracting the isolation definition information of the power domain module from the UPF file according to the starting line and the ending line.

[0017] The technical solution provided in this embodiment of the present application reads the UPF file of the power domain module through a script to determine the isolation definition information of the power domain module, and can quickly extract the isolation definition information from the UPF file.

[0018] In a possible implementation, determining the target internal port signal corresponding to the isolation signal type in the hierarchical information includes: filtering out the internal port signals defined by the isolation signal type from the internal port signals of the power domain module represented by the hierarchical information, and using the filtered out internal port signals as the target internal port signals corresponding to the isolation signal type.

[0019] The technical solution provided in this implementation of the present application screens the internal port signals according to the isolation signal type and filters out irrelevant internal port signals, thereby simplifying the subsequent signal processing process and improving signal processing efficiency.

[0020] In one possible implementation, the signal mapping information represented by the hierarchical information includes one or more groups of signal key-value pairs, the keys in the signal key-value pairs are used to represent the internal port signals of the power domain module, and the values ​​in the signal key-value pairs are used to represent the external signals connected to the internal port signals; after determining the target internal port signals corresponding to the isolation signal type in the hierarchical information, the method further includes: filtering out the signal key-value pairs whose keys are the target internal port signals from the one or more groups of signal key-value pairs, and using the filtered signal key-value pairs as the signal mapping information for mapping processing.

[0021] The technical solution provided in this implementation of the present application refines the concept of key-value pairs, screens multiple groups of key-value pairs through the keys in the signal key-value pairs, and retains only key-value pairs that meet the conditions, thereby reducing the number of key-value pairs and improving data processing efficiency.

[0022] In one possible implementation, determining whether to perform mapping processing on the target internal port signal based on the signal mapping information includes: if the isolation signal type represents the input signal type, determining that mapping processing is not required, and using the target internal port signal as the target isolation function verification signal represented by the judgment result; if the isolation signal type represents the output signal type, determining that mapping processing is required, and using the target external signal after mapping processing of the target internal port signal as the target isolation function verification signal represented by the judgment result.

[0023] The technical solution provided in this embodiment of the present application describes how to determine whether to map the internal port signal. By differentiating the input signal type and the output signal type, the determined target isolation function verification signal can be made more accurate, thereby ensuring that it can be compared with the correct isolation value during subsequent assertion detection.

[0024] In one possible implementation, generating at least one assertion of the target isolation function verification signal includes: reading a pre-generated assertion template, wherein the assertion template is obtained by encapsulating a pre-configured attribute definition by a custom macro, and the attribute definition is used to characterize the detection strategy of the assertion in different scenarios; using the signal identifier of the target isolation function verification signal as a parameter of the assertion template to generate at least one assertion of the target isolation function verification signal through the assertion template.

[0025] The technical solution provided in this embodiment of the present application determines the custom macro features and attribute definition features of the assertion template, and uses the signal identifier of the target isolation function verification signal as a parameter of the assertion template, which can conveniently generate the corresponding assertion, thereby improving the efficiency of assertion generation.

[0026] In one possible implementation, the assertion generated for the target isolation function verification signal includes at least one of the following: after the isolation function control signal is enabled, checking whether the isolation value of the target isolation function verification signal is the same as the isolation value declared in the isolation definition information; or after the isolation function control signal is enabled, the power-on control signal of the power domain module is enabled and the reset signal is effective, checking whether the isolation value and the reset value of the target isolation function verification signal are the same; or after the isolation function control signal is enabled and the power domain module is powered off, checking whether the internal port signal of the power domain module is in an indeterminate state.

[0027] The technical solution provided in this implementation mode of the present application determines the specific contents of the three assertions, and automatically generates isolation function correctness check assertions covering isolation value correctness check, internal port signal indeterminate state check after module power-off and isolation enabled, and isolation value and reset value relationship check, making low power consumption verification more complete.

[0028] In a possible implementation, the assertion template is generated in the following manner: create a top-level folder; create an initial configuration file in the top-level folder, and write the custom macro and the pre-configured property definition into the initial configuration file; in the initial configuration file, use the custom macro to encapsulate the pre-configured property definition into one or more assertion templates.

[0029] In one possible implementation, based on the assertion template, an isolation function check module corresponding to the power domain module is declared in the initial configuration file; a top-level module is generated, and the isolation function check module is instantiated in the top-level module; the top-level module in which the isolation function check module is instantiated is bound to the top level of the verification environment, so as to perform isolation function verification on the power domain module through the isolation function check module in the top-level module in the verification environment.

[0030] The technical solution provided in this embodiment of the present application determines the custom macro and the pre-configured property definition, uses the custom macro to encapsulate the pre-configured property definition into one or more assertion templates, declares the isolation function check module corresponding to the power domain module based on the assertion template, and performs isolation function verification on the power domain module through the isolation function check module in a verification environment.

[0031] The second aspect of the present application provides an isolation function verification device, which is communicatively connected to a chip to be tested, wherein the chip to be tested includes a power domain module with an isolation function to be verified, and the verification device is used to implement the isolation function verification method described in the first aspect.

[0032] The third aspect of the present application provides a verification system for an isolation function, the system comprising a verification device and a chip to be tested, the verification device being communicatively connected to the chip to be tested, the chip to be tested comprising a power domain module for the isolation function to be verified, and the verification device being used to implement the verification method for the isolation function described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 A step diagram of a method for verifying an isolation function provided in an embodiment of the present application; Figure 2 A schematic diagram of a hierarchical structure relationship of an instantiation module provided for an embodiment of the present application; Figure 3 A code schematic diagram of two RTL files with a mapping relationship provided for an embodiment of the present application; Figure 4 A step diagram of a method for obtaining hierarchical structure information provided by an embodiment of the present application; Figure 5 A schematic diagram of a type of assertion generation provided for an embodiment of the present application; Figure 6 A schematic diagram of the composition of a top-level folder provided for one embodiment of the present application; Figure 7 A flowchart of a method for verifying an application isolation function provided in one embodiment of the present application; Figure 8 A schematic diagram of the structure of a verification device for an isolation function provided by an embodiment of the present application; Fig. 9 A schematic diagram of the structure of a verification system for an isolation function provided in one embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0036] In addition, the descriptions involving "first", "second", etc. in this application are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more. In addition, the use of "based on" or "according to" means openness and inclusiveness, because the process, steps, calculations or other actions "based on" or "according to" one or more of the conditions or values ​​can be based on additional conditions or beyond the described values ​​in practice.

[0037] With the continuous development of the integrated circuit industry, the requirements for chip power consumption are becoming increasingly stringent, which makes the design of low-power chips more complicated. When performing low-power verification, in addition to ensuring the correctness of power domain division by verifying the power-on and power-off functions, assertion methods are also required to ensure the correctness of all isolated signal functions. Generally speaking, assertions can be a formal way to describe design behavior, and assertions can be used to check whether specific properties or behaviors in the design meet expectations.

[0038] In the related art, a valid isolation value table file is usually processed through a python script to generate a specific check assertion for each signal to ensure the correctness of the signal isolation function. However, this method requires manual screening of the names of all isolated signals, which is prone to errors and increases time costs. At the same time, if the signal changes, the table cannot be updated quickly to generate assertions, which slows down the verification speed. In addition, the assertion check dimensions for the isolation function in the related art are relatively few, which is not enough to fully guarantee the correctness of the isolation function, and the assertion error information is not processed and analyzed, and the errors of isolation-related functions cannot be efficiently and intuitively displayed.

[0039] In view of this, one or more embodiments of the present disclosure provide a method, device and system for verifying an isolation function, which can solve the above-mentioned problems and realize automatic and efficient generation of assertions for verifying the isolation function.

[0040] See also Figure 1 In one embodiment of the present disclosure, a method for verifying an isolation function is provided, and the method may include the following steps: S1: Obtaining hierarchical structure information of the power domain module in the chip under test, wherein the hierarchical structure information is at least used to characterize internal port signals of the power domain module and signal mapping information of the power domain module in an upper-level module.

[0041] In this embodiment, the chip to be tested includes a power domain module with an isolation function to be verified. Specifically, the power domain module can be an area inside the chip to be tested that distributes and manages power. Dividing the chip into multiple power domain modules for independent power control can optimize power management and reduce chip power consumption. The hierarchical structure information of the divided power domain modules is recorded in an RTL (Register Transfer Level) file, and the RTL file uses the HDL (Hardware Description Language) language to describe the circuit behavior. The signal mapping information is the mapping relationship between the internal port signal of the module and the signal outside the module.

[0042] It should be noted that the power domain module is an instantiated module. In the instantiation process, the power domain module is a submodule, and the module at the previous level is a parent module. The submodule can be used repeatedly in the parent module to construct a complex circuit structure and form a hierarchical structure relationship. Figure 2 , module A and module B form a hierarchical relationship, module B is the current power domain module, module A is the upper level module of module B, and the TOP module represents the overall circuit structure of the chip to be tested. Specifically, the hierarchical information can be represented by the RTL files of modules at different levels. Among them, the RTL file of the power domain module is used to record the signal name of the internal port signal of the power domain module, and the RTL file of the upper level module where the power domain module is located is used to record the signal mapping information, which is used to characterize the mapping relationship between the internal port signal of the power domain module and the external signal of the power domain module.

[0043] S3: Determine the isolation definition information of the power domain module, and identify the isolation signal type from the isolation definition information.

[0044] In this embodiment, the isolation definition information is included in the isolation definition statement of the UPF (Unified Power Format) file, and the UPF file is used to describe the power supply of the RTL file. Among them, the isolation definition information is not limited in this application, for example, it can include: the name of the isolation definition, the isolation definition application signal, the isolation value specified by the isolation definition, the enable signal specified by the isolation definition, etc. The isolation signal type includes but is not limited to the input input signal type and the output output signal type.

[0045] In one embodiment, determining the isolation definition information of the power domain module includes: reading the UPF file of the power domain module, and querying the starting line containing a specified string in the non-comment lines of the UPF file, wherein the specified string is used to characterize the setting of the isolation definition information, starting from the starting line, detecting whether the end of each line carries a second specified symbol, and determining the ending line of the isolation definition information based on the detection result, and extracting the isolation definition information of the power domain module from the UPF file according to the starting line and the ending line.

[0046] Specifically, open the UPF file and filter out all commented lines to obtain the above-mentioned non-comment lines. For example, delete the spaces at the beginning of each line and all lines starting with '#' after the tab character, that is, filter out all commented lines. The isolation definition statement can be found in the non-comment line according to the specified string later. Based on the specified string, the starting line of the isolation definition statement can be determined. The statement from the starting line to the first end without the character "\" can be determined as the termination line of the isolation definition statement. In an application scenario, the above-mentioned starting line can be set_isolationA1_ISO\, and the termination line can be -location parent, indicating the current location of the termination line. Among them, the specified string is "set_isolation", which means setting the isolation definition information, and the second specified symbol is '\'. From this, it can be inferred that the current isolation definition information is named 'A1_ISO'. Subsequently, the information contained in the isolation definition statement here in the UPF file can be extracted according to the grammatical keywords. The syntax keywords include, but are not limited to, 'strategy_name' (strategy name), '-clamp_value' (isolation value), 'signal_list' (signal list), and '-isolation_sense' (isolation enable signal value).

[0047] In one embodiment, the obtained isolation definition information is output in a suitable data format. For example, it can be output in a dictionary format, such as: {'name': signal name of the isolation definition, 'clamp_value': isolation value of the isolation definition, 'signal_list': list of signal names affected by the isolation definition, 'isolation_sense': value of the isolation enable signal when isolation takes effect}.

[0048] In one embodiment, the isolation signal type can be represented by 'applies_to'. For example, '-applies_tooutputs' can represent that the isolation signal type is an output signal, and '-applies_toinputs' can represent that the isolation signal type is an input signal.

[0049] The technical solution provided in this embodiment of the present application reads the UPF file of the power domain module through a script to determine the isolation definition information of the power domain module, and can quickly extract the isolation definition information from the UPF file.

[0050] S5: Determine the target internal port signal corresponding to the isolation signal type in the hierarchical structure information, and determine whether to perform mapping processing on the target internal port signal based on the signal mapping information according to the isolation signal type.

[0051] In this embodiment, according to the above determined isolation signal type, the obtained module internal port signals are screened to find all target internal port signals defined by the isolation signal type, for example, all input type target internal port signals or all output type target internal port signals.

[0052] In this embodiment, the hierarchical structure information includes the RTL file of the upper level module, and the signal mapping relationship of the power domain module can be obtained from the RTL file. The signal mapping relationship can be expressed as a key-value pair, the key in the signal key-value pair is used to represent the internal port signal name of the power domain module, and the value in the signal key-value pair is used to represent the external signal name connected to the internal port signal.

[0053] In this embodiment, determining the target internal port signal corresponding to the isolation signal type in the hierarchical information includes: filtering out the internal port signal defined by the isolation signal type from the internal port signal of the power domain module represented by the hierarchical information, and using the filtered internal port signal as the target internal port signal corresponding to the isolation signal type. Wherein, the signal mapping information represented by the hierarchical information includes one or more groups of signal key-value pairs. After determining the target internal port signal corresponding to the isolation signal type in the hierarchical information, the method further includes: filtering out the signal key-value pair whose key is the target internal port signal from the one or more groups of signal key-value pairs, and using the filtered signal key-value pair as the signal mapping information for mapping processing. Specifically, firstly, the RTL file of the upper-level module of the power domain module is obtained, and the signal mapping relationship represented by the key-value pair of all the power domain modules contained in the RTL file of the upper-level module is read, for example: .XXX(xxx), .YYY(yyy), XXX and YYY are internal port signals. Then, according to the isolation signal type, the signal key-value pairs corresponding to the internal port signals that meet the isolation signal types are filtered out. For example, the signal key-value pair of the input type is {"XXX":"xxx"}, and the signal key-value pair of the output type is {"YYY":"yyy"}, among which the filtered XXX and YYY are the target internal port signals, XXX is the target internal port signal of the input type, and YYY is the target internal port signal of the output type. Finally, the filtered signal key-value pairs {"XXX":"xxx"} or {"YYY":"yyy"} are retained as signal mapping information for subsequent mapping processing.

[0054] The technical solution provided by this embodiment of the present application screens the internal port signals according to the isolation signal type and filters out irrelevant internal port signals, thereby simplifying the subsequent signal processing process and improving the signal processing efficiency. In addition, the present solution further refines the concept of key-value pairs, and screens multiple groups of key-value pairs by the keys in the signal key-value pairs, retaining only the key-value pairs that meet the conditions, thereby reducing the number of key-value pairs and improving the efficiency of data processing.

[0055] Furthermore, determining whether to perform mapping processing on the target internal port signal based on the signal mapping information includes: if the isolation signal type represents the input signal type, determining that mapping processing is not required, and using the target internal port signal as the target isolation function verification signal represented by the judgment result; if the isolation signal type represents the output signal type, determining that mapping processing is required, and using the target external signal after mapping processing of the target internal port signal as the target isolation function verification signal represented by the judgment result.

[0056] In one possible implementation, see Figure 3 , take the target internal port signal of output type as an example. For isolating the output signal, mapping processing is required. The target isolation function verification signal is yyy in module a corresponding to YYY in module b. Get the RTL file of the module, that is, the bv file, and the RTL file of the upper-level module of the power domain module, that is, the av file. The av file records the signal mapping information of the power domain module b. According to the bv file, find all the target internal port signals of output type through the output keyword and generate a list ["YYY"]. Traverse the internal port signals in all av files and correspond to the signals in the above ["YYY"] list, filter out the target internal port signal "YYY", and use the signal key-value pair {"YYY":"yyy"} corresponding to "YYY" as the signal mapping information, and filter out the signal key-value pairs {"XXX":"xxx"} that do not belong to the output type. Use the clamp_value keyword to obtain the isolation definition information. The isolation definition information is generally 0 / 1 / latch. Use the elements keyword to obtain the isolation signal name declared in the isolation definition information. Match the isolation definition information with the isolation signal name, that is, {"1":["YYY"]}. Since YYY is an internal port signal, mapping processing should be performed when isolating the output signal. For external signals, according to the module a part in the av file, yyy is the corresponding target external signal. Therefore, the target isolation function verification signal corresponding to YYY is yyy. The final signal mapping information after mapping processing is {"1":["yyy"]}.

[0057] In one possible implementation, see Figure 3, take the target internal port signal of input type as an example. For isolating the input signal, no mapping processing is required. The target isolation function verification signal is XXX in module b. Get the RTL file of the module, that is, the bv file, and the RTL file of the upper-level module of the power domain module, that is, the av file. The av file records the signal mapping information of the power domain module b. According to the bv file, find all the target internal port signals of input type through the input keyword, generate a list ["XXX"], traverse the internal port signals in all av files, correspond to the signals in the above ["XXX"] list, and filter out the target internal port signal "XXX". Use the clamp_value keyword to obtain the isolation definition information, use the elements keyword to obtain the isolation signal name declared in the isolation definition information, and correspond the isolation definition information with the isolation signal name, that is, {"1":["XXX"]}, no mapping processing is required.

[0058] The technical solution provided in this embodiment of the present application describes how to determine whether to map the internal port signal. By differentiating the input signal type and the output signal type, the determined target isolation function verification signal can be made more accurate, thereby ensuring that it can be compared with the correct isolation value during subsequent assertion detection.

[0059] It should be noted that Figure 3 The RTL file shown in the figure is only an example for better understanding of the present application scheme, and does not represent the RTL file in the actual verification process, nor does it mean that the technical solution of the present application can only be applied to Figure 3 The RTL file shown. Those skilled in the art should know that the simplified representation of the code and the simplified representation of the code file hierarchy are intended to better understand the technical essence of the present application, and this should not limit the scope of protection of the technical solution of the present application. In fact, reasonable deformation and improvement of the technical solution of the present application made by those skilled in the art with understanding the technical essence of the present application should theoretically be included in the scope of protection of the technical solution of the present application.

[0060] S7: generating at least one assertion of the target isolation function verification signal represented by the judgment result, and performing isolation function verification on the power domain module based on the generated assertion.

[0061] In this embodiment, for the target isolation function verification signal characterized by the judgment result, a pre-set assertion template is read, and the signal identifier of the target isolation function verification signal is used as a parameter of the assertion template to generate at least one assertion of the target isolation function verification signal, and the assertion type is not limited in this disclosure. Based on the generated assertion, the isolation function of the power domain module to be tested is verified in a simulation environment to optimize the circuit design.

[0062] In this embodiment, the function codes and function functions required for generating assertions can be encapsulated by pre-declaration and definition, and can be directly referenced in the declaration or definition when generating assertions later, thereby forming an assertion template. By using the signal identifier as a parameter of the assertion template, the corresponding function code and function can be directly called, thereby realizing the generation of assertions while simplifying code editing.

[0063] In this embodiment, after generating at least one assertion of the target isolation function verification signal, the isolation function verification can be performed based on the generated assertion. In practical applications, the generated assertion can be inserted into the design code of the power domain module. The assertion can be written together with the design code, or it can be inserted at different levels of the design (such as the boundary, interface, etc. of the power domain module). It should be noted that the insertion of the assertion should be as close as possible to the functional point to be verified to improve the accuracy and efficiency of the verification. During the simulation process for the power domain module, the assertion will be activated, and according to the function of the assertion, the target isolation function verification signal in the power domain module will be checked to determine whether the isolation value related to the target isolation function verification signal is correct.

[0064] The technical solution provided in this embodiment of the present application determines the custom macro features and attribute definition features of the assertion template, and uses the signal identifier of the target isolation function verification signal as a parameter of the assertion template, which can conveniently generate the corresponding assertion, thereby improving the efficiency of assertion generation.

[0065] Based on the above ideas, the technical solution provided by this embodiment of the present application can obtain the hierarchical information and isolation definition information of the power domain module for the power domain module of the isolation function to be verified in the chip to be tested. Among them, the hierarchical information can reflect the internal port signal of the power domain module in the chip to be tested and the signal mapping information between modules of different levels. After determining the isolation signal type based on the isolation definition information, it can be determined whether it is necessary to perform signal mapping processing on the target internal port signal corresponding to the isolation signal type, so as to ensure the correctness of the target isolation function verification signal. Subsequently, at least one assertion can be generated for the target isolation function verification signal, and the isolation function of the power domain module can be verified based on the generated assertion. It can be seen that the technical solution provided by this embodiment of the present application does not need to collect isolation signal information manually, but can automatically analyze the hierarchical information and isolation definition information to generate corresponding assertions. This process reduces human errors, and when the isolation signal changes, the hierarchical information and isolation definition information will also change accordingly. The assertion generated based on the changed hierarchical information and isolation definition information can also match the new isolation signal, thereby improving the efficiency and accuracy of assertion generation, thereby ensuring that the isolation function verification can proceed smoothly.

[0066] See also Figure 4 In a possible implementation manner, the hierarchical structure information of the power domain module in the chip under test is obtained, and step S1 further includes: S101: Determine a first RTL file path of the power domain module, and determine a second RTL file path of the upper-level module.

[0067] The first RTL file is an RTL file of a power domain module to be tested, and the second RTL file is an RTL file of an upper-level module of the power domain module.

[0068] In practical applications, the first RTL file usually contains the module name of the power domain module to be tested and the port signal name inside the power domain module to be tested. Figure 3In the example, bv can represent the first RTL file, wherein the module name of the power domain module to be tested can be b, and the port signal names inside the power domain module to be tested can be XXX and YYY. In the second RTL file, relevant information of the upper-level module can usually be included. For example, the module name and port signal name of the upper-level module can be included. At the same time, since the power domain module to be tested is instantiated in the upper-level module, some information related to the power domain module to be tested will also be included in the second RTL file. Specifically, the second RTL file can include the instantiation name of the power domain module to be tested, and can also include the mapping relationship between the port signal inside the power domain module to be tested and the external signal in the upper-level module. For example, in Figure 3 In the example, av can represent the second RTL file, in which the module identifier of the upper-level module is a, and the port signal names are xxx and yyy. At the same time, in the second RTL file, the instantiation name B of the power domain module to be tested is also noted, and the mapping relationship between the port signal inside the power domain module to be tested and the external signal in the upper-level module can be given in the form of key-value pairs, for example Figure 3 .XXX(xxx) and .YYY(yyy) in .

[0069] S103: Read a first RTL file in the first RTL file path and a second RTL file in the second RTL file path.

[0070] S105: In the first RTL file, identify the module identifier of the power domain module and obtain the internal port signal of the power domain module.

[0071] In this embodiment, identifying the module identifier of the power domain module includes: filtering out line information containing specified keywords in non-comment lines of the first RTL file, and removing formatting characters in the line information to obtain the module identifier of the power domain module.

[0072] In one embodiment, the module identifier of the power domain module is the module name of the module. Specifically, the first RTL file is opened, and all lines that may declare the module identifier of the power module are found by filtering the keyword "module", and all commented lines are filtered out to obtain lines that contain the keyword 'module' and are not commented out, and the keyword 'module' and other irrelevant characters in the line are removed to obtain the module name of the module.

[0073] The technical solution provided in this embodiment of the present application determines the module identification of the power domain module by screening out the row information containing the specified keywords, thereby improving the recognition accuracy of the module identification.

[0074] S107: Based on the module identifier, determine the instantiation location of the power domain module in the second RTL file, and obtain signal mapping information of the power domain module in the upper-level module from the second RTL file according to the instantiation location.

[0075] In this embodiment, based on the module identifier, determining the instantiation position of the power domain module in the second RTL file includes: in the second RTL file, querying the target row with the module identifier as the starting information; detecting whether the target row contains the instantiation identifier of the power domain module in the upper-level module, and if so, determining the position of the target row as the instantiation position of the power domain module; if not, querying the next target row with the module identifier as the starting information.

[0076] In one embodiment, the second RTL file is opened and traversed in rows. If a row starts with the above module identifier and contains the instantiation identifier of the module, the instantiation position of the module is found. If the instantiation identifier of the module is not contained, a query is performed with the next module identifier as the starting row. After the instantiation position of the module is found, the signal mapping information of the module is obtained. The signal mapping information represents the connection relationship of the module signal, including the port signal within the module and the signal outside the module. Generally, a fixed format is used. For example, all rows containing signal mapping information can be found by judging whether each row starts with ".", and the acquisition of the signal mapping information is terminated by judging whether the row ends with ";". In addition, the signal mapping information is output in a specific manner, such as {"port signal name within the module": "signal name outside the module"}.

[0077] It should be noted that if the second RTL file contains multiple instances instantiated by the module identifier of the power domain module, it is necessary to additionally specify the instance name of the instantiated power domain to be tested. For example, after filtering by the module identifier 'A', two rows containing the module identifier of 'A' are found, namely 'A a1_inst' and 'A a2_inst', then it is necessary to determine the instantiation location of the power domain module by whether it contains the declared instance name 'a1_inst'.

[0078] In one embodiment, see Figure 3, taking bv as the first RTL file of the module to be tested and av as the second RTL file as an example, the module identifier "b" of the module is found by filtering the module keyword, and the module port signal XXX or YYY of the "b" module is obtained. Based on the module name, the instantiation identifier "bB" of the module is determined in the second RTL file. According to the instantiation position, the signal mapping information ".XXX(xxx)" or ".YYY(yyy)" in the upper-level module can be obtained, where xxx or yyy is a signal outside the module, and XXX or YYY is a port signal inside the module. Thus, the signal mapping information is output in a specific manner, for example, using a dictionary output method to output {"XXX":"xxx"} or {"YYY":"yyy"}.

[0079] The technical solution provided in this embodiment of the present application determines the instantiation position of the power domain module by querying the target row with the module identifier as the starting information, thereby improving the positioning accuracy of the instantiation position.

[0080] Based on the above ideas, this solution obtains hierarchical information, including the first RTL file path of the power domain module and the second RTL file path of the upper-level module, and reads the first RTL file and the second RTL file; by obtaining the module identifier of the power domain module, the instantiation position is located in the upper-level module, so as to accurately obtain the internal port signal and signal mapping information of the power domain module, thereby further improving the efficiency of the system.

[0081] See also Figure 5 In a possible implementation manner, the assertion generated for the target isolation function verification signal in step S7 includes at least one of the following: Type 1: After the isolation function control signal is enabled, check whether the isolation value of the target isolation function verification signal is the same as the isolation value declared in the isolation definition information.

[0082] In this embodiment, if the isolation value indicated by the key of the key-value pair of the target isolation function verification signal is 0, then the corresponding assertion should check whether the isolation value declared in the isolation definition information is 0; if the isolation value indicated by the key of the key-value pair of the target isolation function verification signal is 1, then the corresponding assertion should check whether the isolation value declared in the isolation definition information is 1 after the assertion precondition is met.

[0083] Type 2: After the isolation function control signal is enabled, the power-on control signal of the power domain module is enabled, and the reset signal takes effect, check whether the isolation value and reset value of the target isolation function verification signal are the same.

[0084] In this embodiment, the value of the detected signal is an isolation value, and the value of the port signal in the module connected to the detected signal is a reset value. If the isolation function of the power domain module to be tested is applied to the input port, the generation of this type of assertion is skipped, and if the isolation function of the power domain module to be tested is applied to the output port, the generation of this type of assertion continues.

[0085] Type 3: After the isolation function control signal is enabled and the power domain module is powered off, check whether the internal port signal of the power domain module is in an unstable state.

[0086] The indeterminate state of the internal port signal indicates that the output state of the internal port cannot be clearly predicted based on the input signal. Specifically, when the power domain module is powered off, the output state corresponding to the internal port of the power domain module cannot be determined. At this time, the internal port signal of the power domain module should be in an indeterminate state.

[0087] In this embodiment, if the isolation function of the power domain module to be tested is applied to the input port, the generation of this type assertion is skipped; if the isolation function of the power domain module to be tested is applied to the output port, the generation of this type assertion continues.

[0088] The technical solution provided in this implementation mode of the present application determines the specific contents of the three assertions, and automatically generates isolation function correctness check assertions covering isolation value correctness check, internal port signal indeterminate state check after module power-off and isolation enabled, and isolation value and reset value relationship check, making low power consumption verification more complete.

[0089] See also Figure 6 In a possible implementation, in step S7, the assertion template may be generated in the following manner: S701: Create a top-level folder.

[0090] S703: Create an initial configuration file in the top-level folder, and write the custom macro and the pre-configured property definition into the initial configuration file.

[0091] S705: In the initial configuration file, encapsulate the pre-configured attribute definition into one or more assertion templates using the custom macro.

[0092] In this embodiment, a top-level folder is first created, and the top-level folder is used to store all files generated by this script run, such as assertion index files, initialization configuration files, etc. It should be noted that the name of the top-level folder is unique. Optionally, a method of naming with non-repeating random numbers can be adopted, or a method of adding a timestamp of the script run can be adopted to ensure that the name of the top-level folder is unique for comparison and positioning. The assertion index file is used to add the index path of all assertion files generated subsequently to ensure that it can be compiled normally during subsequent simulation. Macro definitions and attribute definitions are declared in the initial configuration file. The macro definition includes a hierarchical index of the RTL file, and the attribute definition includes an assertion type index. The above attribute definitions can be encapsulated into one or more assertion templates using custom macros, for example, the above three assertion types are encapsulated into three assertion templates. After the encapsulation of the assertion template, the generation of the corresponding assertion can be realized by simply using the path of the internal port signal as a parameter of the template, thereby improving the convenience and efficiency of assertion generation. The path of the internal port signal uses the custom macro and signal name corresponding to the hierarchical information as template parameters. For example, the path of the internal port signal can be: "A_PATH, signal_0", A_PATH is the custom macro corresponding to the hierarchical information, and signal_0 is the signal name of the internal port signal. In addition, when the assertion is generated, the index path of the assertion index file and the initial configuration file is printed to the command line interface.

[0093] In this embodiment, the assertion folder also includes assertion files, debug files, and macro definition files. Specifically, each power domain module to be tested has its corresponding assertion folder, and the index path of the assertion folder is added to the assertion index file, and at least one assertion file generated for the power domain module to be tested is written into the assertion folder. Optionally, the assertions in the assertion file can be generated according to the above-mentioned assertion template. Among them, in the corresponding assertion folder, different assertion files are established according to different assertion types. The debug file is used to record information, and the information includes but is not limited to signal mapping information, target internal port signals corresponding to the isolation signal type, and adaptation information between the isolation value and the target isolation function verification signal.

[0094] It should be noted that the macro definition file is used to declare the macro definition corresponding to the signal bit width. In the scenario where the signal bit width involved in the assertion has a macro definition, you need to create an additional file to declare the macro definition. Optionally, you can use the localparam syntax to define the parameter without affecting the macro of the same name in other modules. In addition, in the assertion folder, the macro definition file should be placed before the assertion file.

[0095] The technical solution provided in this embodiment of the present application determines the custom macro and the pre-configured attribute definition, and uses the custom macro to encapsulate the pre-configured attribute definition into one or more assertion templates. By creating files / folders, the assertion generation process and the declaration process of the early assertion template and macro definition are completed, making the generation of assertions more convenient.

[0096] In a possible implementation manner, the isolation function of the power domain module is verified, and step S7 further includes: S711: Based on the assertion template, declare an isolation function check module corresponding to the power domain module in the initial configuration file.

[0097] S713: Generate a top-level module, and instantiate the isolation function check module in the top-level module.

[0098] S715: Bind the top-level module that instantiates the isolation function check module to the top level of the verification environment, so as to perform isolation function verification on the power domain module in the verification environment through the isolation function check module in the top-level module.

[0099] In this embodiment, the instantiation process of a module may refer to the process of creating and using a defined submodule in a top-level module. After the module is instantiated, an instance of the module may be obtained. This process allows designers to construct complex designs in a hierarchical manner by breaking down large designs into smaller, more manageable submodules. Generally speaking, the instantiation of a submodule can be regarded as a replica of the submodule, representing a certain functional structural unit, and different instances are independent of each other and can work in parallel.

[0100] In this embodiment, based on the one or more assertion templates generated above, the initial configuration file is supplemented with isolation function check assertions of each power domain module to generate an isolation function check module corresponding to the power domain module. At the same time, a top-level module containing all the generated assertions is defined, the isolation function check module is instantiated in the top-level module, and the top-level module is instantiated to form an instance. Then, the instantiated top-level module is bound to the top level of the verification environment, and the isolation function of the power domain module is verified through the isolation function check module. Optionally, during the verification process, the bind syntax can be used to bind the module instance containing the assertion to the top-level module of the design, and the assertion is executed during the simulation process to verify the correctness of the power domain module design.

[0101] The technical solution provided in this embodiment of the present application declares the isolation function check module corresponding to the power domain module based on the generated one or more assertion templates, and performs isolation function verification on the power domain module through the isolation function check module in a verification environment to verify the correctness of the power domain module design, so as to optimize the circuit design and make the low power consumption verification more complete.

[0102] In a possible implementation, the assertion template in step S7 also includes an error printing template, which is used to obtain specified information of the erroneous assertion when an assertion error occurs, and print the specified information in the simulation log according to a preset format; wherein the specified information is used to characterize at least one of the assertion type, the power domain module to which the assertion belongs, the target isolation function verification signal of the error, the expected assertion value, and the actual signal value, so as to print out the erroneous assertion to facilitate problem troubleshooting.

[0103] Specifically, the specified information of the error assertion is obtained and printed in the simulation log according to the preset format. The preset format is not limited in this application. Optionally, it can be printed in the following manner: $display("assertion type: independent power domain module, corresponding signal, expected value, actual value"), where display represents the instruction to display and print. After mounting the above assertions in the simulation environment and simulating, all error assertions are filtered out, and all printed specified information is stored in a list. Optionally, it can be stored in the following manner: {'the name of the module when it is instantiated'; 'a list composed of error statements belonging to the module as elements'}. In this way, clear information can be provided for the error signal.

[0104] Please refer to Figure 7 The present application provides an embodiment of applying the above-mentioned isolation function verification method, and the embodiment is performed according to the following steps: Step 1: Collect relevant information about the power domain module to be tested. The relevant information can be recorded in a CSV table.

[0105] The relevant information includes, but is not limited to: the path of the RTL file where the module is located (for example, the path of the first RTL file mentioned above), the path of the RTL file of the previous level that instantiates the module (for example, the path of the second RTL file mentioned above), the isolation function control signal of the module, the power-on and power-off control signals of the module, the reset control signal of the module, the name of the module when it is instantiated, the hierarchical index of the previous level when the module is instantiated, the port type of the module isolation function, and the UPF file path corresponding to the module. The hierarchical information is represented by the RTL file.

[0106] Step 2: Write a script and read the table in a script to generate relevant assertions. The assertion generation process can be implemented according to four components, including: process control component, UPF file analysis component, RTL file analysis component, assertion generation component, and log analysis component.

[0107] Start the process control component to extract the table content and pass key information to subsequent components. First, create a top-level folder to store all files generated by this script run. In the directory of the top-level folder, create a new file with an extension of .flist as an assertion index file, for example, named all_assert_dir.flist. This file will record the index path of all assertion files generated subsequently. Then, in the directory of the top-level folder, create a new file with an extension of .sv as an initialization configuration file, for example, named isolate_signal_assert.sv. This file is used to declare macro definitions and attribute definitions that will be used later. Among them, the macro definition includes the hierarchical index of the RTL file, and the property definition includes the assertion type index. For example, the property definition can be used as the property definition, and the property definition includes three types of assertion type indexes, namely: after the isolation function is enabled, check whether the isolation value of the target isolation function verification signal is the same as the isolation value declared in the isolation definition information; after the isolation function control signal is enabled, the power-on control signal of the power domain module is enabled and the reset signal takes effect, check whether the isolation value of the target isolation function verification signal is the same as the reset value; after the isolation function control signal is enabled and the power domain module is powered off, check whether the internal port signal of the power domain module is in an indeterminate state. Among them, the isolation definition information is represented by the UPF file, and the target isolation function verification signal is the target internal port signal that meets the isolation signal type. The isolation signal type includes but is not limited to the input type and the output type. The target internal port signal is the internal port signal included in the RTL file of the module. Based on these three assertion types, they are encapsulated into three assertion templates using macro definitions, and the corresponding three assertions can be generated by inputting signal identifiers. Subsequently, in the directory of the top-level folder, a new assertion folder of the current power domain module is created, and a new debug file isolate_debug_file.log and a macro definition file isolate_signal_assert.sv are created in the assertion folder.

[0108] Start the UPF file parsing component to extract the isolation definition information of the current power domain module in the UPF file. Specifically, get the path of the UPF file from the above CSV table, open the file, delete all lines starting with '#', and locate the isolation definition statement according to the keyword 'set_isolation'. Extract the isolation definition information contained in the isolation definition statement through syntax keywords and output it in the form of a dictionary. The output format is, for example: {'name': isolation definition name, 'clamp_value': isolation value of isolation definition, 'signal_list': a list of signal names that the isolation definition acts on, 'isolation_sense': the value of the isolation enable signal when isolation takes effect}.

[0109] Start the RTL file parsing component to identify the target internal port signal targeted by the isolation definition information. Specifically, obtain the path of the module RTL file from the above CSV table and open the file, that is, the first RTL file, delete all lines starting with '#', obtain the module identifier of the module according to the keyword 'module', obtain the path of the RTL file of the module of the previous level of the module from the above CSV table and open the file, that is, the second RTL file, find the instantiation location of the module according to the obtained module identifier of the module and the name of the module after instantiation in the CSV table. According to the line where the instantiation location is found in the RTL file of the previous level module, the signal connection relationship of the module is obtained backward, and whether it is a line containing a signal connection relationship is determined by judging whether it starts with '.', and these lines containing signal connection relationships are stored in a list and processed, and a dictionary in the format of {"port signal name in the module":"signal name outside the module"} is output as signal mapping information, and the signal mapping information is stored in the debug file rtl_debug_file.log. According to the port type of the module isolation function in the CSV table, the internal port signals in the first RTL file are screened, and all target internal port signals defined by the port type are found, and the signal names of these target internal port signals are output as a list and stored in the debug file. The signal mapping information in the debug file is traversed, and the target internal port signals in the debug file list are matched to determine the signal mapping information of the target isolation function verification signal, and it is output as a new dictionary for the generation of subsequent assertions, for example: {"Isolation value 1": "Isolation signal list corresponding to the isolation value", "Isolation value 2": "Isolation signal list corresponding to the isolation value", ...}. Among them, if the isolation signal type is an output signal, mapping processing is required, and the target external signal after mapping processing of the target internal port signal is used as the target isolation function verification signal; if the isolation signal type is an input signal, mapping processing is not required. Specifically, please refer to the implementation method of the mapping processing in step S5.

[0110] Start the assertion generation component, and use three predefined assertion templates to construct assertions for the signals in the output dictionary. Specifically, according to the assertion template and the content filled in the CSV table, three types of assertions are constructed for the target isolation function verification signal in the above output dictionary, and these assertions are written into three different assertion files, for example: the three assertion files are saved as name_iso_assert.sv, name_iso_assert_reset_check.sv and name_iso_x_check.sv, respectively, and stored in the assertion folder. Among them, the "name" in the above example can be flexibly changed according to the needs of the actual application scenario, and it does not mean that the technical solution of the present application can only use "name" as the name of the assertion file. The names of the three assertion files in the above example respectively represent: isolation assertion name, reset isolation assertion name and indeterminate state detection isolation assertion name.

[0111] Step 3: Integrate the generated assertions into the RTL+UPF simulation environment to perform the corresponding functional tests. The simulation at the RTL+UPF stage can efficiently and correctly implement the visual detection of the correctness of the isolated functions and analyze the error information.

[0112] Specifically, after obtaining the three types of assertions, configure the simulation environment, which can be a simulation environment that uses RTL and UPF files to simulate hardware design. Perform the assertion integration process, for example: instantiate the module containing the assertion, use the bind statement to bind the assertion module to the top-level module of the RTL design, that is, the isolate_assertion_all (all isolation assertion) module, start the simulation after completing the configuration, and verify the isolation function of the power domain module to be tested in the simulation environment to optimize the circuit design.

[0113] Step 4: Start the log analysis component, filter all error assertions and process the corresponding information into a highly readable file format. Specifically, when an assertion fails, the specific error information of the assertion will be printed in the simulation log, for example: $display("assertion type: independent power domain, corresponding signal, expected value, actual value"). Input the simulation log and the CSV table containing module information into the log analysis component, and the component will perform the following operations: read the "name of the module instantiated" in the CSV table and store it in List A; read the specific information printed by the non-repeated error assertion in the simulation log and store it in List B; match the name of the "independent power domain" in the error information in List B with the module instantiation name in List A. If they are exactly the same, use the dictionary format to associate the error of each independent power domain with the independent power domain name, for example: {name of the module when instantiated: a list composed of error statements belonging to the module}, and write this dictionary into a table file with the extension of '.csv'. By opening this file, you can easily analyze the error problem.

[0114] In this embodiment, the UPF and RTL files are directly processed by the script, and there is no need to manually collect the isolation signal information, which can reduce errors and improve reliability. In addition, this embodiment provides an analysis file for the error assertion, which can automatically filter out all the related assertions of the error. On the other hand, this embodiment can automatically update the table, regenerate the check assertion of the isolation function, speed up the verification convergence speed of the UPF, and this embodiment can automatically generate three types of check assertions to make the low-power verification more complete.

[0115] See also Figure 8 The present application provides a verification device for an isolation function, the verification device is communicatively connected to a chip to be tested, the chip to be tested includes a power domain module for an isolation function to be verified, and the verification device is used to implement the aforementioned verification method for an isolation function.

[0116] See also Fig. 9 The present application also provides a verification system for an isolation function, the verification system includes a verification device and a chip to be tested, the verification device is communicatively connected to the chip to be tested, and the chip to be tested includes a power domain module for the isolation function to be verified.

[0117] The verification system provided in the embodiment of the present application includes the verification device provided in the aforementioned embodiment, and the verification method of the aforementioned isolation function is run in the verification device, so it has the same technical effect as the aforementioned embodiment. For details, please refer to the specific description of the aforementioned embodiment.

[0118] In one embodiment, the above verification device may include one or more processors (or processing circuits) configured to implement the above method, a memory, and a computer program stored in the memory, for implementing any of the above methods. Among them, the processor can be selected as: CPU (Central Processing Unit, Central Processing Unit), GPU (Graphics Processing Unit, Graphics Processing Unit), NPU (Neural Network Processing Unit, Neural Network Processing Unit), TPU (Tensor Processing Unit, Tensor Processing Unit), DPU (Deep Learning Processing Unit, Deep Learning Processor), microprocessor, DSP (Digital Signal Processor, Digital Signal Processor), ASIC (Application Specific Integrated Circuit, Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array, Field Programmable Gate Array), or a combination of at least two of these processor forms. The memory stores instructions that can be executed by at least one processor, and the type of the at least one processor can be different, for example, including CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc. The computer program can be written in Python language, and can also be written in other programming languages, including but not limited to Python, Perl, Tcl.

[0119] In one embodiment, the processor is a circuit with signal processing capability. In one implementation, the processor may be a circuit with instruction reading and execution capability, such as a CPU, microprocessor, GPU, or DSP. In another implementation, the processor may implement certain functions through the logical relationship of a hardware circuit, and the logical relationship of the hardware circuit may be fixed or reconfigurable, such as a hardware circuit implemented by an ASIC or PLD, such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document to implement the hardware circuit configuration may be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. In addition, it may also be a hardware circuit designed for artificial intelligence, which may be understood as an ASIC, such as an NPU, TPU, DPU, etc.

[0120] Some embodiments of the present application provide a method, device and system for verifying an isolation function, which reads a script file, generates an assertion according to the script file, performs a series of processing on the RTL file and the UPF file, obtains a target isolation function verification signal, and uses a template assertion to generate a corresponding assertion for verifying the power domain module of the isolation function to be verified of the chip to be tested. In addition, the assertion can also be mounted in a simulation environment to perform isolation function testing, and output the print information of the error assertion.

[0121] Therefore, this solution does not require manual collection of isolation information, reduces human errors, and improves the reliability and efficiency of assertion generation, so as to achieve automatic and efficient generation of check assertions for chip verification.

[0122] The embodiment of the present application also provides a computer-readable storage medium. The above method according to the embodiment of the present application can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0123] The embodiment of the present application provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method of any embodiment of the present application.

[0124] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

[0125] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0126] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0127] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0128] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0129] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0130] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0131] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0132] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for verifying an isolation function, characterized in that: The method is applied to a chip to be tested, wherein the chip to be tested includes a power domain module whose isolation function is to be verified, and the method includes: Acquire hierarchical structure information of the power domain module in the chip under test, wherein the hierarchical structure information is at least used to characterize internal port signals of the power domain module and signal mapping information of the power domain module in an upper-level module; Determining isolation definition information of the power domain module, and identifying an isolation signal type from the isolation definition information; Determine the target internal port signal corresponding to the isolated signal type in the hierarchical structure information, and determine whether to perform mapping processing on the target internal port signal based on the signal mapping information according to the isolated signal type; For the target isolation function verification signal represented by the judgment result, at least one assertion of the target isolation function verification signal is generated, and the isolation function of the power domain module is verified based on the generated assertion.

2. The method according to claim 1, characterized in that: Acquiring the hierarchical structure information of the power domain module in the chip under test includes: Determine a first RTL file path of the power domain module, and determine a second RTL file path of the upper-level module; Reading a first RTL file under the first RTL file path and a second RTL file under the second RTL file path; In the first RTL file, identifying a module identifier of the power domain module and acquiring an internal port signal of the power domain module; Based on the module identifier, the instantiation location of the power domain module is determined in the second RTL file, and according to the instantiation location, the signal mapping information of the power domain module in the upper-level module is obtained from the second RTL file.

3. The method according to claim 2, characterized in that In the first RTL file, the module identifier for identifying the power domain module includes: The line information containing the specified keyword is screened out from the non-comment lines of the first RTL file, and the formatting characters in the line information are removed to obtain the module identifier of the power domain module.

4. The method according to claim 2, characterized in that: Based on the module identifier, determining the instantiation location of the power domain module in the second RTL file includes: In the second RTL file, searching for a target row with the module identifier as starting information; Detect whether the target row contains the instantiation identifier of the power domain module in the upper-level module. If so, determine the position of the target row as the instantiation position of the power domain module; if not, query the next target row with the module identifier as the starting information.

5. The method according to claim 2 or 4, characterized in that: According to the instantiation position, acquiring the signal mapping information of the power domain module in the upper-level module from the second RTL file includes: Starting from the instantiation position, searching the second RTL file for a candidate line containing a first specified symbol; From each of the candidate rows, the module internal port signals and the module external signals having a mapping relationship are read, and the read module internal port signals and the module external signals having a mapping relationship are converted into signal mapping information in a specified data format.

6. The method according to claim 1, characterized in that Determining the isolation definition information of the power domain module includes: reading a UPF file of the power domain module, and searching for a starting line containing a specified string in a non-comment line of the UPF file, wherein the specified string is used to represent the setting of the isolation definition information; Starting from the start line, detecting whether the end of each line carries a second specified symbol, and determining the end line of the isolation definition information based on the detection result; According to the start line and the end line, the isolation definition information of the power domain module is extracted from the UPF file.

7. The method according to claim 1, characterized in that Determining the target internal port signal corresponding to the isolated signal type in the hierarchical structure information includes: Among the internal port signals of the power domain module represented by the hierarchical structure information, the internal port signals defined by the isolation signal type are screened out, and the screened out internal port signals are used as target internal port signals corresponding to the isolation signal type.

8. The method according to claim 1 or 7, characterized in that: The signal mapping information represented by the hierarchical structure information includes one or more groups of signal key-value pairs, the keys in the signal key-value pairs are used to represent the internal port signals of the power domain module, and the values ​​in the signal key-value pairs are used to represent the external signals connected to the internal port signals; After determining the target internal port signal corresponding to the isolated signal type in the hierarchical structure information, the method further includes: In the one or more groups of signal key-value pairs, the signal key-value pairs whose keys are the target internal port signals are screened out, and the screened signal key-value pairs are used as signal mapping information for mapping processing.

9. The method according to claim 1, characterized in that: Determining whether to perform mapping processing on the target internal port signal based on the signal mapping information includes: If the isolation signal type represents the input signal type, it is determined that no mapping processing is required, and the target internal port signal is used as the target isolation function verification signal represented by the judgment result; If the isolation signal type represents the output signal type, it is determined that mapping processing is required, and the target external signal after the mapping processing of the target internal port signal is used as the target isolation function verification signal represented by the judgment result.

10. The method according to claim 1, characterized in that Generating at least one assertion of the target isolation function verification signal includes: Reading a pre-generated assertion template, where the assertion template is obtained by encapsulating a pre-configured attribute definition by a custom macro, where the attribute definition is used to characterize a detection strategy for assertions in different scenarios; The signal identifier of the target isolation function verification signal is used as a parameter of the assertion template to generate at least one assertion of the target isolation function verification signal through the assertion template.

11. The method according to claim 10, characterized in that The assertion template also includes an error printing template, which is used to obtain specified information of the erroneous assertion when an assertion error occurs, and print the specified information in the simulation log according to a preset format; wherein the specified information is used to characterize at least one of the assertion type, the power domain module to which the assertion belongs, the target isolation function verification signal of the error, the expected assertion value, and the actual signal value.

12. The method according to claim 1 or 10, characterized in that: Assertions generated for validation of the target isolation functionality include at least one of the following: After the isolation function control signal is enabled, check whether the isolation value of the target isolation function verification signal is the same as the isolation value declared in the isolation definition information; or After the isolation function control signal is enabled, the power-on control signal of the power domain module is enabled, and the reset signal takes effect, check whether the isolation value and reset value of the target isolation function verification signal are the same; or After the isolation function control signal is enabled and the power domain module is powered off, check whether the internal port signal of the power domain module is in an unstable state.

13. The method according to claim 10, characterized in that The assertion template is generated as follows: Create a top-level folder; Creating an initial configuration file in the top-level folder, and writing the custom macro and the pre-configured property definition into the initial configuration file; In the initial configuration file, the pre-configured property definition is encapsulated into one or more assertion templates using the custom macro.

14. The method according to claim 13, characterized in that The method further comprises: Based on the assertion template, declaring the isolation function check module corresponding to the power domain module in the initial configuration file; generating a top-level module, and instantiating the isolation function check module in the top-level module; The top-level module in which the isolation function check module is instantiated is bound to the top level of the verification environment, so that the isolation function of the power domain module is verified in the verification environment through the isolation function check module in the top-level module.

15. The method according to claim 13, characterized in that After creating the top-level folder, the method further includes: Create an assertion index file in the top-level folder; Creating an assertion folder corresponding to the power domain module in the top-level folder, and adding an index path of the assertion folder to the assertion index file; At least one assertion file generated for the power domain module is written into the assertion folder, wherein different assertions are represented by different assertion files established in the assertion folder.

16. The method according to claim 15, characterized in that The method further comprises: Creating a debugging file in the assertion folder, wherein the debugging file records at least one of the following information: the signal mapping information, the target internal port signal corresponding to the isolation signal type, and the adaptation information between the isolation value and the target isolation function verification signal; A macro definition file is created in the assertion folder, wherein if a macro definition exists for a signal bit width in the generated assertion, a macro definition corresponding to the signal bit width is declared in the macro definition file.

17. A verification device for isolation function, characterized in that: The verification device is communicatively connected to the chip to be tested, and the chip to be tested includes a power domain module with an isolation function to be verified. The verification device is used to implement the verification method for the isolation function as described in any one of claims 1 to 16.

18. A verification system for isolation function, characterized in that: It comprises a verification device and a chip to be tested; the verification device is communicatively connected with the chip to be tested, the chip to be tested comprises a power domain module of an isolation function to be verified, and the verification device is used to implement the verification method of the isolation function as described in any one of claims 1 to 16.

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