Debugging sampling waveform centralized storage method and system based on RDMA technology

Abstract

The invention discloses a debugging sampling waveform centralized storage method and system based on an RDMA technology, and the method comprises the steps: enabling a DUT with a debugging sampling module to be divided and mapped on different available simulation acceleration carriers for operation, and enabling each carrier to directly or indirectly access a debugging private network; the debugging sampling module comprises an RDMA controller; the debugging host configures and manages a debugging sampling module in the simulation acceleration carrier through a debugging special network; a simulation debugging sampling module is started, and signals transmitted across the simulation acceleration carrier are communicated through a simulation interconnection network and wait for triggering; when a trigger signal is received, a sampling process is triggered, and a waveform signal is stored in a waveform memory bank in a network through an RDMA technology; and the simulation server remotely reads the waveform data from the waveform memory bank through the debugging sampling network based on the RDMA technology. The isolation between the waveform storage and reading process and simulation verification is realized, and the infinite expandability of the waveform storage capacity is also realized.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic design automation, and in particular relates to a centralized storage method and system for debugging sampling waveforms based on RDMA technology. Background Art

[0002] With the improvement of chip manufacturing technology and the mature application of stacked 3D packaging technology, the scale of chips is increasing. At present, the scale of DGX B200 chip has reached 208 billion transistors, which is equivalent to 50 billion logic gates, based on the average of 4 transistors per logic gate. The simulation scale of a single FPGA (AMD Xilinx VU19P) is calculated as 50 million logic gates, and the resource utilization rate is 70%, then 1,500 FPGAs are needed to realize the simulation verification of the chip design. The continuous trend of increasing chip scale has brought greater challenges to the scale and performance of the simulation verification environment required for chip verification. There is an urgent need for a simulation verification environment with sustainable scale expansion, higher simulation performance, and stronger debugging capabilities to support the verification before chip tape-out, so that the verification process is efficient and sufficient enough to discover design problems in advance and reduce the risk of tape-out failure.

[0003] In the existing hardware simulation verification system, as the simulation scale is improved, the storage and reading process of the debugging sampled waveform takes a long time due to the huge amount of data, which affects the performance of the hardware simulation verification system and also poses a challenge to the storage capacity. The waveform data transmission capability during the debugging process often becomes a performance bottleneck, and the contradiction between the transmission bandwidth and the large amount of waveform transmission data has become an urgent problem to be solved. In view of this problem, the present invention proposes a method and system for centralized storage of debugging sampled waveforms based on RDMA technology. Summary of the invention

[0004] In view of the above technical problems, the present invention provides a method and system for centralized storage of debugging sampled waveforms based on RDMA technology.

[0005] The technical solution adopted by the present invention to solve the technical problem is:

[0006] A centralized storage method for debugging sampled waveforms based on RDMA technology, the method comprising the following steps:

[0007] S100: All simulation acceleration carriers are connected to the simulation interconnection network, and the simulation server obtains available simulation acceleration carrier resources in the network by managing and configuring the network;

[0008] S200: Read and compile the DUT design to be verified, and map the DUT with the debugging sampling module to run on different available simulation acceleration carriers, each carrier is directly or indirectly connected to the debugging dedicated network; the debugging sampling modules of the divided blocks communicate with each other through the physical connection between multiple high-speed SerDes ports of the simulation acceleration carrier; wherein the debugging sampling module includes an RDMA controller;

[0009] S300: The debugging host configures and manages the debugging sampling module in the simulation acceleration carrier through the debugging dedicated network;

[0010] S400: Start the simulation debugging sampling module, and the signal transmitted across the simulation acceleration carrier communicates through the simulation interconnection network and waits for a trigger; when the trigger signal is received, the sampling process is triggered to sample the internal signal state of the DUT to be verified, and the waveform signal is stored in the waveform storage body in the network through the RDMA technology;

[0011] S500: The simulation server remotely reads waveform data from the waveform storage body through the debugging sampling network based on the RDMA technology.

[0012] Preferably, S100 includes:

[0013] All simulation acceleration carriers are connected to the simulation interconnection network. The simulation server checks the system status by managing the configuration network. The system status includes the number of all simulation acceleration carriers in the network and their working status. When the working status of the simulation acceleration carrier is idle, it is an available simulation acceleration carrier resource, and then obtains the available simulation acceleration carrier resources in the network.

[0014] Preferably, S200 includes:

[0015] S110: DUT design is described using HDL language, and after synthesis, a logic netlist is obtained, which includes complete resource information and communication information;

[0016] S120: Divide and map the DUT design to be verified according to the resource information and the communication information, the total amount of resources in each divided block does not exceed the resource threshold that can be provided by the corresponding simulation acceleration carrier, and the communication volume is lower than the preset threshold.

[0017] Preferably, the simulation acceleration carrier in S100 includes an FPGA chip and a simulation-specific ASIC chip.

[0018] Preferably, S300 specifically includes:

[0019] The debugging host sets the trigger conditions, selects the debugging probe, and uses the debugging signal window and depth through the debugging dedicated network.

[0020] Preferably, the trigger in S400 is set to a conditional trigger mode or a forced trigger mode. In the conditional trigger mode, once the trigger condition is met, the sampling process is triggered, and the sampled waveform data is stored in the waveform storage body in the network through the RDMA technology; in the forced trigger mode, once it is started, sampling is performed, and the sampled waveform data is stored in the waveform storage body in the network through the RDMA technology.

[0021] Preferably, the storage device in S500 includes a storage server, a disk array and a distributed storage body.

[0022] The debugging sampling waveform centralized storage system based on RDMA technology includes a simulation acceleration carrier, a simulation interconnection network, a debugging dedicated network, a debugging sampling network, a management configuration network, a debugging host, a waveform storage body and a simulation server.

[0023] All simulation acceleration carriers are connected to the simulation interconnection network, and the simulation server obtains the simulation acceleration carrier resources available in the network by managing and configuring the network;

[0024] The simulation server reads and compiles the DUT design to be verified, and maps the DUT with the debugging sampling module to run on different available simulation acceleration carriers. Each carrier is directly or indirectly connected to the dedicated debugging network. The debugging sampling modules of the partition blocks communicate with each other through the physical connection between multiple high-speed SerDes ports of the simulation acceleration carrier.

[0025] The debugging host configures and manages the debugging sampling module in the simulation acceleration carrier through the debugging dedicated network;

[0026] The simulation server starts the simulation debugging sampling module, and the signal transmitted across the simulation acceleration carrier communicates through the simulation interconnection network and waits for triggering; when the trigger signal is received, the sampling process is triggered to sample the internal signal state of the DUT to be verified, and the waveform signal is stored in the waveform storage body in the network through the RDMA technology;

[0027] The simulation server remotely reads waveform data from the waveform storage body through the debugging sampling network based on RDMA technology.

[0028] The above-mentioned debugging sampled waveform centralized storage method and system based on RDMA technology innovatively proposes debugging waveform storage and reading technology based on RDMA, stores the debugging sampled waveform data in a storage body in the network, and the debugging host reads the waveform data through RDMA, thereby realizing the isolation of the waveform storage and reading process from the simulation verification, and also realizing the unlimited scalability of the waveform storage capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1It is a flow chart of a centralized storage method for debugging sampled waveforms based on RDMA technology in one embodiment of the present invention;

[0030] Figure 2 This is a structural diagram of a centralized storage system for debugging sampled waveforms based on RDMA technology in one embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings.

[0032] In one embodiment, Figure 1 As shown, a centralized storage method for debugging sampling waveforms based on RDMA technology includes the following steps:

[0033] S100: All simulation acceleration carriers are connected to the simulation interconnection network, and the simulation server obtains available simulation acceleration carrier resources in the network by managing and configuring the network;

[0034] S200: Read and compile the DUT design to be verified, and map the DUT with the debugging sampling module to run on different available simulation acceleration carriers, each carrier is directly or indirectly connected to the debugging dedicated network; the debugging sampling modules of the divided blocks communicate with each other through the physical connection between multiple high-speed SerDes ports of the simulation acceleration carrier; wherein the debugging sampling module includes an RDMA controller;

[0035] S300: The debugging host configures and manages the debugging sampling module in the simulation acceleration carrier through the debugging dedicated network;

[0036] S400: Start the simulation debugging sampling module, and the signal transmitted across the simulation acceleration carrier communicates through the simulation interconnection network and waits for a trigger; when the trigger signal is received, the sampling process is triggered to sample the internal signal state of the DUT to be verified, and the waveform signal is stored in the waveform storage body in the network through the RDMA technology;

[0037] S500: The simulation server remotely reads waveform data from the waveform storage body through the debugging sampling network based on the RDMA technology.

[0038] Specifically, RDMA, or Remote Direct Memory Access, is a technology that bypasses the OS kernel of a remote host to access data in its memory. The concept is derived from DMA technology. In DMA technology, external devices (PCIe devices) can bypass the CPU and directly access the host memory; while RDMA means that external devices can bypass the CPU and can not only access the memory of the local host, but also the user-mode memory on another host. Since it does not go through the operating system, it not only saves a lot of CPU resources, but also improves system throughput and reduces the system's network communication latency. It has been widely used in high-performance computing and deep learning training.

[0039] The debugging sampling module includes an RDMA controller, which can remotely access the storage body in the network through the debugging dedicated network, so as to actively store the sampling data collected by the debugging sampling module into the storage body in the network.

[0040] The above-mentioned debugging sampled waveform centralized storage method and system based on RDMA technology innovatively proposes debugging waveform storage and reading technology based on RDMA, stores the debugging sampled waveform data in a storage body in the network, and the debugging host reads the waveform data through RDMA, thereby realizing the isolation of the waveform storage and reading process from the simulation verification, and also realizing the unlimited scalability of the waveform storage capacity.

[0041] In one embodiment, S100 includes:

[0042] All simulation acceleration carriers are connected to the simulation interconnection network. The simulation server checks the system status by managing the configuration network. The system status includes the number of all simulation acceleration carriers in the network and their working status. When the working status of the simulation acceleration carrier is idle, it is an available simulation acceleration carrier resource, and then obtains the available simulation acceleration carrier resources in the network.

[0043] Specifically, the management configuration server checks the system status, including the number of all simulation acceleration carriers in the network and their working status, through the management configuration network, and obtains available simulation acceleration carrier resources in the network.

[0044] In one embodiment, S200 includes:

[0045] S110: DUT design is described using HDL language, and after synthesis, a logic netlist is obtained, which includes complete resource information and communication information;

[0046] S120: Divide and map the DUT design to be verified according to the resource information and the communication information, the total amount of resources in each divided block does not exceed the resource threshold that can be provided by the corresponding simulation acceleration carrier, and the communication volume is lower than the preset threshold.

[0047] Specifically, DUT (Design Under Test) refers to the ASIC design that the user wants to simulate and verify using a prototype verification system, and to verify whether the design's functions meet its design specifications through simulation. The user design to be verified (DUT) is mapped to the simulation acceleration carrier and run to verify whether the design's functions and performance meet expectations. A typical scenario is that the DUT is relatively large, and one simulation acceleration carrier cannot accommodate the complete DUT design. In this case, the DUT needs to be divided into multiple partitions, which are mapped to different simulation acceleration carriers in the system. The debugging sampling modules of the partitions need to communicate through the physical connections between the simulation acceleration carriers.

[0048] In one embodiment, the simulation acceleration carrier in S100 includes an FPGA chip and a simulation-specific ASIC chip.

[0049] Further, the high-speed SerDes port of the emulation acceleration carrier includes at least one of a GTH port, a GTX port, a GTY port, a GTP port, a GTZ port and a GTM port.

[0050] In one embodiment, S300 specifically includes:

[0051] The debugging host sets the trigger conditions, selects the debugging probe, and uses the debugging signal window and depth through the debugging dedicated network.

[0052] In one embodiment, the trigger in S400 is set to a conditional trigger mode or a forced trigger mode. In the conditional trigger mode, once the trigger condition is met, the sampling process is triggered, and the sampled waveform data is stored in the waveform storage body in the network through the RDMA technology; in the forced trigger mode, once it is started, sampling is performed, and the sampled waveform data is stored in the waveform storage body in the network through the RDMA technology.

[0053] In one embodiment, the storage device in S500 includes a storage server, a disk array, and a distributed storage body.

[0054] In one embodiment, Figure 2 As shown, the debugging sampling waveform centralized storage system based on RDMA technology includes a simulation acceleration carrier, a simulation interconnection network, a debugging dedicated network, a debugging sampling network, a management configuration network, a debugging host, a waveform storage body and a simulation server.

[0055] All simulation acceleration carriers are connected to the simulation interconnection network, and the simulation server obtains the simulation acceleration carrier resources available in the network by managing and configuring the network;

[0056] The simulation server reads and compiles the DUT design to be verified, and maps the DUT with the debugging sampling module to run on different available simulation acceleration carriers. Each carrier is directly or indirectly connected to the dedicated debugging network. The debugging sampling modules of the partition blocks communicate with each other through the physical connection between multiple high-speed SerDes ports of the simulation acceleration carrier.

[0057] The debugging host configures and manages the debugging sampling module in the simulation acceleration carrier through the debugging dedicated network;

[0058] The simulation server starts the simulation debugging sampling module, and the signal transmitted across the simulation acceleration carrier communicates through the simulation interconnection network and waits for triggering; when the trigger signal is received, the sampling process is triggered to sample the internal signal state of the DUT to be verified, and the waveform signal is stored in the waveform storage body in the network through the RDMA technology;

[0059] The simulation server remotely reads waveform data from the waveform storage body through the debugging sampling network based on RDMA technology.

[0060] Specifically, the hardware simulation verification system maps the user design to be verified (DUT) to a simulation carrier (such as an FPGA chip, a simulation-specific ASIC chip, etc.) to run to verify whether the functions and performance of the design meet expectations. During the simulation process, it is necessary to sample the internal signal state of the DUT under certain specific conditions. This process is called debug sampling. The schematic diagram of the centralized storage system for debug sampling waveforms proposed by the present invention based on RDMA technology is as follows: Figure 2 As shown, in the integrated circuit hardware simulation verification system, the simulation acceleration carrier (such as FPGA chip, simulation-specific ASIC chip, etc.), the debugging host, and the waveform storage body are connected to the debugging-specific network. The waveform data generated by the simulation acceleration carrier is stored in the waveform storage body through the debugging-specific network. The debugging host configures and manages the debugging sampling module in the acceleration carrier through the debugging-specific network, including trigger condition setting, debugging probe selection, debugging signal sampling window and depth, etc. After the trigger is completed, the debugging host reads the waveform data from the waveform storage body through the debugging-specific network. While the debugging host is reading the waveform data, the simulation process continues without interruption.

[0061] The present invention proposes to store the debugging sampled waveform data in a waveform storage body in the network based on the RDMA technology, which solves the problem of online real-time storage and reading of massive data, expands the boundary of the waveform storage capacity of the hardware simulation verification system, can realize unlimited storage of waveform data, and enhances the debugging capability of the hardware simulation verification system.

[0062] The above is a detailed introduction to the centralized storage method and system for debugging sampled waveforms based on RDMA technology provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A centralized storage method for debugging sampling waveforms based on RDMA technology, characterized in that: The method comprises the following steps: S100: All simulation acceleration carriers are connected to the simulation interconnection network, and the simulation server obtains available simulation acceleration carrier resources in the network by managing and configuring the network; S200: Read and compile the DUT design to be verified, and map the DUT with the debugging sampling module to run on different available simulation acceleration carriers, each carrier is directly or indirectly connected to the debugging dedicated network; the debugging sampling modules of the divided blocks communicate with each other through the physical connection between multiple high-speed SerDes ports of the simulation acceleration carrier; wherein the debugging sampling module includes an RDMA controller; S300: The debugging host configures and manages the debugging sampling module in the simulation acceleration carrier through the debugging dedicated network; S400: Start the simulation debugging sampling module, and the signal transmitted across the simulation acceleration carrier communicates through the simulation interconnection network and waits for a trigger; when the trigger signal is received, the sampling process is triggered to sample the internal signal state of the DUT to be verified, and the waveform signal is stored in the waveform storage body in the network through the RDMA technology; S500: The simulation server remotely reads waveform data from the waveform storage body through the debugging sampling network based on the RDMA technology.

2. The method according to claim 1, characterized in that S100 includes: All simulation acceleration carriers are connected to the simulation interconnection network. The simulation server checks the system status by managing the configuration network. The system status includes the number of all simulation acceleration carriers in the network and their working status. When the working status of the simulation acceleration carrier is idle, it is an available simulation acceleration carrier resource, and then obtains the available simulation acceleration carrier resources in the network.

3. The method according to claim 1, characterized in that S200 includes: S110: DUT design is described using HDL language, and after synthesis, a logic netlist is obtained, which includes complete resource information and communication information; S120: Divide and map the DUT design to be verified according to the resource information and the communication information, the total amount of resources in each divided block does not exceed the resource threshold that can be provided by the corresponding simulation acceleration carrier, and the communication volume is lower than the preset threshold.

4. The method according to claim 3, characterized in that The simulation acceleration carrier in S100 includes FPGA chip and simulation-specific ASIC chip.

5. The method according to claim 4, characterized in that S300 is specifically: The debugging host sets the trigger conditions, selects the debugging probe, and uses the debugging signal window and depth through the debugging dedicated network.

6. The method according to claim 5, characterized in that The trigger in S400 is set to conditional trigger mode or forced trigger mode. In the conditional trigger mode, once the trigger condition is met, the sampling process is triggered, and the sampled waveform data is stored in the waveform storage body in the network through the RDMA technology; In the forced trigger mode, sampling is performed once it is started, and the sampled waveform data is stored in the waveform storage body in the network through the RDMA technology.

7. The method according to claim 6, characterized in that The storage devices in S500 include storage servers, disk arrays and distributed storage bodies.

8. A centralized storage system for debugging sampled waveforms based on RDMA technology, characterized in that: It includes simulation acceleration carrier, simulation interconnection network, debugging dedicated network, debugging sampling network, management configuration network, debugging host, waveform storage and simulation server. All simulation acceleration carriers are connected to the simulation interconnection network, and the simulation server obtains the simulation acceleration carrier resources available in the network by managing and configuring the network; The simulation server reads and compiles the DUT design to be verified, and maps the DUT with the debugging sampling module to run on different available simulation acceleration carriers. Each carrier is directly or indirectly connected to the dedicated debugging network. The debugging sampling modules of the partition blocks communicate with each other through the physical connection between multiple high-speed SerDes ports of the simulation acceleration carrier. The debugging host configures and manages the debugging sampling module in the simulation acceleration carrier through the debugging dedicated network; The simulation server starts the simulation debugging sampling module, and the signal transmitted across the simulation acceleration carrier communicates through the simulation interconnection network and waits for triggering; when the trigger signal is received, the sampling process is triggered to sample the internal signal state of the DUT to be verified, and the waveform signal is stored in the waveform storage body in the network through the RDMA technology; The simulation server remotely reads waveform data from the waveform storage body through the debugging sampling network based on RDMA technology.

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