Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel comprises a substrate and a light-emitting device layer arranged on one side of the substrate, and the light-emitting device layer comprises a first light-emitting device and a second light-emitting device; the display area comprises at least two sub display areas; a plurality of driving circuits are arranged in one sub-display area, and the driving circuits comprise a first driving circuit and a second driving circuit; the first driving circuit includes a first transistor and a first driving transistor. According to the invention, first poles of all first driving transistors are electrically connected with the same first power supply voltage signal line; and / or the grids of all the first transistors are electrically connected to the same first scanning signal line; and / or the second electrodes of all the first transistors are electrically connected with the same first data signal line, so that unified control over all the first driving circuits in the same sub-display area is facilitated, local control over the display panel is facilitated, power consumption of the display panel is reduced, and wiring is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of network technology, more and more users need to perform operations such as account transactions on display devices. However, when users perform the above operations in public, it is easy for personal information to be leaked when accessing bank accounts, paying bills or entering personal information. Therefore, display devices with anti-peeping functions have received more and more attention.

[0003] For the display panel, the whole-surface privacy protection has high power consumption requirements. Therefore, how to achieve local privacy protection control of the display panel to reduce the power consumption of the display panel has become one of the technical problems that need to be solved urgently at this stage. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device, which are used to implement local anti-peeping control of the display panel, thereby reducing the power consumption of the display panel.

[0005] In a first aspect, the present disclosure provides a display panel, comprising:

[0006] substrate;

[0007] A light emitting device layer, disposed on one side of the substrate, the light emitting device layer comprising a first light emitting device and a second light emitting device;

[0008] A display area, comprising the first light emitting device and the second light emitting device, and the display area comprises at least two sub-display areas;

[0009] The sub-display area includes M rows×N columns of driving circuits, M≥2, N≥2, and M and N are both integers, and the driving circuit includes a first driving circuit and a second driving circuit; the first driving circuit is used to drive the first light-emitting device to emit light; the second driving circuit is used to drive the second light-emitting device to emit light;

[0010] The first driving circuit includes a first transistor and a first driving transistor; in the same sub-display area, the first electrode of each of the first transistors is electrically connected to the gate of the corresponding first driving transistor; and,

[0011] The first electrodes of all the first driving transistors are electrically connected to the same first power supply voltage signal line; and / or, the gates of all the first transistors are electrically connected to the same first scanning signal line; and / or, the second electrodes of all the first transistors are electrically connected to the same first data signal line.

[0012] In a second aspect, based on the same inventive concept, the present disclosure provides a display device, comprising the display panel as described in the first aspect.

[0013] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0014] The present disclosure provides a display panel and a display device, wherein the display panel includes a substrate, a light-emitting device layer arranged on one side of the substrate, the light-emitting device layer includes a first light-emitting device and a second light-emitting device; the display area includes at least two sub-display areas; a sub-display area includes multiple driving circuits, the driving circuit includes a first driving circuit and a second driving circuit; the first driving circuit is used to drive the first light-emitting device to emit light; the second driving circuit is used to drive the second light-emitting device to emit light; the first driving circuit includes a first transistor and a first driving transistor; in the same sub-display area, the first electrode of each first transistor is electrically connected to the gate of the corresponding first driving transistor. The present disclosure is to set the first electrodes of all first driving transistors to be electrically connected to the same first power supply voltage signal line; and / or, the gates of all first transistors are electrically connected to the same first scanning signal line; and / or, the second electrodes of all first transistors are electrically connected to the same first data signal line. Such a setting is conducive to realizing unified control of all first driving circuits in the same sub-display area, thereby realizing unified control of the first light-emitting devices corresponding to the first driving circuits in the same sub-display area, that is, it is conducive to realizing local control of the display panel, thereby facilitating local anti-peeping of the display panel, reducing the power consumption of the display panel, and reducing wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 Shown is a schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0018] Figure 2 Shown is a schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure;

[0019] Figure 3 Shown is a schematic diagram of a film layer of another display panel provided by an embodiment of the present disclosure;

[0020] Figure 4 Shown is a schematic diagram of a sub-display area provided by an embodiment of the present disclosure;

[0021] Figure 5 FIG. 1 is a schematic diagram of a first driving circuit provided by an embodiment of the present disclosure;

[0022] Figure 6 Shown is a connection diagram of a first power supply voltage signal line provided by an embodiment of the present disclosure;

[0023] Figure 7 Shown is another connection schematic diagram of a first power supply voltage signal line provided by an embodiment of the present disclosure;

[0024] Figure 8 FIG. 1 is a schematic diagram showing a connection of another first power supply voltage signal line provided by an embodiment of the present disclosure;

[0025] Fig. 9 FIG. 1 is a connection diagram of a first scanning signal line provided by an embodiment of the present disclosure;

[0026] Fig.10 FIG. 2 is another schematic diagram of connecting first scanning signal lines provided by an embodiment of the present disclosure;

[0027] Fig.11 FIG. 1 is a schematic diagram showing a connection of another first scanning signal line provided by an embodiment of the present disclosure;

[0028] Fig.12 Shown is a connection diagram of a first data signal line provided by an embodiment of the present disclosure;

[0029] Fig.13 Shown is another connection schematic diagram of a first data signal line provided by an embodiment of the present disclosure;

[0030] Fig.14 FIG. 1 is a schematic diagram showing a connection of another first data signal line provided by an embodiment of the present disclosure;

[0031] Fig.15 Shown is a connection diagram of a third power supply voltage signal line provided by an embodiment of the present disclosure;

[0032] Fig.16 Shown is another connection schematic diagram of a third power supply voltage signal line provided by an embodiment of the present disclosure;

[0033] Fig.17 FIG. 1 is a schematic diagram of another first driving circuit provided by an embodiment of the present disclosure;

[0034] Fig.18 FIG. 1 is a schematic diagram of another first driving circuit provided by an embodiment of the present disclosure;

[0035] Fig.19 This disclosure is shown Fig.18 A timing diagram of a first driving circuit is provided;

[0036] Fig. 20 FIG. 1 is a schematic diagram of a second driving circuit provided by an embodiment of the present disclosure;

[0037] Fig.21 This disclosure is shown Fig. 20 A timing diagram of a second driving circuit is provided;

[0038] Fig. 22 FIG. 1 is a connection diagram of a second driving circuit provided by an embodiment of the present disclosure;

[0039] Fig.23 Shown is a schematic diagram of another sub-display area provided by an embodiment of the present disclosure;

[0040] Fig.24 Shown is a schematic diagram of another seed display area provided by an embodiment of the present disclosure;

[0041] Fig.25 Shown is a schematic diagram of another sub-display area provided by an embodiment of the present disclosure;

[0042] Fig.26 Shown is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0043] Fig. 27 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0044] Fig.28 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0045] Fig.29 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0046] Fig.30 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0047] Fig.31 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0048] Fig.32 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0049] Fig.33 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0050] Fig.34FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0051] Fig.35 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0052] Fig.36 Shown is a schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0054] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0055] The inventors discovered during their research that some anti-peeping display panels have high power consumption requirements when used for anti-peeping purposes. Therefore, how to improve local control of the display panel, achieve local anti-peeping, and thus reduce the power consumption of the display panel has become one of the technical problems that need to be solved urgently at this stage.

[0056] In view of this, the present disclosure provides a display panel and a display device, which are used to implement local anti-peeping control of the display panel, thereby reducing the power consumption of the display panel.

[0057] Figure 1 FIG. 1 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 2 FIG. 1 is a schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure. Figure 3 FIG. 1 is a schematic diagram of a film layer of another display panel provided in an embodiment of the present disclosure. Figure 4 FIG. 1 is a schematic diagram of a sub-display area provided in an embodiment of the present disclosure. Figure 5 FIG. 1 is a schematic diagram of a first driving circuit provided by an embodiment of the present disclosure. Please refer to FIG. Figure 1 to Figure 5 The present disclosure provides a display panel 100, comprising:

[0058] Substrate 00;

[0059] The light emitting device layer 30 is disposed on one side of the substrate 00 , and the light emitting device layer 30 includes a first light emitting device 31 and a second light emitting device 32 ;

[0060] The display area AA includes a first light emitting device 31 and a second light emitting device 32, and the display area AA includes at least two sub-display areas 10;

[0061] A sub-display area 10 includes M rows×N columns of driving circuits 20, M≥2, N≥2, and M and N are both integers, and the driving circuit 20 includes a first driving circuit 21 and a second driving circuit 22; the first driving circuit 21 is used to drive the first light-emitting device 31 to emit light; the second driving circuit 22 is used to drive the second light-emitting device 32 to emit light;

[0062] The first driving circuit 21 includes a first transistor T11 and a first driving transistor T10;

[0063] In the same sub-display area 10, the first electrode of each first transistor T11 is electrically connected to the gate of the corresponding first driving transistor T10; and,

[0064] The first electrodes of all first driving transistors T10 are electrically connected to the same first power supply voltage signal line PVDD1; and / or, the gates of all first transistors T11 are electrically connected to the same first scan signal line Scan1; and / or, the second electrodes of all first transistors T11 are electrically connected to the same first data signal line DATA1.

[0065] It should be noted that the drawings in this disclosure are for illustration only and do not represent the actual structure. Figure 1 The display panel 100 with a rectangular structure is only taken as an example for description, and the actual shape of the display panel 100 is not limited. In some embodiments of the present disclosure, the display panel 100 can also be embodied in any other feasible shape such as a circle, a rounded rectangle, etc.

[0066] For more information, see Figure 1 The present disclosure provides a display panel 100, the display panel 100 includes a display area AA, and the display area AA includes a first light emitting device 31 and a second light emitting device 32 ( Figure 1 ). Figure 2 The display panel 100 includes a substrate 00 and a light-emitting device layer 30. The light-emitting device layer 30 is located on one side of the substrate 00. The light-emitting device layer 30 includes a first light-emitting device 31 and a second light-emitting device 32. Optionally, the display panel 100 provided in this embodiment may be a display panel 100 using an organic light-emitting diode display technology, i.e., an OLED (Organic Light-Emitting Diode) display panel 100. Please continue to refer to Figure 2The first light-emitting device 31 and the second light-emitting device 32 have the same film structure, both including an anode 301, a light-emitting material layer 302 and a cathode 303. When the power supply provides an appropriate voltage, the holes in the anode 301 and the electrons in the cathode 303 will combine in the light-emitting material layer 302 and emit light. The display panel 100 also includes a pixel definition layer 34, which defines a plurality of pixel openings. The light-emitting material layer 302 is at least located in the pixel openings. In a direction perpendicular to the substrate 00, the anode 301 and the cathode 303 are respectively located on both sides of the light-emitting material layer 302, and the anode 301 is located on the side of the cathode 303 facing the substrate 00. Optionally, the display panel 100 also includes an encapsulation layer 50, which is located on the side of the cathode 303 away from the substrate 00. In some optional embodiments, the encapsulation layer 50 includes a first inorganic layer 51, a first organic layer 52 and a second organic layer 53 arranged in a stacked manner. The arrangement of the encapsulation layer 50 is conducive to preventing the light-emitting device layer 30 from being harmed by water vapor and the like, and protecting the light-emitting device layer 30.

[0067] Please refer to Figure 1 to Figure 4 The display area AA includes at least two sub-display areas 10, each of which includes a driving circuit 20. One sub-display area 10 includes M rows×N columns of driving circuits 20. Optionally, please refer to Figure 4 , a sub-display area 10 includes two rows of drive circuits 20 arranged along the second direction F2, and four columns of drive circuits 20 arranged along the first direction F1. It should be noted that this embodiment is only described by taking M=2 and N=4 as an example, and is not limited to this. The drive circuit 20 includes a first drive circuit 21 and a second drive circuit 22. The first drive circuit 21 is used to drive the first light-emitting device 31 to emit light, and the second drive circuit 22 is used to drive the second light-emitting device 32 to emit light. Please refer to Figure 2 The display panel 100 also includes a driving layer 40, in which a first driving circuit 21 and a second driving circuit 22 are provided to drive the first light-emitting device 31 and the second light-emitting device 32 to emit light. The first driving circuit 21 and the second driving circuit 22 respectively include a plurality of transistors. The specific circuit structure of the driving circuit 20 will be illustrated in the subsequent embodiments.

[0068] It can be understood that M can be selected from 2, 3, 4, 5, ..., N can be selected from 2, 3, 4, ... and when the length of the display panel 100 along the second direction F2 is greater than the length along the first direction F1, M≥N can also be achieved.

[0069] Please refer to Figure 4 and Figure 5The first driving circuit 21 includes a first transistor T11 and a first driving transistor T10. For each first driving circuit 21, the first electrode of the first transistor T11 is electrically connected to the gate of the first driving transistor T10, and the second electrode of the first driving transistor T10 is electrically connected to the anode of the first light emitting device 31. Figure 5 In the first driving circuit 21 shown, the first transistor T11 is turned on under the control of the first scanning signal line Scan1, and the first data signal transmitted by the first data signal line DATA1 is transmitted to the gate of the first driving transistor T10; the gate of the first driving transistor T10 receives the first data signal transmitted by the first transistor T11, and is turned on or off under the control of the first data signal. When the first driving transistor T10 is turned on, the first power supply voltage signal transmitted by the first power supply voltage signal line PVDD1 is transmitted to the anode of the first light-emitting device 31, and the first light-emitting device 31 emits light. It should be noted that this embodiment is only described by taking the first driving circuit 21 including the first transistor T11 and the first driving transistor T10 as an example, which does not mean that the first driving circuit 21 can only include the first transistor T11 and the first driving transistor T10. It should also be noted that Figure 4 Only the connection between the first transistor T11, the first driving transistor T10 and the first light emitting device 31 in the first driving circuit 21 is illustrated, and the connection of the first driving circuit 21 in the same sub-display area 10 will be described in subsequent embodiments.

[0070] Figure 6 FIG. 1 is a schematic diagram showing a connection of a first power supply voltage signal line provided in an embodiment of the present disclosure. Figure 7 FIG. 1 is a schematic diagram showing another connection of a first power supply voltage signal line provided in an embodiment of the present disclosure. Figure 8 FIG. 1 is a schematic diagram showing another connection of a first power supply voltage signal line provided in an embodiment of the present disclosure. Please refer to FIG. Figure 6 , Figure 6 A connection method between the first electrode of the first driving transistor T10 and the first power supply voltage signal line PVDD1 in the same sub-display area 10 is shown in the figure. The sub-display area 10 includes four first driving circuits 21, each of which includes a first driving transistor T10. The first electrode of each first driving transistor T10 is correspondingly provided with a first lead line 1, which is connected to the same first power supply voltage signal line PVDD1 through the first lead line 1. With such a configuration, a sub-display area 10 corresponds to only one first power supply voltage signal line PVDD1, which is beneficial to reducing the number of first power supply voltage signal lines PVDD1 required for the sub-display area 10 and simplifying the wiring structure of the display panel 100. It should be noted that Figure 6The first power supply voltage signal line PVDD1 is only shown as being located between the adjacent first drive circuit 21 and the second drive circuit 22, and is not intended to limit the specific location of the first power supply voltage signal line PVDD1. Figure 7 In another embodiment of the present disclosure, the first power supply voltage signal line PVDD1 includes a first power supply voltage signal main line segment PVDD11 and a first power supply voltage signal branch line segment PVDD12, and the first power supply voltage signal main line segment PVDD11 and the first power supply voltage signal branch line segment PVDD12 are electrically connected through a first power supply voltage signal connecting line PVDD1-c. In the same sub-display area 10, the first electrode of each first driving transistor T10 is connected to the first power supply voltage signal main line segment PVDD11 or the first power supply voltage signal branch line segment PVDD12 closest to it through a first lead-out line 1. In this arrangement, the first electrode of the first driving transistor T10 can be connected to the first power supply voltage signal line PVDD1 (the first power supply voltage signal main line segment PVDD11 or the first power supply voltage signal branch line segment PVDD12), which is beneficial to improving the signal transmission rate and reducing the voltage drop. At the same time, one sub-display area 10 only corresponds to one first power supply voltage signal line PVDD1, which is beneficial to reducing the number of first power supply voltage signal lines PVDD1 required for the sub-display area 10, thereby reducing the number of wiring introduced from outside the display area, which is beneficial to reducing the area of ​​the non-display area.

[0071] Please refer to Figure 8 In another embodiment of the present disclosure, the sub-display area 10 includes nine first drive circuits 21 in 3 rows×3 columns, the first power supply voltage signal line PVDD1 includes a first power supply voltage signal main line segment PVDD11 and two first power supply voltage signal branch line segments PVDD12, the first power supply voltage signal main line segment PVDD11 and the two first power supply voltage signal branch line segments PVDD12 are electrically connected through the first power supply voltage signal connection line PVDD1-c, and the first electrode of each first drive transistor T10 is connected to the first power supply voltage signal main line segment PVDD11 or the first power supply voltage signal branch line segment PVDD12 closest to it through the first lead-out line 1. In this way, the first electrode of the first drive transistor T10 can be connected to the first power supply voltage signal line PVDD1 nearby, which is conducive to reducing the voltage drop. At the same time, one sub-display area 10 corresponds to only one first power supply voltage signal line PVDD1, which is conducive to reducing the number of first power supply voltage signal lines PVDD1 required for the sub-display area 10, thereby reducing the number of wiring introduced from outside the display area, which is conducive to reducing the area of ​​the non-display area.

[0072] It should be noted that this disclosure is only Figure 6 to Figure 8The embodiment shown is used for illustration only and is not intended to be limiting. The design may be made according to actual products as long as the first electrodes of all first driving transistors T10 in the same sub-display area 10 are electrically connected to the same first power supply voltage signal line PVDD1 .

[0073] Fig. 9 FIG. 1 is a connection diagram of a first scanning signal line provided by an embodiment of the present disclosure. Fig.10 FIG. 1 is another schematic diagram of connecting first scanning signal lines provided by an embodiment of the present disclosure. Fig.11 FIG. 1 is a schematic diagram showing another connection of the first scanning signal line provided in an embodiment of the present disclosure. Please refer to FIG. Fig. 9 , Fig. 9 A connection method for the gate of a first transistor T11 in the same sub-display area 10 is shown. The sub-display area 10 includes four first drive circuits 21, each of which includes a first transistor T11. The first scan signal line Scan1 includes a first scan signal main line segment Scan11 and a first scan signal branch line segment Scan12. The first scan signal main line segment Scan11 and the first scan signal branch line segment Scan12 are electrically connected through a first scan signal connection line Scan1-c. The first transistor T11 in each first drive circuit 21 is connected to the nearest first scan signal main line segment Scan11 or first scan signal branch line segment Scan12 through a second lead-out line 2. In this way, the gates of all first transistors T11 in the same sub-display area 10 are electrically connected to the same first scan signal line Scan1, which is conducive to achieving unified control of all first transistors T11 in the same sub-display area 10, thereby facilitating unified control of the first light-emitting devices 31 in the same sub-display area 10.

[0074] Please refer to Fig.10 In another embodiment of the present disclosure, the sub-display area 10 includes 9 first drive circuits 21 in 3 rows×3 columns, the first scan signal line Scan1 includes a first scan signal main line segment Scan11, two first scan signal branch line segments Scan12 and a first scan signal connection line Scan1-c, each first scan signal branch line segment Scan12 is electrically connected to the first scan signal main line segment Scan11 through the first scan signal connection line Scan1-c, and the gate of each first transistor T11 is connected to the nearest first scan signal main line segment Scan11 or first scan signal branch line segment Scan12 through the second lead-out line 2. Please refer to Fig.11In another embodiment of the present disclosure, the first scan signal line Scan1 includes a first scan signal main line segment Scan11 and two first scan signal branch line segments Scan12, wherein the first scan signal branch line segments Scan12 are distributed on both sides of the first scan signal main line segment Scan11, the first scan signal branch line segments Scan12 are electrically connected to the first scan signal main line segment Scan11 through the first scan signal connecting line Scan1-c, and the gate of each first transistor T11 is connected to the nearest first scan signal main line segment Scan11 or the first scan signal branch line segment Scan12 through the second lead-out line 2. Fig.10 and Fig.11 In the illustrated embodiment, within the same sub-display area 10, the gate of the first transistor T11 is electrically connected to the first scan signal main line segment Scan11 or the first scan signal branch line segment Scan12. Finally, the gates of all the first transistors T11 within the same sub-display area 10 are electrically connected to the same first scan signal line Scan1. Such a configuration is conducive to achieving simultaneous control of all the first transistors T11 within the same sub-display area 10, thereby facilitating unified control of the first light-emitting devices 31 within the same sub-display area 10.

[0075] It should be noted that Figures 9 to 11 This is merely an illustration of an implementation in which the gate of the first transistor T11 in the same sub-display area 10 is electrically connected to the first scan signal line Scan1, but the present disclosure is not limited thereto. It is sufficient that the gates of all first transistors T11 in the same sub-display area 10 are electrically connected to the same first scan signal line Scan1.

[0076] Fig.12 FIG. 1 is a connection diagram of a first data signal line provided by an embodiment of the present disclosure. Fig.13 FIG. 1 is another schematic diagram of connecting first data signal lines provided by an embodiment of the present disclosure. Fig.14 FIG. 1 is a schematic diagram showing another connection of a first data signal line provided in an embodiment of the present disclosure. Please refer to FIG. Fig.12 , Fig.12 A connection method of the second electrode of the first transistor T11 in the same sub-display area 10 is shown. The sub-display area 10 includes 4 first drive circuits 21 in 2 rows×2 columns. The second electrode of each first drive circuit 21 is electrically connected to the first data signal line DATA1 through the third lead line 3. The second electrodes of all the first transistors T11 in the same sub-display area 10 are electrically connected to the same first data signal line DATA1. In this way, the same first data signal is transmitted to the second electrodes of all the first transistors T11 in the same sub-display area 10, which is conducive to the unified transmission of the first data signal in the same sub-display area 10, thereby facilitating the unified control of the first light-emitting devices 31 in the same sub-display area 10.

[0077] Please refer to Fig.13 In another embodiment of the present disclosure, the first data signal line DATA1 includes a first data signal main line segment DATA11 and a first data signal branch line segment DATA12, the first data signal main line segment DATA11 and the first data signal branch line segment DATA12 are electrically connected through a first data signal connecting line DATA1-c, and the second electrode of the first transistor T11 is connected to the first data signal main line segment DATA11 or the first data signal branch line segment DATA12 nearby, so that the second electrodes of all the first transistors T11 in the same sub-display area 10 are electrically connected to the same first data signal line DATA1, and the same first data signal is transmitted to the second electrodes of all the first transistors T11 in the same sub-display area 10, which is conducive to realizing the unified transmission of the first data signal in the same sub-display area 10, thereby facilitating the unified control of the first light-emitting devices 31 in the same sub-display area 10, and is also conducive to improving the uniformity of the brightness of the first light-emitting devices 31 in the same sub-display area 10.

[0078] Please refer to Fig.14 , in yet another embodiment of the present disclosure, Fig.14 A sub-display area 10 is shown, which includes 9 first driving circuits 21 in 3 rows×3 columns. The first data signal line DATA1 includes a first data signal main line segment DATA11 and two first data signal branch line segments DATA12. The first data signal branch line segments DATA12 are symmetrically distributed on both sides of the first data signal main line segment DATA11. The first data signal branch line segment DATA12 is electrically connected to the first data signal main line segment DATA11 through the first data signal connecting line DATA1-c. The second electrode of the first transistor T11 is connected to the nearest first data signal main line segment DATA11 or the first data signal branch line segment DATA12 through the third lead-out line 3. In the sub-display area 10, the second electrodes of all the first transistors T11 are connected to the same first data signal line DATA1, that is, one sub-display area 10 corresponds to one first data signal line DATA1, and the same first data signal is transmitted to the second electrodes of all the first transistors T11 in the same sub-display area 10, which is conducive to the unified transmission of the first data signal in the same sub-display area 10, thereby facilitating the unified control of the first light-emitting device 31 in the same sub-display area 10, and is also conducive to improving the uniformity of the brightness of the first light-emitting device 31 in the same sub-display area 10.

[0079] Understandably, Figure 12 to Figure 14In the illustrated embodiment, the second electrode of the first transistor T11 in the same sub-display area 10 is connected to the same first data signal line DATA1, and a sub-display area 10 only needs to introduce one first data signal line DATA1 from the non-display area, which is beneficial to reduce the number of first data signal lines DATA1 introduced into the display area, thereby reducing the area of ​​the non-display area and the number of binding pins in the binding area.

[0080] It should be noted that Figure 12 to Figure 14 The embodiment in which the second electrodes of the first transistors T11 in the same sub-display area 10 are connected to the first data signal line DATA1 is merely illustrative, but the present disclosure is not limited thereto, and it is sufficient that the second electrodes of all the first transistors T11 in the same sub-display area 10 are electrically connected to the same first data signal line DATA1.

[0081] It can be understood that the present disclosure is arranged in the same sub-display area 10, and the first electrodes of all the first driving transistors T10 are electrically connected to the same first power supply voltage signal line PVDD1; and / or, the gates of all the first transistors T11 are electrically connected to the same first scanning signal line Scan1; and / or, the second electrodes of all the first transistors T11 are electrically connected to the same first data signal line DATA1. Such an arrangement is conducive to achieving unified control of all the first driving circuits 21 in the same sub-display area 10, thereby achieving unified control of the first light-emitting devices 31 corresponding to the first driving circuits 21 in the same sub-display area 10. Different sub-display areas 10 can be controlled separately, and the display modes of different sub-display areas 10 can be selected as needed, which is conducive to achieving local control of the display panel 100, reducing the power consumption of the display panel 100, and reducing wiring. The present disclosure provides an optional implementation manner in which the first light-emitting device 31 is an anti-peeping light-emitting device, and the second light-emitting device 32 is a conventional light-emitting device. The present disclosure is conducive to achieving unified control of the anti-peeping light-emitting devices in the same sub-display area 10, and different sub-display areas 10 can be controlled separately. When some sub-display areas 10 need to achieve anti-peeping, these sub-display areas 10 can be individually controlled to enter the anti-peeping mode, and other sub-display areas 10 remain in normal mode, which is conducive to achieving local anti-peeping and reducing the power consumption of the display panel 100.

[0082] It should be noted that, for the sake of clarity, the embodiments of the present disclosure provide separate examples for the following three methods: method 1: the first electrodes of all first driving transistors T10 are electrically connected to the same first power supply voltage signal line PVDD1; method 2: the gates of all first transistors T11 are electrically connected to the same first scanning signal line Scan1; and method 3: the second electrodes of all first transistors T11 are electrically connected to the same first data signal line DATA1. The present disclosure only uses this as an example for illustration and is not limited thereto. Optionally, different combinations of methods 1 to 3 may also be used.

[0083] It should also be noted that the anode of the first light emitting device 31 is electrically connected to the second electrode of the first driving transistor T10, receives the first power supply voltage signal transmitted by the first power supply voltage signal line PVDD1, and the cathode of the first light emitting device 31 is electrically connected to the third power supply voltage signal line PVEE1. In order to further facilitate the unified control of the first light emitting devices 31 in the same sub-display area 10, the cathodes of all the first light emitting devices 31 in the same sub-display area 10 are electrically connected to the same third power supply voltage signal line PVEE1. Fig.15 FIG. 1 is a schematic diagram showing a connection of a third power supply voltage signal line provided in an embodiment of the present disclosure. Fig.16 FIG. 1 is a schematic diagram showing another connection diagram of a third power supply voltage signal line provided in an embodiment of the present disclosure. Please refer to FIG. Fig.15 The present disclosure provides an optional implementation mode that, in the same sub-display area 10, the cathodes of all the first light-emitting devices 31 are connected to the same third power supply voltage signal line PVEE1 through the fifth lead line 5. In this way, one sub-display area 10 corresponds to only one third power supply voltage signal line PVEE1, which is beneficial to reduce the number of third power supply voltage signal lines PVEE1 required for the sub-display area 10 and simplify the wiring structure of the display panel 100. Please refer to Fig.16 The present disclosure provides another optional implementation manner, in which the sub-display area 10 includes 9 first drive circuits 21 in 3 rows×3 columns, the third power supply voltage signal line PVEE1 includes a third power supply voltage signal main line segment PVEE11 and a third power supply voltage signal branch line segment PVEE12, the third power supply voltage signal main line segment PVEE11 and the third power supply voltage signal branch line segment PVEE12 are electrically connected through the third power supply voltage signal connection line PVEE1-c, and in the sub-display area 10, the cathodes of all first light-emitting devices 31 are electrically connected to the nearest third power supply voltage signal main line segment PVEE11 or the third power supply voltage signal branch line segment PVEE12 through the fifth lead-out line 5. With such an arrangement, the cathode of the first light-emitting device 31 can be connected to the third power supply voltage signal line PVEE1 nearby, which is beneficial to reducing the voltage drop. At the same time, one sub-display area 10 corresponds to only one third power supply voltage signal line PVEE1, which is beneficial to reducing the number of third power supply voltage signal lines PVEE1 required for the sub-display area 10 and simplifying the wiring structure of the display panel 100.

[0084] Please refer to Figure 2 , the present disclosure provides an optional implementation manner, the display mode of the display panel 100 includes an anti-peeping mode and a normal mode;

[0085] The display panel 100 further includes a shielding layer 60, which is located on a side of the light emitting device layer 30 away from the substrate 00; the shielding layer 60 includes a plurality of shielding portions 61 and a plurality of light-transmitting openings 62;

[0086] Along a direction perpendicular to the plane where the substrate 00 is located, the second light emitting device 32 at least partially overlaps with the light-transmitting opening 62 , and the first light emitting device 31 is located in the shielding portion 61 ;

[0087] In the anti-peeping mode, the first light emitting device 31 and the second light emitting device 32 in the same sub-display area 10 both emit light;

[0088] In the normal mode, the second light emitting device 32 in the same sub-display area 10 emits light, and the first light emitting device 31 does not emit light.

[0089] Specifically, in the present embodiment, the display panel 100 includes a stacked substrate 00, a driving layer 40, a light-emitting device layer 30, an encapsulation layer 50, and a shielding layer 60. The first light-emitting device 31 and the second light-emitting device 32 are located in the light-emitting device layer 30. The shielding layer 60 is located on the side of the light-emitting device layer 30 away from the substrate 00. The shielding layer 60 includes a shielding portion 61 and a light-transmitting opening 62. In a direction perpendicular to the plane where the substrate 00 is located, the first light-emitting device 31 is located in the shielding portion 61, and the second light-emitting device 32 at least partially overlaps with the light-transmitting opening 62. When the first light-emitting device 31 emits light under the drive of the driving layer 40, the light with a large viewing angle emitted by the first light-emitting device 31 is emitted through the light-transmitting opening 62 (such as Figure 2 When the user observes the display panel 100 at a wide viewing angle, the light of the first light emitting device 31 will enter the user's line of sight, causing interference to the user. When the second light emitting device 32 is driven by the second driving circuit 22 to emit light, the light of the second light emitting device 32 is emitted through the light transmission port 62 (as shown in FIG. Figure 2 When the user looks directly at the display panel 100 , the picture is displayed to the user.

[0090] In the display panel 100 provided in this embodiment, in the anti-peeping mode, the first light-emitting device 31 and the second light-emitting device 32 in the same sub-display area 10 both emit light, and the light of the first light-emitting device 31 interferes with the line of sight of the user who is not looking directly at the screen, thereby realizing the anti-peeping function; in the normal mode, the first light-emitting device 31 in the same sub-display area 10 does not emit light, and the second light-emitting device 32 emits light. The inventors have found in their research that in the anti-peeping mode, when the first light-emitting devices 31 in the display panel 100 are fully illuminated, the power consumption of the display panel 100 is relatively high. Therefore, the present disclosure is configured that, in the same sub-display area 10, the first electrodes of all the first driving transistors T10 are electrically connected to the same first power supply voltage signal line PVDD1; and / or, the gates of all the first transistors T11 are electrically connected to the same first scan signal line Scan1; and / or, the second electrodes of all the first transistors T11 are electrically connected to the same first data signal line DATA1, which is conducive to achieving unified control of the first light-emitting devices 31 in the same sub-display area 10, turning on the first light-emitting devices 31 in some areas, and further facilitating local anti-peeping and reducing the power consumption of the display panel 100.

[0091] Please refer to Figure 3 , the present disclosure provides an optional implementation manner, the display mode of the display panel 100 includes an anti-peeping mode and a normal mode;

[0092] The display panel 100 further includes a shielding layer 60, which is located on a side of the light emitting device layer 30 away from the substrate 00; the shielding layer 60 includes a plurality of shielding portions 61 and a plurality of light-transmitting openings 62;

[0093] Along a direction perpendicular to the plane where the substrate 00 is located, the first light emitting device 31 at least partially overlaps with the light transmission opening 62, and the second light emitting device 32 at least partially overlaps with the light transmission opening 62;

[0094] In the anti-peeping mode, the first light emitting device 31 in the same sub-display area 10 emits light and the second light emitting device 32 does not emit light;

[0095] In the normal mode, the first light emitting device 31 and the second light emitting device 32 in the same sub-display area 10 both emit light, or the second light emitting device 32 emits light and the first light emitting device 31 does not emit light.

[0096] Specifically, in this embodiment, the display panel 100 includes a stacked substrate 00, a driving layer 40, a light-emitting device layer 30, an encapsulation layer 50, and a shielding layer 60. The first light-emitting device 31 and the second light-emitting device 32 are located in the light-emitting device layer 30. The shielding layer 60 is located on the side of the light-emitting device layer 30 away from the substrate 00. The shielding layer 60 includes a shielding portion 61 and a light-transmitting opening 62. In a direction perpendicular to the plane where the substrate 00 is located, the first light-emitting device 31 at least partially overlaps with the light-transmitting opening 62, and the second light-emitting device 32 also at least partially overlaps with the light-transmitting opening 62. The difference is that the light emitted by the first light-emitting device 31 (please refer to Figure 3 The viewing angle formed by the second light emitting device 32 is relatively narrow (as shown by the dashed arrow in the middle). When the user is within the narrow viewing angle range, the content displayed by the display panel 100 can be clearly observed; the light emitted by the second light emitting device 32 (please refer to Figure 3 The viewing angle formed (as shown by the time arrow in the middle) is larger, and the user can clearly observe the content of the display panel 100 in a larger range.

[0097] In the display panel 100 provided in the present embodiment, in the anti-peeping mode, the first light-emitting device 31 in the same sub-display area 10 emits light, and the second light-emitting device 32 does not emit light, that is, in the sub-display area 10, the user can clearly observe the narrow viewing angle of the display panel 100 display screen, thereby achieving the anti-peeping effect; in the normal mode, in the same sub-display area 10, the second light-emitting device 32 emits light, and the user can clearly observe the display panel 100 display screen with a wide viewing angle, and the first light-emitting device 31 can emit light or not. The present disclosure is set that in the same sub-display area 10, the first electrodes of all first driving transistors T10 are electrically connected to the same first power supply voltage signal line PVDD1; and / or, the gates of all first transistors T11 are electrically connected to the same first scan signal line Scan1; and / or, the second electrodes of all first transistors T11 are electrically connected to the same first data signal line DATA1, so as to facilitate the unified control of the first light-emitting devices 31 in the same sub-display area 10, turn on the first light-emitting devices 31 in some areas, and then facilitate the local anti-peeping.

[0098] It should be noted that Figure 2 In the embodiment shown, anti-peeping is achieved by interference. When the display panel 100 is in anti-peeping mode, in the anti-peeping area, both the first light emitting device 31 and the second light emitting device 32 emit light. This embodiment is more suitable for small-sized products such as mobile phones. Figure 3In the embodiment shown, by reasonably setting the structure of the shielding layer 60, the viewing angle formed by the light emitted by the first light-emitting device 31 is narrower, and the viewing angle formed by the light emitted by the second light-emitting device 32 is larger. When the display panel 100 is in the anti-peeping mode, in the anti-peeping area, the first light-emitting device 31 emits light, and the second light-emitting device 32 may or may not emit light. This embodiment is more suitable for medium and large-sized products such as flat panels and vehicle-mounted display screens.

[0099] Fig.17 FIG. 1 is a schematic diagram of another first driving circuit provided in an embodiment of the present disclosure. Please refer to FIG. Fig.17 The present disclosure provides an optional implementation manner in which the first driving circuit 21 further includes a first storage capacitor C11, and the first storage capacitor C11 is electrically connected between the gate and the first electrode of the first driving transistor T10.

[0100] Specifically, the first driving circuit 21 includes a first transistor T11, a first driving transistor T10 and a first storage capacitor C11; the gate of the first transistor T11 is electrically connected to the first scanning signal line Scan1, the first electrode of the first transistor T11 is electrically connected to the gate of the first driving transistor T10, and the second electrode of the first transistor T11 is electrically connected to the first data signal line DATA1; the first electrode of the first driving transistor T10 is electrically connected to the first power supply voltage signal line PVDD1, the second electrode of the first driving transistor T10 is electrically connected to the anode of the first light emitting device 31, and the cathode of the first light emitting device 31 is electrically connected to the third power supply voltage signal line PVEE1. The light emitting process of the first driving circuit 21 includes: the first transistor T11 is turned on under the control of the first scanning signal line Scan1, and the first data signal is transmitted to the gate of the first driving transistor T10; the first driving transistor T10 is turned on under the control of the first data signal, and the first power supply voltage signal is transmitted to the first light emitting device 31, thereby driving the first light emitting device 31 to emit light. In this embodiment, the first driving circuit 21 also includes a first storage capacitor C11, which is connected between the gate and the first electrode of the first driving transistor T10. In this way, the first storage capacitor C11 can maintain the gate potential of the first driving transistor T10 to avoid the gate potential of the driving transistor being coupled and changed when the first transistor T11 is turned off.

[0101] Fig.18 FIG. 1 is a schematic diagram of another first driving circuit provided in an embodiment of the present disclosure. Please refer to FIG. Fig.18, the present disclosure provides an optional implementation, the first driving circuit 21 further includes a first initialization module 212, a first threshold compensation module 213 and a first storage module 214, one end of the first initialization module 212 is electrically connected to the gate of the first driving transistor T10; the first threshold compensation module 213 is electrically connected between the gate and the second electrode of the first driving transistor T10; the first storage module 214 is electrically connected between the gate and the first electrode of the first driving transistor T10;

[0102] In the sub-display area 10 , the first data signal line DATA1 transmits a data signal, and the other ends of all the first initialization modules 212 are electrically connected to the same first reset signal line Vref1 .

[0103] Specifically, the present disclosure provides an implementation of a first driving circuit 21, wherein the first driving circuit 21 includes a first transistor T11 and a first driving transistor T10, wherein the first transistor T11 is used to provide a first data signal to the gate of the first driving transistor T10; and the first driving transistor T10 is used to provide a first power supply voltage signal to the first light-emitting device 31. The first driving circuit 21 also includes a first initialization module 212, a first threshold compensation module 213 and a first storage module 214. Exemplarily, the first initialization module 212 includes a first initialization transistor T12, the first threshold compensation module 213 includes a first threshold compensation transistor T13, and the first initialization module 212 includes a first storage capacitor C11. Among them, the first initialization module 212 is electrically connected to the gate of the first driving transistor T10, and is used to provide a first reset signal to the gate of the first driving transistor T10 to reset the gate of the first driving transistor T10; the first threshold compensation module 213 is electrically connected between the gate and the second pole of the first driving transistor T10, and when the first transistor T11 is turned on, the first threshold compensation module 213 is turned on to capture the threshold voltage of the first driving transistor T10 to the gate of the first driving transistor T10, thereby achieving compensation of the threshold voltage of the first driving transistor T10; the first storage module 214 is electrically connected between the gate and the first pole of the first driving transistor T10, and the first storage module 214 can maintain the gate potential of the first driving transistor T10 to avoid the gate potential of the driving transistor being coupled and changing when the first transistor T11 is turned off. Please continue to refer to Fig.18The first driving circuit 21 also includes a first light-emitting control module and a first light-emitting initialization module. The first light-emitting control module includes a first A light-emitting control transistor T14 and a first B light-emitting control transistor T15. The gate of the first A light-emitting control transistor T14 is connected to the first light-emitting control signal line Emit1, and the first electrode and the second electrode are respectively connected to the first power supply voltage signal line PVDD1 and the first electrode of the first driving transistor T10. The gate of the first B light-emitting control transistor T15 is connected to the first light-emitting control signal line Emit1, and the first electrode and the second electrode are respectively connected to the second electrode of the first driving transistor T10 and the anode of the first light-emitting device 31; the first light-emitting initialization module includes a first light-emitting initialization transistor T16. The gate of the first light-emitting initialization transistor T16 is connected to the third scanning signal line Scan3, and the first electrode and the second electrode are respectively electrically connected to the first reset signal line Vref1 and the anode of the first light-emitting device 31.

[0104] It should be noted that, in the present embodiment, in the same sub-display area 10, all first initialization modules 212 are electrically connected to the same first reset signal line Vref1. In this way, all first initialization modules 212 in the same sub-display area 10 receive the same first reset signal, which is conducive to resetting the gates of all first driving transistors T10 in the same sub-display area 10 to the same potential, thereby facilitating unified control of the first light-emitting devices 31 in the same sub-display area 10. However, the present application is not limited thereto, and the first initialization modules 212 may also be connected to different reset signal lines respectively, thereby receiving different reset voltages.

[0105] Fig.19 This disclosure is shown Fig.18 For the timing diagram of the first drive circuit provided, please refer to Fig.18 and Fig.19 ,against Fig.18 For the working timing diagram of the first driving circuit 21 shown in FIG. Fig.19, the specific working process includes: initialization stage T1, data writing stage T2 and light emitting stage T3. In the initialization stage T1, the first initialization transistor T12 and the first light emitting initialization transistor T16 are turned on, the first reset signal is transmitted to the gate of the first driving transistor T10 for initialization, and the first reset signal is transmitted to the anode of the first light emitting device 31 for initialization, so that the residual charge of the previous frame can be eliminated to improve the display effect of the display panel 100. It should be noted that the initialization of the anode of the first light emitting device 31 can also be performed in the data writing stage T2, and the corresponding timing can be modified. The present disclosure is only described as an example and is not limited to this. In the data writing stage T2, the first transistor T11 and the first threshold compensation transistor T13 are turned on, the first data signal is written into the first driving transistor T10, and the first threshold compensation transistor T13 is connected between the gate and the second electrode of the first driving transistor T10, and the threshold voltage of the first driving transistor T10 can be captured to the gate of the first driving transistor T10 to achieve threshold voltage compensation. The first storage capacitor C11 is connected between the gate and the first electrode of the first driving transistor T10, and can maintain the gate potential of the first driving transistor T10. In the light-emitting stage T3, the first A light-emitting control transistor T14, the first B light-emitting control transistor T15 and the first driving transistor T10 are all turned on, and the driving current is transmitted to the anode of the first light-emitting device 31, and the first light-emitting device 31 emits light. It should be noted that the present disclosure is only based on Fig.18 The first driving circuit 21 is described as an example. Fig.19 The timing diagram is only for illustration and is not intended to be limiting. In some other embodiments of the present disclosure, the first driving circuit 21 may also be embodied as other feasible structures. At the same time, the present disclosure does not limit the type of transistors in the first driving circuit 21.

[0106] Fig. 20 FIG. 1 is a schematic diagram of a second driving circuit provided in an embodiment of the present disclosure. Please refer to FIG. Fig. 20 , the present disclosure provides an optional implementation, the second driving circuit 22 includes a second driving transistor T20, a second initialization module 222, a second storage module 224, a second threshold compensation module 223, and a second data writing module 221;

[0107] The first electrode of the second driving transistor T20 is electrically connected to the second power supply voltage signal line PVDD2; the second storage module 224 is electrically connected between the gate and the first electrode of the second driving transistor T20; the second threshold compensation module 223 is connected between the second electrode and the gate of the second driving transistor T20; the second data writing module 221 is electrically connected between the second data signal line DATA2 and the first electrode of the second driving transistor T20; the second initialization module 222 is electrically connected between the gate of the second driving transistor T20 and the second reset signal line Vref2.

[0108] Specifically, the second driving circuit 22 is used to drive the second light-emitting device 32 to emit light. The present disclosure provides an implementation of the second driving circuit 22, wherein the second driving circuit 22 includes a second driving transistor T20, a second initialization module 222, a second storage module 224, a second threshold compensation module 223, and a second data writing module 221, wherein the second driving transistor T20 is used to transmit a second power supply voltage signal to the second light-emitting device 32, the second initialization module 222 is used to initialize the gate of the second driving transistor T20, the second storage module 224 is used to maintain the gate potential of the second driving transistor T20, the second threshold compensation module 223 is used to compensate for the threshold voltage of the second driving transistor T20, and the second data writing module 221 is used to write a second data signal to the second driving transistor T20. Exemplarily, the second initialization module 222 includes a second initialization transistor T22, the gate of the second initialization transistor T22 is electrically connected to the fourth scan signal line Scan4, and the first electrode and the second electrode are respectively electrically connected to the second reset signal line Vref2 and the gate of the second driving transistor T20; the second storage module 224 includes a second storage capacitor C2, and the second storage capacitor C2 is electrically connected between the gate and the first electrode of the second driving transistor T20; the second threshold compensation module 223 includes a second threshold compensation transistor T24, the gate of the second threshold compensation transistor T24 is electrically connected to the second scan signal line Scan2, and the first electrode and the second electrode are respectively electrically connected to the gate and the first electrode of the second driving transistor T20; the second data writing module 221 includes a second data writing transistor T21, the gate of the second data writing transistor T21 is electrically connected to the second scan signal line Scan2, and the first electrode and the second electrode are respectively electrically connected to the second data signal line DATA2 and the first electrode of the second driving transistor T20. Optionally, the second driving circuit 22 also includes a second A light-emitting control transistor T25, a second B light-emitting control transistor T27 and a second light-emitting initialization transistor T23, the gate of the second A light-emitting control transistor T25 is electrically connected to the second light-emitting control signal line Emit2, and the first electrode and the second electrode are respectively electrically connected to the second power supply voltage signal line PVDD2 and the first electrode of the second driving transistor T20; the gate of the second B light-emitting control transistor T27 is electrically connected to the second light-emitting control signal line Emit2, and the first electrode and the second electrode are respectively electrically connected to the second electrode of the second driving transistor T20 and the anode of the second light-emitting device 32; the gate of the second light-emitting initialization transistor T23 is electrically connected to the fourth scanning signal line Scan4, and the first electrode and the second electrode are respectively electrically connected to the second reset signal line Vref2 and the anode of the second light-emitting device 32.

[0109] against Fig. 20 For the working timing diagram of the second driving circuit 22 shown in FIG. Fig.21 , Fig.21 This disclosure is shown Fig. 20The timing diagram of the second driving circuit provided, the specific working process includes: initialization stage T1, data writing stage T2 and light emitting stage T3. In the initialization stage T1, the second initialization transistor T22 and the second light emitting initialization transistor T23 are turned on, the second reset signal is transmitted to the gate of the second driving transistor T20 for initialization, and the second reset signal is transmitted to the anode of the second light emitting device 32 for initialization, so that the residual charge of the previous frame can be eliminated to improve the display effect of the display panel 100. It should be noted that the initialization of the anode of the second light emitting device 32 can also be performed in the data writing stage T2, and the present disclosure is only described as an example and is not limited to this. In the data writing stage T2, the second data writing transistor T21 and the second threshold compensation transistor T24 are turned on, the second data signal is written into the second driving transistor T20, and the second threshold compensation transistor T24 is connected between the gate and the second pole of the second driving transistor T20, and the threshold voltage of the second driving transistor T20 can be captured to the gate of the second driving transistor T20 to achieve threshold voltage compensation. The second storage capacitor C2 is connected between the gate of the second driving transistor T20 and the first electrode, and can maintain the gate potential of the second driving transistor T20. In the light-emitting stage T3, the second A light-emitting control transistor T25, the second B light-emitting control transistor T27 and the second driving transistor T20 are all turned on, and the driving current is transmitted to the anode of the second light-emitting device 32, and the second light-emitting device 32 emits light. It should be noted that the present disclosure is only based on Fig. 20 The second driving circuit 22 is described by taking the example as an example. Fig.21 The timing diagram is only for illustration and is not intended to be limiting. In some other embodiments of the present disclosure, the second driving circuit 22 may also be embodied as other feasible structures. At the same time, the present disclosure does not limit the type of transistors in the second driving circuit 22.

[0110] Fig. 22 FIG. 1 is a connection diagram of a second driving circuit provided in an embodiment of the present disclosure. Please refer to FIG. Fig. 22 , Fig. 22In the illustrated embodiment, an embodiment of the second driving circuit 22 in the sub-display area 10 is illustrated, and each second driving circuit 22 is electrically connected to the corresponding second power supply voltage signal line PVDD2, the second data signal line DATA2, the second reset signal line Vref2, the second scan signal line Scan2, the fourth scan signal line Scan4 and the second light-emitting control signal line Emit2. Among them, the first electrode of the second A light-emitting control transistor T25 is electrically connected to the second power supply voltage signal line PVDD2; the gate of the second data writing transistor T21 is electrically connected to the second scan signal line Scan2, and the first electrode of the second data writing transistor T21 is electrically connected to the second data signal line DATA2; the first electrode of the second initialization transistor T22 and the first electrode of the second light-emitting initialization transistor T23 are electrically connected to the second reset signal line Vref2; the gate of the second initialization transistor T22 and the gate of the second light-emitting initialization transistor T23 are electrically connected to the fourth scan signal line; the gate of the second A light-emitting control transistor T25 and the gate of the second B light-emitting control transistor T27 are electrically connected to the second light-emitting control signal line Emit2. It should be noted that the present disclosure is only based on Fig. 22 The illustrated implementation is provided for illustration only and is not intended to be limiting.

[0111] Fig.23 FIG. 1 is a schematic diagram of another sub-display area provided in an embodiment of the present disclosure. Please refer to FIG. Fig.23 The present disclosure provides an optional implementation manner, the voltage transmitted by the first power supply voltage signal line PVDD1 is VD1, and the voltage transmitted by the second power supply voltage signal line PVDD2 is VD2, wherein VD1 ≥ VD2.

[0112] Specifically, the sub-display area 10 includes a total of 8 driving circuits 20 arranged in 2 rows and 4 columns. The driving circuit 20 includes a first driving circuit 21 and a second driving circuit 22. The first poles of the first transistors T11 in each first driving circuit 21 are electrically connected to the same first power supply voltage signal line PVDD1; the first poles of the first light-emitting control transistors T14 in each second driving circuit 22 are electrically connected to the corresponding second power supply voltage signal line PVDD2. That is, the first power supply voltage signal line PVDD1 provides the first power supply voltage signal to at least four first driving circuits 21 in the sub-display area 10, and the four second driving circuits 22 in the sub-display area 10 can be respectively provided with corresponding second power supply voltage signal lines PVDD2 to supply the second power supply voltage signal to the second driving circuit 22. The voltage transmitted by the first power supply voltage signal line PVDD1 is VD1, and the voltage transmitted by the second power supply voltage signal line PVDD2 is VD2. When VD1 < VD2, the voltage attenuation of the voltage transmitted by the first power supply voltage signal line PVDD1 to each first light-emitting device 31 is relatively large, resulting in a relatively large difference between the voltage of the first power supply voltage signal transmitted to the first light-emitting device 31 and the voltage of the second power supply voltage signal transmitted to the second light-emitting device 32. The magnitude of the power supply voltage received by the light-emitting device affects the light-emitting brightness. Therefore, when the difference in the magnitudes of the voltages received by the first light-emitting device 31 and the second light-emitting device 32 is relatively large, the difference in the light-emitting brightness between the first light-emitting device 31 and the second light-emitting device 32 is relatively large, which is not conducive to improving the brightness uniformity of the display panel 100. Therefore, in this embodiment, VD1≥VD2 is set. In this way, since only one first power supply voltage signal line PVDD1 is provided for each sub-display area 10, and the first power supply voltage signal line PVDD1 supplies the first power supply voltage to multiple first driving circuits 21 in the sub-display area 10, the first power supply voltage transmitted to the first driving circuit 21 may be less than VD1. Setting VD1≥VD2 is beneficial to reducing the difference between the voltage transmitted to each first light-emitting device 31 and the voltage transmitted to each second light-emitting device 32, thereby being beneficial to reducing the difference in the light-emitting brightness between the first light-emitting device 31 and the second light-emitting device 32, and further improving the brightness uniformity of the display panel 100.

[0113] Fig.24 The following figure shows another schematic diagram of the sub-display area provided by the embodiment of the present disclosure. Please refer to Fig.24 In an optional embodiment provided by the present disclosure, the extending directions of the first data signal line DATA1 and the second data signal line DATA2 are the same. Along the direction perpendicular to the extending direction of the first data signal line DATA1, the width of the first data signal line DATA1 is W1, and the width of the second data line is W2, where W1≥W2.

[0114] Specifically, the sub-display area 10 includes a plurality of drive circuits 20, the drive circuits 20 include a first drive circuit 21 and a second drive circuit 22, the first data signal line DATA1 transmits a first data signal to the first drive circuit 21, the second data signal line DATA2 transmits a second data signal to the second drive circuit 22, and the first data signal line DATA1 and the second data signal line DATA2 both extend along the second direction F2. In this embodiment, the width W1 of the first data signal line DATA1 along the first direction F1 is set to be greater than or equal to the width W2 of the second data signal line DATA2 along the second direction F2. It can be understood that when the width of the data signal line is wider, it is beneficial to reduce the voltage drop of the data signal line. The present disclosure is arranged that, in the same sub-display area 10, the first electrodes of all the first transistors T11 are electrically connected to the same first data signal line DATA1, and the second data writing transistors T21 in the second drive circuit 22 are respectively electrically connected to the second data signal line DATA2. In order to reduce the voltage difference between the data signals received by the first drive circuit 21 and the second drive circuit 22, the present embodiment is arranged that W1≥W2. In this way, it is beneficial to reduce the voltage drop of the first data signal line DATA1, thereby reducing the voltage difference between the data signals received by the first drive circuit 21 and the second drive circuit 22. Therefore, it is beneficial to improve the brightness uniformity of the first light-emitting device 31 and the second light-emitting device 32.

[0115] Similarly, please refer to Fig.25 , Fig.25 The figure shows a schematic diagram of another sub-display area provided by an embodiment of the present disclosure. The present disclosure provides another optional implementation mode, in which the first power supply voltage signal line PVDD1 and the second power supply voltage signal line PVDD2 both extend along the second direction F2, and the width W3 of the first power supply voltage signal line PVDD1 along the first direction F1 is greater than or equal to the width W4 of the second power supply voltage signal line PVDD2 along the first direction F1. This is beneficial to reducing the voltage drop of the first power supply voltage signal line PVDD1, thereby reducing the difference in power supply voltage received by the first drive circuit 21 and the second drive circuit 22, and therefore, is beneficial to improving the brightness uniformity of the first light-emitting device 31 and the second light-emitting device 32.

[0116] Fig.26 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure, please refer to FIG. Fig.26 , the present disclosure provides an optional implementation manner, wherein a plurality of sub-display areas 10 are arranged in a row-column matrix;

[0117] The first driving circuits 21 corresponding to all the sub-display areas 10 in the same column are electrically connected to the same first data signal line DATA1 .

[0118] Specifically, the display panel 100 includes a plurality of sub-display areas 10, and the sub-display areas 10 are arranged in an array. Fig.26 The example of the display panel 100 including 5 rows×7 columns and a total of 35 sub-display areas 10, each of which includes 8 driving circuits 20, is used for illustration, which does not represent the actual number and structure, nor is it limited to this. In the same sub-display area 10, all the first driving circuits 21 are electrically connected to the same first data signal line DATA1, and the sub-display areas 10 in the same column correspond to the same first data signal line DATA1, that is, the first driving circuits 21 in the sub-display areas 10 in the same column are electrically connected to the same first data signal line DATA1, which is conducive to achieving unified control of the first driving circuits 21 in the same sub-display area 10, and at the same time, it is also conducive to reducing the number of binding pins connected to the first data signal line DATA1, simplifying the structure of the driving chip and the display panel 100.

[0119] Fig. 27 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure. Please refer to FIG. Fig. 27 , the present disclosure provides an optional implementation, including a plurality of first data signal line groups 80 , the first data signal line group 80 includes X first data signal lines DATA1 , X ≥ 2 and is an integer;

[0120] The display panel 100 further includes a plurality of multiplexer units 81, X switch control lines SW and a plurality of data source lines 82; the multiplexer unit 81 includes X switch elements 811, and the switch element 811 includes a control end, an input end and an output end; the input ends of the X switch elements 811 of the same multiplexer unit 81 are electrically connected to the same data source line 82, and the multiplexer unit 81 is connected to the data source line 82 in a one-to-one correspondence; the control ends of the X switch elements 811 of the multiplexer unit 81 are connected to the X switch control lines SW in a one-to-one correspondence; the output ends of the X switch elements 811 of the multiplexer are connected to the X first data signal lines DATA1 in a one-to-one correspondence.

[0121] Specifically, this embodiment is described by taking X=2 as an example. A multiplexing unit 81 is correspondingly provided for every two columns of sub-display areas 10. The multiplexing unit 81 includes two switch elements 811. The control end of each switch element 811 is electrically connected to the corresponding switch control line SW. The control end of the switch element 811 in the same multiplexing unit 81 is connected to different switch control lines SW. For example, this embodiment includes two switch elements 811. The control end of one switch element 811 is connected to the first switch control line SW1, and the control end of the other switch element 811 is connected to the second switch control line SW2. The input end of the switch element 811 in the same multiplexing unit 81 is connected to the same data source line 82, and the output end is connected to different first data signal lines DATA1. In this way, a data signal can be provided to X first data signal lines DATA1 through one data source line 82, which is conducive to reducing the wiring of the display panel 100. It should be noted that this embodiment is described by taking X=2 as an example only, and is not limited thereto. X can be any other integer greater than or equal to 2.

[0122] Fig.28 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure, please refer to FIG. Fig.28 The present disclosure provides an optional implementation manner, in which a plurality of sub-display areas 10 are arranged in a row-column matrix, and the first driving circuits 21 corresponding to all the sub-display areas 10 in the same row are electrically connected to the same first scanning signal line Scan1.

[0123] For more information, see Fig.28 The display panel 100 includes a plurality of sub-display areas 10. A sub-display area 10 includes eight drive circuits 20 in 2 rows×4 columns. The drive circuits 20 include a first drive circuit 21 and a second drive circuit 22. In the same sub-display area 10, all first drive circuits 21 are electrically connected to the same first scan signal line Scan1. Specifically, please refer to Figures 9 to 11 The first driving circuit 21 includes a first transistor T11 and a first driving transistor T10, a first electrode of the first transistor T11 is electrically connected to a gate of the corresponding first driving transistor T10, and a second electrode of the first transistor T11 is electrically connected to the same first scanning signal line Scan1, so that it is conducive to achieving unified control of the first driving circuit 21 in the same sub-display area 10. In this embodiment, it is also arranged that the first driving circuits 21 corresponding to all sub-display areas 10 in the same row are electrically connected to the same first scanning signal line Scan1, so that it is conducive to reducing the number of first scanning signal lines Scan1, thereby simplifying the structure of the display panel 100.

[0124] Fig.29 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure, please refer to FIG. Fig.29, the present disclosure provides an optional implementation manner, further comprising a non-display area NA, the non-display area NA at least partially surrounding the display area AA;

[0125] The non-display area NA includes a plurality of first shift registers 91 , and a first shift register 91 is electrically connected to at least one first scan signal line Scan1 .

[0126] Specifically, the display panel 100 includes a display area AA and a non-display area NA, and the non-display area NA at least partially surrounds the display area AA. It should be noted that the embodiment of the present disclosure is only described by taking the non-display area NA surrounding the display area AA as an example, and is not limited to this. The display area AA includes a plurality of sub-display areas 10, and the sub-display area 10 includes a plurality of first drive circuits 21. In this embodiment, the first drive circuits 21 corresponding to all sub-display areas 10 in the same row are electrically connected to the same first scan signal line Scan1. The non-display area NA includes a plurality of first shift registers 91, and the first shift register 91 is electrically connected to the first scan signal line Scan1. It should be noted that the embodiment of the present disclosure is only described by taking a first shift register 91 connected to a first scan signal line Scan1 as an example, and is not limited to this, and can be designed according to actual needs. Such a setting is conducive to reducing the number of first scan signal lines Scan1 and first shift registers 91, thereby helping to simplify the structure of the display panel 100.

[0127] Fig.30 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure. Fig.31 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure, please refer to FIG. Figure 29 to Figure 31 The present disclosure provides an optional implementation manner, in which the first shift registers 91 are all located on the same side of the display area AA, or are respectively located on both sides of the display area AA.

[0128] Specifically, Fig.29 In the embodiment shown, the first shift registers 91 are all located on the same side of the display area AA. With this arrangement, the layout and connection of the first shift registers 91 are relatively simple, which is conducive to reducing the difficulty of design and the complexity of production. Fig.30 The present disclosure provides another optional implementation mode, in which the first shift registers 91 are respectively located on both sides of the display area AA along the first direction F1, and one first scan signal line Scan1 is correspondingly connected to two first shift registers 91, and the two first shift registers 91 simultaneously provide signals to the first scan signal line Scan1, which is beneficial to effectively reduce the voltage decay phenomenon, thereby improving the display effect of the display panel 100. Please refer to Fig.31The present disclosure provides another optional implementation, in which the first shift registers 91 are respectively located on both sides of the display area AA along the first direction F1, and one first scan signal line Scan1 is correspondingly connected to one first shift register 91, the first shift register 91 on one side of the display area AA is connected to the odd-numbered first scan signal lines Scan1, and the first shift register 91 on the other side of the display area AA is connected to the even-numbered first scan signal lines Scan1. In this way, it is beneficial to reduce the width of the non-display area NA along the first direction F1, thereby helping to reduce the border width of the display panel 100.

[0129] Fig.32 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure, please refer to FIG. Fig.32 , the present disclosure provides an optional implementation, further comprising a second scanning signal line Scan2, the second scanning signal line Scan2 being electrically connected to the second driving circuit 22;

[0130] The first shift register 91 is electrically connected to the second scan signal line Scan2.

[0131] Specifically, the driving circuit 20 includes a first driving circuit 21 and a second driving circuit 22, wherein the first driving circuit 21 is electrically connected to the first scanning signal line Scan1, and the second driving circuit 22 is electrically connected to the second scanning signal line Scan2. The non-display area NA of the display panel 100 includes a first shift register 91, wherein the first shift register 91 is electrically connected to the second scanning signal line Scan2, and at the same time, the first shift register 91 can also be electrically connected to the first scanning signal line Scan1, that is, the first shift register 91 can provide drive to both the second scanning signal line Scan2 and the first scanning signal line Scan1, that is, the first scanning signal line Scan1 and the second scanning signal line Scan2 share the first shift register 91, and the first scanning signal line Scan1 and the second scanning signal line Scan2 are connected in parallel, which is beneficial to reducing the number of the first shift registers 91, thereby facilitating the simplification of the structure of the display panel 100.

[0132] Fig.33 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure, please refer to FIG. Fig.33 The present disclosure provides an optional implementation, the sub-display area 10 includes a first sub-display area 11 and a second sub-display area 12, the first sub-display area 11 includes M1 row × N1 column driving circuits 20, the second sub-display area 12 includes M2 row × N2 column driving circuits 20, M1≥2, N1≥2, M2≥2, N2≥2 and M1, N1, M2, N2 are all integers, M1≥M2, N1≥N2.

[0133] Specifically, the display panel 100 includes a plurality of sub-display areas 10, and one sub-display area 10 includes M rows×N columns of driving circuits 20, M≥2, N≥2, that is, one sub-display area 10 includes at least 2 rows×2 columns of driving circuits 20. In the aforementioned embodiments of the present disclosure, the sizes of the sub-display areas 10 are the same, but the present disclosure is not limited thereto. Please refer to Fig.33 In this embodiment, the sub-display area 10 includes a first sub-display area 11 and a second sub-display area 12. The first sub-display area 11 includes M1 rows×N1 columns of driving circuits 20, and the second sub-display area 12 includes M2 rows×N2 columns of driving circuits 20, M1≥M2, N1≥N2, that is, the number of driving circuits 20 included in the first sub-display area 11 and the second sub-display area 12 is different. For example, the first sub-display area 11 includes 4 rows×3 columns of driving circuits 20, and the second sub-display area 12 includes 3 rows×2 columns of driving circuits 20. It should be noted that the present disclosure is only described by taking this as an example, and is not limited thereto.

[0134] Fig.34 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure. Fig.35 FIG. 1 is a schematic diagram of another display panel provided by an embodiment of the present disclosure, please refer to FIG. Fig.34 and Fig.35 Optionally, a plurality of drive circuit rows 29 are arranged along an extending direction perpendicular to the first scan signal line Scan1, the drive circuit row 29 includes a first drive circuit row 291 and a second drive circuit row 292, the first drive circuit 21 is located in the first drive circuit row 291, and the second drive circuit 22 is located in the second drive circuit row 292;

[0135] and / or, a plurality of drive circuit columns 28 arranged along an extending direction parallel to the first scan signal line Scan1, the drive circuit columns 28 comprising a first drive circuit column 281 and a second drive circuit column 282, the first drive circuit 21 being located in the first drive circuit column 281, and the second drive circuit 22 being located in the second drive circuit column 282;

[0136] and / or, a plurality of drive circuit rows 29 arranged along an extending direction perpendicular to the first scan signal line Scan1, the drive circuit row 29 including a first drive circuit 21 and a second drive circuit 22;

[0137] and / or, a plurality of drive circuit columns 28 arranged in parallel with the extending direction of the first scan signal line Scan1 , wherein the drive circuit column 28 includes a first drive circuit 21 and a second drive circuit 22 .

[0138] It should be noted that Fig.34 and Fig.35The illustrated embodiment is only an illustration of the arrangement of the driving circuit 20. The first scanning signal line Scan1 in the figure is only an illustration of the extension direction and the arrangement direction. The first scanning signal line Scan1 extends along the first direction F1 and is arranged along the second direction F2. That is, the first direction F1 is the extension direction of the first scanning signal line Scan1, and the second direction F2 is the arrangement direction of the first scanning signal line Scan1.

[0139] For more information, see Fig.34 In an optional embodiment of the present disclosure, the display panel 100 includes a plurality of drive circuit columns 28, the drive circuit columns 28 are arranged along the first direction F1, the drive circuit columns 28 include a first drive circuit column 281 and a second drive circuit column 282, the first drive circuit column 281 includes a plurality of first drive circuits 21 arranged along the second direction F2, and the second drive circuit column 282 includes a plurality of second drive circuit columns 282 arranged along the second direction F2. The display panel 100 also includes a plurality of drive circuit rows 29, the drive circuit rows 29 are arranged along the second direction F2, and the drive circuit rows 29 include a first drive circuit 21 and a second drive circuit 22. Please refer to Fig.35 In another optional embodiment of the present disclosure, the display panel 100 includes a plurality of drive circuit rows 29, the drive circuit rows 29 are arranged along the second direction F2, the drive circuit rows 29 include a first drive circuit row 291 and a second drive circuit row 292, the first drive circuit row 291 includes a plurality of first drive circuits 21 arranged along the first direction F1, and the second drive circuit row 292 includes a plurality of second drive circuits 22 arranged along the first direction F1. The display panel 100 also includes a plurality of drive circuit columns 28, the drive circuit columns 28 are arranged along the first direction F1, and the drive circuit columns 28 include the first drive circuit 21 and the second drive circuit 22.

[0140] It should be noted that this disclosure Fig.34 and Fig.35 The illustrated embodiment provides an arrangement of the first driving circuit 21 and the second driving circuit 22 , but the present disclosure only uses this as an example for illustration and is not limited thereto, and can be designed according to actual needs.

[0141] Based on the same inventive concept, the present disclosure also provides a display device, Fig.36 FIG. 1 is a schematic diagram of a display device provided by an embodiment of the present disclosure, please refer to FIG. Fig.36 , the display device 200 includes any one of the display panels 100 provided in the embodiments of the present disclosure.

[0142] It should be noted that the embodiment of the display device 200 provided in the embodiment of the present disclosure can refer to the embodiment of the display panel 100 described above, and will not be repeated. The display device 200 provided in the present disclosure can be: a mobile phone, a tablet computer, a television, a touch controller, a laptop computer, a car display screen, or any other product or component with a display function.

[0143] It can be seen from the above embodiments that the display panel and the display device provided by the present disclosure achieve at least the following beneficial effects:

[0144] The present disclosure provides a display panel and a display device, wherein the display panel includes a substrate, a light-emitting device layer arranged on one side of the substrate, the light-emitting device layer includes a first light-emitting device and a second light-emitting device; the display area includes at least two sub-display areas; a sub-display area includes multiple driving circuits, the driving circuit includes a first driving circuit and a second driving circuit; the first driving circuit is used to drive the first light-emitting device to emit light; the second driving circuit is used to drive the second light-emitting device to emit light; the first driving circuit includes a first transistor and a first driving transistor; in the same sub-display area, the first electrode of each first transistor is electrically connected to the gate of the corresponding first driving transistor. The present disclosure is to set the first electrodes of all first driving transistors to be electrically connected to the same first power supply voltage signal line; and / or, the gates of all first transistors are electrically connected to the same first scanning signal line; and / or, the second electrodes of all first transistors are electrically connected to the same first data signal line. Such a setting is conducive to realizing unified control of all first driving circuits in the same sub-display area, thereby realizing unified control of the first light-emitting devices corresponding to the first driving circuits in the same sub-display area, that is, it is conducive to realizing local control of the display panel, reducing the power consumption of the display panel, and is conducive to reducing wiring.

[0145] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0146] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: substrate; A light emitting device layer, disposed on one side of the substrate, the light emitting device layer comprising a first light emitting device and a second light emitting device; A display area, comprising the first light emitting device and the second light emitting device, and the display area comprises at least two sub-display areas; The sub-display area includes M rows×N columns of driving circuits, M≥2, N≥2, and M and N are both integers, and the driving circuit includes a first driving circuit and a second driving circuit; the first driving circuit is used to drive the first light-emitting device to emit light; the second driving circuit is used to drive the second light-emitting device to emit light; The first driving circuit includes a first transistor and a first driving transistor; In the same sub-display area, the first electrode of each first transistor is electrically connected to the gate of the corresponding first driving transistor; and, The first electrodes of all the first driving transistors are electrically connected to the same first power supply voltage signal line; and / or, the gates of all the first transistors are electrically connected to the same first scanning signal line; and / or, the second electrodes of all the first transistors are electrically connected to the same first data signal line.

2. The display panel according to claim 1, characterized in that: The display mode of the display panel includes an anti-peeping mode and a normal mode; The display panel further comprises a shielding layer, the shielding layer being located on a side of the light emitting device layer away from the substrate; the shielding layer comprises a plurality of shielding portions and a plurality of light transmission openings; Along a direction perpendicular to the plane where the substrate is located, the second light emitting device at least partially overlaps with the light transmission opening, and the first light emitting device is located in the shielding portion; In the anti-peeping mode, the first light-emitting device and the second light-emitting device in the same sub-display area both emit light; In the normal mode, the second light emitting device in the same sub-display area emits light, and the first light emitting device does not emit light.

3. The display panel according to claim 1, characterized in that: The display mode of the display panel includes an anti-peeping mode and a normal mode; The display panel further comprises a shielding layer, the shielding layer being located on a side of the light emitting device layer away from the substrate; the shielding layer comprises a plurality of shielding portions and a plurality of light transmission openings; Along a direction perpendicular to the plane where the substrate is located, the first light emitting device at least partially overlaps with the light transmission opening, and the second light emitting device at least partially overlaps with the light transmission opening; In the anti-peeping mode, the first light-emitting device in the same sub-display area emits light and the second light-emitting device does not emit light; In the normal mode, the first light emitting device and the second light emitting device in the same sub-display area both emit light, or the second light emitting device emits light and the first light emitting device does not emit light.

4. The display panel according to claim 1, characterized in that: The first driving circuit further includes a first storage capacitor electrically connected between the gate and the first electrode of the first driving transistor.

5. The display panel according to claim 1, characterized in that: The first driving circuit further includes a first initialization module, a first threshold compensation module and a first storage module, one end of the first initialization module is electrically connected to the gate of the first driving transistor; the first threshold compensation module is electrically connected between the gate and the second electrode of the first driving transistor; the first storage module is electrically connected between the gate and the first electrode of the first driving transistor; In the sub-display area, the first data signal line transmits a data signal, and the other ends of all the first initialization modules are electrically connected to the same first reset signal line.

6. The display panel according to claim 1, characterized in that: The second driving circuit includes a second driving transistor, a second initialization module, a second storage module, a second threshold compensation module, and a second data writing module; The first electrode of the second driving transistor is electrically connected to the second power supply voltage signal line; the second storage module is electrically connected between the gate and the first electrode of the second driving transistor; the second threshold compensation module is connected between the second electrode and the gate of the second driving transistor; the second data writing module is electrically connected between the second data signal line and the first electrode of the second driving transistor; and the second initialization module is electrically connected between the gate of the second driving transistor and the second reset signal line.

7. The display panel according to claim 6, characterized in that: The voltage transmitted by the first power supply voltage signal line is VD1, and the voltage transmitted by the second power supply voltage signal line is VD2, wherein VD1≥VD2.

8. The display panel according to claim 6, characterized in that: The first data signal line and the second data signal line have the same extension direction. In a direction perpendicular to the extension direction of the first data signal line, the width of the first data signal line is W1, and the width of the second data line is W2, wherein W1≥W2.

9. The display panel according to claim 1, characterized in that: The plurality of sub-display areas are arranged in a row-column matrix; The first driving circuits corresponding to all the sub-display areas in the same column are electrically connected to the same first data signal line.

10. The display panel according to claim 9, characterized in that: comprising a plurality of first data signal line groups, wherein the first data signal line group comprises X first data signal lines, where X is greater than or equal to 2 and is an integer; The display panel further includes a plurality of multiplexer units, X switch control lines and a plurality of data source lines; the multiplexer unit includes X switch elements, and the switch element includes a control end, an input end and an output end; the input ends of the X switch elements of the same multiplexer unit are electrically connected to the same data source line, and the multiplexer unit is connected to the data source line in a one-to-one correspondence; the control ends of the X switch elements of the multiplexer unit are connected to the X switch control lines in a one-to-one correspondence; the output ends of the X switch elements of the multiplexer are connected to the X first data signal lines in a one-to-one correspondence.

11. The display panel according to claim 1, characterized in that: The plurality of sub-display areas are arranged in a matrix of rows and columns, and the first driving circuits corresponding to all the sub-display areas in the same row are electrically connected to the same first scanning signal line.

12. The display panel according to claim 1, characterized in that: Also comprising a non-display area, the non-display area at least partially surrounding the display area; The non-display area includes a plurality of first shift registers, and one of the first shift registers is electrically connected to at least one of the first scanning signal lines.

13. The display panel according to claim 12, characterized in that: The first shift registers are all located on the same side of the display area, or are respectively located on both sides of the display area.

14. The display panel according to claim 12, characterized in that: Also comprising a second scanning signal line, wherein the second scanning signal line is electrically connected to the second driving circuit; The first shift register is electrically connected to the second scanning signal line.

15. The display panel according to claim 1, characterized in that: The sub-display area includes a first sub-display area and a second sub-display area, the first sub-display area includes M1 rows×N1 columns of the driving circuit, the second sub-display area includes M2 rows×N2 columns of the driving circuit, M1≥2, N1≥2, M2≥2, N2≥2 and M1, N1, M2, N2 are all integers, M1≥M2, N1≥N2.

16. The display panel according to claim 1, characterized in that: include A plurality of drive circuit rows arranged along a direction perpendicular to the extension direction of the first scanning signal line, the drive circuit rows comprising a first drive circuit row and a second drive circuit row, the first drive circuit being located in the first drive circuit row, and the second drive circuit being located in the second drive circuit row; and / or, a plurality of drive circuit columns arranged in parallel with the extending direction of the first scanning signal line, the drive circuit columns comprising a first drive circuit column and a second drive circuit column, the first drive circuit being located in the first drive circuit column, and the second drive circuit being located in the second drive circuit column; and / or, a plurality of drive circuit rows arranged along a direction perpendicular to the extension direction of the first scanning signal line, the drive circuit rows including the first drive circuit and the second drive circuit; And / or, a plurality of drive circuit columns are arranged along an extension direction parallel to the first scan line, and the drive circuit columns include the first drive circuit and the second drive circuit.

17. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 16.

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