On-chip terminal control circuit and memory

Abstract

The invention provides an on-chip terminal control circuit and a memory. The on-chip terminal control circuit includes a decoder, a mode signal generation circuit, and a control signal generation circuit. The decoder is used for receiving the command / address signal, decoding the command / address signal in a first clock period after a chip selection signal corresponding to the command / address signal is in an effective level, and generating an on-chip terminal command signal; the mode signal generation circuit is used for receiving the chip selection signal and an external clock signal, sampling a level value of a second clock period after the chip selection signal is at an effective level based on the external clock signal, and generating an on-chip terminal mode signal; the control signal generation circuit is coupled with the decoder and the mode signal generation circuit, and is used for receiving the on-chip terminal command signal and the on-chip terminal mode signal, and generating an on-chip terminal control signal according to the on-chip terminal command signal and the on-chip terminal mode signal. According to the embodiment of the invention, the delay time of ODT signal output can be shortened.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to an on-chip terminal control circuit and a memory using the on-chip terminal control circuit. Background Art

[0002] On-Die Termination (ODT) technology is used to match the terminal impedance of DRAM signals to the output impedance of the memory storage to eliminate interference and distortion caused by signal reflection, providing better signal integrity and reliability for high-speed memory systems.

[0003] In DDR5, the ODT signal is generated according to a write command in target mode, a write command in non-target mode, or a read command in non-target mode. When designing the circuit, it is necessary to match the generation and transmission path of the ODT signal (ODT path for short) with the DLL path. Among them, DLL (Delay Locked Loop) is a clock synchronization technology. In DDR5 memory, DLL generates a phase difference through a feedback line and returns the phase difference to the input reference clock. It synchronizes according to the feedback phase difference or signal delay to ensure synchronization between the input and output clocks and prevent clock offset and timing distortion in the memory system. The timing of the DLL path needs to be consistent with the timing of the memory controller, ODT, and DRAM memory to achieve high-speed data transmission and higher memory bandwidth.

[0004] In the related art, the delay time of the ODT path is much longer than that of the DLL path. Therefore, shortening the delay time of the ODT path is a difficult problem in DDR5 circuit design.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The object of the present disclosure is to provide an on-chip termination control circuit and a memory, which are used to shorten the generation of an ODT signal in the memory and the delay time of the transmission path.

[0007] According to a first aspect of the present disclosure, an on-chip terminal control circuit is provided, which is applied to a memory, and the on-chip terminal control circuit includes: a decoder, which is used to receive a command / address signal, and decode the command / address signal within the first clock cycle after receiving a chip select signal corresponding to the command / address signal, to generate an on-chip terminal command signal; a mode signal generating circuit, which is used to receive a chip select signal and an external clock signal, and sample and detect the pulse width of the chip select signal based on the external clock signal to generate an on-chip terminal mode signal; wherein the on-chip terminal mode signal indicates that the memory is in a target ODT mode or a non-target ODT mode; a control signal generating circuit, which is coupled to the decoder and the mode signal generating circuit, and is used to receive an on-chip terminal command signal and an on-chip terminal mode signal, and generate an on-chip terminal control signal according to the on-chip terminal command signal and the on-chip terminal mode signal, so that the memory performs a corresponding ODT operation according to the on-chip terminal control signal.

[0008] In an exemplary embodiment of the present disclosure, when the pulse width of the chip select signal detected by sampling is one clock cycle of an external clock signal, the on-chip terminal mode signal indicates that the memory is in the target ODT mode; when the pulse width of the chip select signal detected by sampling is two clock cycles of the external clock signal, the on-chip terminal mode signal indicates that the memory is in the non-target ODT mode.

[0009] In an exemplary embodiment of the present disclosure, a mode signal generating circuit includes: a signal buffer, for receiving a chip select signal, and driving and amplifying the chip select signal and then outputting it; a signal identifier, connected to the signal buffer, for receiving the driven and amplified chip select signal, the signal identifier being used to output an on-chip terminal mode signal in a first state to indicate that the memory is in a target ODT mode when it is determined that the pulse width of the chip select signal is only a clock cycle of an external clock signal, and to output an on-chip terminal mode signal in a second state to indicate that the memory is in a non-target ODT mode when it is determined that the pulse width of the chip select signal is two clock cycles of the external clock signal.

[0010] In an exemplary embodiment of the present disclosure, the signal identifier includes: a first sampling unit, a signal input end of the first sampling unit is used to receive a chip select signal after driving and amplification, a clock input end of the first sampling unit is used to receive an odd clock signal, and the first sampling unit samples the level value of the chip select signal based on the odd clock signal within a clock cycle of a first external clock signal after receiving the chip select signal and then outputs it; a second sampling unit, a signal input end of the second sampling unit is connected to the signal input end of the first sampling unit, and is used to receive the chip select signal after driving and amplification, and the clock input end of the second sampling unit is used to receive an even clock signal, and the second sampling unit samples the level value of the chip select signal within a clock cycle of a second external clock signal after receiving the chip select signal and then outputs it; wherein the frequency of the even clock signal and the odd clock signal is half of the external clock signal, and the even clock signal is an inverted signal of the odd clock signal; a logic processing unit is connected to the first sampling unit and the second sampling unit, respectively, and is used to perform logic processing on the sampling results of the first sampling unit and the second sampling unit and then output an on-chip terminal mode signal of a first state or a second state.

[0011] In an exemplary embodiment of the present disclosure, the first sampling unit and the second sampling unit are both implemented by a D flip-flop, and the logic processing unit includes: an NOR gate, wherein two input ends of the NOR gate are respectively connected to the output end of the first sampling unit and the output end of the second sampling unit; an SR latch, wherein the first input end of the SR latch is connected to the output end of the NOR gate, the second input end of the SR latch is used to receive a reset signal, and the output end of the SR latch is used to output an on-chip terminal mode signal.

[0012] In an exemplary embodiment of the present disclosure, the logic processing unit also includes: a clock counter, wherein the first input terminal of the clock counter is used to receive a command / address signal, the second input terminal of the clock counter is used to receive an external clock signal, and the clock counter is used to count the clock cycle of the external clock signal after the command / address signal is in a valid state, and when the count value of the clock cycle reaches a preset value, output a reset signal in a valid state through the output terminal.

[0013] In an exemplary embodiment of the present disclosure, the decoder is further configured to generate an internal read / write command signal based on the command / address signal, and the control signal generation circuit determines the category of the on-chip terminal command signal according to the internal read / write command signal.

[0014] In an exemplary embodiment of the present disclosure, the on-chip terminal control signal includes a non-target read ODT signal, a non-target write ODT signal, and a target write ODT signal, and the control signal generating circuit includes: a logic unit having an input end, two control ends, and three output ends, the input end of the logic unit is used to receive an on-chip terminal command signal, the two control ends of the logic unit are used to receive an on-chip terminal mode signal and an internal read / write command signal, and the logic unit outputs the on-chip terminal command signal from one of the three output ends in response to the internal read / write command signal and the on-chip terminal mode signal; a signal processing unit is respectively connected to the three output ends of the logic unit, and is used to process the on-chip terminal command signal according to the output end that outputs the on-chip terminal command signal, so as to output one of the non-target read ODT signal, the non-target write ODT signal, and the target write ODT signal.

[0015] In an exemplary embodiment of the present disclosure, the logic unit includes: a read on-chip terminal command strobe unit, the input end of which is used to receive an on-chip terminal command signal, the control end of which is used to receive an internal read / write command signal, and is used to output the on-chip terminal command signal as a read on-chip terminal command signal when the internal read / write command signal indicates that a read operation is to be performed; a write on-chip terminal command strobe unit, the input end of which is used to receive an on-chip terminal command signal, the control end of which is used to receive an internal read / write command signal, and is used to output the on-chip terminal command signal as a write on-chip terminal command signal when the internal read / write command signal indicates that a write operation is to be performed; a first selector, having an input end, a control end, a first output end, and a second output end, the input end of the first selector receiving the read on-chip terminal command signal, the control end of the first selector receiving the on-chip terminal mode signal; the first selector is used to output the read on-chip terminal command signal as a write on-chip terminal command signal when the on-chip terminal mode signal indicates that a non-target ODT mode is to be performed. The on-chip terminal command signal is output from its first output terminal as a non-target read ODT initial signal; wherein, the first output terminal of the first selector is the first output terminal of the logic unit; the second selector has an input terminal, a control terminal, a first output terminal and a second output terminal, the input terminal of the second selector receives the write on-chip terminal command signal, and the control terminal of the second selector receives the on-chip terminal mode signal; the second selector is used to output the write on-chip terminal command signal as a non-target write ODT initial signal from its first output terminal when the on-chip terminal mode signal indicates that it is in a non-target ODT mode; the second selector is also used to output the write on-chip terminal command signal as a target write ODT initial signal from its second output terminal when the on-chip terminal mode signal indicates that it is in a target ODT mode; wherein, the first output terminal of the second selector is the second output terminal of the logic unit, and the second output terminal of the second selector is the third output terminal of the logic unit.

[0016] In an exemplary embodiment of the present disclosure, the signal processing unit includes three signal processing sub-units, which are connected to the three output ends of the logic unit one by one, and are respectively used to receive a non-target read ODT initial signal, a non-target write ODT initial signal, and a target write ODT initial signal, and after performing pulse width adjustment and offset calibration on the non-target read ODT initial signal, the non-target write ODT initial signal, and the target write ODT initial signal, the non-target read ODT signal, the non-target write ODT signal, and the target write ODT signal are correspondingly output.

[0017] In an exemplary embodiment of the present disclosure, the decoder includes: a buffer for receiving and buffering command / address signals according to an external clock signal; and a command decoder connected to the buffer for decoding the command / address signals to generate an on-chip terminal command signal.

[0018] According to a second aspect of the present disclosure, a memory is provided, comprising the on-chip termination control circuit as described in any one of the above items.

[0019] The disclosed embodiment uses a chip select signal to determine whether the current command / address signal corresponds to a non-target ODT mode or a target ODT mode, and then processes the on-chip terminal command signal output by the decoder through a control signal generation circuit, and executes the judgment of the command / address signal in parallel, thereby improving the output speed of the on-chip terminal control signal (ODT control signal) and reducing the delay time of the ODT path.

[0020] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0022] Figure 1 Schematic diagram of the structure of an on-chip terminal control circuit in an exemplary embodiment of the present disclosure.

[0023] Figure 2 Schematic diagram of a chip select signal in one embodiment of the present disclosure.

[0024] Figure 3 Schematic diagram of a mode signal generating circuit in one embodiment of the present disclosure.

[0025] Figure 4It is a schematic diagram of a signal identifier in one embodiment of the present disclosure.

[0026] Figure 5 It is a schematic diagram of a logic processing unit in one embodiment of the present disclosure.

[0027] Figure 6 yes Figure 5 Timing diagram of the logical processing unit shown.

[0028] Figure 7 is a schematic diagram of a logic processing unit in another embodiment of the present disclosure.

[0029] Figure 8 It is a schematic diagram of a signal identifier in another embodiment of the present disclosure.

[0030] Fig. 9 yes Figure 8 Timing diagram of the signal identifier shown.

[0031] Fig.10 is a schematic diagram of a control signal generating circuit in one embodiment of the present disclosure.

[0032] Fig.11 is a schematic diagram of a logic unit in one embodiment of the present disclosure.

[0033] Fig.12 is a circuit diagram of a gate in one embodiment of the present disclosure.

[0034] Fig.13 is a schematic diagram of a decoder in one embodiment of the present disclosure.

[0035] Fig.14 Schematic diagram of an on-chip terminal control circuit in one embodiment of the present disclosure.

[0036] Fig.15 1 is a diagram showing the difference in timing of on-chip terminal command signals before and after applying the embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0038] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0039] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0040] Figure 1 Schematic diagram of the structure of an on-chip terminal control circuit in an exemplary embodiment of the present disclosure.

[0041] refer to Figure 1 , the on-chip termination control circuit 100 may include:

[0042] Decoder 1, for receiving a command / address signal CA, and decoding the command / address signal CA in a first clock cycle after a chip select signal CS corresponding to the command / address signal CA is at a valid level, to generate an on-chip terminal command signal CODT;

[0043] A mode signal generating circuit 2 is used for receiving a chip select signal CS and an external clock signal CLK, and sampling a level value of a second clock cycle after the chip select signal CS is at a valid level based on the external clock signal CLK, to generate an on-chip terminal mode signal S0; wherein the on-chip terminal mode signal S0 indicates that the memory is in a target ODT mode or a non-target ODT mode;

[0044] The control signal generating circuit 3 is coupled to the decoder 1 and the mode signal generating circuit 2, and is used to receive the on-chip terminal command signal CODT and the on-chip terminal mode signal S0, and generate the on-chip terminal control signal SODT according to the on-chip terminal command signal CODT and the on-chip terminal mode signal S0, so as to perform the corresponding ODT operation according to the on-chip terminal control signal SODT.

[0045] In DDR5 technology, the memory controller sends a chip select signal CS and a command / address signal CA to the memory (DRAM). The chip select signal CS carries read / write command tag information, which is used to identify whether the read / write command in the command / address signal CA belongs to a non-target read / write command or a target read / write command. Among them, the non-target read / write command includes a non-target write command and a non-target read command, and the target read / write command includes a target write command.

[0046] Non-target write is the opposite of target write. Target write refers to writing data to a memory address, while non-target write refers to writing data to other memory areas that are not the target address. In DDR5 memory, non-target write can be used to pre-start the data transfer for the next access to improve the efficiency of data exchange. At the same time, since the data in the memory can be processed in other areas, non-target write also helps reduce the demand for memory access bandwidth and improve the overall performance of the memory system.

[0047] Non-target read commands can read other associated locations at the same time as memory reads, without having to wait for the next target address to be transmitted, thereby improving memory read efficiency, reducing the memory bus bandwidth usage, and improving overall memory performance. Through non-target read technology, DDR5 memory can provide higher throughput at the same clock frequency, more than 50% higher than DDR4 memory.

[0048] Figure 2 Schematic diagram of a chip select signal in one embodiment of the present disclosure.

[0049] refer to Figure 2 In one embodiment, when the read / write command in the command / address signal CA belongs to a non-target read / write command, the chip select signal CS (marked as CS_NT) occupies two clock cycles of the external clock signal CLK, namely the first clock cycle T1 and the second clock cycle T2; when the read / write command in the command / address signal CA belongs to a target read / write command, the chip select signal CS (marked as CS_T) occupies one clock cycle of the external clock signal CLK, namely the first clock cycle T1.

[0050] exist Figure 2 In the illustrated embodiment, the effective state of the chip select signal CS is a low level. In other embodiments, the chip select signal CS may also be in other forms. As long as the chip select signal CS carries the read and write command mark information through the number of occupied clock cycles, the technical solutions of the disclosed embodiments may be applied.

[0051] The disclosed embodiment judges the chip select signal CS by using the mode signal generating circuit 2, and outputs an on-chip terminal mode signal S0 for indicating that the memory is in the target ODT mode or the non-target ODT mode. When the pulse width of the chip select signal CS detected by sampling is one clock cycle of an external clock signal, the on-chip terminal mode signal S0 indicates that the memory is in the target ODT mode; when the pulse width of the chip select signal CS detected by sampling is two clock cycles of the external clock signal, the on-chip terminal mode signal S0 indicates that the memory is in the non-target ODT mode.

[0052] The control signal generating circuit 3 processes the on-chip terminal command signal CODT output by the decoder 1 according to the on-chip terminal mode signal S0 to output an on-chip terminal control signal SODT, wherein the on-chip terminal control signal SODT can be divided into three types: non-target read ODT signal, non-target write ODT signal, and target write ODT signal.

[0053] The improvement principle is introduced in detail below.

[0054] Figure 3 Schematic diagram of a mode signal generating circuit in one embodiment of the present disclosure.

[0055] refer to Figure 3 In one embodiment, the mode signal generating circuit 2 may include:

[0056] The signal buffer 21 is used to receive the chip selection signal CS, drive and amplify the chip selection signal and then output it;

[0057] The signal identifier 22, whose input end is connected to the signal buffer 21, is used to receive the chip select signal CS after the drive amplification. The signal identifier 22 is used to determine how many clock cycles the pulse width of the chip select signal CS is, and when it is determined that the pulse width of the chip select signal CS is only one clock cycle, it outputs the on-chip terminal mode signal S0 in the first state, and when it is determined that the pulse width of the chip select signal CS is two clock cycles, it outputs the on-chip terminal mode signal S0 in the second state. If not specifically emphasized later, the clock cycle refers to the clock cycle of the external clock signal CLK.

[0058] The signal buffer 21 (buffer) is used to adjust the timing of the chip select signal CS and drive it to be amplified and then output, so that the chip select signal CS is aligned to the clock edge of the circuit, ensuring that the chip select signal CS is in the correct clock cycle. Therefore, the signal buffer 21 also receives the external clock signal CLK. In addition, the signal buffer 21 can amplify the chip select signal CS to increase its level change rate, reduce the impact of clock jitter on the signal, etc., and adjust the amplitude of the signal to ensure the reliability of the chip select signal CS. Finally, the signal buffer 21 can protect the subsequent circuit from the influence of the external environment, such as temperature changes, electromagnetic signal interference and other problems. At the same time, an isolation area can be introduced to protect the device from the influence of electrostatic discharge and voltage fluctuations, ensure the signal transmission timing of the chip select signal CS is accurate, reduce the bit error rate, and improve the reliability of the system. The signal buffer 21 can be implemented by a variety of circuits, which will not be repeated in this disclosure.

[0059] It can be understood that the signal output by the signal buffer 21 is the chip select signal CS after adjustment and optimization, which is the same signal as the received chip select signal CS but has different signal quality. Subsequently, the signal output by the signal buffer 21 is still referred to as the chip select signal CS.

[0060] The signal identifier 22 can identify the duration of the effective state (e.g., the low level described above) of the chip select signal CS after the drive amplification output by the signal buffer 21. In one embodiment, the signal identifier 22 uses the odd clock signal CLKE and the even clock signal CLKO to identify the duration of the effective state of the chip select signal CS.

[0061] Figure 4 is a schematic diagram of a signal identifier 22 in one embodiment of the present disclosure.

[0062] refer to Figure 4 In one embodiment, the signal identifier 22 may include:

[0063] A first sampling unit 221, wherein the signal input terminal of the first sampling unit 221 is used to receive the chip selection signal CS, and the clock input terminal of the first sampling unit 221 is used to receive the odd clock signal CLKE, and is used to sample the level value of the chip selection signal CS based on the odd clock signal CLKE within the first clock cycle T1 and then output it;

[0064] A second sampling unit 222, wherein the signal input end of the second sampling unit 222 is used to receive the chip select signal CS, and the clock input end of the second sampling unit 222 is used to receive the even clock signal CLKO, and is used to sample the level value of the chip select signal CS based on the even clock signal CLKO in the second clock cycle T2 and then output it;

[0065] The logic processing unit 223 is connected to the output end of the first sampling unit 221 and the output end of the second sampling unit 222, and is used to output the on-chip terminal mode signal S0 of the first state or the second state after performing logic processing based on the sampling results of the first clock cycle T1 and the second clock cycle T2.

[0066] In one embodiment, the first sampling unit 221 and the second sampling unit 222 are both implemented by a D flip-flop. The D flip-flop has a data input terminal D, a clock input terminal and an output terminal Q. When the level rising edge of the clock input signal arrives, the output terminal Q of the D flip-flop will save the current signal state in a flip-flop element called a memory unit according to the level state of its input terminal D. Since the D flip-flop is a synchronous flip-flop, the input signal can only be recorded when the rising edge of the clock signal arrives, so the stability and reliability of the timing circuit can be ensured.

[0067] exist Figure 4 In the illustrated embodiment, the clock input terminal of the D flip-flop of the first sampling unit 221 receives the odd clock signal CLKE (CLK Even) to sample the chip select signal CS in the first clock cycle T1; the clock input terminal of the D flip-flop of the second sampling unit 222 receives the even clock signal CLKO (CLK Odd) to sample the chip select signal CS in the second clock cycle T2.

[0068] The types of clock signals in DDR5 can include the usual external clock signal CLK, and the odd clock signal CLKE and the even clock signal CLKO generated according to the odd and even bits of the external clock signal CLK, wherein the frequencies of the even clock signal CLKO and the odd clock signal CLKE are both half of the external clock signal CLK, and the even clock signal CLKO is the inverted signal of the odd clock signal CLKE. The DDR5 memory clock frequency is already very high, reaching 4800MT / s. In order to ensure sufficient signal stability and electrical performance, the amount of data that needs to be transmitted at the same time needs to be reduced. Dividing the clock signal into even and odd bits can reduce the mutual interference of clock signals on different bits, thereby improving the accuracy and reliability of the timing circuit. In addition, the clock signal speed of DDR5 works at double the frequency, so the frequency of the clock signal can be higher, avoiding the transmission delay of the small signal clock edge, improving the transmission rate and efficiency, increasing the bandwidth of the bus, effectively reducing the delay and waiting time of data transmission, and can improve the memory transmission speed and system performance, reduce power consumption, optimize memory transmission performance, and improve system performance.

[0069] Figure 4The illustrated embodiment uses an odd clock signal CLKE and an even clock signal CLKO to control two sampling units, samples the chip select signal CS within two clock cycles to determine the extension time of the effective state of the chip select signal CS, and can work effectively when the effective state of the chip select signal CS is a low level or a high level, thereby increasing the adaptability of the circuit.

[0070] Figure 5 It is a schematic diagram of a logic processing unit in one embodiment of the present disclosure.

[0071] refer to Figure 5 In one embodiment, the logic processing unit 223 may include:

[0072] A NOR gate NOR, wherein two input terminals of the NOR gate NOR are respectively connected to the output terminal of the first sampling unit 221 and the output terminal of the second sampling unit 222;

[0073] SR latch TG, a first input end of the SR latch TG is connected to the input end of the NOR gate NOR, a second input end of the SR latch TG is used to receive a reset signal, and an output end of the SR latch TG is used to output an on-chip terminal mode signal S0.

[0074] The SR latch TG can be implemented by a flip-flop consisting of two NOR gates.

[0075] Figure 6 yes Figure 5 The following is a timing diagram of the logic processing unit. Figure 6 The timing diagram shown is Figure 5 The working principle of the logical processing unit shown is explained.

[0076] refer to Figure 6 On the left side, when the effective state of the chip select signal CS is low and the chip select signal CS occupies one clock cycle (the first clock cycle T1), the sampling result S211 of the first sampling unit 221 is 0 before the next rising edge of the odd clock signal CLKE arrives, the sampling result S222 of the second sampling unit 222 is always 1, the output signal SNOR of the NOR gate NOR is always 0, and the SR latch TG outputs S0=1 when the reset signal Rst is in the invalid state, that is, the on-chip terminal mode signal S0 of the first state.

[0077] refer to Figure 6On the right side, when the effective state of the chip select signal CS is low level, and the chip select signal CS occupies two clock cycles (the first clock cycle T1 and the second clock cycle T2), the sampling result S221 of the first sampling unit 221 is 0 before the next rising edge of the odd clock signal CLKE arrives, and the sampling result S222 of the second sampling unit 222 is 0 before the next rising edge of the even clock signal CLKO arrives, and the output signal SNOR of the NOR gate NOR is 1 between the rising edge of the even clock signal CLKO and the next rising edge of the odd clock signal CLKE. When the reset signal Rst is in the invalid state, the SR latch TG starts to output S0=0 at the rising edge of the even clock signal CLKO, that is, the on-chip terminal mode signal S0 of the second state. Only when the reset signal Rst is in the effective state, the SR latch TG can re-adjust the state of the on-chip terminal mode signal S0 based on the output signal SNOR of the NOR gate NOR. That is, the reset signal Rst can be used to maintain the state duration of the on-chip terminal mode signal S0.

[0078] Depend on Figure 6 It can be seen from the timing diagram that the on-chip termination mode signal S0 can be output before the end of the second clock cycle after the chip select signal CS is in the valid state, and the signal output speed is very fast.

[0079] In one embodiment, the logic processing unit 223 may further include a circuit for controlling a reset signal Rst.

[0080] Figure 7 is a schematic diagram of a logic processing unit in another embodiment of the present disclosure.

[0081] refer to Figure 7 In another embodiment, the logic processing unit 223 may further include a clock counter CN, wherein the first input terminal of the clock counter CN is used to receive the command / address signal CA, and the second input terminal is used to receive the clock signal CLK. The clock counter CN is used to count the clock cycles of the external clock signal CLK after the command / address signal CA is in a valid state, and when the count value of the clock cycle reaches a preset value, the reset signal Rst in a valid state is output through the output terminal.

[0082] The preset value is, for example, equal to 128. That is, in the 129th clock cycle after the command / address signal CA is in the valid state, the reset signal Rst is in the valid state. Figure 6 As shown in the timing diagram, the state of the on-chip terminal mode signal S0 remains unchanged after the output signal of the NOR gate NOR changes and before the reset signal Rst is in the valid state, so that the control signal generating circuit 3 has enough time to output the on-chip terminal control signal SODT based on the state of the on-chip terminal mode signal S0.

[0083] In other embodiments of the present disclosure, the first input end of the clock counter CN can also receive a chip select signal CS, and count the clock cycles of the external clock signal CLK after the chip select signal CS is in a valid state. When the count value of the clock cycle reaches a preset value, a reset signal Rst in a valid state is output through the output end.

[0084] In addition to sampling the chip select signal CS in two clock cycles, in another embodiment, the signal identifier 22 may sample the chip select signal CS in the second clock cycle (eg, Figure 2 The chip select signal CS is sampled in the second clock cycle T2 (the T2 phase shown). If the sampling result of the chip select signal CS in the second clock cycle T2 shows that the chip select signal CS is in a valid state (e.g., a low level), the signal identifier 22 can output the on-chip terminal mode signal S0 in the second state to indicate that the on-chip terminal command signal CODT belongs to a non-target read / write instruction, or to indicate that the on-chip terminal control signal is in a non-target ODT mode. If the sampling result of the chip select signal CS in the second clock cycle shows that the chip select signal CS is in an invalid state (e.g., a high level), the signal identifier 22 can output the on-chip terminal mode signal S0 in the first state to indicate that the on-chip terminal command signal CODT belongs to a target read / write instruction, or to indicate that the on-chip terminal control signal is in a target ODT mode.

[0085] Figure 8 It is a schematic diagram of a signal identifier in another embodiment of the present disclosure.

[0086] refer to Figure 8 In another embodiment, the signal identifier 22 may include a second sampling unit 222, an SR latch TG, and an inverter OP. The signal input end of the second sampling unit 222 is used to receive the chip select signal CS, and the clock input end is used to receive the even clock signal CLKO. The second sampling unit 222 samples the chip select signal CS in the second clock cycle T2. The first input end of the SR latch TG is connected to the output end of the second sampling unit 222, and the second input end is used to receive a reset signal. The input end of the inverter OP is connected to the output end of the SR latch TG, and is used to output the on-chip terminal mode signal S0.

[0087] The structure of SR latch TG can be Figure 5 The embodiments shown are the same or may be different. When the structure of the SR latch TG is the same as Figure 5 The embodiment shown in FIG. 1 is the same as that shown in FIG. 1 , and the definitions of the first state and the second state of the on-chip terminal mode signal S0 are also the same as those shown in FIG. Figure 5When the illustrated embodiment is the same, the output end of the SR latch TG may be connected to an odd number of inverters OP to ensure that the first state and the second state of the on-chip termination mode signal S0 correctly correspond to the sampling result of the second sampling unit 222 .

[0088] Fig. 9 yes Figure 8 Timing diagram of the signal identifier shown.

[0089] refer to Fig. 9 ,exist Figure 8 In the illustrated embodiment, when the effective state of the chip select signal CS is a low level and the chip select signal CS occupies one clock cycle (the first clock cycle T1), the sampling result S222 of the second sampling unit 222 is always 1, the output signal STG of the SR latch TG is always 0, and the inverter OP always outputs S0=1, that is, the on-chip terminal mode signal S0 of the first state.

[0090] When the effective state of the chip select signal CS is low level, and the chip select signal CS occupies two clock cycles (the first clock cycle T1 and the second clock cycle T2), the sampling result S222 of the second sampling unit 222 is 0 between the two rising edges of the even clock signal CLKO, and the output signal of the SR latch TG starts to be 1 at the first rising edge of the even clock signal CLKO. At the same time, the inverter OP outputs S0=1, that is, the on-chip terminal mode signal S0 of the second state. When the reset signal Rst is in an invalid state, the output signal state of the SR latch TG remains unchanged; when the reset signal Rst is in a valid state, the SR latch TG can re-adjust the state of the output signal STG based on the sampling result S222 of the second sampling unit 222. Among them, the reset signal Rst can be used to maintain the state duration of the on-chip terminal mode signal S0. The generation circuit of the reset signal Rst can, for example, be Figure 7 The circuit shown.

[0091] Depend on Fig. 9 It can be seen from the timing diagram that the on-chip termination mode signal S0 can be output before the end of the second clock cycle after the chip select signal CS is in the valid state, and the signal output speed is very fast.

[0092] Figure 8 The embodiment shown samples the chip select signal CS only in the second clock cycle T2 after the chip select signal CS is in the valid state, which can save circuit settings, reduce power consumption and layout area. However, this method can only correspond to the situation where the effective state of the chip select signal CS is fixed.

[0093] In the disclosed embodiment, the decoder 1 is further configured to generate an internal read / write command signal RW based on the command / address signal CA, and the control signal generating circuit 3 determines the category of the on-chip terminal command signal CODT according to the internal read / write command signal RW.

[0094] Fig.10 is a schematic diagram of a control signal generating circuit in one embodiment of the present disclosure.

[0095] refer to Fig.10 In one embodiment, the control signal generating circuit 3 may include:

[0096] The logic unit 31 has an input terminal, two control terminals and three output terminals. The input terminal of the logic unit 31 is connected to the decoder 1 for receiving the on-chip terminal command signal CODT. The two control terminals of the logic unit 31 are respectively connected to the decoder 1 and the connection mode signal generating circuit 2 for receiving the internal read / write command signal RW and the on-chip terminal mode signal S0. The logic unit 31 is used to output the on-chip terminal command signal CODT from one of the three output terminals based on the internal read / write command signal RW and the on-chip terminal mode signal S0.

[0097] The signal processing unit 32 is connected to the three output ends of the logic unit 31, and is used to process the on-chip terminal command signal CODT according to the output end of the on-chip terminal command signal CODT to output one of the non-target read ODT signal, the non-target write ODT signal, and the target write ODT signal.

[0098] exist Fig.10 In the illustrated embodiment, the signal processing unit 32 can be respectively connected to the three output ends of the logic unit 31 through three sub-units, namely, a first sub-unit 321, a second sub-unit 322 and a third sub-unit 323, wherein the first sub-unit 321 is used to process the non-target read ODT initial signal output by the logic unit 31, and perform pulse width adjustment and offset calibration on the non-target read ODT initial signal to output the non-target read ODT signal; the second sub-unit 322 is used to process the non-target write ODT initial signal, and perform pulse width adjustment and offset calibration on the non-target write ODT initial signal to output the non-target write ODT signal; the third sub-unit 323 is used to process the target write ODT initial signal, and perform pulse width adjustment and offset calibration on the target write ODT initial signal to output the target write ODT signal.

[0099] The first subunit 321, the second subunit 322 and the third subunit 323 all have a latency shift function and an offset generation function. The latency shift function can dynamically adjust the timing parameters of the DRAM memory to optimize the response speed and data throughput of the memory system. This technology can dynamically adjust the latency of the DRAM memory according to the changes in the memory load, so as to adapt to the access requirements of the memory under different loads and improve the overall performance and response speed of the memory system. Specifically, the latency shift function can improve the read performance by reducing the read latency of the DRAM memory, or improve the write performance by increasing the latency. In addition, the latency shift function can also adjust the functions of the write corridor and the read corridor of the memory system according to the changes in the CPU load. By dynamically adjusting the memory latency, the latency shift function can improve the flexibility and adaptability of the memory system, thereby optimizing the memory access performance and improving the overall efficiency and reliability of the system. The offset generation function is used to generate an offset in a memory access command. An offset is a pointer value that indicates the difference between a memory address and the location of read and write data. When the CPU requests to read or write data at a relative address, the offset is added to the memory base address to derive the actual physical address. Since DDR5 memory is typically high-density and high-speed, offsets need to be processed frequently when processing large amounts of data in order to achieve the corresponding memory access latency. Using the offset generation function can reduce the CPU burden and improve memory access performance and efficiency. At the same time, the offset generation function can help create efficient address mapping tables to optimize stack management and page table access of memory storage, improving memory system performance and reliability.

[0100] When the type of the internal read / write command signal RW is different and the state of the on-chip terminal mode signal S0 is different, the logic unit 31 will only output the on-chip terminal command signal CODT through one output terminal at a time, that is, for one CA signal transmission, only one of the first subunit 321, the second subunit 322 and the third subunit 323 will receive the on-chip terminal command signal CODT, and process and output the on-chip terminal command signal CODT. The subunits that process the on-chip terminal command signal CODT are different, and the output paths of the on-chip terminal control signal SODT output by the control signal generating circuit 3 are different, thereby indicating that the types of the on-chip terminal control signal SODT are different.

[0101] Fig.11 is a schematic diagram of a logic unit in one embodiment of the present disclosure.

[0102] refer to Fig.11 In one embodiment, the logic unit 31 may include:

[0103] A read on-chip terminal command strobe unit 311, whose input end is used to receive an on-chip terminal command signal CODT, and whose control end is used to receive an internal read / write command signal RW, and is used to output the on-chip terminal command signal CODT as a read on-chip terminal command signal R-CODT when the internal read / write command signal RW indicates to perform a read operation;

[0104] A write on-chip terminal command strobe unit 312, whose input end is used to receive an on-chip terminal command signal CODT, and whose control end is used to receive an internal read / write command signal RW, and is used to output the on-chip terminal command signal CODT as a write on-chip terminal command signal W-CODT when the internal read / write command signal RW indicates to perform a write operation;

[0105] The first selector 313 has an input end, a control end, a first output end, and a second output end. The input end of the first selector 313 receives the on-chip terminal command signal R-CODT, and the control end of the first selector 313 receives the on-chip terminal mode signal S0. The first selector 313 is used to output the on-chip terminal command signal R-CODT as a non-target read ODT initial signal from its first output end when the on-chip terminal mode signal S0 indicates that the on-chip terminal mode is in a non-target ODT mode. The first output end of the first selector 313 is the first output end of the logic unit 31.

[0106] The second selector 314 has an input end, a control end, a first output end and a second output end. The input end of the second selector 314 receives the write-on-chip terminal command signal W-CODT, and the control end of the second selector receives the on-chip terminal mode signal S0. The second selector 314 is used to output the write-on-chip terminal command signal W-CODT as a non-target write ODT initial signal from its first output end when the on-chip terminal mode signal S0 indicates that it is in a non-target ODT mode. The second selector 314 is also used to output the write-on-chip terminal command signal W-CODT as a target write ODT initial signal from its second output end when the on-chip terminal mode signal S0 indicates that it is in a target ODT mode. The first output end of the second selector 314 is the second output end of the logic unit 31, and the second output end of the second selector 314 is the third output end of the logic unit 31.

[0107] Among them, the on-chip terminal mode signal S0 is used to control whether the first selector 313 outputs the read on-chip terminal command signal R-CODT to the signal processing unit 32, or to control the second selector 314 to output the write on-chip terminal command signal W-CODT to the signal processing unit 32 through the first input end of the second selector 314 or the second output end of the second selector.

[0108] When the internal read / write command signal RW is a read command, the read on-chip terminal command selection unit 311 transcodes the on-chip terminal command signal CODT and outputs the read on-chip terminal command signal R-CODT, such as performing burst length generation (BLG). BLG is an important function in the DDR5 memory controller, which is used to generate the Burst Length information in the memory command. Burst Length refers to the number of data blocks contained in the continuously transmitted data of the memory data channel. BLG dynamically generates the optimal Burst Length information according to the specific data pattern requested by the processor by reading the memory mapping table in the memory to optimize the access efficiency and response speed of the memory system. Since the use of Burst Length can merge multiple memory access requests together, the number of transmissions of the memory bus can be greatly reduced, thereby greatly improving the transmission efficiency and bandwidth of the memory. In addition, by using the BLG function, the latency of the memory bus can also be reduced, making memory access faster and more efficient.

[0109] The on-chip terminal command enable unit 311 performs BLG, mainly to widen the pulse width of the on-chip terminal command signal CODT, because the burst length requires serial reading / writing of a string of data, and it is necessary to ensure that when reading / writing a string of data, the corresponding ODT signal should remain valid, that is, it is necessary to ensure sufficient pulse width.

[0110] Correspondingly, the first selector 313 can receive the input signal (read on-chip terminal command signal R-CODT), and the second selector 314 cannot receive the input signal (write on-chip terminal command signal W-CODT). Since the control end of the first selector 313 is connected to the output end of the mode signal generating circuit 2, when the on-chip terminal mode signal S0 is in the first state (S0=1, indicating a non-target read / write mode), the first selector 313 outputs the received read on-chip terminal command signal R-CODT through the first output end; when the on-chip terminal mode signal S0 is in the second state (S0=0, indicating a target read / write mode), the first selector 313 can output the read on-chip terminal command signal R-CODT through its second output end, but since the signal of the target read mode does not need to be processed in this link, the second output end of the first selector 313 is vacant.

[0111] When the internal read / write command signal RW is a write command, the write on-chip terminal command strobe unit 312 transcodes the on-chip terminal command signal CODT and outputs the write on-chip terminal command signal W-CODT), for example, performing a burst length generation process. Correspondingly, the first strobe 313 cannot receive the input signal (the read on-chip terminal command signal R-CODT), and the second strobe 314 can receive the input signal (the write on-chip terminal command signal W-CODT). Since the control end of the second selector 314 is connected to the output end of the mode signal generating circuit 2, when the on-chip terminal mode signal S0 is in the first state (S0=1, indicating a non-target read / write mode), the second selector 314 outputs the received write on-chip terminal command signal W-CODT through its first output end to indicate that the write on-chip terminal command signal W-CODT is a signal of a non-target write mode; when the on-chip terminal mode signal S0 is in the second state (S0=0, indicating a target read / write mode), the second selector 314 outputs the received write on-chip terminal command signal W-CODT through its second output end to indicate that the write on-chip terminal command signal W-CODT is a signal of a target write mode.

[0112] The write-on-chip terminal command strobe unit 312 performs BLG, which is mainly to widen the pulse width of the on-chip terminal command signal CODT, which is the same as the read-on-chip terminal command strobe unit 311 and will not be described in detail.

[0113] The signal processing unit 32 uses different sub-units to process the signal according to different ports of the received signal, so as to output an on-chip terminal control signal SODT.

[0114] Fig.12 is a circuit diagram of a gate in one embodiment of the present disclosure. Fig.11 In the embodiment shown, the first gate 313 and the second gate 314 can both be used. Fig.12 This is achieved by the gate structure shown.

[0115] refer to Fig.12 The gate 1200 includes a first AND gate A1, a second AND gate A2 and an inverting unit O1, wherein the first input terminals of the first AND gate A1 and the second AND gate A2 both receive an input signal S, the second input terminal of the first AND gate A1 receives a control signal CON, and the second input terminal of the second AND gate A2 receives an inverted signal \CON of the control signal CON processed by the inverting unit O1. The inverting unit O1 can be implemented by any circuit having a signal inverting function.

[0116] When the control signal CON is 1, the signal at the second input terminal of the first AND gate A1 is 1, and the output signal of the first AND gate A1 changes with the input signal S; the signal at the second input terminal of the second AND gate A2 is 0 output by the inverting unit O1, and the second AND gate A2 always outputs 0. In this case, when a high-level pulse appears in the input signal S, the high-level pulse can be output through the output terminal of the first AND gate A1, while no pulse is output at the output terminal of the second AND gate A2.

[0117] When the control signal CON is 0, the signal at the second input terminal of the first AND gate A1 is 0, and the output signal of the first AND gate A1 is always 0; the signal at the second input terminal of the second AND gate A2 is 1 output by the inverting unit O1, and the output signal of the second AND gate A2 changes with the input signal S. In this case, when a high-level pulse appears in the input signal S, the high-level pulse can be output through the output terminal of the second AND gate A2, while no pulse is output at the output terminal of the first AND gate A1.

[0118] Therefore, by setting the value of the control signal CON to be different, the output signal S can be set to be output from a certain output terminal of the gate 1200 (the output terminal of the first AND gate A1 or the output terminal of the second AND gate A2) to achieve signal gating.

[0119] Apart from Fig.12 The circuit shown can also realize the selector by two transmission gates. For example, the input ends of the first transmission gate and the second transmission gate are both set to receive the input signal S, and the control signals of the first transmission gate and the second transmission gate are set to be inverted. Then, when the control signal is a first value, the first transmission gate can output the signal S, and the second transmission gate has no output signal; when the control signal is a second value, the second transmission gate can output the signal S, and the first transmission gate has no output signal. In this embodiment, one input end of the transmission gate is in a high impedance state, and there is no output signal.

[0120] There are many ways to implement the transmission gate, and those skilled in the art can set it according to actual conditions, and the present disclosure does not impose any special restrictions on this.

[0121] Fig.13 is a schematic diagram of a decoder in one embodiment of the present disclosure.

[0122] refer to Fig.13 In one embodiment, the decoder 1 may include:

[0123] The buffer 11 is used for receiving and buffering the command / address signal CA according to the external clock signal CLK;

[0124] The command decoder 12 is connected to the output end of the buffer 11 and is used for decoding the command / address signal CA to generate an on-chip terminal command signal CODT.

[0125] Among them, the buffer 11 can be divided into a command / address signal buffer 111 and an external clock signal buffer 121 to adjust and optimize the command / address signal CA and the external clock signal CLK; the decoding trigger 12 is composed of a plurality of parallel D flip-flops (DFFs), which receive and buffer the command / address signal CA according to the external clock signal CLK; the command decoder 12 determines whether the command / address signal CA corresponds to a write command or a read command, and based on the decoding result, generates and outputs an internal read / write command signal RW while generating an on-chip terminal command signal CODT, and the internal read / write command signal RW indicates whether the on-chip terminal command signal CODT is a read type or a write type, so as to provide Fig.11 The read on-chip terminal command strobe unit 311 and the write on-chip terminal command strobe unit 312 are shown to perform further processing.

[0126] Different from the related art, the decoder 1 of the embodiment of the present disclosure is not provided with the function of distinguishing whether the on-chip terminal command signal CODT belongs to a non-target read / write command or a target read / write command. Therefore, the decoder 1 can speed up the output of the on-chip terminal command signal CODT and improve the output speed of the overall on-chip terminal control signal SODT.

[0127] Fig.14 Schematic diagram of an on-chip terminal control circuit in one embodiment of the present disclosure. Fig.14 In the embodiment shown, the Fig.13 The decoder 1 of the embodiment shown, Figure 7 The mode signal generating circuit 2 of the embodiment shown and Fig.11 The control signal generating circuit 3 is shown.

[0128] In other embodiments of the present disclosure, the decoder 1 may also include other structures. For example, the command decoder 12 in the decoder 1 may be implemented in a variety of known ways; the control signal generating circuit 3 may also be implemented in addition to Fig.11 For implementations of other logic circuits other than the logic circuit 31 shown, a variety of logic circuits can be constructed according to the logic according to the embodiment of the present disclosure, as long as the following logic is satisfied: when the on-chip terminal mode signal S0 is in the second state and the internal read / write command signal RW is of the read type, the control signal generating circuit 3 can output a non-target read ODT signal; when the on-chip terminal mode signal S0 is in the second state and the internal read / write command signal RW is of the write type, the control signal generating circuit 3 can output a non-target write ODT signal; when the on-chip terminal mode signal S0 is in the first state and the internal read / write command signal RW is of the write type, the control signal generating circuit 3 can output a target write ODT signal.

[0129] Fig.15 1 is a diagram showing the difference in timing of on-chip terminal command signals before and after applying the embodiment of the present disclosure.

[0130] refer to Fig.15 On the left, before the embodiment of the present disclosure is applied, the on-chip terminal command signal CODT is output in the first clock cycle after the command / address signal CA is completely output; Fig.15 On the right side, after applying the embodiment of the present disclosure, the on-chip terminal command signal CODT is output in the second clock cycle when the command / address signal CA is at a valid level, and the output timing of the on-chip terminal command signal CODT is accelerated by one clock cycle.

[0131] For the subsequent control signal generating circuit 3, the received on-chip terminal command signal CODT is earlier, and the formation of the on-chip terminal mode signal S0 does not occupy the time for the control signal generating circuit 3 to process the signal. Therefore, the control signal generating circuit 3 can output an earlier on-chip terminal control signal SODT based on the earlier on-chip terminal command signal CODT, so as to control the subsequent ODT operation earlier, shorten the ODT path delay time, make the ODT path delay and the DLL path delay more matched, and optimize the overall timing of the memory.

[0132] According to a second aspect of the present disclosure, a memory is provided, using the on-chip termination control circuit of any of the above embodiments. The memory provided by the embodiment of the present disclosure has better timing matching performance.

[0133] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0134] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. An on-chip terminal control circuit, characterized in that: Applied to memory, including: A decoder, for receiving a command / address signal, and decoding the command / address signal within a first clock cycle after receiving a chip select signal corresponding to the command / address signal, to generate an on-chip terminal command signal; A mode signal generating circuit, configured to receive the chip select signal and an external clock signal, and sample and detect the pulse width of the chip select signal based on the external clock signal to generate an on-chip terminal mode signal; wherein the on-chip terminal mode signal indicates that the memory is in a target ODT mode or a non-target ODT mode; A control signal generating circuit is coupled to the decoder and the mode signal generating circuit, and is used to receive the on-chip terminal command signal and the on-chip terminal mode signal, and generate an on-chip terminal control signal according to the on-chip terminal command signal and the on-chip terminal mode signal, so that the memory performs a corresponding ODT operation according to the on-chip terminal control signal.

2. The on-chip termination control circuit according to claim 1, characterized in that: When sampling detects that the pulse width of the chip select signal is a clock cycle of an external clock signal, the on-chip terminal mode signal indicates that the memory is in the target ODT mode; when sampling detects that the pulse width of the chip select signal is two clock cycles of the external clock signal, the on-chip terminal mode signal indicates that the memory is in the non-target ODT mode.

3. The on-chip terminal control circuit according to claim 1 or 2, characterized in that: The mode signal generating circuit comprises: A signal buffer, used for receiving the chip select signal, driving and amplifying the chip select signal and then outputting it; A signal identifier is connected to the signal buffer and is used to receive the chip select signal after driving and amplification. The signal identifier is used to output the on-chip terminal mode signal in a first state to indicate that the memory is in a target ODT mode when it is determined that the pulse width of the chip select signal is only a clock cycle of an external clock signal, and to output the on-chip terminal mode signal in a second state to indicate that the memory is in a non-target ODT mode when it is determined that the pulse width of the chip select signal is two clock cycles of the external clock signal.

4. The on-chip termination control circuit according to claim 3, characterized in that: The signal identifier comprises: a first sampling unit, wherein a signal input end of the first sampling unit is used to receive the chip select signal after driving and amplification, a clock input end of the first sampling unit is used to receive an odd clock signal, and the first sampling unit samples a level value of the chip select signal based on the odd clock signal within a clock cycle of a first external clock signal after receiving the chip select signal, and then outputs the sampled level value; a second sampling unit, wherein the signal input end of the second sampling unit is connected to the signal input end of the first sampling unit, and is used to receive the chip selection signal after driving and amplifying, and the clock input end of the second sampling unit is used to receive an even clock signal, and the second sampling unit samples the level value of the chip selection signal within the clock cycle of the second external clock signal after receiving the chip selection signal based on the even clock signal, and then outputs the sample; wherein the frequency of the even clock signal and the odd clock signal is half of the external clock signal, and the even clock signal is an inverted signal of the odd clock signal; A logic processing unit is connected to the first sampling unit and the second sampling unit respectively, and is used to output the on-chip terminal mode signal of the first state or the second state after performing logic processing on the sampling results of the first sampling unit and the second sampling unit.

5. The on-chip termination control circuit according to claim 4, characterized in that: The first sampling unit and the second sampling unit are both implemented by D flip-flops, and the logic processing unit includes: A NOR gate, wherein two input terminals of the NOR gate are respectively connected to the output terminal of the first sampling unit and the output terminal of the second sampling unit; An SR latch, wherein a first input end of the SR latch is connected to an output end of the NOR gate, a second input end of the SR latch is used to receive a reset signal, and an output end of the SR latch is used to output the on-chip terminal mode signal.

6. The on-chip termination control circuit according to claim 5, characterized in that: The logic processing unit also includes: A clock counter, wherein the first input terminal of the clock counter is used to receive the command / address signal, the second input terminal of the clock counter is used to receive the external clock signal, and the clock counter is used to count the clock cycles of the external clock signal after the command / address signal is in a valid state, and when the count value of the clock cycle reaches a preset value, output the reset signal in a valid state through the output terminal.

7. The on-chip termination control circuit according to claim 1, characterized in that: The decoder is further configured to generate an internal read / write command signal based on the command / address signal, and the control signal generating circuit determines the type of the on-chip terminal command signal according to the internal read / write command signal.

8. The on-chip termination control circuit according to claim 7, characterized in that: The on-chip termination control signal includes a non-target read ODT signal, a non-target write ODT signal, and a target write ODT signal, and the control signal generating circuit includes: a logic unit having an input terminal, two control terminals and three output terminals, wherein the input terminal of the logic unit is used to receive the on-chip terminal command signal, the two control terminals of the logic unit are used to receive the on-chip terminal mode signal and the internal read / write command signal, and the logic unit outputs the on-chip terminal command signal from one of the three output terminals in response to the internal read / write command signal and the on-chip terminal mode signal; The signal processing unit is respectively connected to the three output ends of the logic unit, and is used to process the on-chip terminal command signal according to the output end that outputs the on-chip terminal command signal to output one of a non-target read ODT signal, a non-target write ODT signal, and a target write ODT signal.

9. The on-chip termination control circuit according to claim 8, characterized in that: The logic unit comprises: A read on-chip terminal command strobe unit, whose input end is used to receive the on-chip terminal command signal, and whose control end is used to receive the internal read / write command signal, and is used to output the on-chip terminal command signal as a read on-chip terminal command signal when the internal read / write command signal indicates to perform a read operation; A write on-chip terminal command strobe unit, whose input end is used to receive the on-chip terminal command signal, and whose control end is used to receive the internal read / write command signal, and is used to output the on-chip terminal command signal as a write on-chip terminal command signal when the internal read / write command signal indicates to perform a write operation; A first gate having an input end, a control end, a first output end and a second output end, wherein the input end of the first gate receives the read on-chip terminal command signal, and the control end of the first gate receives the on-chip terminal mode signal; the first gate is used to output the read on-chip terminal command signal as a non-target read ODT initial signal from its first output end when the on-chip terminal mode signal indicates that it is in a non-target ODT mode; wherein the first output end of the first gate is the first output end of the logic unit; The second gate has an input end, a control end, a first output end and a second output end. The input end of the second gate receives the write on-chip terminal command signal, and the control end of the second gate receives the on-chip terminal mode signal. The second gate is used to output the write on-chip terminal command signal as a non-target write ODT initial signal from its first output end when the on-chip terminal mode signal indicates that it is in a non-target ODT mode. The second gate is also used to output the write on-chip terminal command signal as a target write ODT initial signal from its second output end when the on-chip terminal mode signal indicates that it is in a target ODT mode. The first output end of the second gate is the second output end of the logic unit, and the second output end of the second gate is the third output end of the logic unit.

10. The on-chip termination control circuit according to claim 9, characterized in that: The signal processing unit includes three signal processing sub-units, which are connected to the three output ends of the logic unit in a one-to-one correspondence, and are respectively used to receive the non-target read ODT initial signal, the non-target write ODT initial signal and the target write ODT initial signal, and after performing pulse width adjustment and offset calibration on the non-target read ODT initial signal, the non-target write ODT initial signal and the target write ODT initial signal, the non-target read ODT signal, the non-target write ODT signal and the target write ODT signal are correspondingly output.

11. The on-chip termination control circuit according to claim 1, characterized in that: The decoder comprises: a buffer, for receiving and buffering the command / address signal according to an external clock signal; A command decoder is connected to the buffer, decodes the command / address signal, and generates the on-chip terminal command signal.

12. A memory, characterized in that: The invention comprises an on-chip terminal control circuit as claimed in any one of claims 1 to 11.

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