Memory device and method of operating memory device

Abstract

The invention relates to a memory device and a method of operating the memory device. According to an embodiment of the present disclosure, a memory device includes: a memory cell array including a plurality of memory cells respectively connected to a plurality of word lines; a peripheral circuit including a voltage generation circuit and a page buffer connected to the memory cells and latching data sensed from the memory cells; and a control logic configured to sense data stored in the memory cell in response to a cache read command received from an external device, and configured to control the peripheral circuit to output the data latched in the page buffer to the external device, and the control logic controls the peripheral circuit to generate an operation voltage to be applied to the word line based on a comparison result of a first address corresponding to a first cache read command received from an external device and a second address corresponding to a second cache read command.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method of operating a memory device. Background Art

[0002] With the development of mobile systems and various applications, the demand for NAND type flash memory devices with high integration and storage devices for controlling flash memory has been increasing. Flash memory devices have the ability to store a large amount of data information, but the disadvantage is that the data read and write time is slightly longer than the data read and write time of RAM. The performance of a system including such a flash memory device is limited by the read operation time of the flash memory device. The limitation of the flash memory device on the system performance can be solved by supporting cache read operations. Summary of the invention

[0003] According to an embodiment of the present disclosure, a memory device may include: a memory cell array, which includes a plurality of memory cells respectively connected to a plurality of word lines; a peripheral circuit, which includes: a voltage generating circuit, which generates a voltage applied to the memory cell array; and a page buffer, which is connected to the memory cell through a bit line and latches data sensed from the memory cell; and a control logic, which is configured to sense the data stored in the memory cell in response to a cache read command received from an external device, and is configured to control the peripheral circuit to output the data latched in the page buffer to the external device, and the control logic may control the peripheral circuit to generate an operating voltage to be applied to the word line based on a comparison result of a first address corresponding to a first cache read command received from the external device and a second address corresponding to a second cache read command.

[0004] According to an embodiment of the present disclosure, a method for operating a memory device may include: applying a first read voltage to a first word line corresponding to a first address among a plurality of word lines connected to a plurality of memory cells in response to a first cache read command; sensing first read data stored at a position corresponding to the first address through a bit line to store the first read data in a sense latch connected to the memory cell through the bit line; receiving a second cache read command and a second address; moving the first read data stored in the sense latch to a cache latch connected to the sense latch through the bit line; applying an operating voltage determined based on a comparison result of the first address and the second address to the first word line and a second word line corresponding to the second address; and sensing second read data stored at a position corresponding to the second address to store the second read data in the sense latch, and outputting the first read data stored in the cache latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0006] Figure 2 It is an example Figure 1 Diagram of a voltage control circuit of a memory device.

[0007] Figure 3 It is an example Figure 2 Diagram of the address comparison circuit.

[0008] Figure 4 It is an example Figure 2 Diagram of the voltage controlled signal generator.

[0009] Figure 5 It is an example Figure 1 Figure 1 shows a diagram of a page buffer group.

[0010] Figure 6 is a diagram illustrating data transfer during a normal read operation.

[0011] Figure 7 is a diagram illustrating data transfer during a cache read operation.

[0012] Figure 8 is a timing diagram illustrating a cache read operation.

[0013] Fig. 9 is a diagram illustrating voltages applied to various lines during a cache read operation.

[0014] Fig.10 is a timing diagram illustrating a cache read operation of a memory device according to an embodiment of the present disclosure.

[0015] Fig.11 is a diagram illustrating an example of voltages applied to respective lines during a cache read operation of a memory device according to an embodiment of the present disclosure.

[0016] Fig.12 is a diagram illustrating another example of voltages applied to respective lines during a cache read operation of a memory device according to an embodiment of the present disclosure.

[0017] Fig.13 is a timing diagram illustrating a cache read operation of a memory device according to another embodiment of the present disclosure.

[0018] Fig.14 is a diagram illustrating voltages applied to respective lines during a cache read operation of a memory device according to another embodiment of the present disclosure.

[0019] Fig.15is a block diagram illustrating a storage device including a memory device according to an embodiment of the present disclosure.

[0020] Fig.16 It is an example Fig.15 FIG. 1 is a diagram of another embodiment of a memory controller.

[0021] Fig.17 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0022] Fig.18 is a flowchart illustrating a voltage application process in a method of operating a memory device according to an embodiment of the present disclosure.

[0023] Fig.19 is a flowchart illustrating a voltage application process in a method of operating a memory device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The specific structural or functional description of the embodiments of the concepts of the present disclosure disclosed in this specification or application is only exemplified for describing the embodiments of the concepts of the present disclosure. The embodiments of the concepts of the present disclosure can be implemented in various forms and are not limited to the embodiments described in this specification or application.

[0025] Embodiments of the present disclosure provide a memory device capable of improving read operation performance and a method of operating the memory device.

[0026] According to the present technology, a memory device capable of improving read operation performance and a method of operating the memory device are provided.

[0027] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0028] Reference Figure 1 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0029] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be connected to the row decoder 121 through a row line RL. Here, the row line RL may include at least one source selection line, a plurality of word lines, and at least one drain selection line. The plurality of memory blocks BLK1 to BLKz may be connected to the page buffer group 123 through bit lines BL1 to BLn. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. As an embodiment, the plurality of memory cells may be nonvolatile memory cells. The memory cells connected to the same word line may be defined as one page. Therefore, one memory block may include a plurality of pages.

[0030] In any one of the plurality of memory blocks BLKi, a plurality of word lines arranged in parallel to each other may be connected between a first selection line and a second selection line. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. More specifically, the memory block BLKi may include a plurality of strings ST connected between the bit lines BL1 to BLn and the source line SL. The bit lines BL1 to BLn may be connected to the string ST, respectively, and the source line SL may be connected to the string ST in common. Since the strings ST may be constructed to be identical to each other, the string ST connected to the first bit line BL1 is specifically described as an example.

[0031] The string ST may include a source selection transistor SST, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST connected in series between a source line SL and a first bit line BL1. One string ST may include at least one or more source selection transistors SST and at least one or more drain selection transistors DST, and may include memory cells MC1 to MC16. However, one string ST may include more memory cells than shown in the figure.

[0032] The source of the source select transistor SST may be connected to the source line SL, and the drain of the drain select transistor DST may be connected to the first bit line BL1. The memory cells MC1 to MC16 may be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST may be connected to the source select line SSL, the gates of the drain select transistors DST may be connected to the drain select line DSL, and the gates of the memory cells MC1 to MC16 may be connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a physical page PPG. Therefore, the memory block BLKi may include a physical page PPG of the number of word lines WL1 to WL16.

[0033] Each memory cell included in the memory cell array 110 may be configured as a single level cell (SLC) storing one data bit, a multi level cell (MLC) storing two data bits, a triple level cell (TLC) storing three data bits, or a quad level cell (QLC) storing four data bits.

[0034] The SLC can store one bit of data. One physical page PPG of the SLC can store one logical page of data. One logical page LPG of data can include data bits corresponding to the number of cells included in one physical page PPG.

[0035] MLC, TLC, and QLC can store two or more bits of data. In this case, one physical page PPG can store two or more logical pages of data.

[0036] The peripheral circuit 120 may be configured to perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 under the control of the control logic 130. That is, the peripheral circuit 120 may drive the memory cell array 110 under the control of the control logic 130. For example, under the control of the control logic 130, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLn, or may discharge the applied voltage. Here, the operation of discharging the applied voltage may also be described as applying a discharge voltage.

[0037] Specifically, the peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , an input / output circuit 125 , and a sensing circuit 126 .

[0038] The row decoder 121 may be connected to the memory cell array 110 via a row line RL. The row line RL may include at least one source selection line, a plurality of word lines, and at least one drain selection line. In an embodiment, the word line may include a normal word line and a dummy word line. In addition, the row line RL may also include a pipeline selection line.

[0039] The row decoder 121 may be configured to operate in response to the control of the control logic 130. The row decoder 121 may receive a row address RADD from the control logic 130. Specifically, the row decoder 121 may be configured to decode the row address RADD. The row decoder 121 may select at least one of the memory blocks BLK1 to BLKz according to the decoded row address RADD. In addition, the row decoder 121 may select at least one word line of the memory block according to the decoded address, the memory block being selected to apply the voltage generated by the voltage generator 122 to the at least one word line.

[0040] For example, during a program operation, the row decoder 121 may apply a program voltage to a selected word line, and may apply a program pass voltage having a lower level than the program voltage to unselected word lines. During a program verification operation, the row decoder 121 may apply a verification voltage to a selected word line, and may apply a verification pass voltage having a higher level than the verification voltage to unselected word lines. During a read operation, the row decoder 121 may apply a read voltage to a selected word line, and may apply a read pass voltage having a higher level than the read voltage to unselected word lines.

[0041] In an embodiment, the erase operation of the memory cell array 110 may be performed in units of memory blocks. During the erase operation, the row decoder 121 may select a memory block according to a decoded address, and the row decoder 121 may apply a ground voltage to a word line connected to the selected memory block.

[0042] The voltage generator 122 may operate in response to the control of the control logic 130. The voltage generator 122 may be configured to generate a plurality of voltages by using an external power supply voltage provided to the memory device 100. For example, the voltage generator 122 may generate a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc. in response to the control of the control logic 130. That is, the voltage generator 122 may generate various operation voltages V for program operation, read operation, and erase operation in response to the operation signal OPSIG and the voltage control signal VCSIG. op .

[0043] As an embodiment, the voltage generator 122 may generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 may be used as an operation voltage of the memory cell array 110.

[0044] As an embodiment, the voltage generator 122 can generate a plurality of voltages by using an external power supply voltage or an internal power supply voltage. For example, in response to the control of the control logic 130, the voltage generator 122 may include a plurality of pumping capacitors receiving the internal power supply voltage, and the plurality of pumping capacitors may be selectively activated to generate a plurality of voltages. In addition, the generated voltages may be provided to the memory cell array 110 through the row decoder 121.

[0045] The page buffer group 123 may include a first page buffer PB1 to an nth page buffer PBn. The first page buffer PB1 to the nth page buffer PBn may be connected to the memory cell array 110 through the first bit line BL1 to the nth bit line BLn, respectively. In addition, the first page buffer PB1 to the nth page buffer PBn may operate in response to the control of the control logic 130. Specifically, the first page buffer PB1 to the nth page buffer PBn may operate in response to the page buffer control signal PBSIGNALS. For example, during a read operation or a verification operation, the first page buffer PB1 to the nth page buffer PBn may temporarily store data received through the first bit line BL1 to the nth bit line BLn or may sense the voltage or current of the bit lines BL1 to BLn.

[0046] Specifically, during a programming operation, when a programming pulse is applied to a selected word line, the first page buffer PB1 to the nth page buffer PBn may transmit data DATA received through the input / output circuit 125 to the selected memory cell through the first bit line BL1 to the nth bit line BLn. The memory cells of the selected page may be programmed according to the transmitted data DATA. The memory cells of the page selected according to the transmitted data DATA may be programmed. The memory cells connected to the bit lines to which a programming enable voltage (e.g., a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit lines to which a programming inhibit voltage (e.g., a power supply voltage) is applied may be maintained.

[0047] During a program verification operation, the first to nth page buffers PB1 to PBn may read page data from selected memory cells through the first to nth bit lines BL1 to BLn.

[0048] During a read operation, under the control of the column decoder 124 , the first to nth page buffers PB1 to PBn may read data DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn and may output the read data DATA to the input / output circuit 125 .

[0049] During an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn.

[0050] In an embodiment, each of the page buffers PB1 to PBn may include a sense latch and a cache latch. The sense latch may latch read data sensed through the bit lines BL1 to BLn. The cache latch may cache data stored in the sense latch.

[0051] In an implementation, under the control of the control logic 130 , the page buffer group 123 may latch the sensed read data to the sense latch and may output the data stored in the cache latch at the same time.

[0052] In an implementation, under the control of the control logic 130 , the page buffer group 123 may move the read data latched in the sense latch to the cache latch.

[0053] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may exchange data with the first to nth page buffers PB1 to PBn through the data lines DL, or may exchange data with the input / output circuit 125 through the column lines CL.

[0054] The input / output circuit 125 may transfer a command CMD and an address ADDR received from the external memory controller 200 to the control logic 130, or may exchange data DATA with the memory controller through the input / output line DQ. In addition, the input / output circuit may exchange data with the column decoder 124 through the column line CL.

[0055] The sensing circuit 126 may generate a reference current in response to the enable bit signal VRY_BIT during a read operation or a verification operation, and may compare a sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0056] The control logic 130 may output an operation signal OPSIG, a voltage control signal VCSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit signal VRY_BIT in response to a command CMD and an address ADDR to control the peripheral circuit 120 .

[0057] The control logic 130 may control the peripheral circuit 120 to perform a normal read operation and a cache read operation according to a command CMD provided from the outside. In an embodiment, the control logic 130 may include a voltage control circuit 131. The voltage control circuit 131 may control the voltage generator 122 to generate an operation voltage V by outputting an operation signal OPSIG and a voltage control signal VCSIG. op .

[0058] In an embodiment, the voltage control circuit 131 may generate a voltage control signal VCSIG in response to an address ADDR received from the input / output circuit 125, and more specifically, the voltage control circuit 131 may generate a voltage control signal VCSIG related to a cache read operation based on a comparison result of addresses corresponding to consecutive cache read commands.

[0059] In addition, the voltage control circuit 131 may receive word line state information WL INFO from the peripheral circuit 120. The voltage control circuit 131 may generate a voltage control signal VCSIG related to a cache read operation based on the word line state information WL INFO at a time point when a cache read command is received.

[0060] In addition, the control logic 130 may generate an operation signal OPSIG in response to the command CMD, and the voltage generator 122 may generate an operation voltage V based on the received operation signal OPSIG and the voltage control signal VCSIG. op .

[0061] exist Figure 1 In the embodiment, the voltage control circuit 131 may be included in the control logic 130. However, the embodiment is not limited thereto, and the voltage control circuit 131 may be included in the peripheral circuit 120 or may be a separate configuration distinguished from the control logic 130 and the peripheral circuit 120.

[0062] Figure 2 It is an example Figure 1 Diagram of a voltage control circuit of a memory device.

[0063] Reference Figure 1 and Figure 2 , the voltage control circuit 131 may include an address comparison circuit 131a and a voltage control signal generator 131b. The address comparison circuit 131a may receive an address ADDR through an input / output line DQ.

[0064] In an embodiment, the address comparison circuit 131a may latch the received address. In an embodiment, the address comparison circuit 131a may compare the latched first address with the newly received second address.

[0065] In an embodiment, the address comparison circuit 131a may be enabled according to a cache read command. That is, when the address comparison circuit 131a receives a cache read command, the address comparison circuit 131a may compare the first address with the second address. In an embodiment, the address comparison circuit 131a may latch the received address according to whether the cache read command has been received, and thus, the address comparison circuit 131a may compare the latched address with the newly received address. In another embodiment, the address comparison circuit 131a may compare the latched address with the newly received address according to whether the cache read command has been received, and thus, the address comparison circuit 131a may output the address comparison result.

[0066] In an embodiment, the address comparison circuit 131a may compare the block address of the first address with the block address of the second address. In addition, in an embodiment, the address comparison circuit 131a may compare the word line address of the first address with the word line address of the second address.

[0067] In an embodiment, the address comparison circuit 131a may output a comparison result of the address. In an embodiment, the address comparison circuit 131a may output at least one of a block address comparison result and a word line address comparison result as the address comparison result.

[0068] The voltage control signal generator 131b may receive the address comparison result output from the address comparison circuit 131a. In addition, the voltage control signal generator 131b may receive word line state information WL INFO from the peripheral circuit 120. The word line state information WL INFO may indicate the voltage applied to each word line connected to the memory cell. In an embodiment, the word line state information WL INFO may include information about the voltage applied to one or more word lines among the word line corresponding to the first address and the word line corresponding to the second address. In addition, in an embodiment, the word line state information WL INFO may also include information about the voltage applied to the drain selection line. More specifically, the word line state information WL INFO may also include information about the voltage applied to the selected drain selection line and the voltage applied to the unselected drain selection line.

[0069] The voltage control signal generator 131 b may output a voltage control signal VCSIG based on the address comparison result received from the address comparison circuit 131 a and the word line state information WL INFO received from the peripheral circuit 120 .

[0070] In an embodiment, when the command CMD received by the control logic 130 is a cache read command, the voltage generator 122 may generate a voltage for a cache read operation. Therefore, the voltage control signal generator 131b may generate and output a voltage control signal VCSIG so that the voltage generator 122 generates at least one of: one or more read voltages applied to a selected word line and sensing data stored in a memory cell; one or more pass voltages applied to an unselected word line and maintaining a memory cell connected to the unselected word line in a turned-on state, an equalization voltage for synchronizing the voltages of the selected word line and the unselected word line, and a discharge voltage for discharging the selected word line and the unselected word line.

[0071] Figure 3 It is an example Figure 2 Diagram of the address comparison circuit.

[0072] Reference Figures 1 to 3 , a signal indicating whether a previous address, a current address, and a subsequent read command have been received may be input to the address comparison circuit 131a.

[0073] In an implementation, the memory device 100 may sequentially receive a first cache read command and a second cache read command from an external device, and may receive a first address and a second address corresponding to the respective cache read commands.

[0074] Therefore, the first block address AX_1 corresponding to the first address st BLK, the second block address AX_2 corresponding to the first address nd BLK, a first word line address AX_1 corresponding to the first address st WL, a second word line address AX_2 corresponding to the second address nd WL, and a second cache read command enable signal 2 indicating that a second cache read command has been received nd _READ_CMD_EN may be input to the address comparison circuit 131 a .

[0075] In an embodiment, the address comparison circuit 131a can generate a cache read command enable signal 2 according to the second cache read command enable signal 2 nd That is, when the memory device 100 receives the second cache read command, the address comparison circuit 131a may output an address comparison result based on the comparison between the first address and the second address.

[0076] The address comparison circuit 131a may compare the first block address AX_1 st BLK and the second block address AX_2 ndThe address comparison circuit 131a can compare the first word line address AX_1 st WL and the second word line address AX_2 nd WL for comparison.

[0077] The address comparison circuit 131a can compare the first block address AX_1 st BLK and the second block address AX_2 nd BLK is the same, and the block address comparison result BLC_SAME_EN is output. In addition, the address comparison circuit 131a can output the block address comparison result BLC_SAME_EN according to the first word line address AX_1 st WL and second word line address AX_2 nd Whether WL is the same, the word line address comparison result WL_SAME_EN is output.

[0078] Figure 4 It is an example Figure 2 Diagram of the voltage controlled signal generator.

[0079] Reference Figures 1 to 4 , a signal indicating the address comparison result and the word line state information may be input to the voltage control signal generator 131 b.

[0080] In an implementation, the voltage control signal generator 131 b may receive the block address comparison result BLC_SAME_EN and the word line address comparison result WL_SAME_EN from the address comparison circuit 131 a .

[0081] In addition, the voltage control signal generator 131 b may receive word line state information, more specifically, equalization voltage applying information SELWL_EQ of a selected word line and discharge voltage applying information SELWL_DC of a selected word line from the peripheral circuit 120 .

[0082] The voltage control signal generator 131b may output a voltage control signal VCSIG based on the received address comparison result and word line state information. In an embodiment, the voltage control signal may include an equalization enable signal EQ_EN requesting generation of an equalization voltage for performing equalization, a discharge enable signal DC_EN requesting generation of a discharge voltage for performing discharge, and a sensing enable signal SEN_EN requesting generation of a read voltage for performing a sensing operation. However, the voltage control signal VCSIG is not limited thereto, and may also include various types of signals requesting generation of an operation voltage for performing a read operation and a preparation operation and a completion operation of the read operation.

[0083] Figures 2 to 4 Illustrated Figure 1 However, the configuration of the voltage control circuit 131 is not limited to Figures 2 to 4 Any construction that is capable of controlling the generation of an operating voltage based on a comparison result of an address corresponding to a cache read command and word line state information corresponding to a reception time point of a subsequent cache read command is not limited and can be adopted as the construction of the voltage control circuit 131.

[0084] Figure 5 It is an example Figure 1 Figure 1 shows a diagram of a page buffer group.

[0085] Reference Figure 1 and Figure 5 , each of the page buffers PB1 , PB2 , . . . , and PBn included in the page buffer group 123 may include a sense latch SLATCH and a cache latch CLATCH.

[0086] The page buffers PB1, PB2, ..., and PBn may operate during a read operation in response to a control signal of the control logic 130. Specifically, the control logic 130 may receive a cache read command from the memory controller, and in response to the cache read command, the control logic 130 may generate a control signal PBSIGNALS for controlling a cache read operation of the page buffers PB1, PB2, ..., and PBn and transmit the control signal to the page buffers PB1, PB2, ..., and PBn, and the page buffers PB1, PB2, ..., and PBn may perform a cache read operation in response to the page buffer control signal.

[0087] The sense latch SLATCH may store data sensed from the bit line. The data sensed from the bit line may be data determined according to the threshold voltage characteristics of the memory cell connected to the selected word line among the local word lines. For example, the sense latch SLATCH of the first page buffer PB1 may be connected to the first bit line BL1 and may latch (or store) the data sensed from the first bit line BL1.

[0088] The cache latch CLATCH may be electrically connected to the sense latch SLATCH and may cache (or store) data stored in the sense latch SLATCH in response to a page buffer control signal. In addition, the cache latch CLATCH may be connected to a data line DL and may output cached data to the column decoder 124 through the data line DL.

[0089] The sense latch SLATCH included in the page buffers PB1, PB2, ..., and PBn may be referred to as one data register DRT, and the cache latch CLATCH included in the page buffer may be referred to as one cache register CRT. At this time, since the data register DRT and the cache register CRT store or cache data sensed from a memory cell connected to one word line, data corresponding to one page may be stored.

[0090] The data cached in the cache register CRT can be output to the input / output line DQ through the column decoder 124 and the input / output circuit 125, and the memory controller can receive the data cached in the cache register CRT through the input / output line DQ in response to a cache read command sent to the control logic 130.

[0091] Figure 6 is a diagram illustrating data transfer during a normal read operation.

[0092] Reference Figure 1 , Figure 5 and Figure 6 , the memory device 100 may receive a first normal read command and a first address corresponding thereto. Therefore, a data sensing operation (Data1 Sensing) for page N corresponding to the first address in the memory cell array 110 may be performed. As a result, data of page N may be stored in a data register DRT including a sense latch.

[0093] Next, a data transfer operation (Data1Transfer) may be performed on the data of page N stored in the data register DRT, so that the data of page N stored in the data register DRT may be transferred to the cache register CRT including the cache latch.

[0094] Next, an output operation (Data1Out) of the data of page N stored in the cache register CRT may be performed, whereby the data of page N stored in the cache register CRT may be output to the external memory controller through the input / output line DQ.

[0095] When the output operation (Data1 Out) of the data of page N is completed, the memory device 100 may receive a second normal read command and a second address corresponding thereto. Therefore, a data sensing operation (Data2 Sensing) for page N+1 corresponding to the second address in the memory cell array 110 may be performed. As a result, the data of page N+1 may be stored in the data register DRT.

[0096] Next, as a data transfer operation (Data2Transfer) of the data of page N+1 stored in the data register DRT is performed, the data of page N+1 stored in the data register DRT may be transferred to the cache register CRT.

[0097] Next, an output operation (Data2Out) of the data of page N+1 stored in the cache register CRT may be performed, whereby the data of page N+1 stored in the cache register CRT may be output to the external memory controller through the input / output line DQ.

[0098] Figure 7 is a diagram illustrating data transfer during a cache read operation.

[0099] Reference Figure 1 , Figure 5 and Figure 7 , the memory device 100 may receive a first cache read command and a first address corresponding thereto. Therefore, a data sensing operation (Data1 Sensing) for page N corresponding to the first address in the memory cell array 110 may be performed. As a result, the data of page N may be stored in a data register DRT including a sense latch.

[0100] Next, a data transfer operation (Data1Transfer) of the data of page N stored in the data register DRT may be performed, whereby the data of page N stored in the data register DRT may be transferred to the cache register CRT including the cache latch. In an embodiment, during the data transfer operation, the memory device 100 may receive a second cache read command and a second address corresponding thereto.

[0101] Next, an output operation (Data1Out) of the data of page N stored in the cache register CRT may be performed, and a data sensing operation (Data2 Sensing) for page N+1 corresponding to the second address in the memory cell array 110 may be performed at the same time. Therefore, the data of page N stored in the cache register CRT may be output to the external memory controller through the input / output line DQ, and the data of page N+1 may be stored in the data register DRT at the same time.

[0102] Next, a data transfer operation (Data2Transfer) of the data of page N+1 stored in the data register DRT may be performed, whereby the data of page N stored in the data register DRT may be transferred to the cache register CRT including the cache latch. In an embodiment, during the data transfer operation, the memory device 100 may receive a third cache read command and a third address corresponding thereto.

[0103] Next, an output operation (Data2Out) of the data of page N+1 stored in the cache register CRT may be performed, and at the same time, a data sensing operation (Data2 Sensing) for page N+2 corresponding to the third address in the memory cell array 110 may be performed. Therefore, the data of page N+1 stored in the cache register CRT may be output to the external memory controller through the input / output line DQ, and at the same time, the data of page N+2 may be stored in the data register DRT.

[0104] That is, in the case of a cache read operation, the time for reading data can be shortened compared to a normal read operation.

[0105] Figure 8 is a timing diagram illustrating a cache read operation.

[0106] Reference Figure 1 , Figure 7 and Figure 8 , Figure 8 Shown by Figure 1 The commands and addresses input through the input / output line DQ and the data output through the input / output line DQ. Figure 8 Shown by Figure 1 The memory device 100 may include a ready busy signal output by a ready busy line RB of the memory device 100, and an operation performed in the memory device in response to the ready busy signal.

[0107] In an embodiment, during a cache read operation, a command and an address may be input through an input / output line DQ from a memory controller outside the memory device 100. During a cache read operation, a 00h command CMD 00h, an (N+1)th address ADDR(N+1)th, and a 31h command CMD 31h are sequentially input through the input / output line DQ.

[0108] In an embodiment, data corresponding to the Nth address ADDR Nth may be sensed (Read Data Sensing (Nth)) before the 31h command CMD 31h is input. The Nth address ADDR Nth may be an address received before the (N+1)th address ADDR(N+1)th is received.

[0109] When all data corresponding to the Nth address ADDR Nth are stored in the data register DRT, the data stored in the data register DRT can be transferred to the cache register CRT (D.Transfer(Nth)). At this time, the equalization operation Equalization and the discharge operation Discharge of the selected word line can be performed simultaneously. Here, the selected word line can be the word line corresponding to the Nth address ADDR Nth.

[0110] The equalizing operation Equalizing may be an operation of synchronizing the voltages of the selected word line and the unselected word line before discharging each of the selected word line to which the read voltage is applied and the unselected word line to which the pass voltage is applied. The equalizing voltage may be applied to both the selected word line and the unselected word line for the equalizing operation Equalizing.

[0111] The discharge operation Discharge may be an operation of discharging a selected word line to which a read voltage is applied and an unselected word line to which a pass voltage is applied. A discharge voltage may be applied to both the selected word line and the unselected word line for the discharge operation Discharge.

[0112] The equalizing operation Equalizing may be an operation selectively performed before the discharging operation Discharge. However, when the equalizing operation Equalizing is performed before the discharging operation Discharge, the voltage levels of the selected word line and the unselected word line may be the same. Therefore, when the discharging operation Discharge is performed on the selected word line and the unselected word line on which the equalizing operation Equalizing has been performed, the selected word line and the unselected word line may be discharged to the same level at the same discharging time.

[0113] Thereafter, the memory device 100 may output data (DOUT Nth) corresponding to the Nth address ADDR Nth stored in the cache register CRT through the input / output line DQ, and may sense data corresponding to the (N+1)th address ADDR(N+1)th at the same time (Read Data Sensing((N+1)th)). In a cache read operation, since data is stored in the data register DRT and the data stored in the cache register CRT is output at the same time, data corresponding to the (N+1)th address ADDR(N+1)th may be stored in the data register DRT and data corresponding to the Nth address ADDR Nth stored in the cache register CRT may be output to an external memory controller at the same time.

[0114] At this time, the voltage setting operation Bias Setting may be performed before the data sensing operation Read Data Sensing ((N+1)th) for the selected word line. Here, the selected word line may be a word line corresponding to the (N+1)th address ADDR (N+1)th.

[0115] The voltage setting operation Bias Setting may be an operation of changing a voltage applied to a selected word line to a read voltage for sensing data corresponding to the (N+1)th address ADDR(N+1)th. In an embodiment, the voltage applied to the selected word line during the voltage setting operation Bias Setting may be changed from a discharge voltage to a read voltage. In another embodiment, the voltage applied to the selected word line during the voltage setting operation Bias Setting may be precharged from a discharge voltage to a precharge voltage and then may be changed to a read voltage.

[0116] In an embodiment, when outputting data corresponding to the Nth address ADDR Nth, the memory device 100 may receive a subsequent cache read command and address from the memory controller through the input / output line DQ. For example, after outputting data corresponding to the Nth address ADDR Nth, the memory device 100 may receive a 00h command CMD 00h, an (N+2)th address ADDR(N+2)th, and a 31h command CMD 31h through the input / output line DQ.

[0117] After receiving the 31h command CMD 31h, when all data corresponding to the (N+1)th address ADDR(N+1)th are stored in the data register DRT, the data stored in the data register DRT can be transferred to the cache register CRT (D.Transfer((N+1)th)). At this time, the equalization operation Equalization and the discharge operation Discharge of the selected word line can be performed simultaneously. Here, the selected word line can be the word line corresponding to the (N+1)th address ADDR(N+1)th.

[0118] Thereafter, the memory device 100 may output the data corresponding to the (N+1)th address ADDR(N+1)th stored in the cache register CRT through the input / output line DQ (DOUT(N+1)th), and may sense the data corresponding to the (N+2)th address ADDR(N+2)th at the same time (Read Data Sensing((N+2)th)). In the cache read operation, since the data is stored in the data register DRT and the data stored in the cache register CRT is output at the same time, the data corresponding to the (N+2)th address ADDR(N+2)th may be stored in the data register DRT, and the data corresponding to the (N+1)th address ADDR(N+1)th stored in the cache register CRT may be output to the external memory controller at the same time.

[0119] At this time, a voltage setting operation Bias Setting may be performed before a data sensing operation (Read Data Sensing ((N+2)th)) for a selected word line. Here, the selected word line may be a word line corresponding to the (N+2)th address ADDR (N+2)th.

[0120] Fig. 9 is a diagram illustrating voltages applied to various lines during a cache read operation.

[0121] Reference Figure 8 and Fig. 9 According to the voltage setting operation BiasSetting performed before the operation of sensing data corresponding to the (N+1)th address ADDR(N+1)th (Read Data Sensing((N+1)th)), the operating voltage applied to the selected word line SEL WL may be changed from the initial voltage V int Change to the first read voltage V read1 , and the operating voltage applied to the unselected word line UNSEL WL can be increased from the initial voltage V int Change to pass voltage V pass In an embodiment, during the voltage setting operation Bias Setting, the operating voltage applied to the selected word line SEL WL may be increased from the initial voltage V to the initial voltage V together with the operating voltage applied to the unselected word line UNSEL WL. int Precharge to pass voltage V pass , and then can be changed to the first reading voltage V read1 .

[0122] During the operation of sensing data corresponding to the (N+1)th address ADDR(N+1)th (Read Data Sensing ((N+1)th)), the operating voltage applied to the selected word line SELWL may be maintained at the first read voltage V read1 , and the operating voltage applied to the unselected word line UNSEL WL can be maintained at the pass voltage V pass .exist Fig. 9 In the first reading voltage V read1 and the voltage V pass Each of them may be a single-level voltage, but is not limited thereto, and the first read voltage V read1 and the voltage V pass Each of can be configured by multiple read voltages and pass voltages of different levels.

[0123] After completing sensing of the data corresponding to the (N+1)th address ADDR(N+1)th, an equalization operation may be performed. eq It can be applied to the selected word line SEL WL and the unselected word line UNSEL WL. In an embodiment, the equalization voltage V eq can be equal to or greater than the first read voltage V read1 and is equal to or less than the pass voltage V pass , but the implementation mode is not limited thereto.

[0124] When the equalization operation is completed, a discharge operation can be performed, thereby making it possible to utilize V eq The voltage applied to the selected word line SEL WL and the unselected word line UNSEL WL is discharged synchronously. In other words, the discharge voltage V disc It can be applied to the selected word line SEL WL and the unselected word line UNSEL WL. Fig. 9 In the discharge voltage V disc Can be compared with the initial voltage V int Same, but equal to or less than the equilibrium voltage V eq Or the first read voltage V read1 The voltage is not limited and can be used as the discharge voltage V disc .

[0125] Thereafter, the voltage setting operation Bias Setting may be performed again, and thus the operating voltage applied to the selected word line SEL WL may be increased from the discharge voltage V disc The second read voltage V is changed to be used for sensing the data corresponding to the (N+2)th address ADDR(N+2)th. read2 , and the operating voltage applied to the unselected word line UNSEL WL can be discharged from the voltage V disc Change to pass voltage Vpass In an embodiment, during the voltage setting operation Bias Setting, the operating voltage applied to the selected word line SEL WL may be increased from the discharge voltage V to the discharge voltage V together with the operating voltage applied to the unselected word line UNSEL WL. disc Precharge to pass voltage V pass , and then can be changed to the second reading voltage V read2 .

[0126] After the voltage setting operation Bias Setting is completed, an operation of sensing data corresponding to the (N+2)th address ADDR(N+2)th (Read Data Sensing((N+2)th)) may be performed. At this time, the operating voltage applied to the selected word line SEL WL may be maintained at the second read voltage V read2 , while the operating voltage applied to the unselected word line UNSEL WL can be maintained at the pass voltage V pass .exist Fig. 9 In the example, the second read voltage V for sensing the data corresponding to the (N+2)th address ADDR(N+2)th is used. read2 may be different from the first read voltage V for sensing data corresponding to the (N+1)th address ADDR(N+1)th. read1 , but in another embodiment, the second read voltage V read2 can be compared with the first read voltage V read1 same.

[0127] Fig.10 is a timing diagram illustrating a cache read operation of a memory device according to an embodiment of the present disclosure.

[0128] Reference Figure 1 , Figure 8 and Fig.10 , Fig.10 shows the output through the input / output line DQ Figure 8 The operation of the data (DOUT Nth) corresponding to the Nth address ADDRNth.

[0129] The memory device 100 can output data corresponding to the Nth address ADDR Nth stored in the cache register CRT through the input / output line DQ (DOUT Nth), and can sense data corresponding to the (N+1)th address ADDR(N+1)th at the same time (Read Data Sensing((N+1)th)). In the cache read operation, since data is stored in the data register DRT and the data stored in the cache register CRT is output at the same time, data corresponding to the (N+1)th address ADDR(N+1)th can be stored in the data register DRT and data corresponding to the Nth address ADDR Nth stored in the cache register CRT can be output to the external memory controller at the same time.

[0130] At this time, a voltage setting operation Bias Setting may be performed before a data sensing operation (Read Data Sensing ((N+1)th)) for a selected word line. Here, the selected word line may be a word line corresponding to the (N+1)th address ADDR (N+1)th.

[0131] The voltage setting operation Bias Setting may be an operation of changing a voltage applied to a selected word line to a read voltage for sensing data corresponding to the (N+1)th address ADDR(N+1)th. In an embodiment, during the voltage setting operation Bias Setting, the voltage applied to the selected word line may be changed from a discharge voltage to a read voltage. In another embodiment, during the voltage setting operation Bias Setting, the voltage applied to the selected word line may be precharged from a discharge voltage to a precharge voltage and then may be changed to a read voltage.

[0132] In an embodiment, when outputting data corresponding to the Nth address ADDR Nth, the memory device 100 may receive a subsequent cache read command and address from the memory controller through the input / output line DQ. For example, after outputting data corresponding to the Nth address ADDR Nth, the memory device 100 may receive a 00h command CMD 00h, an (N+2)th address ADDR(N+2)th, and a 31h command CMD 31h through the input / output line DQ.

[0133] At this time, when the voltage control circuit 131 receives the (N+2)th address ADDR(N+2)th, the voltage control circuit 131 may compare the (N+1)th address ADDR(N+1)th with the (N+2)th address ADDR(N+2)th. At this time, at the time point of receiving the (N+2)th address ADDR(N+2)th or completing the reception of the 31h command CMD31h corresponding to the (N+2)th address ADDR(N+2)th before the time point of performing the equalization operation, the voltage setting operation Bias Setting may be directly performed on the word line of the memory device 100 without the equalization operation and the discharge operation.

[0134] When all data corresponding to the (N+1)th address ADDR(N+1)th are stored in the data register DRT, the data stored in the data register DRT can be transferred to the cache register CRT (D.Transfer((N+1)th)). At this time, the voltage setting operation Bias Setting can be directly performed on the word line corresponding to the (N+2)th address ADDR(N+2)th (which is the selected word line) at the same time without performing the equalization operation and the discharge operation as described above. That is, at least a part of the operation of transferring the data stored in the data register DRT to the cache register CRT and the voltage setting operation can be performed simultaneously.

[0135] Thereafter, the memory device 100 may output the data corresponding to the (N+1)th address ADDR(N+1)th stored in the cache register CRT through the input / output line DQ (DOUT(N+1)th), and may sense the data corresponding to the (N+2)th address ADDR(N+2)th at the same time (Read Data Sensing((N+2)th)). In the cache read operation, since the data is stored in the data register DRT and the data stored in the cache register CRT is output at the same time, the data corresponding to the (N+2)th address ADDR(N+2)th may be stored in the data register DRT, and the data corresponding to the (N+1)th address ADDR(N+1)th stored in the cache register CRT may be output to the external memory controller at the same time.

[0136] At this time, a data sensing operation (Read Data Sensing ((N+2)th)) for the selected word line may be performed after the voltage setting operation Bias Setting. In the cache read operation of the memory device according to the embodiment of the present disclosure, the voltage setting operation Bias Setting may be performed earlier by omitting the equalization operation and the discharge operation, and thus, the required time for the cache read operation may be shortened.

[0137] Fig.11 is a diagram illustrating an example of voltages applied to respective lines during a cache read operation of a memory device according to an embodiment of the present disclosure.

[0138] Reference Fig.10 and Fig.11 , according to the voltage setting operation BiasSetting performed before the operation of sensing data corresponding to the (N+1)th address ADDR(N+1)th (Read Data Sensing((N+1)th)), applied to the first word line 1 st The operating voltage of WL (which is the selected word line SEL WL) can be changed from the initial voltage V int Change to the first read voltage V readl , and applied to the second word line 2 nd The operating voltage of WL (which is the unselected word line UNSEL WL) can be changed from the initial voltage V int Change to pass voltage V pass In an embodiment, during the voltage setting operation Bias Setting, the voltage applied to the first word line 1 st The operating voltage of WL can be the same as that applied to the second word line 2 nd The operating voltage of WL is increased from the initial voltage V int Precharge to pass voltage V pass , and then can be changed to the first reading voltage V read1 .

[0139] During the operation of sensing data corresponding to the (N+1)th address ADDR(N+1)th (Read Data Sensing((N+1)th)), the first word line 1 is applied. st The operating voltage of WL can be maintained at the first read voltage V read1 , and applied to the second word line 2 nd The operating voltage of WL can be maintained at the pass voltage V pass .exist Fig.11 In the first reading voltage V read1 and the voltage V passEach of them may be a single-level voltage, but is not limited thereto, and the first read voltage V read1 and the voltage V pass Each of can be configured by multiple read voltages and pass voltages of different levels.

[0140] During the operation of sensing data corresponding to the (N+1)th address ADDR(N+1)th (Read Data Sensing((N+1)th)), the memory device may receive the (N+2)th address ADDR(N+2)th. The time point of receiving the (N+2)th address ADDR(N+2)th may be before performing the equalization operation and the discharge operation.

[0141] The memory device may compare the (N+1)th address ADDR(N+1)th with the (N+2)th address ADDR(N+2)th, and as a result of the comparison, may obtain a result that the block address and the word line address of the (N+1)th address ADDR(N+1)th and the (N+2)th address ADDR(N+2)th are the same. st WL can be continuously maintained as the selected word line SEL WL, and the second word line 2 nd WL may continuously remain as the unselected word line UNSEL WL.

[0142] After the sensing of the data corresponding to the (N+1)th address ADDR(N+1)th is completed, the voltage setting operation Bias Setting can be directly performed without performing the equalization operation and the discharge operation. st WL continues to be the selected word line SEL WL, so during the voltage setting operation Bias Setting, the first word line 1 st The operating voltage of WL can be read from the first voltage V read1 Change to the second reading voltage V read2 .exist Fig.11 In the example, the second read voltage V for sensing the data corresponding to the (N+2)th address ADDR(N+2)th is used. read2 may be different from the first read voltage V for sensing data corresponding to the (N+1)th address ADDR(N+1)th. read1 , but in another embodiment, the second read voltage V read2 can be compared with the first read voltage V read1 same.

[0143] In addition, since the second word line 2 ndWL continues to be the unselected word line UNSEL WL, so during the voltage setting operation Bias Setting, the second word line 2 nd The operating voltage of WL can be maintained at the pass voltage V pass .

[0144] That is, the memory device according to the embodiment of the present disclosure can pre-check that the selected word line SEL WL has not changed by comparing the previously received address with the currently received address, so the equalization operation, discharge operation, etc. can be omitted, thereby shortening the time required for the cache read operation.

[0145] Fig.12 is a diagram illustrating another example of voltages applied to respective lines during a cache read operation of a memory device according to an embodiment of the present disclosure.

[0146] Reference Fig.10 and Fig.12 , according to a voltage setting operation Bias Setting performed before the operation of sensing data corresponding to the (N+1)th address ADDR(N+1)th (Read Data Sensing((N+1)th)), applied to the first word line 1 st The operating voltage of WL (which is the selected word line SEL WL) can be changed from the initial voltage V int Change to the first read voltage V readl , and applied to the second word line 2 nd The operating voltage of WL (which is the unselected word line UNSEL WL) can be changed from the initial voltage V int Change to pass voltage V pass In an embodiment, during the voltage setting operation Bias Setting, the voltage applied to the first word line 1 st The operating voltage of WL can be the same as that applied to the second word line 2 nd The operating voltage of WL is increased from the initial voltage V int Precharge to pass voltage V pass , and then can be changed to the first reading voltage V read1 .

[0147] During the operation of sensing data corresponding to the (N+1)th address ADDR(N+1)th (Read Data Sensing((N+1)th)), the first word line 1 is applied. st The operating voltage of WL can be maintained at the first read voltage V read1 , and applied to the second word line 2 nd The operating voltage of WL can be maintained at the pass voltage V pass .exist Fig.12 In the first reading voltage V read1 and the voltage V pass Each of them is a single-level voltage, but is not limited thereto, and the first read voltage V read1 and the voltage V pass Each of can be configured by multiple read voltages and pass voltages of different levels.

[0148] During the operation of sensing data corresponding to the (N+1)th address ADDR(N+1)th (Read Data Sensing((N+1)th)), the memory device may receive the (N+2)th address ADDR(N+2)th. The time point of receiving the (N+2)th address ADDR(N+2)th may be before performing the equalization operation and the discharge operation.

[0149] The memory device may compare the (N+1)th address ADDR(N+1)th with the (N+2)th address ADDR(N+2)th, and as a result of the comparison, may obtain a result that the block addresses of the (N+1)th address ADDR(N+1)th and the (N+2)th address ADDR(N+2)th are the same and the word line addresses of the (N+1)th address ADDR(N+1)th and the (N+2)th address ADDR(N+2)th are different from each other. Therefore, according to the (N+1)th address ADDR(N+1)th as the first word line SEL WL selected, st WL may be changed to an unselected word line UNSEL WL according to the (N+2)th address, and a second word line 2 may be changed to an unselected word line UNSEL WL according to the (N+1)th address. nd WL may be changed to a selected word line SEL WL according to the (N+2)th address.

[0150] After completing the sensing of the data corresponding to the (N+1)th address ADDR(N+1)th, the voltage setting operation Bias Setting can be directly performed without performing the equalization operation and the discharge operation. As described above, since the first word line 1 st WL changes to the unselected word line UNSEL WL, so during the voltage setting operation Bias Setting, the first word line 1 st The operating voltage of WL can be read from the first voltage V read1 Change to pass voltage V pass .

[0151] In addition, since the second word line 2 nd WL changes to the selected word line SEL WL, so during the voltage setting operation Bias Setting, the second word line 2nd The operating voltage of WL can be adjusted from the voltage V pass Change to the second reading voltage V read2 .

[0152] exist Fig.12 In the example, the second read voltage V for sensing the data corresponding to the (N+2)th address ADDR(N+2)th is used. read2 may be different from the first read voltage V for sensing data corresponding to the (N+1)th address ADDR(N+1)th. read1 , but in another embodiment, the second read voltage V read2 can be compared with the first read voltage V read1 same.

[0153] When a result that the block address is different is obtained as a result of comparing the (N+1)th address ADDR(N+1)th with the (N+2)th address ADDR(N+2)th, since the read voltage and the pass voltage are applied only to the blocks including the first word line 1 st The memory block WL has a word line of a different memory block, so the equalization operation and the discharge operation can be performed on the memory block including the first word line. Therefore, the power applied to the first word line 1 st The voltage of WL may be changed to a discharge voltage (or initial voltage) by the equalization voltage.

[0154] That is, the memory device according to the embodiment of the present disclosure can pre-check the change of the selected word line SEL WL by comparing the previously received address with the currently received address, so the equalization operation, the discharge operation, etc. can be omitted, thereby shortening the time required for the cache read operation.

[0155] Fig.13 is a timing diagram illustrating a cache read operation of a memory device according to another embodiment of the present disclosure.

[0156] Reference Figure 1 , Figure 8 and Fig.13 , Fig.13 shows the output through the input / output line DQ and Figure 8 The operation is performed on the data (DOUT Nth) corresponding to the Nth address ADDRNth.

[0157] The memory device 100 can output data (DOUT Nth) corresponding to the Nth address ADDR Nth stored in the cache register CRT through the input / output line DQ, and simultaneously sense data corresponding to the (N+1)th address ADDR(N+1)th (Read Data Sensing((N+1)th)). In the cache read operation, since data is stored in the data register DRT and the data stored in the cache register CRT is output simultaneously, data corresponding to the (N+1)th address ADDR(N+1)th can be stored in the data register DRT, and data corresponding to the Nth address ADDR Nth stored in the cache register CRT can be output to the external memory controller at the same time.

[0158] At this time, a voltage setting operation Bias Setting may be performed before a data sensing operation (Read Data Sensing ((N+1)th)) for a selected word line. Here, the selected word line may be a word line corresponding to the (N+1)th address ADDR (N+1)th.

[0159] The voltage setting operation Bias Setting may be an operation of changing a voltage applied to a selected word line to a read voltage for sensing data corresponding to the (N+1)th address ADDR(N+1)th. In an embodiment, during the voltage setting operation Bias Setting, the voltage applied to the selected word line may be changed from a discharge voltage to a read voltage. In another embodiment, during the voltage setting operation Bias Setting, the voltage applied to the selected word line may be precharged from a discharge voltage to a precharge voltage and then may be changed to a read voltage.

[0160] In an embodiment, when outputting data corresponding to the Nth address ADDR Nth, the memory device 100 may receive a subsequent cache read command and address from the memory controller through the input / output line DQ. For example, after outputting data corresponding to the Nth address ADDR Nth, the memory device 100 may receive a 00h command CMD 00h, an (N+2)th address ADDR(N+2)th, and a 31h command CMD 31h through the input / output line DQ.

[0161] At this time, when the voltage control circuit 131 receives the (N+2)th address ADDR(N+2)th, the voltage control circuit 131 may compare the (N+1)th address ADDR(N+1)th with the (N+2)th address ADDR(N+2)th. At this time, the time point at which the (N+2)th address ADDR(N+2) is received or the time point at which the reception of the 31h command CMD 31h corresponding to the (N+2)th address ADDR(N+2)th is completed is during the time point at which the equalization operation is performed, and after the equalization is completed, the voltage setting operation Bias Setting may be directly performed on the word line of the memory device 100 without the discharge operation.

[0162] When all data corresponding to the (N+1)th address ADDR(N+1)th are stored in the data register DRT, the data stored in the data register DRT can be transferred to the cache register CRT (D.Transfer((N+1)th)). At this time, there is no need for the discharge operation as described above, and the voltage setting operation Bias Setting can be directly performed simultaneously on the word line corresponding to the (N+2)th address ADDR N+2th (which is the selected word line). That is, the equalization operation, the voltage setting operation, and at least part of the operation of transferring the data stored in the data register DRT to the cache register CRT can be performed simultaneously.

[0163] Thereafter, the memory device 100 may output the data corresponding to the (N+1)th address ADDR(N+1)th stored in the cache register CRT through the input / output line DQ (DOUT(N+1)th), and may simultaneously sense the data corresponding to the (N+2)th address ADDR N+2th (Read Data Sensing(N+2th)). In a cache read operation, since the data is stored in the data register DRT and the data stored in the cache register CRT is simultaneously output, the data corresponding to the (N+2)th address ADDR N+2th may be stored in the data register DRT, and the data corresponding to the (N+1)th address ADDR(N+1)th stored in the cache register CRT may simultaneously be output to the external memory controller.

[0164] At this time, a data sensing operation (Read Data Sensing (N+2th)) for the selected word line can be performed after the voltage setting operation Bias Setting. In the cache read operation of the memory device according to the embodiment of the present disclosure, by omitting the discharge operation, the voltage setting operation Bias Setting can be performed earlier, and thus, the required time for the cache read operation can be shortened.

[0165] Fig.14 is a diagram illustrating voltages applied to respective lines during a cache read operation of a memory device according to another embodiment of the present disclosure.

[0166] Reference Fig.13 and Fig.14 , according to the voltage setting operation BiasSetting performed before the operation of sensing data corresponding to the (N+1)th address ADDR(N+1)th (Read Data Sensing((N+1)th)), applied to the first word line 1 st The operating voltage of WL (which is the selected word line SEL WL) can be changed from the initial voltage V int Change to the first read voltage V readl , and applied to the second word line 2 nd The operating voltage of WL (which is the unselected word line UNSEL WL) can be changed from the initial voltage V int Change to pass voltage V pass In an embodiment, during the voltage setting operation Bias Setting, the voltage applied to the first word line 1 st The operating voltage of WL can be the same as that applied to the second word line 2 nd The operating voltage of WL is increased from the initial voltage V int Precharge to pass voltage V pass , and then can be changed to the first reading voltage V read1 .

[0167] During the operation of sensing data corresponding to the (N+1)th address ADDR(N+1)th (Read Data Sensing((N+1)th)), the first word line 1 is applied. st The operating voltage of WL can be maintained at the first read voltage V read1 , and applied to the second word line 2 nd The operating voltage of WL can be maintained at the pass voltage V pass .exist Fig.14 In the first reading voltage V read1 and the voltage V pass Each of them may be a single-level voltage, but is not limited thereto, and the first read voltage V read1 and the voltage V pass Each of can be configured by multiple read voltages and pass voltages of different levels.

[0168] Afterwards, the first word line 1 can be st WL and second word line 2 nd WL performs a balancing operation. Therefore, the balancing voltage V eqcan be applied to the first word line 1 st WL and second word line 2 nd WL both, as a result, the first word line 1 st WL and second word line 2 nd The voltage of WL can be synchronized.

[0169] During the equalization operation, the memory device may receive an (N+2)th address ADDR N+2th. A time point of receiving the (N+2)th address ADDR N+2th may be after the equalization operation starts and may be before the discharge operation is performed.

[0170] The memory device may compare the (N+1)th address ADDR(N+1)th with the (N+2)th address ADDR N+2th.

[0171] As a result of the comparison, it can be obtained that the block address and the word line address of the (N+1)th address ADDR(N+1)th and the (N+2)th address ADDR N+2th are all the same. In this case, as shown by the solid line, during the voltage setting operation BiasSetting, the first word line 1 st The operating voltage of WL can be adjusted from the equilibrium voltage V eq Change to the second reading voltage V read2 In addition, during the voltage setting operation Bias Setting, the second word line 2 nd The operating voltage of WL can be adjusted from the equilibrium voltage V eq Change to pass voltage V pass .

[0172] As a result of the comparison, it can be obtained that the block addresses of the (N+1)th address ADDR(N+1)th and the (N+2)th address ADDR N+2th are the same and the word line addresses of the (N+1)th address ADDR(N+1)th and the (N+2)th address ADDR N+2th are different. In this case, as shown by the dot-dash line, during the voltage setting operation Bias Setting, the first word line 1 st The operating voltage of WL can be adjusted from the equilibrium voltage V eq Change to pass voltage V pass In addition, during the voltage setting operation Bias Setting, the second word line 2 nd The operating voltage of WL can be adjusted from the equilibrium voltage V eq Change to the second reading voltage V read2 .

[0173] exist Fig.14 In the example, a second read voltage V is used to sense data corresponding to the (N+2)th address ADDR N+2th.read2 may be different from the first read voltage V for sensing data corresponding to the (N+1)th address ADDR(N+1)th. readl , but in another embodiment, the second read voltage V read2 can be compared with the first read voltage V read1 same.

[0174] When a result that the block address is different is obtained as a result of comparing the (N+1)th address ADDR(N+1)th with the (N+2nd address ADDR N+2th, since the read voltage and the pass voltage are applied only to the blocks including the first word line 1 st The memory block WL has a word line of a different memory block, so the discharge operation can be performed on the memory block including the first word line. Therefore, the power applied to the first word line 1 st The voltage of WL may be changed to a discharge voltage (or an initial voltage).

[0175] That is, the memory device according to the embodiment of the present disclosure can omit a discharge operation and the like by comparing a previously received address with a currently received address, thereby shortening the time required for a cache read operation.

[0176] Fig.15 is a block diagram illustrating a storage device including a memory device according to an embodiment of the present disclosure.

[0177] Reference Fig.15 , the storage device 50 may include a memory device 100 and a memory controller 200. The storage device 50 may be a device that stores data under the control of a host such as a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system. Alternatively, the storage device 50 may be a device that stores data under the control of a host such as a server or a data center that stores a large amount of data in one place.

[0178] The storage device 50 may be manufactured as one of various types of storage devices according to a host interface as a communication method with a host. In addition, the storage device 50 may be manufactured as any of various types of packages.

[0179] The memory device 100 may store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may be Figure 1The memory device 100 shown. Therefore, the memory device 100 may include: a memory cell array 110 including a plurality of memory cells; a page buffer group 123 connected to the memory cells through a bit line; and a control logic 130 for controlling a peripheral circuit. Each memory cell may be configured as an SLC storing one data bit, an MLC storing two data bits, a TLC storing three data bits, or a QLC capable of storing four data bits. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0180] In implementations, the memory device 100 may be various types of volatile memories, nonvolatile memories, etc. In this specification, for ease of description, it is assumed that the memory device 100 is a NAND flash memory.

[0181] The memory device 100 may be configured to receive a command and an address from the memory controller 200 and access an area selected by the address in the memory cell array. The memory device 100 may perform an operation indicated by a command on the area selected by the address. For example, the memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. During a programming operation, the memory device 100 may program data in an area selected by an address. During a read operation, the memory device 100 may read data from an area selected by an address. During an erase operation, the memory device 100 may erase data stored in an area selected by an address. In an embodiment, training information may be stored in the memory device 100.

[0182] The memory controller 200 may control overall operations of the storage device 50 .

[0183] When power is applied to the storage device 50 , the memory controller 200 may execute firmware such as a flash translation layer (FTL) for controlling communication between a host and the memory device 100 .

[0184] In an embodiment, the memory controller 200 may receive data and a logical address (LA) from a host, and may convert the LA into a physical address (PA) indicating an address of a memory cell in the memory device 100 where data is to be stored or read.

[0185] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation according to a request of the host. During a program operation, the memory controller 200 may provide a program command, a PA, and data to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a PA to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and a PA to the memory device 100.

[0186] In an embodiment, the memory controller 200 may independently generate commands, addresses, and data regardless of a request from the host, and transmit the commands, addresses, and data to the memory device 100. For example, the memory controller 200 may provide the memory device 100 with commands, addresses, and data for performing a program operation, a read operation, and an erase operation accompanied by performing wear leveling, read reclamation, garbage collection, etc.

[0187] In an embodiment, the memory controller 200 may control at least two or more memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operation performance. The interleaving method may be a method of controlling operations of at least two memory devices 100 to overlap with each other.

[0188] In an embodiment, the memory controller 200 may include a read operation manager 210. The read operation manager 210 may provide a normal read command Normal Read CMD or a cache read command Cache Read CMD to the memory device 100 according to an external request or its own decision. The memory device 100 may provide read data to the memory controller 200 in response to the normal read command Normal Read CMD or the cache read command Cache Read CMD.

[0189] Fig.16 It is an example Fig.15 FIG. 1 is a diagram of another embodiment of a memory controller.

[0190] Reference Fig.16 , the memory controller 1000 may include a processor 1010 , an internal memory 1020 , an error correction circuit 1030 , a host interface 1040 , a buffer memory interface 1050 , and a memory interface 1060 .

[0191] The processor 1010 may perform various operations or may generate various commands for controlling the memory device 100. When a request is received from the host, the processor 1010 may generate a command according to the received request, and may send the generated command to a queue controller (not shown). The processor 1010 may control subsequent operations of the memory device 100 based on the verification result received from the memory device 100 through the memory interface 1060. In an embodiment, the processor 1010 may generate a normal read command or a cache read command.

[0192] The internal memory 1020 may store various information required for the operation of the memory controller 1000. For example, the internal memory 1020 may include a logical and physical address mapping table.

[0193] The error correction circuit 1030 may be configured to detect and correct an error of data received from the memory device 100 by using an error correction code (ECC). The processor 1010 may adjust a read voltage according to an error detection result of the error correction circuit 1030, and may control the memory device 100 to perform a re-read. In an exemplary embodiment, the error correction block may be provided as a component of the memory controller 1000.

[0194] The host interface 1040 may exchange commands, addresses, data, etc. between the memory controller 1000 and the host. For example, the host interface 1040 may receive a request, address, data, etc. from the host, and may output data read from the memory device 100 to the host. The host interface 1040 may communicate with the host using various protocols.

[0195] The buffer memory interface 1050 may transfer data between the processor 1010 and a buffer memory (not shown). The buffer memory may be used as an operation memory or a cache memory of the memory controller 1000, and may store data used in a storage device. The buffer memory may be used by the processor 1010 as a read buffer, a write buffer, a mapping buffer, etc.

[0196] The memory interface 1060 may exchange commands, addresses, data, etc. between the memory controller 1000 and the memory device 100. For example, the memory interface 1060 may send commands, addresses, data, etc. to the memory device 100 through a channel, and may receive data, etc. from the memory device 100. The memory interface 1060 may provide a cache read command or a normal read command to the memory device 100 according to an instruction of the processor 1010, and thus, the memory interface 1060 may receive read data from the memory device 100.

[0197] Fig.17is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0198] Reference Figure 1 and Fig.17 In operation S1701, the input / output circuit 125 of the memory device 100 may receive a first cache read command and a first address corresponding thereto. In an implementation, the first cache read command and the first address may be provided from an external memory controller.

[0199] Next, in operation S1703, the peripheral circuit 120 of the memory device 100 may apply a first read voltage V to the first word line WL1 according to the first address. read1 In operation S1705, according to the first read voltage V applied to the first word line WL1, read1 , the memory device may sense first read data R.Data1 stored in memory cells connected to the first word line and may store the sensed first read data R.Data1 in sense latches in the page buffer group 123. The sense latches may be connected to the memory cells through the bit lines BL1 to BLn.

[0200] Next, in operation S1707, the memory device 100 may transfer the first read data R.Data1 stored in the sense latch from the sense latch to the cache latch. The cache latch may be connected to the sense latch through the bit lines BL1 to BLn.

[0201] Furthermore, in operation S1709, the input / output circuit 125 may receive a second cache read command and a second address corresponding thereto. Operation S1709 may be performed between operations S1705 and S1707.

[0202] In operation S1711, the peripheral circuit 120 of the memory device 100 may apply an operating voltage V to the first word line WL1 and the second word line WL2 according to the second address. op The operating voltage V applied to the first word line WL1 and the second word line WL2 may be determined based on the address comparison result and the time point at which operation S1709 is performed. op That is, the control logic 130 of the memory device 100 may determine the operating voltage V applied to the first word line WL1 and the second word line WL2 based on the comparison result between the first word line WL1 and the second word line WL2 and the time point of receiving the second cache read command. op . Operating voltage V opIt may include one or more of the following: a pass voltage, a first read voltage corresponding to a first cache read command, a second read voltage corresponding to a second cache read command, an equalization voltage for synchronizing the voltages of a selected word line and an unselected word line, and a discharge voltage for discharging the selected word line and the unselected word line.

[0203] For example, in operation S1711, the first read voltage, the second read voltage, or the pass voltage may be finally applied, and before that, an equalization voltage, and / or a discharge voltage, etc. may be selectively additionally applied.

[0204] Thereafter, in operation S1713, the memory device 100 may sense the second read data R.Data2 to store the second read data R.Data2 in the sense latch, and may simultaneously output the first read data R.Data1 stored in the cache latch to an external device through the input / output line DQ. The sensing operation of the second read data R.Data2 may be performed by applying a second read voltage V to the second word line WL2 according to the second address by the peripheral circuit 120. read2 to execute.

[0205] Fig.18 is a flowchart illustrating a voltage application process in a method of operating a memory device according to an embodiment of the present disclosure.

[0206] Reference Figure 1 , Fig.17 and Fig.18 , Fig.18 A more detailed example may be Fig.17 Flow chart of operation S1711.

[0207] In operation S1801, the memory device 100 may check whether an equalization operation is performed. Fig.19 Describes the circumstances under which a balancing operation is performed.

[0208] When the equalization operation is not performed, the memory device 100 may compare addresses in operation S1803. That is, the first address according to the first read command and the second address according to the second read command may be compared.

[0209] In operation S1805, the memory device 100 may check whether the block addresses of the first address and the second address are the same. When the block addresses of the first address and the second address are different, the memory device 100 may set the operating voltage V of the first word line WL1 to 0 according to operation S1813. op From the first read voltage V read1 Change to the balanced voltage V eq In addition, the memory device 100 may set the operating voltage Vop Set to the second read voltage V read2 In an embodiment, the balanced voltage V eq The operating voltage V of the first word line WL1 op The discharge voltage V can be changed disc In another embodiment, the equalization operation may be omitted, and in this case, the operating voltage V of the first word line WL1 is op The voltage V can be read from the first read1 Change to the balanced voltage V eq .

[0210] When the block address of the first address and the block address of the second address are the same, in operation S1807, the memory device 100 may check whether the word line address of the first address and the word line address of the second address are the same. That is, it may be checked whether the first word line WL1 and the second word line WL2 are the same. When the word line address of the first address and the word line address of the second address are different, the memory device 100 may increase the operating voltage V of the first word line WL1 according to operation S1811. op From the first read voltage V read1 Change to pass voltage V pass In addition, the memory device 100 may set the operating voltage V op From the voltage V pass Change to the second reading voltage V read2 .

[0211] When the word line address of the first address and the word line address of the second address are the same, since the first word line WL1 and the second word line WL2 are the same, the memory device 100 can set the operating voltage V of the first word line WL1 to op From the first read voltage V read1 Change to the second reading voltage V read2 When the first reading voltage V read1 and the second read voltage V read2 When the voltage V of the first word line WL1 is the same, the operating voltage V op In addition, the operating voltage V op Can be maintained as a pass voltage V pass .

[0212] Fig.19 is a flowchart illustrating a voltage application process in a method of operating a memory device according to another embodiment of the present disclosure.

[0213] Reference Figure 1 , Fig.17 and Fig.19 , Fig.19 It can be illustrated in more detail Fig.17 Flow chart of operation S1711.

[0214] In operation S1901, the memory device 100 may check whether an equalization operation is performed. Fig.18 The operation of the memory device 100 without performing the equalization operation is the same as that of the operation S1801. Fig.18 Same as described.

[0215] When performing the equalization operation, the memory device 100 may check whether to perform a discharge operation in operation S1903. When performing the discharge operation, the memory device 100 may maintain the operating voltage of the first word line as the discharge voltage V according to operation S1917. disc In addition, the memory device 100 may set the voltage of the second word line WL2 to the second read voltage V read2 .

[0216] When the discharge operation is not performed, the memory device 100 may compare addresses in operation S1905. That is, the first address according to the first read command and the second address according to the second read command may be compared.

[0217] In operation S1907, the memory device 100 may check whether the block address of the first address and the block address of the second address are the same. When the block address of the first address and the block address of the second address are different, the memory device 100 may set the operating voltage V of the first word line WL1 to 0 according to operation S1915. op From the balanced voltage V eq Change to discharge voltage V disc In addition, the memory device 100 may set the operating voltage V op Set to the second read voltage V read2 .

[0218] When the block address of the first address and the block address of the second address are the same, in operation S1909, the memory device 100 may check whether the word line address of the first address and the word line address of the second address are the same. That is, it may be checked whether the first word line WL1 and the second word line WL2 are the same. When the word line address of the first address and the word line address of the second address are different, the memory device 100 may increase the operating voltage V of the first word line WL1 according to operation S1913. op From the balanced voltage V eq Change to pass voltage V pass In addition, the memory device 100 may set the operating voltage V op From the balanced voltage V eq Change to the second reading voltage V read2 .

[0219] When the word line address of the first address and the word line address of the second address are the same, since the first word line WL1 and the second word line WL2 are the same, the memory device 100 can set the operating voltage V of the first word line WL1 to 0 according to operation S1911. op From the balanced voltage V eq Change to the second reading voltage V read2 In addition, the operating voltage V op The balanced voltage V eq Change to pass voltage V pass .

[0220] CROSS-REFERENCE TO RELATED APPLICATIONS

[0221] This application claims the priority of Korean Patent Application No. 10-2023-0076771 filed on June 15, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, the memory device include: a memory cell array including a plurality of memory cells respectively connected to a plurality of word lines; A peripheral circuit, the peripheral circuit comprising: a voltage generating circuit that generates a voltage to be applied to the memory cell array; and A page buffer connected to the memory cell through a bit line and latching data sensed from the memory cell; and a control logic that senses the data stored in the memory cell in response to a cache read command received from an external device and controls the peripheral circuit to output the data latched in the page buffer to the external device, The control logic controls the peripheral circuit to generate an operating voltage to be applied to the word line based on a comparison result of a first address corresponding to a first cache read command received from the external device and a second address corresponding to a second cache read command.

2. The memory device according to claim 1, in, The control logic controls the peripheral circuit to receive word line state information indicating a voltage applied to the word line from the peripheral circuit, and generates the operation voltage based on the word line state information.

3. The memory device according to claim 2, in, The operating voltage includes at least one of the following: a pass voltage, a first read voltage corresponding to the first cache read command, a second read voltage corresponding to the second cache read command, an equalization voltage for synchronizing voltages of a selected word line and an unselected word line, and a discharge voltage for discharging the selected word line and the unselected word line.

4. The memory device according to claim 3, in, The control logic generates the equalization voltage and the discharge voltage based on the word line state information corresponding to a time point at which reception of the second cache read command is completed.

5. The memory device according to claim 4, in, When the word line state information indicates that the equalization voltage and the discharge voltage are not applied to a first word line corresponding to the first address, the control logic controls the peripheral circuit so that an operating voltage applied to the first word line is changed from the first read voltage to the pass voltage or the second read voltage.

6. The memory device according to claim 5, in, When the block address and the word line address of the first address are the same as the block address and the word line address of the second address, the control logic controls the peripheral circuit so that the operating voltage applied to the first word line is changed from the first read voltage to the second read voltage and the operating voltage applied to the unselected word line is maintained at the pass voltage.

7. The memory device according to claim 5, in, When the block address of the first address and the block address of the second address are the same and the word line address of the first address and the word line address of the second address are different, the control logic controls the peripheral circuit so that the operating voltage applied to the first word line is changed from the first read voltage to the pass voltage, and the operating voltage applied to the second word line corresponding to the second address is changed from the pass voltage to the second read voltage.

8. The memory device according to claim 5, in, When the block address of the first address and the block address of the second address are different, the control logic controls the peripheral circuit so that the operating voltage applied to the first word line changes from the first read voltage to one or more operating voltages among the equalization voltage and the discharge voltage.

9. The memory device according to claim 4, in, When the word line state information indicates that the equalization voltage is applied to a first word line corresponding to the first address and the discharge voltage is not applied to the first word line, the control logic controls the peripheral circuit so that an operating voltage applied to the first word line is changed from the equalization voltage to the pass voltage or the second read voltage.

10. The memory device according to claim 9, in, When the block address and the word line address of the first address are the same as the block address and the word line address of the second address, the control logic controls the peripheral circuit so that the operating voltage applied to the first word line is changed from the equilibrium voltage to the second read voltage, and the operating voltage applied to the unselected word line is changed from the equilibrium voltage to the pass voltage.

11. The memory device according to claim 9, in, When the block address of the first address and the block address of the second address are the same and the word line address of the first address and the word line address of the second address are different, the control logic controls the peripheral circuit so that the operating voltage applied to the first word line is changed from the equalization voltage to the pass voltage, and the operating voltage applied to the second word line corresponding to the second address is changed from the equalization voltage to the second read voltage.

12. The memory device according to claim 9, in, When a block address of the first address and a block address of the second address are different, the control logic controls the peripheral circuit so that an operating voltage applied to the first word line is changed from the equalization voltage to the discharge voltage.

13. The memory device according to claim 1, in, Each of the page buffers includes a sense latch latching read data sensed through the bit line and a cache latch caching the data latched in the sense latch.

14. The memory device according to claim 13, in, The control logic controls the peripheral circuit in response to the second cache read command so that second read data stored at a location corresponding to the second address is stored in the sense latch and first read data corresponding to the first cache read command and stored in the cache latch is output.

15. A method of operating a memory device, the method The following steps are involved: applying a first read voltage to a first word line corresponding to a first address among a plurality of word lines connected to a plurality of memory cells in response to a first cache read command; sensing first read data stored at a location corresponding to the first address through a bit line to store the first read data in a sense latch connected to the memory cell through the bit line; receiving a second cache read command and a second address; moving first read data stored in the sense latch to a cache latch connected to the sense latch through the bit line; applying an operating voltage determined based on a comparison result of the first address and the second address to the first word line and a second word line corresponding to a second address; as well as Second read data stored at a location corresponding to the second address is sensed to store the second read data in the sense latch, and the first read data stored in the cache latch is output.

16. The method according to claim 15, in, The operating voltage applied to the first word line includes at least one of the following: a pass voltage, the first read voltage, a second read voltage corresponding to the second cache read command, an equalization voltage for synchronizing voltages of a selected word line and an unselected word line, and a discharge voltage for discharging the selected word line and the unselected word line.

17. The method according to claim 16, in, When the equalization voltage and the discharge voltage are not applied to the first word line at a time point when reception of the second cache read command is completed, an operation voltage applied to the first word line is changed from the first read voltage to the pass voltage or the second read voltage.

18. The method according to claim 17, in, When the block address and the word line address of the first address are the same as the block address and the word line address of the second address, changing the operating voltage applied to the first word line from the first read voltage to the second read voltage, and Wherein, when the block address of the first address and the block address of the second address are the same and the word line address of the first address and the word line address of the second address are different, the operating voltage applied to the first word line is changed from the first read voltage to the pass voltage and the operating voltage applied to the second word line is changed from the pass voltage to the second read voltage.

19. The method according to claim 16, in, When the equalization voltage is applied to the first word line and the discharge voltage is not applied at a time point when reception of the second cache read command is completed, an operation voltage applied to the first word line is changed from the equalization voltage to the pass voltage or the second read voltage.

20. The method according to claim 19, in, When the block address and the word line address of the first address are the same as the block address and the word line address of the second address, changing the operating voltage applied to the first word line from the equalization voltage to the second read voltage, and Wherein, when the block address of the first address and the block address of the second address are the same and the word line address of the first address and the word line address of the second address are different, the operating voltage applied to the first word line is changed from the equalization voltage to the pass voltage, and the operating voltage applied to the second word line is changed from the equalization voltage to the second read voltage.

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