Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a forming method thereof. A method according to one embodiment of the present disclosure includes bonding a first semiconductor substrate having a (110) orientation on a second semiconductor substrate having a (100) orientation; forming a stack over the first semiconductor substrate, the stack including a plurality of channel layers interleaved with the plurality of sacrificial layers; patterning the stack to form a fin-shaped structure, wherein the fin-shaped structure comprises a channel region and a source / drain region; recessing the source / drain region to form a source / drain trench; forming a dielectric film in the source / drain trench; and epitaxially growing an epitaxial feature over the dielectric film, the epitaxial feature being in contact with the plurality of channel layers. The epitaxial feature has an orientation (110). The embodiment of the invention also relates to a semiconductor device and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as IC technology moves toward smaller nodes, multi-gate metal oxide semiconductor field effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and multi-bridge channel (MBC) transistors are examples of multi-gate devices, which have become popular and promising candidate devices for high performance and low leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., a gate wraps around the top and sidewalls of a semiconductor material "fin" extending from a substrate). MBC transistors have a gate structure that can extend partially or completely around a channel region to provide access to a channel region on two or more sides. Because its gate structure surrounds the channel region, MBC transistors can also be referred to as gate-around transistors (SGTs) or gate-all-around (GAA) transistors.

[0004] To improve the performance of MBC transistors, efforts have been invested in developing features and structures in the source / drain regions that strain the channel and suppress substrate current leakage.While conventional features and structures in the source / drain regions are generally adequate for their intended purposes, they are not satisfactory in all respects. Summary of the invention

[0005] Some embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: bonding a first semiconductor substrate having a (110) orientation to a second semiconductor substrate having a (100) orientation; forming a stack above the first semiconductor substrate, the stack comprising a plurality of channel layers interlaced with a plurality of sacrificial layers; patterning the stack to form a fin-shaped structure, the fin-shaped structure comprising a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing a gate spacer layer above the dummy gate stack; recessing the source / drain region to form a plurality of The invention relates to a method for forming a gate electrode and a gate stack of the plurality of sacrificial layers; forming a source / drain groove on the sidewalls of the channel layer and the plurality of sacrificial layers; recessing the plurality of sacrificial layers partially to form a plurality of internal spacer grooves; forming a plurality of internal spacer components in the plurality of internal spacer grooves; forming a dielectric film in the source / drain grooves; epitaxially growing an epitaxial component over the dielectric film, the epitaxial component contacting the plurality of channel layers, the epitaxial component having a (110) orientation; after forming the epitaxial component, removing the pseudo gate stack; releasing the plurality of channel layers in the channel region as a plurality of channel components; and forming a gate structure wrapping each of the plurality of channel components.

[0006] Other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a hybrid substrate, the hybrid substrate having: a first region having a top surface located in a (100) crystal plane and a second region having a top surface located in a (110) crystal plane; patterning the second region to form a fin-shaped substrate; forming a plurality of channel components arranged above the fin-shaped substrate; forming a plurality of internal spacer components interlaced with the plurality of channel components; depositing a dielectric material layer on the plurality of internal spacer components and above the top surface of the fin-shaped substrate; etching back the dielectric material layer to form a dielectric film; depositing an epitaxial component above the dielectric film, the epitaxial component contacting the plurality of channel components, the epitaxial component having a top surface located in the (110) crystal plane; and forming a gate structure wrapping each of the plurality of channel components.

[0007] Still other embodiments of the present application provide a semiconductor device, comprising: a fin-shaped base protruding from a semiconductor substrate, the top surface of the fin-shaped base being located in a (110) crystal plane; a plurality of channel components arranged above the top surface of the fin-shaped base; a plurality of internal spacer components interlaced with the plurality of channel components; a gate structure wrapping each of the plurality of channel components; a source / drain component contacting the plurality of channel components and the plurality of internal spacer components, the top surface of the source / drain component being located in the (110) crystal plane; and a dielectric film directly located below the source / drain component and above the top surface of the fin-shaped base. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 A flow chart of a method for forming a semiconductor device according to one or more aspects of an embodiment of the present disclosure is shown.

[0010] Figure 2 The workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Figure 1 A perspective view of the method during the bonding process.

[0011] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 and Fig.26 The workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Figure 1 A partial cross-sectional view during the manufacturing process of the method. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] In addition, when "about," "approximately," or the like is used to describe a numerical value or a range of numerical values, as understood by one of ordinary skill in the art, the term is intended to encompass numerical values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the numerical values, the numerical value or range of numerical values ​​encompasses a reasonable range that includes the described numerical value, such as within + / - 10% of the described numerical value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer known to one of ordinary skill in the art is + / - 15%. Further, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] The disclosed embodiments generally relate to multi-gate transistors and manufacturing methods, and more specifically, to multilayer components developed in the source / drain region of an MBC transistor. The channel region of an MBC transistor can be arranged in a nanowire channel member, a strip channel member, a nanosheet channel member, a nanostructure channel member, a columnar channel member, a rod-shaped channel member, and / or other suitable channel configurations. Depending on the shape of the channel member, the MBC transistor may also be referred to as a nanowire transistor or a nanosheet transistor. Regardless of the shape, each of the channel members of the MBC transistor extends between and is coupled to two epitaxial members (also referred to as source / drain epitaxial members or source / drain members) formed in the source / drain region. The source / drain region may refer to a source or a drain, individually or collectively depending on the context. The ideal source / drain member of the MBC transistor introduces strain on the channel member and provides low resistance. During the formation of the MBC transistor, inserting a dielectric film separating the bottom surface of the source / drain components can help isolate the source / drain components from the substrate and thus inhibit leakage current from entering the substrate. Although such a dielectric film helps improve AC performance, it may deteriorate DC performance in p-type transistors with increased resistance. The deterioration of DC performance in p-type transistors may be due to the loss of compressive strain.

[0016] The disclosed embodiments provide embodiments of semiconductor devices having a hybrid substrate. The hybrid substrate provides a (100) crystal plane in an NFET region (where an n-type transistor is formed) and a (110) crystal plane in a PFET region (where a p-type transistor is formed). An epitaxial stack including channel layers for n-type transistors and p-type transistors is epitaxially grown from the (100) crystal plane and the (110) crystal plane, respectively. The channel layer inherits the crystal orientation from the hybrid substrate, producing a high mobility channel not only in n-type transistors but also in p-type transistors. Not only the channel layer, but also the source / drain components epitaxially grown from the end portions of the corresponding channel layers and the corresponding channel layers inherit the crystal orientation of the hybrid substrate. The (110) source / drain components in the p-type transistor mitigate the compressive strain loss caused by inserting a dielectric film under the corresponding source / drain components. Therefore, the AC and DC performance of the transistors in the NFET and PFET regions are optimized without sacrificing the DC performance of the transistors in the PFET region. Furthermore, a base epitaxial layer may be optionally formed between the substrate and the dielectric film. The base epitaxial layer may be undoped to increase its resistance, which further improves suppression of leakage current from the source / drain features into the substrate.

[0017] Various aspects of the disclosed embodiments will now be described in more detail with reference to the accompanying drawings. Figure 11 is a flow chart illustrating a method 100 of forming a semiconductor device from a workpiece according to an embodiment of the present disclosure. The method 100 is merely an example and is not intended to limit the disclosed embodiments to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, deleted, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Figures 2 to 26 Describing method 100, Figures 2 to 26 is based on Figure 1 1 and 2. The workpiece 200 of the embodiment of the method 100 in FIG. 1 is a perspective view and a partial cross-sectional view at different manufacturing stages. Because the workpiece 200 will be manufactured into a semiconductor device, the workpiece 200 may be referred to as a semiconductor device 200 in this article as the context requires. For avoidance, Figures 2 to 26 The X, Y and Z directions are perpendicular to each other. Throughout the embodiments of the present disclosure, the same reference numerals denote the same components unless otherwise specified.

[0018] refer to Figure 1 and Figures 2 to 3 , the method 100 includes a block 102, in which a first semiconductor substrate 202 and a second semiconductor substrate 204 are bonded together to form a workpiece 200. In some embodiments, the first semiconductor substrate 202 is a first wafer, such as a first silicon wafer, and the second semiconductor substrate 204 is a second wafer, such as a second silicon wafer. The first semiconductor substrate 202 and the second semiconductor substrate 204 have different crystal plane orientations.

[0019] In crystalline semiconductor materials, the atoms that make up the solid are arranged in a periodic manner. If there is a periodic arrangement throughout the solid, the material is defined as being formed by a crystal. The periodic arrangement of atoms in a crystal is generally referred to as a "lattice". The lattice also includes a volume representing the entire lattice, and is referred to as a unit cell that is regularly repeated throughout the crystal. For example, silicon has a diamond cubic lattice structure, which can be represented as two interpenetrating face-centered cubic lattices. Therefore, the simplicity of analyzing and visualizing the cubic lattice can be extended to the characterization of silicon crystals. In the description herein, various planes in a semiconductor crystal (e.g., silicon crystal) will be referenced, especially (100), (110) and (111) crystal planes. These planes define the orientation of the plane of semiconductor atoms relative to the main crystal axis. The numerical value (xyz) is called the Miller index, and is determined by the inverse of the point where the crystal plane of silicon intersects the main crystal axis.

[0020] For example, in the illustrated embodiment, the first semiconductor substrate 202 may have a top surface located in a (100) crystal plane, and the second semiconductor substrate 204 may have a top surface located in a (110) crystal plane. The first semiconductor substrate 202 is also referred to as a (100) semiconductor substrate or a semiconductor substrate having a (100) orientation. The second semiconductor substrate 204 is also referred to as a (110) semiconductor substrate or a semiconductor substrate having a (110) orientation. In some embodiments, the two semiconductor substrates 202 and 204 are silicon substrates (e.g., silicon wafers). However, the disclosed structures and methods are not limiting and may be extended to other suitable semiconductor substrates and other suitable crystal orientations. For example, any one of the semiconductor substrates 202 and 204 may include, in the same or different crystal structures: an elemental semiconductor, such as germanium; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; or a combination thereof.

[0021] Figure 2 and Figure 3 The example shows that two semiconductor substrates 202 and 204 are bonded together with such a configuration by an appropriate bonding technique, such as direct bonding, eutectic bonding, fusion bonding, diffusion bonding, anodic bonding or other suitable bonding methods. In one embodiment, the semiconductor substrates are bonded together by direct silicon bonding (DSB). For example, the direct silicon bonding process may include pretreatment, pre-bonding at a lower temperature, and annealing at a higher temperature. When the two substrates are bonded together, a buried silicon oxide layer (BOX), or silicon oxide layer, may be implemented between them.

[0022] refer to Figure 1 and Figure 4 , the method 100 includes a frame 104, in which the semiconductor substrate 204 is thinned downward. In some embodiments, a thinning process is applied to thin the semiconductor substrate 204 downward from its backside surface. The thinning process may include a mechanical grinding process and a chemical thinning process. During the mechanical grinding process, a large amount of substrate material may be first removed from the semiconductor substrate 204. Thereafter, the chemical thinning process may apply etching chemicals to the back side of the semiconductor substrate 204 to further thin the semiconductor substrate 204 to an appropriate thickness. The thickness affects the crystal quality of the epitaxial layer subsequently formed on the workpiece 200. In some embodiments, the thickness of the semiconductor substrate 204 is in the range of about 30nm to about 100nm.

[0023] refer to Figure 1 and Figure 5, the method 100 includes a frame 106, wherein a patterned mask 206 is formed on the top surface of the workpiece 200. The patterned mask 206 includes an opening that exposes a first region 208 of the workpiece 200 and covers a second region 210 of the workpiece 200. The first region 208 is a region of the workpiece 200 defined as being used for one or more n-type field effect transistors (FETs), and the second region 210 is a region of the workpiece 200 defined as being used for one or more p-type FETs. In this context, the first region 208 is also referred to as an NFET region 208, and the second region 210 is also referred to as a PFET region 210. The patterned mask 206 can be a soft mask such as a patterned resist layer, or a hard mask such as a dielectric material layer, or a combination thereof. In one embodiment, the patterned mask 206 is a hard mask having a patterned resist layer (not shown) formed on the hard mask by a photolithography process. The hard mask is etched to transfer the opening from the patterned resist layer to the hard mask. In some instances, the hard mask includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon nitride, other semiconductor materials and / or other dielectric materials. In an embodiment, the hard mask has a thickness in the range of about 1 nm to about 40 nm. The hard mask can be formed by thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD) or any other suitable method. An exemplary photolithography process may include: forming a resist layer; exposing the resist by a photolithography exposure process; implementing a post-exposure baking process; and developing the photoresist layer to form a patterned photoresist layer. The photolithography process may be optionally replaced by other techniques, such as electron beam writing, ion beam writing, maskless patterning or molecular printing. In some embodiments, the patterned resist layer can be directly used as an etching mask for subsequent etching processes. After the hard mask is patterned, the patterned resist layer can be removed by a suitable process, such as wet stripping or plasma ashing.

[0024] refer to Figure 1 and Figure 6, the method 100 includes a block 108, wherein an etching process is performed through the opening defined in the patterned mask 206. The etching process removes the semiconductor substrate 204 from the NFET region 208 until the semiconductor substrate 202 is exposed, resulting in a recess 212. The etching process uses the patterned mask 206 as an etching mask. The etching process may further continue to recess the semiconductor substrate 202 so that the top surface of the semiconductor substrate 202 is located below the bottom surface of the semiconductor substrate 204. The sidewalls of the semiconductor substrate 204 are also exposed, defining the edges of the recess 212. The etching process may include dry etching, wet etching, or a combination thereof. The patterned mask 206 protects the semiconductor substrate 204 within the PFET region 210 from etching. In various examples, the etching process may include dry etching with a suitable etchant, such as a fluorine-containing etching gas or a chlorine-containing etching gas, such as Cl2, CCl2F2, CF4, SF6, NF3, CH2F2, or other suitable etching gases. In some other examples, the etching process may include wet etching with a suitable etchant, such as a hydrofluoric acid (HF)-based solution, a sulfuric acid (H2SO4)-based solution, a hydrochloric acid (HCl)-based solution, an ammonium hydroxide (NH4OH)-based solution, other suitable etching solutions, or combinations thereof. The etching process may include more than one step.

[0025] refer to Figure 1 and Figure 7 , the method 100 includes a block 110, in which epitaxial growth is performed to grow the thickness of the semiconductor substrate 202 in the NFET region 208. In an example where the semiconductor substrate 202 is a silicon wafer, crystalline silicon is epitaxially grown in the recess 212 and has the crystal structure of the semiconductor substrate 202. That is, the top surface of the epitaxially grown crystalline silicon has a (100) crystal plane. In the illustrated embodiment, the elevated top surface of the semiconductor substrate 202 is located above the top surface of the semiconductor substrate 204 and intersects the sidewalls of the patterned mask 206. The crystalline silicon can be grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process such as a metal organic CVD (MOCVD) process, and / or other suitable epitaxial growth process. The patterned mask 206 prevents epitaxial growth from occurring in the PFET region 210. At the end of the epitaxial growth, the top surface of the semiconductor substrate 202 can be higher than the top surface of the semiconductor substrate 204 by a range of about 30 nm to about 100 nm.

[0026] refer to Figure 1 and Figure 8, the method 100 includes a block 112, in which a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to planarize the top surface of the workpiece 200. The patterned mask 206 can be used as a polishing stop layer during the CMP process and removed by etching after the CMP. Alternatively, the patterned mask 206 can be removed by the CMP process. After the CMP process, the top surfaces of the semiconductor substrates 202 and 204 are both exposed and substantially coplanar. The remaining thickness of the semiconductor substrate 204 is in the range of about 30 nm to about 100 nm. Because the elevated portion of the semiconductor substrate 202 is formed by epitaxial growth from the (100) crystal plane, it is located in the crystal structure and has the same crystal orientation. That is, the top surface of the semiconductor substrate 202 in the NFET region 208 is still located in the (100) crystal plane, while the top surface of the semiconductor substrate 204 in the PFET region 210 is located in the (110) crystal plane. At the conclusion of block 112 , the semiconductor substrate 202 and the semiconductor substrate 204 (also referred to as the semiconductor layer 204 ) together define a hybrid substrate 205 .

[0027] refer to Figure 1 and Fig. 9 , the method 100 includes a frame 114, in which a stack 214 of alternating semiconductor layers is formed above the hybrid substrate 205. In some embodiments, before forming the stack 214, the NFET region 208 and the PFET region 210 are doped with corresponding doping profiles depending on design requirements known in the art. For example, a p-type dopant can be doped into the NFET region 208 to form a p-type well (or p-well), and an n-type dopant can be doped into the PFET region 210 to form an n-type well (or n-well). The n-type dopant for forming the n-type well may include phosphorus (P) or arsenic (As). The p-type dopant for forming the p-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of the dopant. After the dopant implantation, the stack 214 is epitaxially grown above the hybrid substrate 205.

[0028] In some embodiments, the stack 214 includes sacrificial layers 216 of a first semiconductor composition interleaved with channel layers 218 of a second semiconductor composition. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layers 216 include silicon germanium (SiGe) and the channel layers 218 include silicon (Si). It should be noted that the three (3) layers of the sacrificial layers 216 and the three (3) layers of the channel layers 218 are arranged alternately, as shown in FIG. Fig. 9 , which is for illustrative purposes only and is not intended to be limiting beyond what is specifically recited in the claims. It is understood that any number of epitaxial layers can be formed in the stack 214. The number of layers depends on the desired number of channel members for the workpiece 200. In some embodiments, the number of channel layers 218 is between 1 and 20.

[0029] In some embodiments, all sacrificial layers 216 may have a substantially uniform first thickness between about 3 nm and about 10 nm, and all channel layers 218 may have a substantially uniform second thickness between about 3 nm and about 15 nm. The first thickness and the second thickness may be the same or different. As described in more detail below, the channel layer 218 or a portion thereof may be used as a channel member for a subsequently formed multi-gate device, and the thickness of each of the channel layers 218 is selected based on device performance considerations. The sacrificial layer 216 in the channel region may be ultimately removed and used to define the vertical distance between adjacent channel regions for a subsequently formed multi-gate device, and the thickness of each of the sacrificial layers 216 is selected based on device performance considerations.

[0030] The layers in stack 214 may be deposited using a molecular beam epitaxy (MBE) process, a vapor phase epitaxy (VPE) process, and / or other suitable epitaxial growth processes. Therefore, stack 214 is also referred to as epitaxial stack 214. As described above, in at least some examples, sacrificial layer 216 includes an epitaxially grown silicon germanium (SiGe) layer, and channel layer 218 includes an epitaxially grown silicon (Si) layer. In some embodiments, sacrificial layer 216 and channel layer 218 are substantially free of dopants (i.e., have a dopant content of from about 0 cm -3 About 1×10 17 cm -3 extrinsic dopant concentration) where, for example, no intentional doping is performed during the epitaxial growth process for the stack 214. In the NFET region 208, the top surface of the semiconductor substrate 202 lies in the (100) crystal plane, and thus each layer of the stack 214 in the NFET region 208 has a (100) top surface. In the PFET region 210, the top surface of the semiconductor layer 204 lies in the (110) crystal plane, and thus each layer of the stack 214 in the PFET region 210 has a (110) top surface.

[0031] refer to Figure 1 and Fig.10 , the method 100 includes block 116, where a fin structure 222 is formed by patterning the stack 214 and a top portion of the hybrid substrate 205. In the illustrated embodiment, a fin structure 222N is formed in the NFET region 208 by patterning the stack 214 and a top portion of the semiconductor substrate 202, and a fin structure 222P is formed in the PFET region 210 by patterning the stack 214, the semiconductor layer 204, and a top portion of the semiconductor substrate 202.

[0032] In order to pattern the stack 214, a hard mask (not shown) may be deposited over the stack 214 to form an etching mask. The hard mask may be a single layer or multiple layers. For example, the hard mask may include a pad oxide layer and a pad nitride layer over the pad oxide layer. The fin structure 222 may be patterned from the stack 214 and the hybrid substrate 205 using a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods.

[0033] In some embodiments, a double patterning or multiple patterning process can be used to define a fin structure having a pitch smaller than that obtainable using a single, direct lithography process, for example. For example, in one embodiment, a material layer is formed and patterned over a substrate using a lithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 222 by etching the stack 214 and the top portion of the hybrid substrate 205. The patterned top portion of the hybrid substrate 205 is also represented as a fin base 212B. In the NFET region 208, the fin base 212B includes the top portion of the semiconductor substrate 202. In the PFET region 210, the fin base 212B includes the semiconductor layer 204 and the top portion of the semiconductor substrate 202. Each of the fin structures 222 (which includes the patterned stack 214 and the fin base 212B) extends vertically in the Z direction and extends longitudinally in the X direction. In some examples, each of the fin structures 222 has a width measured along the Y direction between about 6 nm and about 80 nm, and a distance between opposite sidewalls of two adjacent fin structures 222 is measured along the Y direction between about 6 nm and about 115 nm.

[0034] Still reference Fig.10, an isolation component 224 may be formed adjacent to the fin-shaped structure 222. In some embodiments, the isolation component 224 may be formed in a trench between adjacent fin-shaped structures 222 to isolate the fin-shaped structures 222 from each other. The isolation component 224 may also be referred to as a shallow trench isolation (STI) component 224. For example, in some embodiments, a dielectric layer is first deposited over the hybrid substrate 205, and the trench is filled with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, a spin coating process, and / or other suitable processes. Then, for example, by a CMP process, the deposited dielectric material is thinned and planarized. The planarized dielectric layer is further recessed or pulled back by a dry etching process, a wet etching process, and / or a combination thereof to form the STI component 224. After being recessed, the fin structure 222 rises above the STI feature 224. The recessed top surface of the STI feature 224 may be flush with or below the bottom surface of the patterned stack 214.

[0035] refer to Figure 1 and Fig.11 The method 100 includes block 118 where a dummy gate stack 230 is formed over the channel region of the fin structure 222 . Fig.11 Shown are respectively through Fig.10 AA and BB lines in the cross-sectional view. In some embodiments, a gate replacement process (or a gate-last process) is adopted, in which the dummy gate stack 230 is used as a placeholder to undergo various processes, and is removed and replaced by a functional gate structure. Other processes and configurations are also possible. The dummy gate stack 230 is formed above the fin structure 222, and the fin structure 222 is divided into a channel region located below the dummy gate stack 230 and a source / drain region not located below the dummy gate stack 230. The channel region is adjacent to the source / drain region, wherein each channel region is arranged between two source / drain regions along the X direction.

[0036] The formation of the dummy gate stack 230 may include deposition of layers in the dummy gate stack 230 and patterning of these layers. Fig.11, a dummy dielectric layer 226, a dummy electrode layer 228, and a gate top hard mask layer 232 may be blanket deposited over the workpiece 200. In some embodiments, the dummy dielectric layer 226 may be formed on the fin structure 222 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, or other suitable process. In some instances, the dummy dielectric layer 226 may include silicon oxide. Thereafter, the dummy electrode layer 228 may be deposited over the dummy dielectric layer 226 using a CVD process, an ALD process, or other suitable process. In some instances, the dummy electrode layer 228 may include polysilicon. For patterning purposes, the gate top hard mask layer 232 may be deposited on the dummy electrode layer 228 using a CVD process, an ALD process, or other suitable process. Then, the gate top hard mask layer 232, the dummy electrode layer 228, and the dummy dielectric layer 226 may be patterned to form a dummy gate stack 230, such as Fig.11 As shown in . For example, the patterning process may include a lithography process (e.g., photolithography or electron beam lithography), which may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. In some embodiments, the gate top hard mask layer 232 may include a silicon oxide layer 234 and a silicon nitride layer 236 above the silicon oxide layer 234.

[0037] refer to Figure 1 and Fig.12 , the method 100 includes a frame 120, wherein a gate spacer layer 238 is deposited over the dummy gate stack 230. In some embodiments, the gate spacer layer 238 is conformally deposited over the workpiece 200, including over the top surface and sidewalls of the dummy gate stack 230. The term "conformal" is used herein to facilitate describing a layer having a substantially uniform thickness over various regions. The gate spacer layer 238 may be a single layer or multiple layers. At least one layer of the gate spacer layer 238 may include silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, or silicon nitride. The gate spacer layer 238 may be deposited over the dummy gate stack 230 using a process such as a CVD process, a sub-atmospheric pressure CVD (SACVD) process, an ALD process, or other suitable process. In one embodiment, the gate spacer layer 238 includes a first layer and a second layer disposed over the first layer. The first layer may include silicon oxynitride, and the second layer may include silicon nitride. In some examples, the gate spacer layer 238 has a thickness between about 3 nm and about 8 nm measured along the X direction.

[0038] refer to Figure 1 and Fig.13, method 100 includes frame 122, in which the source / drain region of the fin structure 222 is recessed to form a source / drain trench 240. In some embodiments, the source / drain region not covered by the dummy gate stack 230 and the gate spacer layer 238 is etched by dry etching or a suitable etching process to form the source / drain trench 240. For example, the dry etching process can be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. Fig.13 In some embodiments shown in , the source / drain regions of the fin structure 222 are recessed to expose the sidewalls of the sacrificial layer 216 and the channel layer 218. In some embodiments, the source / drain trenches 240 extend under the stack 214 into the hybrid substrate 205. Fig.13 As shown in FIG. 2 , the semiconductor substrate 202 is exposed in the source / drain trenches 240 in the NFET region 208 , and the semiconductor layer 204 is exposed in the source / drain trenches 240 in the PFET region 210 . The semiconductor substrate 202 remains covered by the semiconductor layer 204 in the PFET region 210 .

[0039] refer to Figure 1 , Fig.14 and Fig.15 , the method 100 includes block 124, in which an inner spacer feature 244 is formed. The operations in block 124 may include: selectively and partially removing the sacrificial layer 216 to form an inner spacer recess 242; depositing an inner spacer material over the workpiece 200; and etching back the inner spacer material to form the inner spacer feature 244 in the inner spacer recess 242. The sacrificial layer 216 ( Fig.14) is selectively and partially recessed to form an internal spacer recess 242. Due to limited etching contrast, the end portions of the channel layer 218 as exposed by the internal spacer recess 242 may also suffer some etching loss, so that the end portions of the channel layer 218 may be moderately etched and become thinner than the central portion of the channel layer 218 measured along the Z direction. In an embodiment where the channel layer 218 is primarily composed of silicon (Si) and the sacrificial layer 216 is primarily composed of silicon germanium (SiGe), a selective wet etching process or a selective dry etching process may be used to implement the selective recessing of the sacrificial layer 216. The selectivity and partial recessing of the sacrificial layer 216 may include a SiGe oxidation process and subsequent SiGe oxide removal. In this embodiment, the SiGe oxidation process may include the use of ozone. In some other embodiments, the selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0040] After forming the inner spacer recess 242, an inner spacer material is deposited over the workpiece 200, including over the inner spacer recess 242. The inner spacer material may include a metal oxide, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material. The metal oxide may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides. Although not explicitly shown, the inner spacer material may be a single layer or multiple layers. In some embodiments, the inner spacer material may be deposited using CVD, PECVD, SACVD, ALD, or other suitable methods. The inner spacer material is deposited into the inner spacer recess 242 and over the sidewalls of the channel layer 218 exposed in the source / drain trench 240. Reference Fig.15 , and then etch back the deposited internal spacer material to remove the internal spacer material from the sidewalls of the channel layer 218 to form an internal spacer feature 244 in the internal spacer recess 242. In block 124, the internal spacer material may also be removed from the top surface and / or sidewalls of the gate top hard mask layer 232 and the gate spacer layer 238. In some embodiments, the etch back operation performed in block 124 may include using hydrogen fluoride (HF), fluorine gas (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), or other fluorine-based etchants. Fig.15 As shown in , each of the inner spacer features 244 is in direct contact with the recessed sacrificial layer 216 and is disposed between two adjacent channel layers 218. In some examples, each of the inner spacer features 244 measures a thickness between about 3 nm and about 5 nm along the X direction.

[0041] refer to Figure 1and Fig.16 , method 100 includes frame 126, in which a cleaning process 300 is implemented. The cleaning process 300 may include dry cleaning, wet cleaning, or a combination thereof. In some instances, wet cleaning may include using standard cleaning 1 (RCA SC-1, a mixture of deionized (DI) water, ammonium hydroxide, and hydrogen peroxide), standard cleaning 2 (RCA SC-2, a mixture of DI water, hydrochloric acid, and hydrogen peroxide), SPM (sulfuric acid peroxide mixture), and / or hydrofluoric acid for oxide removal. The dry cleaning process may include helium (He) and hydrogen (H2) treatment at a temperature between about 250° C. and about 550° C. and at a pressure between about 75 mTorr and about 155 mTorr. The hydrogen treatment may convert silicon on the surface into silane (SiH4), which may be extracted for removal. In some embodiments, the cleaning process is configured to selectively remove or trim portions of the channel layer without substantially removing the internal spacer features 244. The cleaning process 300 may remove surface oxides and debris to ensure a clean semiconductor surface, which facilitates growth of the base epitaxial layer in block 128 .

[0042] refer to Figure 1 and Fig.17 , the method 100 includes a block 128, in which a base epitaxial layer 246 is deposited in the bottom of each of the source / drain trenches 240. In the illustrated embodiment, the base epitaxial layer 246 formed in the NFET region 208 is represented as a base epitaxial layer 246N, and the base epitaxial layer 246 formed in the PFET region 210 is represented as a base epitaxial layer 246P. The base epitaxial layer 246N has the same crystal structure of the semiconductor substrate 202. That is, the top surface of the base epitaxial layer 246N has a (100) crystal plane. The base epitaxial layer 246P has the same crystal structure of the semiconductor layer 204. That is, the top surface of the base epitaxial layer 246P has a (110) crystal plane. In some embodiments, the base epitaxial layer 246 includes the same material as the channel layer 218, such as silicon (Si). In particular, the base epitaxial layer 246 is made of undoped silicon. In some embodiments, the base epitaxial layer 246 includes the same material as the sacrificial layer 216, such as silicon germanium (SiGe), wherein the germanium (Ge) content is the same as or different from that of the sacrificial layer 216. In particular, the base epitaxial layer 246 is made of undoped silicon germanium. In various embodiments, the base epitaxial layer 246 has no dopants, wherein, for example, no intentional doping is performed during the epitaxial growth process. The base epitaxial layer 246 without dopants provides a high resistance path at the bottom of the source / drain trench 240, thereby inhibiting leakage current from entering the substrate.

[0043] Suitable epitaxial processes for block 128 include vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), selective CVD, and / or other suitable processes. Various deposition parameters may be adjusted to selectively deposit semiconductor material on the exposed semiconductor surface in the source / drain trench 240, such as deposition gas composition, carrier gas composition, deposition gas flow rate, carrier gas flow rate, deposition time, deposition pressure, deposition temperature, source power, RF bias voltage, DC bias voltage, RF bias voltage, DC bias voltage, other suitable deposition parameters, or combinations thereof. In some embodiments, when forming the base epitaxial layer 246, the workpiece 200 is exposed to a deposition mixture including DCS and / or SiH4 (silicon-containing precursor), H2 (carrier precursor), and HCl (etchant-containing precursor). In some embodiments, the selective CVD process implements a deposition temperature of about 600°C to about 750°C. In some embodiments, the selective CVD process implements a deposition pressure of about 10 Torr to about 100 Torr. In some embodiments, the selective CVD process is configured as a bottom-up deposition process, so that the base epitaxial layer 246 grows from the exposed semiconductor surface at the bottom of the source / drain trench 240, but does not grow from the exposed end portion of the channel layer 218. The growth of the base epitaxial layer 246 is under time control, so that the top surface of the base epitaxial layer 246 can be finely adjusted to be flush with the bottom surface of the bottommost sacrificial layer 216, below or above the bottom surface of the bottommost sacrificial layer 216, depending on the device performance requirements. If the top surface of the base epitaxial layer 246 is below the bottom surface of the bottommost sacrificial layer 216, the base epitaxial layer 246 may not be in physical contact with the bottommost internal spacer component 244. Otherwise, the base epitaxial layer 246 may be in physical contact with the bottommost internal spacer component 244.

[0044] refer to Figure 1 , Fig.18 and Fig.19 , the method 100 includes a block 130, in which a dielectric film 250 is formed in the bottom of the source / drain trench 240 and on the base epitaxial layer 246. The operations in block 130 may include: depositing a dielectric material 248 over the workpiece 200; and etching back the dielectric material 248 to form the dielectric film 250 in the bottom of the source / drain trench 240. The dielectric material 248 is deposited over the workpiece 200, including over the sidewalls and bottom surface of the source / drain trench 240 and over the sidewalls and top surface of the dummy gate stack 230, as shown in FIG. Fig.18. In some embodiments, the dielectric material 248 may include a metal oxide or a metal nitride, such as La2O3, Al2O3, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Y2O3, AlON, TaCN, other suitable materials, or combinations thereof. In some embodiments, the dielectric material 248 may include silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material. In some embodiments, the dielectric material 248 may be deposited using a directional deposition process (such as PEALD with RF plasma treatment) or other suitable method. Under directional plasma treatment, the horizontal portion of the dielectric material 248 receives more plasma bombardment than the vertical portion, so that the horizontal portion and the vertical portion have different etching selectivities, allowing the dielectric material 248 to be etched back while the horizontal portion remains at the bottom of the source / drain trench 240. Alternatively, the directional deposition process can form the dielectric material 248 having a thicker horizontal portion (e.g., on the bottom surface of the source / drain trench 240) and a thinner vertical portion (e.g., on the sidewalls of the dummy gate stack 230), which also allows the horizontal portion to remain after etching back the dielectric material 248. In some embodiments, the horizontal portion of the dielectric material 248 has a thickness in a range of about 4.5 nm to about 10.5 nm, while the vertical portion of the dielectric material 248 has a thinner thickness in a range of about 3.5 nm to about 5.5 nm.

[0045] refer to Fig.19 , and then etch back the deposited dielectric material 248 to remove the thinner vertical portion from the sidewalls of the dummy gate stack 230. In some embodiments, the etch back operation performed in frame 130 may include the use of hydrogen fluoride (HF), fluorine gas (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), or other fluorine-based etchants. Due to the loading effect, the horizontal portion on the top of the dummy gate stack 230 may also be removed, while the horizontal portion in the bottom of the source / drain trench 240 is thinned downward, but still remains as a dielectric film 250, which covers the base epitaxial layer 246. In some embodiments, the dielectric film 250 has a thickness (measured in the Z direction) in the range of about 1 nm to about 5 nm. The top surface of the dielectric film 250 can be located above the bottom surface of the bottommost sacrificial layer 216, but lower than the top surface of the bottommost sacrificial layer 216. The bottommost inner spacer component 244 may have a height measured in the Z direction from about 5 nm to about 7 nm, such that the dielectric film 250 is in physical contact with the bottommost inner spacer component 244, while the top portion of the bottommost inner spacer component 244 is located above the top surface of the dielectric film 250. In the depicted embodiment, the top surface of the dielectric film 250 has a flat profile. Alternatively, the top surface of the dielectric film 250 may have a concave profile or a convex profile.

[0046] refer to Figure 1 and Fig. 20 , the method 100 includes a block 132 in which the channel layer 218 in the PFET region 210 is laterally recessed. The etching back of the channel layer 218 in the PFET region 210 produces a smaller channel length in the PFET region 210 than in the NFET region 208. The etching back of the channel layer 218 in the PFET region 210 pushes the junction back closer to the gate structure in the PFET, which is beneficial to the PFET performance. In some embodiments, a resist layer is formed over the NFET region 208, while the PFET region 210 is exposed. The etching back operation performed in block 132 may include using hydrogen fluoride (HF), fluorine gas (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), or other fluorine-based etchants. In the illustrated embodiment, the end portions of the channel layer 218 vertically stacked between the inner spacer features 244 are removed from the PFET region 210. In some embodiments, the operations in block 132 are optional, and method 100 may proceed to block 134 without performing the operations in block 132 .

[0047] refer to Figure 1 and Fig.21 , the method 100 includes block 134, in which source / drain features 256 are epitaxially and selectively formed from the exposed sidewalls of the channel layer 218, while the sidewalls of the sacrificial layer 216 remain covered by the inner spacer features 244. Suitable epitaxial processes for block 134 include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. In the illustrated embodiment, the source / drain features 256 formed in the NFET region 208 are denoted as source / drain features 256N, and the source / drain features 256 formed in the PFET region 210 are denoted as source / drain features 256P. The source / drain features 256N have the same crystal structure of the semiconductor substrate 202 and the channel layer 218 in the NFET region 208. That is, the top surface of the source / drain features 256N has a (100) crystal plane. The source / drain feature 256P has the same crystal structure of the semiconductor layer 204 and the channel layer 218 in the PFET region 210. That is, the top surface of the source / drain feature 256P has a (110) crystal plane.

[0048] Source / drain features 256N and 256P may be formed separately. For example, source / drain feature 256N may be epitaxially grown in source / drain trench 240 in NFET region 208, while source / drain trench 240 in PFET region 210 is covered under a resist layer that blocks epitaxial growth from occurring in PFET region 210. After forming source / drain feature 256N, source / drain feature 256P is epitaxially grown in source / drain trench 240 in PFET region 210, while NFET region 208 is covered under a resist layer that blocks epitaxial growth from occurring in NFET region 208. Alternatively, source / drain feature 256P may be epitaxially grown before source / drain feature 256N.

[0049] In the NFET region 208, the source / drain feature 256N may include Si, SiP, SiAs, SiC, SiCP, SiCAs, or other suitable semiconductor materials. The source / drain feature 256N may be doped with a dopant such as arsenic (As) or phosphorus (P). In one example, the source / drain feature 256N may be doped with a dopant having a value from about 5×10 20 cm -3 About 4×10 21 cm -3 When the source / drain feature 256N includes carbon, the carbon atomic percentage can be in the range of about 10% to about 20%. In some embodiments, the source / drain feature 256N includes the same semiconductor material as the base epitaxial layer 246N, but has a higher dopant concentration. For example, the source / drain feature 256N and the base epitaxial layer 246N can both include silicon, while the source / drain feature 256N is doped with phosphorus, while the base epitaxial layer 246N is substantially free of dopants.

[0050] In the PFET region 210, the source / drain feature 256P may include SiGe, SiSn, or other suitable semiconductor materials. The source / drain feature 256P may be doped with dopants such as germanium (Ge) or boron (B). In one example, the source / drain feature 256P is doped with boron (B), and the source / drain feature 256P includes SiGeB, SiSnB, or a SiGeB having a value from about 4×10 20 cm -3 About 2×10 21 cm -3When the source / drain feature 256P includes germanium, the atomic percentage of germanium can be in the range of about 10% to about 60%. In some embodiments, the source / drain feature 256P includes the same semiconductor material as the base epitaxial layer 246P, but has a higher dopant concentration. For example, the source / drain feature 256P and the base epitaxial layer 246P can both include SiGe, while the source / drain feature 256P is doped with boron and the base epitaxial layer 246P is substantially free of dopants. If the channel layer 218 in the PFET region 210 is laterally recessed in box 132, the source / drain feature 256P has a lateral protrusion that extends to a position directly below the gate spacer layer 238 (or even directly below the dummy gate stack 230) and is vertically stacked with the internal spacer feature 244, such as Fig.23 In addition, due to those additional protruding portions, the source / drain feature 256P may have a larger volume than the source / drain feature 256N.

[0051] Fig. 22 Shown are respectively through Fig.21 Cross-sectional view cut along CC line and DD line in FIG. In the NFET region 208 and the PFET region 210, the gate spacer layer 238 formed in the frame 120 is also deposited on the sidewalls of the fin structures 222N and 222P in the source / drain region, respectively. The portion of the gate spacer layer 238 located in the source / drain region is also referred to as the fin spacer layer 238'. After the fin structures 222N and 222P are recessed and the substrate epitaxial layers 246N and 246P are epitaxially grown, the fin spacer layer 238' is located above the sidewalls of the substrate epitaxial layers 246N and 246P. The fin spacer layer 238' limits the epitaxial growth of the substrate epitaxial layers 246N and 246P in the Y direction. The recessing of the fin structures 222N and 222P also recesses the STI component 224. The fin spacer layer 238′ can protect the portion of the STI feature 224 directly below it from etching loss, while recessing other portions of the STI feature 224. The bottom surfaces of the base epitaxial layers 246N and 246P can be located above the recessed top surfaces of the STI features 224. The bottom surface of the semiconductor layer 204 can also be located above the recessed top surfaces of the STI features 224.

[0052] Still reference Fig. 22, for clarity of spatial relationship, the channel layer 218 and the sacrificial layer 216 in the channel region are superimposed, as shown by the dashed box. In some embodiments, the top surface of the dielectric film 250 can be located above the bottom surface of the bottommost sacrificial layer 216 and below the top surface of the bottommost sacrificial layer 216. In some embodiments, the bottom surface of the dielectric film 250 can be flush with the bottom surface of the bottommost sacrificial layer 216. In some embodiments, the thickness of the dielectric film 250 after epitaxially growing the source / drain features 256N and 256P can be in the range of about 0.5 nm to about 6.5 nm. In the NFET region 208, the top surface of the source / drain feature 256N can be grown above the top surface of the fin-shaped structure 222N (i.e., the top surface of the topmost channel layer 218). In some embodiments, the top surface of the source / drain feature 256N is located above the top surface of the fin-shaped structure 222N by a distance Hn in the range of about 1 nm to about 11 nm. In some embodiments, the width Wn of the source / drain feature 256N measured in the Y direction may be in the range of about 33 nm to about 42 nm. In the PFET region 210, the top surface of the source / drain feature 256P may be grown above the top surface of the fin structure 222P (i.e., the top surface of the topmost channel layer 218). In some embodiments, the top surface of the source / drain feature 256P is located above the top surface of the fin structure 222P by a distance Hp in the range of about 1 nm to about 11 nm. In some embodiments, the width Wp of the source / drain feature 256P measured in the Y direction may be in the range of about 33 nm to about 42 nm.

[0053] refer to Figure 1 and Fig.23 , the method 100 includes a block 136, wherein the workpiece 200 is annealed in an annealing process 400. In some embodiments, the annealing process 400 may include a rapid thermal annealing (RTA) process, a laser spike annealing process, a rapid annealing process, or a furnace annealing process. The annealing process 400 may include a peak annealing temperature between about 900° C. and about 1000° C. In these embodiments, the peak annealing temperature may be maintained for a duration measured in seconds or microseconds. Through the annealing process 400, a desired electron contribution of a p-type dopant in a semiconductor body, such as silicon germanium (SiGe) or germanium (Ge), may be obtained. The annealing process 400 may generate vacancies that promote movement of the p-type dopant from an interstitial position to a substitutional lattice position and reduce damage or defects in the lattice of the semiconductor body.

[0054] refer to Figure 1 and Figure 24 to Figure 26 , the method 100 includes block 138, where further processing is performed. Such further processing may include, for example, depositing a contact etch stop layer (CESL) 258 ( Fig.24 ); an interlayer dielectric (ILD) layer 260 is deposited over the CESL 258 ( Fig.24 ); removing the dummy gate stack 230 ( Fig.25 ); selectively removing the sacrificial layer 216 in the channel region to release the channel layer 218 as a channel member ( Fig.25 ); and forming a gate structure 266 ( Fig.26 ).

[0055] Reference now Fig.24 , the CESL 258 is formed before forming the ILD layer 260. In some instances, the CESL 258 includes silicon nitride, silicon oxynitride, and / or other materials known in the art. The CESL 258 can be formed by ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition processes. The ILD layer 260 is then deposited over the CESL 258. In some embodiments, the ILD layer 260 includes materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer 260 can be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 260, the workpiece 200 can be annealed to improve the integrity of the ILD layer 260. Fig.24 As shown in FIG. 2 , the CESL 258 is disposed directly on the top surface of the source / drain features 256. After the CESL 258 and the ILD layer 260 are deposited, the workpiece 200 may be planarized by a planarization process to expose the dummy gate stack 230. For example, the planarization process may include a chemical mechanical planarization (CMP) process. After the CMP process, the distance from the top surface of the dummy gate stack 230 to the top surface of the topmost channel layer 218 may be between 5 nm and about 50 nm measured along the Z direction.

[0056] The exposure of the dummy gate stack 230 allows the dummy gate stack 230 to be removed and the channel layer 218 to be released. Fig.25. In some embodiments, removing the dummy gate stack 230 creates a gate trench 262 above the channel region. Removing the dummy gate stack 230 may include one or more etching processes that are selective to the material of the dummy gate stack 230. For example, removing the dummy gate stack 230 may be implemented using selective wet etching, selective dry etching, or a combination thereof that is selective to the dummy gate stack 230. After removing the dummy gate stack 230, the sidewalls of the channel layer 218 and the sacrificial layer 216 in the channel region are exposed in the gate trench 262. After removing the dummy gate stack 230, the method 100 may include an operation of selectively removing the sacrificial layer 216 between the channel layers 218 in the channel region. Selectively removing the sacrificial layer 216 releases the channel layer 218 to form a channel member (also numbered 218). Selectively removing the sacrificial layer 216 also leaves a space 264 between the channel members 218. The selective removal of the sacrificial layer 216 may be implemented by selective dry etching, selective wet etching, or other selective etching processes. An exemplary selective dry etching process may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process may include APM etching (eg, ammonium hydroxide-hydrogen peroxide-water mixture).

[0057] refer to Fig.26, the method 100 may include further operations to form a gate structure 266 to wrap each of the channel members 218. In some embodiments, the gate structure 266 is formed in the gate trench 262 and in the space 264 left by removing the sacrificial layer 216. At this point, the gate structure 266 wraps each of the channel members 218. The gate structure 266 includes a gate dielectric layer 268 and a gate electrode layer 270 above the gate dielectric layer 268. In some embodiments, although not explicitly shown in the figure, the gate dielectric layer 268 includes an interface layer and a high-K gate dielectric layer. High-K dielectric materials (as used and described herein) include dielectric materials with a high dielectric constant (~3.9) greater than, for example, the dielectric constant of thermal silicon oxide. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-K gate dielectric layer may include hafnium oxide. Alternatively, the high-K gate dielectric layer may include other high-K dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium oxide silicon (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-K gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0058] The gate electrode layer 270 of the gate structure 266 may include a single layer or optionally a multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy or various combinations of metal silicides. For example, the gate electrode layer 270 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer 270 may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In various embodiments, a CMP process may be performed to remove excess metal, thereby providing a substantially planar top surface of the gate structure 266. The gate structure 266 includes a portion between the channel members 218 in the channel region.

[0059] Still reference Fig.26At the end of the operation in box 138, transistors 280 are substantially formed, particularly one or more n-type transistors (NFET) 280N in the NFET region 208 and one or more p-type transistors (PFET) 280P in the PFET region 210. The transistor 280 includes channel members 218 vertically stacked along the Z direction. Each of the channel members 218 is wrapped by a corresponding gate structure 266. The channel member 218 extends along the X direction or is sandwiched between two source / drain features 256. Below the source / drain features 256 are the dielectric film 250 and the base epitaxial layer 246. The dielectric film 250 and the base epitaxial layer 246 exhibit high resistivity, thereby providing a high resistance path from the source / drain features 256 to the substrate, thereby suppressing leakage current from entering the substrate. In particular, in the NFET region 208, the channel member 218, the base epitaxial layer 246N, and the source / drain feature 256N all have a (100) crystal structure, which is the same as the semiconductor substrate 202; in the PFET region 210, the channel member 218, the base epitaxial layer 246P, and the source / drain feature 256P all have a (110) crystal structure, which is the same as the semiconductor layer 204. The (110) crystal structure of the channel member 218 provides a higher carrier mobility for the p-type transistor, while the (110) crystal structure of the source / drain feature 256P mitigates the loss of compressive strain caused by inserting the dielectric film 250 under the source / drain feature 256P. Therefore, the AC and DC performance of the transistors in the NFET region 208 and the PFET region 210 are optimized without sacrificing the DC performance of the p-type transistor in the PFET region 210.

[0060] In one exemplary aspect, the disclosed embodiments relate to a method. The method includes: bonding a first semiconductor substrate having a (110) orientation to a second semiconductor substrate having a (100) orientation; forming a stack above the first semiconductor substrate, the stack including a plurality of channel layers interlaced with a plurality of sacrificial layers; patterning the stack to form a fin-shaped structure, the fin-shaped structure including a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing a gate spacer layer above the dummy gate stack; recessing the source / drain region to form a plurality of channel layers and a plurality of sacrificial layers; The method further comprises: forming a source / drain trench on the sidewall of the layer; recessing a plurality of sacrificial layer portions to form a plurality of internal spacer grooves; forming a plurality of internal spacer components in the plurality of internal spacer grooves; forming a dielectric film in the source / drain trench; epitaxially growing an epitaxial component over the dielectric film, the epitaxial component in contact with a plurality of channel layers, the epitaxial component having a (110) orientation; removing the dummy gate stack after forming the epitaxial component; releasing a plurality of channel layers in the channel region as a plurality of channel components; and forming a gate structure encapsulating each of the plurality of channel components. In some embodiments, the method also comprises: depositing a base epitaxial layer in the source / drain trench before depositing the dielectric film. In some embodiments, the base epitaxial layer is free of dopants. In some embodiments, the base epitaxial layer has a (110) orientation. In some embodiments, the channel layer in the stack has a (110) orientation. In some embodiments, the sacrificial layer in the stack has a (110) orientation. In some embodiments, the epitaxial component is doped with a p-type dopant. In some embodiments, the epitaxial component comprises silicon germanium. In some embodiments, forming the dielectric film includes: depositing a dielectric layer over the bottom surface and sidewall surfaces of the source / drain trench; and removing the dielectric layer from the sidewall surfaces of the source / drain trench. In some embodiments, the fin structure includes a first semiconductor substrate and a top portion of a second semiconductor substrate.

[0061] In another exemplary aspect, the disclosed embodiments relate to a method. The method includes: forming a hybrid substrate, the hybrid substrate having: a first region having a top surface located in a (100) crystal plane and a second region having a top surface located in a (110) crystal plane; patterning the second region to form a fin-shaped substrate; forming a plurality of channel components disposed above the fin-shaped substrate; forming a plurality of internal spacer components interlaced with the plurality of channel components; depositing a dielectric material layer on the plurality of internal spacer components and above the top surface of the fin-shaped substrate; etching back the dielectric material layer to form a dielectric film; depositing an epitaxial component above the dielectric film, the epitaxial component contacting the plurality of channel components, the epitaxial component having a top surface located in a (110) crystal plane; and forming a gate structure encapsulating each of the plurality of channel components. In some embodiments, the method also includes: before depositing the dielectric material layer, depositing a base epitaxial layer on the top surface of the fin-shaped substrate, the base epitaxial layer having a top surface located in a (110) crystal plane. In some embodiments, forming the hybrid substrate includes: bonding a first semiconductor substrate having a top surface located in a (110) crystal plane to a second semiconductor substrate having a top surface located in a (100) crystal plane; removing the first semiconductor substrate from the first region; thickening the second semiconductor substrate in the first region; and planarizing the first semiconductor substrate and the second semiconductor substrate. In some embodiments, the dielectric film is in physical contact with a bottommost one of the plurality of internal spacer components. In some embodiments, the method also includes: laterally recessing the channel component after etching back the dielectric material layer. In some embodiments, the epitaxial component includes a lateral protrusion between two adjacent internal spacer components vertically stacked in the plurality of internal spacer components.

[0062] In another exemplary aspect, the disclosed embodiments relate to a semiconductor device. The semiconductor device includes: a fin-shaped base protruding from a semiconductor substrate, the top surface of the fin-shaped base being located in a (110) crystal plane; a plurality of channel components disposed above the top surface of the fin-shaped base; a plurality of internal spacer components interlaced with the plurality of channel components; a gate structure wrapping each of the plurality of channel components; a source / drain component contacting the plurality of channel components and the plurality of internal spacer components, the top surface of the source / drain component being located in a (110) crystal plane; and a dielectric film directly located below the source / drain component and above the top surface of the fin-shaped base. In some embodiments, the semiconductor device also includes: an undoped epitaxial layer directly located below the dielectric film and above the top surface of the fin-shaped base, the top surface of the undoped epitaxial layer being located in a (110) crystal plane. In some embodiments, the fin-shaped base includes a semiconductor layer disposed on a top portion of a semiconductor substrate, the top portion of the semiconductor substrate having a top surface located in a (100) crystal plane. In some embodiments, the source / drain component is doped with a p-type dopant.

[0063] Some embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: bonding a first semiconductor substrate having a (110) orientation to a second semiconductor substrate having a (100) orientation; forming a stack above the first semiconductor substrate, the stack comprising a plurality of channel layers interlaced with a plurality of sacrificial layers; patterning the stack to form a fin-shaped structure, the fin-shaped structure comprising a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing a gate spacer layer above the dummy gate stack; recessing the source / drain region to form a plurality of The invention relates to a method for forming a gate electrode and a gate stack of the plurality of sacrificial layers; forming a source / drain groove on the sidewalls of the channel layer and the plurality of sacrificial layers; recessing the plurality of sacrificial layers partially to form a plurality of internal spacer grooves; forming a plurality of internal spacer components in the plurality of internal spacer grooves; forming a dielectric film in the source / drain grooves; epitaxially growing an epitaxial component over the dielectric film, the epitaxial component contacting the plurality of channel layers, the epitaxial component having a (110) orientation; after forming the epitaxial component, removing the pseudo gate stack; releasing the plurality of channel layers in the channel region as a plurality of channel components; and forming a gate structure wrapping each of the plurality of channel components.

[0064] In some embodiments, the method further comprises: depositing a base epitaxial layer in the source / drain trench prior to depositing the dielectric film. In some embodiments, the base epitaxial layer is free of dopants. In some embodiments, the base epitaxial layer has a (110) orientation. In some embodiments, the channel layer in the stack has a (110) orientation. In some embodiments, the sacrificial layer in the stack has a (110) orientation. In some embodiments, the epitaxial component is doped with a p-type dopant. In some embodiments, the epitaxial component comprises silicon germanium. In some embodiments, forming the dielectric film comprises: depositing a dielectric layer over a bottom surface and a sidewall surface of the source / drain trench; and removing the dielectric layer from the sidewall surface of the source / drain trench. In some embodiments, the fin structure comprises a top portion of the first semiconductor substrate and the second semiconductor substrate.

[0065] Other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a hybrid substrate, the hybrid substrate having: a first region having a top surface located in a (100) crystal plane and a second region having a top surface located in a (110) crystal plane; patterning the second region to form a fin-shaped substrate; forming a plurality of channel components arranged above the fin-shaped substrate; forming a plurality of internal spacer components interlaced with the plurality of channel components; depositing a dielectric material layer on the plurality of internal spacer components and above the top surface of the fin-shaped substrate; etching back the dielectric material layer to form a dielectric film; depositing an epitaxial component above the dielectric film, the epitaxial component contacting the plurality of channel components, the epitaxial component having a top surface located in the (110) crystal plane; and forming a gate structure wrapping each of the plurality of channel components.

[0066] In some embodiments, the method further comprises: depositing a base epitaxial layer on the top surface of the fin-shaped substrate before depositing the dielectric material layer, the base epitaxial layer having a top surface located in a (110) crystal plane. In some embodiments, forming the hybrid substrate comprises: bonding a first semiconductor substrate having a top surface located in a (110) crystal plane to a second semiconductor substrate having a top surface located in a (100) crystal plane; removing the first semiconductor substrate from the first region; thickening the second semiconductor substrate in the first region; and planarizing the first semiconductor substrate and the second semiconductor substrate. In some embodiments, the dielectric film is in physical contact with a bottommost internal spacer component of the plurality of internal spacer components. In some embodiments, the method further comprises: laterally recessing the channel component after etching back the dielectric material layer. In some embodiments, the epitaxial component comprises a lateral protrusion between two adjacent internal spacer components vertically stacked among the plurality of internal spacer components.

[0067] Still other embodiments of the present application provide a semiconductor device, comprising: a fin-shaped base protruding from a semiconductor substrate, the top surface of the fin-shaped base being located in a (110) crystal plane; a plurality of channel components arranged above the top surface of the fin-shaped base; a plurality of internal spacer components interlaced with the plurality of channel components; a gate structure wrapping each of the plurality of channel components; a source / drain component contacting the plurality of channel components and the plurality of internal spacer components, the top surface of the source / drain component being located in the (110) crystal plane; and a dielectric film directly located below the source / drain component and above the top surface of the fin-shaped base.

[0068] In some embodiments, the semiconductor device further comprises: an undoped epitaxial layer directly below the dielectric film and above the top surface of the fin-shaped substrate, the top surface of the undoped epitaxial layer being in a (110) crystal plane. In some embodiments, the fin-shaped substrate comprises a semiconductor layer disposed on a top portion of the semiconductor substrate, wherein the top portion of the semiconductor substrate has a top surface in a (100) crystal plane. In some embodiments, the source / drain features are doped with a p-type dopant.

[0069] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a substrate to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: Bonding a first semiconductor substrate having a (110) orientation to a second semiconductor substrate having a (100) orientation; forming a stack over the first semiconductor substrate, the stack comprising a plurality of channel layers interleaved with a plurality of sacrificial layers; patterning the stack to form a fin structure, the fin structure comprising a channel region and a source / drain region; forming a dummy gate stack over the channel region of the fin structure; depositing a gate spacer layer over the dummy gate stack; recessing the source / drain region to form a source / drain trench exposing sidewalls of the plurality of channel layers and the plurality of sacrificial layers; recessing the plurality of sacrificial layer portions to form a plurality of inner spacer recesses; forming a plurality of inner spacer members in the plurality of inner spacer grooves; forming a dielectric film in the source / drain trench; epitaxially growing an epitaxial component over the dielectric film, the epitaxial component contacting the plurality of channel layers, the epitaxial component having a (110) orientation; After forming the epitaxial component, removing the dummy gate stack; releasing the plurality of channel layers in the channel region as a plurality of channel members; as well as A gate structure is formed surrounding each of the plurality of channel members.

2. The method according to claim 1, further comprising: Prior to depositing the dielectric film, a base epitaxial layer is deposited in the source / drain trenches.

3. The method according to claim 2, wherein: The base epitaxial layer has no dopant.

4. The method according to claim 2, wherein: The base epitaxial layer has a (110) orientation.

5. The method according to claim 1, wherein: The channel layer in the stack has a (110) orientation.

6. The method according to claim 1, wherein: The sacrificial layer in the stack has a (110) orientation.

7. The method according to claim 1, wherein: The epitaxial feature is doped with a p-type dopant.

8. The method according to claim 1, wherein: The epitaxial feature includes silicon germanium.

9. A method for manufacturing a semiconductor device, comprising: forming a hybrid substrate having: a first region having a top surface located in a (100) crystal plane and a second region having a top surface located in a (110) crystal plane; patterning the second region to form a fin-shaped substrate; forming a plurality of channel members disposed above the fin-shaped substrate; forming a plurality of interior spacer components interleaved with the plurality of channel members; depositing a layer of dielectric material on the plurality of inner spacer features and over a top surface of the fin substrate; Etching back the dielectric material layer to form a dielectric film; depositing an epitaxial feature over the dielectric film, the epitaxial feature contacting the plurality of channel members, the epitaxial feature having a top surface lying in a (110) crystal plane; as well as A gate structure is formed surrounding each of the plurality of channel members.

10. A semiconductor device comprising: A fin-shaped base protrudes from the semiconductor substrate, wherein a top surface of the fin-shaped base is located in a (110) crystal plane; a plurality of channel members disposed above the top surface of the fin-shaped substrate; a plurality of internal spacer components interleaved with the plurality of channel members; a gate structure wrapping each of the plurality of channel members; a source / drain feature in contact with the plurality of channel members and the plurality of internal spacer members, a top surface of the source / drain feature being located in a (110) crystal plane; as well as A dielectric film is located directly below the source / drain features and above the top surface of the fin-shaped substrate.

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