Interconnection structure based on back power supply and preparation method thereof

Abstract

The invention provides an interconnection structure based on back surface power supply and a preparation method thereof, and relates to the technical field of integrated circuits, a power supply wiring layer is formed on the back surface of an epitaxial layer by using a metalized nano embedded power supply rail for a metalized back surface contact hole, namely back surface power supply is realized. Therefore, the high voltage drop caused by the same-side arrangement of the traditional power line and signal line can be effectively relieved, the power transmission performance is improved, the wiring congestion is reduced, and more importantly, the resistance can be further reduced by utilizing the metalized nano embedded power supply rail, and the design compatibility is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an interconnection structure based on back-side power supply and a preparation method thereof. Background Art

[0002] Chip manufacturing starts with the smallest component, the transistor, and then gradually builds smaller and smaller wiring layers to connect transistors and various parts of the chip and to power the chip. Therefore, the wiring layer usually includes power lines and signal lines on the same side of the chip. But as transistors become smaller and denser, the wiring layer where signal lines and power lines coexist has become an increasingly chaotic network, becoming an obstacle to improving the overall performance of the chip.

[0003] In order to optimize the layout structure of the circuit layer and improve the overall performance of the chip, the concept of back power supply was proposed. Back power supply is to find a way to move the power line to the back of the chip so that the front of the chip can only focus on signal interconnection. This can effectively alleviate the voltage drop caused by the high resistance of the power line and improve power transmission performance. However, the back power supply structure in the industry currently has high resistance and poor design compatibility. Summary of the invention

[0004] The purpose of the present application is to provide an interconnection structure based on back-side power supply and a preparation method thereof in view of the deficiencies in the above-mentioned prior art.

[0005] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] In one aspect of an embodiment of the present application, a method for preparing an interconnect structure based on back-side power supply is provided, the method comprising:

[0007] Select a wafer substrate with an epitaxial layer of a certain thickness (the thickness of the epitaxial layer will affect the final thickness of the substrate after thinning, preferably an epitaxial layer of 2um to 6um).

[0008] Metal power rails and device structures are formed at intervals on the front side of the epitaxial layer, wherein the metal power rails include nano-embedded power rails extending from the front side of the epitaxial layer into the epitaxial layer and front metal filled in the nano-embedded power rails; in other words, for a silicon substrate wafer (wafer substrate) with an epitaxial layer of a certain thickness, the metal power rails are formed on the surface and inside of the epitaxial layer, first there is a silicon substrate wafer, then an epitaxial layer is grown on the surface of the silicon substrate wafer, and then a device structure is formed on the surface of the epitaxial layer.

[0009] Forming a signal wiring layer covering the metal power rail and the device structure on the front side of the epitaxial layer, wherein the signal wiring layer is respectively connected to the metal power rail and the device structure;

[0010] Bonding a carrier wafer on the front side of the signal wiring layer;

[0011] thinning at least the wafer substrate to expose the epitaxial layer from the back side;

[0012] forming a back contact hole on the back side of the epitaxial layer, which is in communication with the nano embedded power rail;

[0013] Filling the back contact hole with a back metal that contacts the front metal;

[0014] A power wiring layer is formed on the back side of the epitaxial layer, wherein the power wiring layer is connected to the back side metal.

[0015] Optionally, the nano buried power rail is any one of a long strip groove, a ring groove and a circular groove.

[0016] Optionally, there are multiple back contact holes, and the multiple back contact holes are correspondingly connected to the same nano embedded power rail.

[0017] Optionally, forming spaced metal power rails and device structures on the front side of the epitaxial layer includes:

[0018] forming a nano buried power rail extending into the epitaxial layer on the front side of the epitaxial layer;

[0019] Filling the front-side metal in nano buried power rails;

[0020] A device structure is formed on the front side of the epitaxial layer and is located next to the nano-embedded power rail.

[0021] Optionally, forming a nano buried power rail extending into the epitaxial layer on the front side of the epitaxial layer comprises:

[0022] forming a first dielectric layer on the front side of the epitaxial layer;

[0023] Forming a first window exposing the epitaxial layer on the first dielectric layer by photolithography;

[0024] The first dielectric layer is used as a mask layer, and the epitaxial layer is etched in the first window to form a nano buried power rail.

[0025] Optionally, filling the front side metal in the nano buried power rail includes:

[0026] forming a first isolation buffer layer on the bottom wall and side walls of the nano buried power rail;

[0027] forming a first metal barrier layer on the surface of the first isolation buffer layer;

[0028] A front metal in the nano buried power rail is formed on the surface of the first metal barrier layer.

[0029] Optionally, a device structure located beside the nano embedded power rail is formed on the front side of the epitaxial layer, including:

[0030] Depositing a first insulating layer covering the front metal on the front side of the first dielectric layer;

[0031] The first insulating layer and the first dielectric layer are sequentially etched to form a second window exposing the epitaxial layer, wherein the second window is located beside the nano-embedded power rail;

[0032] A device structure is formed on the epitaxial layer within the second window.

[0033] Optionally, thinning at least the wafer substrate to expose the epitaxial layer from the back side includes:

[0034] performing rough thinning on the wafer substrate from the back side of the wafer substrate to form a thinned wafer;

[0035] Fine Thinning After the wafer is thinned, the epitaxial layer is further finely thinned to a preset depth so that the first isolation buffer layer in the nano-embedded power rail is exposed at the back of the epitaxial layer.

[0036] Optionally, forming a back contact hole on the back side of the epitaxial layer corresponding to and connected to the nano embedded power rail comprises:

[0037] forming a composite dielectric layer on the back side of the epitaxial layer;

[0038] Etching to form a first contact hole on the back side of the composite dielectric layer, wherein the first contact hole terminates at the middle layer in the composite dielectric layer;

[0039] Etching is performed from the back side of the composite dielectric layer to form a wiring groove overlapping with the first contact hole in the composite dielectric layer;

[0040] The composite dielectric layer and the first isolation buffer layer are sequentially etched in the first contact hole to form a second contact hole in the composite dielectric layer and the first isolation buffer layer, wherein the front metal is exposed in the second contact hole, and the first contact hole and the second contact hole serve as back contact holes.

[0041] Optionally, filling the back metal in the back contact hole to contact the front metal includes:

[0042] A second metal barrier layer and a back metal are formed in the wiring trench and the back contact hole by a damascene process.

[0043] Another aspect of an embodiment of the present application provides an interconnect structure based on back side power supply, which is prepared by using any of the above-mentioned methods for preparing an interconnect structure based on back side power supply.

[0044] The beneficial effects of this application include:

[0045] The present application provides an interconnect structure based on back-side power supply and a preparation method thereof, which forms a power wiring layer on the back side of the epitaxial layer by using a metallized nano-embedded power rail to a metallized back contact hole, that is, realizing back-side power supply. This can not only effectively alleviate the high voltage drop caused by the traditional arrangement of power lines and signal lines on the same side, improve power transmission performance, and reduce wiring congestion, but more importantly, it can use the metallized nano-embedded power rail to further reduce resistance and improve design compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 One of the state schematic diagrams of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0048] Figure 2 A second state schematic diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0049] Figure 3 A third state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0050] Figure 4 A fourth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0051] Figure 5 A fifth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0052] Figure 6 A sixth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0053] Figure 7 A seventh state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0054] Figure 8 An eighth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0055] Fig. 9A ninth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0056] Fig.10 A tenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0057] Fig.11 The eleventh state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0058] Fig.12 A twelfth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0059] Fig.13 The thirteenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0060] Fig.14 A fourteenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0061] Fig.15 A fifteenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0062] Fig.16 A sixteenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0063] Fig.17 The seventeenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0064] Fig.18 The eighteenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0065] Fig.19 One of the schematic diagrams of the shape of a nano embedded power rail provided in an embodiment of the present application;

[0066] Fig. 20 A second schematic diagram of the shape of a nano embedded power rail provided in an embodiment of the present application;

[0067] Fig.21 A third schematic diagram of the shape of a nano embedded power rail provided in an embodiment of the present application;

[0068] Fig. 22 A schematic diagram of the corresponding relationship between a nano embedded power rail and a back contact hole provided in an embodiment of the present application.

[0069] Icons: 110-wafer substrate; 111-thinned wafer; 120-epitaxial layer; 130-first dielectric layer; 140-alignment mark; 150-first window; 160-nanometer buried power rail; 170-first isolation buffer layer; 180-metal power rail; 181-front metal; 190-first insulating layer; 210-second window; 220-device structure; 230-second insulating layer; 240-first contact via; 250-signal wiring layer; 260-carrier wafer; 310-back metal; 320-power wiring layer; 330-wiring groove; 350-metal block; 360-fourth insulating layer; 371-first silicon oxide layer; 372-first silicon nitride layer; 373-second silicon oxide layer; 380-back contact hole; 381-first contact hole; 382-second contact hole. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0071] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. It should be noted that, in the absence of conflict, the various features in the embodiments of the present application can be combined with each other, and the combined embodiments are still within the scope of protection of the present application.

[0072] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0073] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0074] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0075] In one aspect of an embodiment of the present application, a method for preparing an interconnect structure based on back-side power supply is provided, the method comprising:

[0076] S10: Select a wafer substrate having an epitaxial layer of a certain thickness.

[0077] like Figure 1 As shown, a wafer substrate 110 having an epitaxial layer 120 of a certain thickness is selected. The epitaxial layer 120 can be doped to achieve a different doping concentration control from the wafer substrate 110 during the deposition process. It is understandable that the epitaxial layer 120 will affect the final thickness of the substrate after subsequent S50 thinning (e.g. Fig.18 The thickness of the remaining epitaxial layer 120 shown in FIG. 1 is less than the thickness of the epitaxial layer 120 before thinning). Therefore, the epitaxial layer 120 with a thickness of 2 to 6 microns can be selected. The front and back surfaces of the epitaxial layer 120 are the two opposite surfaces of the epitaxial layer 120 in the thickness direction, for example Figure 1 In the figure, the side pointed by arrow a is the front side (the same applies to the subsequent figures), that is, the upper surface of the epitaxial layer 120 is the front side, and the lower surface of the epitaxial layer 120 is the back side.

[0078] S20: forming spaced metal power rails 180 and a device structure 220 on the front side of the epitaxial layer 120 , wherein the metal power rail 180 includes a nano buried power rail 160 extending from the front side of the epitaxial layer 120 into the epitaxial layer 120 and a front side metal 181 filled in the nano buried power rail 160 .

[0079] like Figures 2 to 8 As shown, a metal power rail 180 and a device structure 220 are formed on the front side of the epitaxial layer 120 through a series of processes (such as etching, deposition, ion implantation, etc.), and the metal power rail 180 and the device structure 220 are spaced apart from each other. In other words, the front side of the epitaxial layer 120 can be divided into a first non-intersecting area and a second area, wherein the metal power rail 180 is located in the first area, and the device structure 220 is located in the second area.

[0080] Metal power rail 180 is buried in epitaxial layer 120, such as Figures 2 to 4As shown, the metal power rail 180 includes a nano-embedded power rail 160 and a front metal 181. Specifically, the nano-embedded power rail 160 is a groove that opens from the front side of the epitaxial layer 120 and extends toward the back side of the epitaxial layer 120 to a certain depth inside the epitaxial layer 120 (not penetrating the epitaxial layer 120), and then the front metal 181 is filled in the groove by metallizing the groove.

[0081] like Figures 5 to 8 As shown, a device structure 220 is made in the second region on the front side of the epitaxial layer 120, and the device structure 220 can be a transistor, a chip, etc. It should be understood that the present application does not limit the number of metal power rails 180 and device structures 220 arranged on the front side of the epitaxial layer 120. In addition, it should also be understood that the nano-embedded power rail 160 is different from the nano-silicon through-hole, wherein the nano-embedded power rail 160 has a larger structural cross-section than the nano-silicon through-hole and has a lower resistance. In addition, the nano-embedded power rail 160 can be designed in different shapes and sizes according to needs, so as to be compatible with a variety of designs and have better performance. Therefore, the structures and application scenarios of the two are different.

[0082] S30 : forming a signal wiring layer 250 covering the metal power rail 180 and the device structure 220 on the front side of the epitaxial layer 120 , wherein the signal wiring layer 250 is metal-connected to the metal power rail 180 and the device structure 220 , respectively.

[0083] like Fig. 9 and Fig.10 As shown, after the metal power rail 180 and the device structure 220 are fabricated on the front side of the epitaxial layer 120 through S20, the signal wiring layer 250 is further fabricated on the front side of the epitaxial layer 120. In order to facilitate interconnection, the signal wiring layer 250 can cover the metal power rail 180 and the device structure 220, and the signal wiring layer 250 can be metal-connected to the metal power rail 180 and the device structure 220, respectively, so that the signal of the device structure 220 can be conveniently led out through the signal wiring layer 250.

[0084] S40 : bonding the carrier wafer 260 to the front side of the signal wiring layer 250 .

[0085] like Fig.11 As shown, in order to facilitate the construction of the power wiring layer 320 on the back of the epitaxial layer 120, a carrier wafer 260 is bonded to the front of the signal wiring layer 250, and the entire device is supported by the carrier wafer 260. Fig.11 As shown, the side pointed by arrow b is the back side (the same applies to subsequent figures).

[0086] S50: thinning at least the wafer substrate 110 to expose the epitaxial layer 120 from the back side.

[0087] like Fig.12 As shown, after S40, the device is flipped so that the carrier wafer 260 is at the bottom and the wafer substrate 110 is at the top, which facilitates the process of the wafer substrate 110. However, it should be understood that the front and back sides of the epitaxial layer 120 remain consistent with the above definition and do not change, that is, Fig.12 As shown, because it has been flipped, the upper surface of the epitaxial layer 120 is now the back surface, and the lower surface is the front surface.

[0088] Then at least the wafer substrate 110 is thinned, and finally the epitaxial layer 120 is exposed from the back side. Fig.11 and Fig.12 As shown, during the thinning process, the wafer substrate 110 is thinned. During the process, the epitaxial layer 120 can be used as an etch stop layer so that the thinning stops at the back of the epitaxial layer, thereby improving the consistency of the thinning.

[0089] After thinning the wafer substrate, the epitaxial layer 120 can be further thinned to a certain thickness from the back side of the epitaxial layer 120. The thinning can be performed by wet etching so that the exposed surface of the thinned epitaxial layer 120 serves as the back side. In this way, the epitaxial layer 120 can be exposed from the back side of the entire device. At the same time, the epitaxial layer 120 can be used to improve the consistency of silicon thickness during the thinning process.

[0090] S60 : forming a back contact hole 380 on the back side of the epitaxial layer 120 , which is in communication with the nano embedded power rail 160 .

[0091] S70 : filling the back contact hole 380 with the back metal 310 in contact with the front metal 181 .

[0092] S80 : forming a power wiring layer 320 on the back side of the epitaxial layer 120 , wherein the power wiring layer 320 is metal-connected to the back side metal 310 .

[0093] like Figures 13 to 18 As shown, after the epitaxial layer 120 is exposed from the back side of the entire device, a back contact hole 380 can be formed on the back side of the epitaxial layer 120. It should be understood that the back contact hole 380 can be formed in one step or multiple steps according to the needs, for example, it can be formed by one etching or multiple etchings. There is no limit on the number of back contact holes 380 and nano buried power rails 160, which can be at least one, but it should be satisfied that multiple back contact holes 380 are connected to the same nano buried power rail 160, and the back metal 310 in contact with the front metal 181 is filled in the back contact hole 380, so that it is convenient to use the back contact hole 380 and the metal column in the nano buried power rail 160 to lead out the power wiring layer 320 for back power supply from the back side of the entire device.

[0094] Then, a power wiring layer 320 is formed on the back side of the epitaxial layer 120 , wherein the power wiring layer 320 is metal-connected to the back side metal 310 .

[0095] In summary, by using the metallized nano embedded power rail 160 to metallize the back contact hole 380, a power wiring layer 320 is formed on the back of the epitaxial layer 120, that is, back power supply is realized, which can effectively alleviate the high voltage drop caused by the traditional power line and signal line being arranged on the same side, improve power transmission performance, reduce wiring congestion, and more importantly, the metallized nano embedded power rail 160 can be used to further reduce resistance and improve design compatibility. In addition, in some units with sensitive devices, the metallized nano embedded power rail 160 can be used to enclose the devices to play a role in physical isolation.

[0096] Optionally, S20: forming a spaced metal power rail 180 and a device structure 220 on the front side of the epitaxial layer 120, wherein the metal power rail 180 includes a nano buried power rail 160 extending from the front side of the epitaxial layer 120 into the epitaxial layer 120 and a front metal 181 filled in the nano buried power rail 160 including:

[0097] S21 : forming a nano buried power rail 160 extending into the epitaxial layer 120 on the front side of the epitaxial layer 120 .

[0098] S22 : Filling the front side metal 181 in the nano buried power rail 160 .

[0099] like Figures 2 to 4 As shown, a nano embedded power rail 160 extending to the inside of the epitaxial layer 120 is formed on the front side of the epitaxial layer 120 by etching, and the bottom wall of the nano embedded power rail 160 is at a certain distance from the back side of the epitaxial layer 120. The nano embedded power rail 160 can be formed in one step or multiple steps according to the needs, for example, by one etching or multiple etchings.

[0100] like Figure 5 As shown, the front side metal 181 is filled in the nano buried power rail 160 .

[0101] S23 : A device structure 220 is formed on the front side of the epitaxial layer 120 and is located next to the nano embedded power rail 160 .

[0102] like Figures 6 to 8As shown, a device structure 220 is formed on the front side of the epitaxial layer 120, and the device structure 220 is located beside the nano buried power rail 160, so that the two are spaced and distributed on the front side of the epitaxial layer 120. Since the order of the steps for making the metal power rail 180 is earlier than the device structure 220, the method can be used to form the buried metal power rail 180 before the device structure 220 is formed, which helps to improve the flexibility of the design and is compatible with traditional and advanced processes.

[0103] Optionally, S21: forming a nano buried power rail 160 extending into the epitaxial layer 120 on the front side of the epitaxial layer 120 includes:

[0104] S211 : forming a first dielectric layer 130 on the front surface of the epitaxial layer 120 .

[0105] S212 : forming a first window 150 exposing the epitaxial layer 120 on the first dielectric layer 130 by photolithography.

[0106] S213 : using the first dielectric layer 130 as a mask layer, etching the epitaxial layer 120 in the first window 150 to form a nano embedded power rail 160 .

[0107] like Figures 2 to 3 As shown, the first dielectric layer 130 is first deposited on the front side of the epitaxial layer 120, and then a photoresist is coated on the front side of the first dielectric layer 130. A first window 150 is formed on the first dielectric layer 130 through a photolithography process, and the epitaxial layer 120 below the first dielectric layer 130 is exposed in the first window 150. The number of the first windows 150 corresponds to the number of the nano buried power rails 160. Then, the first dielectric layer 130 having the first windows 150 is used as a mask layer, and the epitaxial layer 120 is etched in the first windows 150 to form the nano buried power rails 160. The opening size and depth of the nano buried power rails 160 can be reasonably set according to requirements.

[0108] It should be understood that when a nano-buried power rail 160 extending into the epitaxial layer 120 is formed on the front side of the epitaxial layer 120, a one-step or multi-step forming method can be selected according to the situation. It is preferred to use photoresist as a blocking etching to form a dielectric hard mask layer on the surface of the silicon substrate, and then use the dielectric as a hard mask to etch the silicon of the substrate portion to form a nano-BPR (nano-buried power rail 160). The dielectric layer is preferably made of common semiconductor materials such as silicon nitride and silicon oxide.

[0109] The first dielectric layer 130 may be a conventional semiconductor material such as a silicon nitride layer, a silicon oxide layer or a composite thin film.

[0110] Optionally, S22: filling the front side metal 181 in the nano buried power rail 160 includes:

[0111] S221 : forming a first isolation buffer layer 170 on the bottom wall and side walls of the nano buried power rail 160 .

[0112] A first isolation buffer layer 170 is deposited on the bottom wall and sidewalls of the nano buried power rail 160. Figure 4 As shown, when the first dielectric layer 130 is formed on the front side of the epitaxial layer 120, the first isolation buffer layer 170 may be located on the bottom wall and side walls of the nano buried power rail 160 and the side walls and front side of the first dielectric layer 130. It is understood that, considering the step coverage of thin film deposition, it is preferred to use thermal oxygen or atomic layer deposition ALD to grow the first dielectric layer 130.

[0113] S222 : forming a first metal barrier layer on the surface of the first isolation buffer layer 170 .

[0114] S223: forming a front metal 181 in the nano embedded power rail 160 on the surface of the first metal barrier layer.

[0115] like Figure 5 As shown, the nano embedded power rail 160 can be metallized. Specifically, a first metal barrier layer is first formed on the surface of the first isolation buffer layer 170. The first metal barrier layer is located in the nano embedded power rail 160. A metal nitride by atomic layer deposition ALD is preferred, such as tungsten nitride, titanium nitride, etc. Then, a front metal 181 located in the nano embedded power rail 160 is formed on the surface of the first metal barrier layer. The front metal 181 must have high temperature stability (600°C to 1000°C). A metal tungsten, ruthenium, etc. by atomic layer deposition ALD or chemical vapor deposition is preferred. The first metal barrier layer can avoid the diffusion of the front metal 181, which helps to improve the device performance.

[0116] Then, the metal formed outside the nano-embedded power rail 160 (such as the entire device surface) during the above-mentioned process of making the first metal barrier layer and the front metal 181 is removed, and only the first metal barrier layer and the front metal 181 inside the nano-embedded power rail 160 are retained. Here, chemical mechanical masking or dry etching is preferably used.

[0117] Optionally, S23: forming a device structure 220 located beside the nano embedded power rail 160 on the front side of the epitaxial layer 120, including:

[0118] S231 : depositing a first insulating layer 190 on the front surface of the first dielectric layer 130 and covering the front metal 181 .

[0119] like Figure 6As shown, a first insulating layer 190 covering the front metal 181 is first deposited on the front side of the first dielectric layer 130, so that the metal power rail 180 can be covered by the first insulating layer 190 to avoid affecting it during the subsequent preparation of the device structure 220. Usually, the first insulating layer 190 is a nitride film, such as silicon nitride. Here, the thickness of the first insulating layer 190 needs to be determined in consideration of the subsequent process requirements, and is generally about 1 micron.

[0120] S232 : etching the first insulating layer 190 and the first dielectric layer 130 in sequence to form a second window 210 exposing the epitaxial layer 120 , wherein the second window 210 is located beside the nano embedded power rail 160 .

[0121] like Figure 7 As shown, by sequentially etching the first insulating layer 190 and the first dielectric layer 130, a second window 210 is formed in a region without the metal power rail 180. For example, the second window 210 is located beside the nano-embedded power rail 160 (or the metal power rail 180), and a portion of the front surface of the epitaxial layer 120 is exposed through the second window 210. Dry etching or wet etching with a high etching selectivity ratio can be selected here.

[0122] S233 : forming a device structure 220 on the epitaxial layer 120 in the second window 210 .

[0123] like Figure 8 As shown, a device structure 220 is fabricated on the front side of the epitaxial layer 120 exposed in the second window 210 .

[0124] Optionally, S30: forming a signal wiring layer 250 covering the metal power rail 180 and the device structure 220 on the front side of the epitaxial layer 120, wherein the signal wiring layer 250 is metal-connected to the metal power rail 180 and the device structure 220 respectively, including: Fig. 9 As shown, a second insulating layer 230 is formed on the front side of the epitaxial layer 120, and then a first contact through hole 240 penetrating the second insulating layer 230 is formed by etching. The number of the first contact through holes 240 is multiple and can be reasonably set according to the needs. When the device structure 220 is connected through the metallized first contact through holes 240, the metal power rail 180 is also connected. Fig.10 As shown, a signal wiring layer 250 is continuously formed above the second insulating layer 230, and the metal lines in the signal wiring layer 250 are connected to the metalized first contact vias 240 through metal. In this way, the metal lines in the signal wiring layer 250 can be respectively connected to the metal power rail 180 and the device structure 220 through different first contact vias 240.

[0125] It should be understood that the signal wiring layer 250 may include multiple layers of stacked metal circuits, and two adjacent metal circuit layers may be separated by a third insulating layer, so that the desired wiring can be smoothly achieved.

[0126] Optionally, in S40: before bonding the carrier wafer 260 to the front side of the signal wiring layer 250 , the front side of the signal wiring layer 250 may be planarized and de-edged before bonding, and then the carrier wafer 260 may be bonded to the front side of the signal wiring layer 250 .

[0127] In addition, if Figures 2 to 18 As shown, an alignment mark 140 may be formed on the epitaxial layer 120 for alignment of the nano buried power rail 160 , the back contact hole 380 , and the 2D process.

[0128] In the process of at least thinning the wafer substrate 110 to expose the epitaxial layer 120 from the back side through S50, the thinning process can be divided into two stages: rough thinning and fine thinning, which specifically include:

[0129] S51 : roughly thinning the wafer substrate 110 from the back side of the wafer substrate 110 to form a thinned wafer 111 .

[0130] like Fig.12 As shown, the wafer substrate 110 is roughly thinned using the carrier wafer 260 as a support, so that the remaining wafer substrate 110 forms a thinned wafer 111. For example, the back side of the wafer substrate 110 is roughly thinned, and this step requires the wafer substrate 110 to be thinned from a thickness of about 775um to a thickness of 7-50um.

[0131] S53 : Fine Thinning After the wafer 111 is thinned, the epitaxial layer 120 is further finely thinned to a preset depth, so that the first isolation buffer layer 170 in the nano-embedded power rail 160 is exposed at the back side of the epitaxial layer 120 .

[0132] like Fig.13 As shown, after the wafer 111 is finely thinned, the epitaxial layer 120 is finely thinned to a preset depth, which can be achieved by chemical mechanical grinding, wet etching, dry etching, or a combination of these processes. For example, the process of fine thinning the epitaxial layer 120 is divided into two steps: the first step is to perform preliminary fine thinning on the epitaxial layer 120 by combining wet etching with a high selectivity ratio and chemical mechanical grinding. When the depth of the first fine thinning is about to reach the preset depth, the second fine thinning step is performed, that is, using dry etching with a high selectivity ratio, the back of the epitaxial layer 120 is continuously thinned until the first isolation buffer layer 170 in the nano-embedded power rail 160 is exposed from the back of the epitaxial layer 120.

[0133] S60: forming a back contact hole 380 corresponding to and connected to the nano embedded power rail 160 on the back side of the epitaxial layer 120, including:

[0134] S64 : forming a composite dielectric layer on the back side of the epitaxial layer 120 .

[0135] like Fig.14 As shown, a composite dielectric layer is deposited on the back of the epitaxial layer 120 after thinning, and then the back of the composite dielectric layer is planarized to repair the height difference caused by the exposure of the first isolation buffer layer 170 during the thinning process. Fig.14 As shown, the composite dielectric layer may include a first silicon oxide layer 371 , a first silicon nitride layer 372 , and a second silicon oxide layer 373 sequentially deposited on the back side of the epitaxial layer 120 .

[0136] S65: etching to form a first contact hole 381 on the back side of the composite dielectric layer, wherein the first contact hole 381 terminates at the middle layer in the composite dielectric layer.

[0137] like Fig.15 As shown, the composite dielectric layer is etched from the back side of the composite dielectric layer to form a first contact hole 381 extending toward the inside of the composite dielectric layer, and the first contact hole 381 ends at an intermediate layer in the composite dielectric layer, where the intermediate layer refers to a layer other than the outermost layer of the composite dielectric layer. Fig.15 As shown, when the composite dielectric layer includes a first silicon oxide layer 371, a first silicon nitride layer 372 and a second silicon oxide layer 373 deposited sequentially on the back side of the epitaxial layer 120, the first contact hole 381 terminates in the first silicon nitride layer 372, and the etching rate ratio of the second silicon oxide and the first silicon nitride is generally >5:1.

[0138] S66: Etching is performed from the back side of the composite dielectric layer to form a wiring trench 330 overlapping with the first contact hole 381 in the composite dielectric layer.

[0139] S67: The composite dielectric layer and the first isolation buffer layer 170 are sequentially etched in the first contact hole 381 to form a second contact hole 382 in the composite dielectric layer and the first isolation buffer layer 170 , wherein the front metal 181 is exposed in the second contact hole 382 , and the first contact hole 381 and the second contact hole 382 serve as back contact holes 380 .

[0140] like Fig.16As shown, the composite dielectric layer is etched from the back side of the composite dielectric layer, thereby forming a wiring groove 330 in the composite dielectric layer, and the wiring groove 330 overlaps with the first contact hole 381. Then, the first silicon nitride layer 372 and the first silicon oxide layer 371 in the composite dielectric layer and the first isolation buffer layer 170 are etched, thereby forming a second contact hole 382 in the first silicon nitride layer 372, the first silicon oxide layer 371 and the first isolation buffer layer 170, so that the front metal 181 is exposed in the second contact hole 382, ​​and the first contact hole 381 and the second contact hole 382 are connected to form a back contact hole 380 located on the back side of the epitaxial layer 120.

[0141] S70: Filling the back metal 310 in the back contact hole 380 in contact with the front metal 181 includes: Fig.17 As shown, a second metal barrier layer and a back metal 310 are formed in the wiring trench 330 and the back contact hole 380 by a damascene process. The metallization process is divided into the deposition of the second metal barrier layer and the filling of the back metal 310. The metallization process includes processes such as electroplating and chemical mechanical polishing. The back metal 310 includes a metal block 350 located in the wiring trench 330.

[0142] Then, a fourth insulating layer 360 is formed on the back of the composite dielectric layer. Fig.18 As shown, the power wiring layer 320 is continuously formed on the fourth insulating layer 360, and the nano buried power rail 160 is connected to the back of the epitaxial layer 120 by using the back contact hole 380, and then the back power wiring layer 320 is continuously formed, and then the power wiring layer 320 is metal-connected to the back metal 310. The power wiring layer 320 may include multiple layers of metal lines, and the multiple layers of metal lines may be separated from each other by the third insulating layer, so that the expected wiring can be smoothly realized.

[0143] Alternatively, if Fig.19 As shown, the nano buried power rail 160 is a circular groove, such as Fig. 20 As shown, the nano embedded power rail 160 is a long strip groove (or plate shape), such as Fig.21 As shown, the nano embedded power rail 160 is an annular groove. When there are multiple nano embedded power rails 160, the multiple nano embedded power rails 160 can be one or a combination of circular grooves, elongated grooves and annular grooves. Alternatively, the nano embedded power rail 160 can also be formed by at least two elongated grooves spliced ​​at an angle.

[0144] Alternatively, if Fig. 22 As shown, there are multiple back contact holes 380 , and some of the multiple back contact holes 380 are correspondingly connected to the same nano-embedded power rail 160 .

[0145] Another aspect of the present application provides an interconnect structure based on back power supply, which is prepared by any of the above-mentioned methods for preparing an interconnect structure based on back power supply. The interconnect structure based on back power supply can be Fig.18 The structure shown.

[0146] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing an interconnection structure based on back-side power supply, characterized in that: The method comprises: Selecting a wafer substrate having an epitaxial layer of a certain thickness; Forming spaced metal power rails and device structures on the front side of the epitaxial layer, wherein the metal power rails include nano-embedded power rails extending from the front side of the epitaxial layer into the epitaxial layer and front side metal filled in the nano-embedded power rails; Forming a signal wiring layer covering the metal power rail and the device structure on the front side of the epitaxial layer, wherein the signal wiring layer is respectively connected to the metal power rail and the device structure by metal; Bonding a carrier wafer on the front side of the signal wiring layer; At least thinning the wafer substrate to expose the epitaxial layer from the back side; forming a back contact hole on the back side of the epitaxial layer, which is in communication with the nano embedded power rail; Filling the back contact hole with a back metal in contact with the front metal; A power wiring layer is formed on the back side of the epitaxial layer, wherein the power wiring layer is connected to the back side metal.

2. The method according to claim 1, characterized in that The nano embedded power rail is any one of a long strip groove, a ring groove and a circular groove.

3. The method according to claim 1, characterized in that There are multiple back contact holes, and among the multiple back contact holes, at least two back contact holes are correspondingly connected to the same nano embedded power rail.

4. The method according to claim 1, characterized in that The metal power rails and device structures formed on the front side of the epitaxial layer are spaced apart and distributed, and include: forming a nano buried power rail extending into the epitaxial layer on the front side of the epitaxial layer; filling front side metal in the nano buried power rail; A device structure located beside the nano embedded power rail is formed on the front side of the epitaxial layer.

5. The method according to claim 4, characterized in that The forming of a nanometer embedded power rail extending into the epitaxial layer on the front side of the epitaxial layer comprises: forming a first dielectric layer on the front side of the epitaxial layer; Forming a first window exposing the epitaxial layer on the first dielectric layer by photolithography; The first dielectric layer is used as a mask layer, and the epitaxial layer is etched in the first window to form the nano embedded power rail.

6. The method according to claim 4, characterized in that Filling the front side metal in the nano buried power rail comprises: forming a first isolation buffer layer on the bottom wall and side walls of the nano buried power rail; forming a first metal barrier layer on a surface of the first isolation buffer layer; The front metal located in the nano embedded power rail is formed on the surface of the first metal barrier layer.

7. The method according to claim 5, characterized in that A device structure located beside the nano embedded power rail is formed on the front side of the epitaxial layer and includes: Depositing a first insulating layer covering the front metal on the front side of the first dielectric layer; The first insulating layer and the first dielectric layer are sequentially etched to form a second window exposing the epitaxial layer, wherein the second window is located beside the nano embedded power rail; The device structure is formed on the epitaxial layer in the second window.

8. The method according to claim 6, characterized in that The step of at least thinning the wafer substrate to expose the epitaxial layer from the back side comprises: performing rough thinning on the wafer substrate from the back side of the wafer substrate to form a thinned wafer; After fine thinning the thinned wafer, the epitaxial layer is further fine thinned to a preset depth so that the first isolation buffer layer in the nano-embedded power rail is exposed at the back side of the epitaxial layer.

9. The method according to claim 8, characterized in that The back contact hole formed on the back side of the epitaxial layer and correspondingly connected to the nano embedded power rail comprises: forming a composite dielectric layer on the back side of the epitaxial layer; Etching a first contact hole on the back side of the composite dielectric layer, wherein the first contact hole terminates at an intermediate layer in the composite dielectric layer; Etching from the back side of the composite dielectric layer to form a wiring groove in the composite dielectric layer that overlaps with the first contact hole; The composite dielectric layer and the first isolation buffer layer are sequentially etched in the first contact hole to form a second contact hole in the composite dielectric layer and the first isolation buffer layer, wherein the front metal is exposed in the second contact hole, and the first contact hole and the second contact hole serve as the back contact holes.

10. The method according to claim 9, characterized in that The back metal filled in the back contact hole and in contact with the front metal comprises: A second metal barrier layer and the back metal are formed in the wiring trench and the back contact hole by a damascene process.

11. An interconnection structure based on back-side power supply, characterized in that: The method for preparing an interconnect structure based on back power supply as claimed in any one of claims 1 to 10 is used for preparation.

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