Interconnection structure based on back power supply and preparation method thereof

Abstract

The invention provides an interconnection structure based on back surface power supply and a preparation method thereof, and relates to the technical field of integrated circuits, and a power supply wiring layer is formed on the back surface of an epitaxial layer through metalized front surface nanometer through holes and metalized back surface nanometer through holes, namely back surface power supply is realized. Therefore, high voltage drop caused by same-side arrangement of a traditional power line and a traditional signal line can be effectively relieved, the power transmission performance is improved, and wiring congestion is reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an interconnection structure based on back-side power supply and a preparation method thereof. Background Art

[0002] Chip manufacturing starts with the smallest component, the transistor, and then gradually builds smaller and smaller wiring layers to connect transistors and various parts of the chip and to power the chip. Therefore, the wiring layer usually includes power lines and signal lines on the same side of the chip. But as transistors become smaller and denser, the wiring layer where signal lines and power lines coexist has become an increasingly chaotic network, becoming an obstacle to improving the overall performance of the chip.

[0003] In order to optimize the layout structure of the circuit layer and improve the overall performance of the chip, the concept of back-side power supply was proposed. Back-side power supply is to find a way to move the power line to the back of the chip so that the front of the chip can only focus on signal interconnection. This can effectively alleviate the voltage drop caused by the high resistance of the power line and improve power transmission performance. However, the industry currently does not provide a feasible preparation process for back-side power supply. Summary of the invention

[0004] The purpose of the present application is to provide an interconnection structure based on back-side power supply and a preparation method thereof in view of the deficiencies in the above-mentioned prior art.

[0005] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] In one aspect of an embodiment of the present application, a method for preparing an interconnect structure based on back-side power supply is provided, the method comprising:

[0007] Select a wafer substrate with an epitaxial layer of a certain thickness; (the thickness of the epitaxial layer will affect the final thickness of the substrate after thinning, and a 2um to 6um epitaxial layer is preferred).

[0008] On the front side of the epitaxial layer, a front metal structure and a device structure are formed with intervals, wherein the front metal structure includes a front nano-via extending from the front side of the epitaxial layer into the epitaxial layer and a front metal column filled in the front nano-via. In other words, for a silicon substrate wafer (wafer substrate) with an epitaxial layer of a certain thickness, the front metal structure is formed on the surface and inside of the epitaxial layer. First, there is a silicon substrate wafer, then an epitaxial layer is grown on the surface of the silicon substrate wafer, and then a device structure is formed on the surface of the epitaxial layer.

[0009] Forming a signal wiring layer covering the front metal structure and the device structure on the front side of the epitaxial layer, wherein the signal wiring layer is metal-connected to the front metal structure and the device structure respectively;

[0010] Bonding a carrier wafer on the front side of the signal wiring layer;

[0011] thinning at least the wafer substrate to expose the epitaxial layer from the back side;

[0012] forming a back nano-through hole on the back side of the epitaxial layer, which is connected to the front nano-through hole correspondingly;

[0013] filling the back-side metal pillars in contact with the front-side metal pillars in the back-side nano-vias;

[0014] A power wiring layer is formed on the back side of the epitaxial layer, wherein the power wiring layer is metal-connected to the back side metal pillar.

[0015] Optionally, forming a front metal structure and a device structure distributed at intervals on the front side of the epitaxial layer includes:

[0016] forming a front nano-via extending into the epitaxial layer on the front side of the epitaxial layer;

[0017] filling the front-side nanovias with front-side metal pillars;

[0018] A device structure located beside the front nano-through hole is formed on the front side of the epitaxial layer.

[0019] Optionally, forming a front nano-via extending into the epitaxial layer on the front side of the epitaxial layer comprises:

[0020] forming a first dielectric layer on the front side of the epitaxial layer;

[0021] Forming a first window exposing the epitaxial layer on the first dielectric layer by photolithography;

[0022] The first dielectric layer is used as a mask layer, and the epitaxial layer is etched in the first window to form a front nano-through hole.

[0023] Optionally, filling the front metal pillars in the front nano vias comprises:

[0024] forming a first isolation buffer layer on the bottom wall and side wall of the front nano-through hole;

[0025] forming a first metal barrier layer on the surface of the first isolation buffer layer;

[0026] A front metal column located in the front nano-via hole is formed on the surface of the first metal barrier layer.

[0027] Optionally, a device structure located beside the front nano-through hole is formed on the front side of the epitaxial layer, including:

[0028] Depositing a first insulating layer covering the front metal pillar on the front side of the first dielectric layer;

[0029] The first insulating layer and the first dielectric layer are sequentially etched to form a second window exposing the epitaxial layer, wherein the second window is located beside the front nano-through hole;

[0030] A device structure is formed on the epitaxial layer within the second window.

[0031] Optionally, thinning at least the wafer substrate to expose the epitaxial layer from the back side includes:

[0032] performing rough thinning on the wafer substrate from the back side of the wafer substrate to form a thinned wafer;

[0033] Fine thinning the wafer, or, after fine thinning the wafer, continuing to fine thin the epitaxial layer to a preset depth, so that the distance from the exposed back side of the epitaxial layer to the front side nano-through hole is 0.2 to 1 micron.

[0034] Optionally, forming a back nano-through hole on the back side of the epitaxial layer that is connected to the front nano-through hole correspondingly comprises:

[0035] forming a second dielectric layer on the back side of the epitaxial layer;

[0036] forming a third window exposing the epitaxial layer on the second dielectric layer by photolithography;

[0037] The second dielectric layer is used as a mask layer, and the epitaxial layer is etched in the third window to form a back nano-via, wherein the back nano-via extends from the back of the epitaxial layer to the front nano-via.

[0038] Optionally, filling the back side metal pillars in the back side nano vias to contact the front side metal pillars comprises:

[0039] forming a second isolation buffer layer on the bottom wall and side wall of the back nano-through hole;

[0040] At least etching the second isolation buffer layer located at the bottom wall of the rear nano-through hole to expose the front metal column;

[0041] forming a second metal barrier layer on the surface of the second isolation buffer layer;

[0042] A back side metal column located in the back side nano-via hole is formed on the surface of the second metal barrier layer.

[0043] Optionally, filling the back side metal pillars in the back side nano vias to contact the front side metal pillars comprises:

[0044] forming a second isolation buffer layer on the bottom wall and side wall of the rear nano-through hole and the side wall of the third window;

[0045] Etching is performed from the back side of the second dielectric layer to form a wiring groove overlapping with the third window in the second dielectric layer;

[0046] At least etching the second isolation buffer layer located at the bottom wall of the rear nano-through hole to expose the front metal column;

[0047] A second metal barrier layer and a back metal column are formed on the surface of the second isolation buffer layer in the wiring groove and the back nano-via by a damascene process.

[0048] Optionally, thinning at least the wafer substrate to expose the epitaxial layer from the back side includes:

[0049] performing rough thinning on the wafer substrate from the back side of the wafer substrate to form a thinned wafer;

[0050] Fine Thinning After the wafer is thinned, the epitaxial layer is further finely thinned to a preset depth so that the first isolation buffer layer in the front nano-through hole is exposed at the back of the epitaxial layer.

[0051] Optionally, forming a back nano-through hole on the back side of the epitaxial layer that is connected to the front nano-through hole correspondingly comprises:

[0052] forming a composite dielectric layer on the back side of the epitaxial layer;

[0053] Etching a first back contact hole on the back side of the composite dielectric layer, wherein the first back contact hole terminates at the middle layer in the composite dielectric layer;

[0054] Etching is performed from the back side of the composite dielectric layer to form a wiring groove in the composite dielectric layer that overlaps with the first back side contact hole;

[0055] The composite dielectric layer and the first isolation buffer layer are sequentially etched in the first back contact hole to form a second back contact hole in the composite dielectric layer and the first isolation buffer layer, wherein the front metal column is exposed in the second back contact hole, and the first back contact hole and the second back contact hole serve as back nanovias.

[0056] Optionally, filling the back side metal pillars in the back side nano vias to contact the front side metal pillars comprises:

[0057] A second metal barrier layer and a back metal column are formed in the wiring trench and the back nano-via by a damascene process.

[0058] Another aspect of an embodiment of the present application provides an interconnect structure based on back side power supply, which is prepared by using any of the above-mentioned methods for preparing an interconnect structure based on back side power supply.

[0059] The beneficial effects of this application include:

[0060] The present application provides an interconnect structure based on back-side power supply and a preparation method thereof, which forms a power wiring layer on the back side of the epitaxial layer by utilizing metallized front-side nano-vias to metallized back-side nano-vias, that is, back-side power supply is realized. This can effectively alleviate the high voltage drop caused by the traditional arrangement of power lines and signal lines on the same side, improve power transmission performance, and reduce wiring congestion. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0062] Figure 1 One of the state schematic diagrams of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0063] Figure 2 A second state schematic diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0064] Figure 3 A third state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0065] Figure 4 A fourth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0066] Figure 5 A fifth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0067] Figure 6 A sixth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0068] Figure 7 A seventh state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0069] Figure 8 An eighth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0070] Fig. 9 A ninth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0071] Fig.10 A tenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0072] Fig.11 The eleventh state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0073] Fig.12 A twelfth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0074] Fig.13 The thirteenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0075] Fig.14 A fourteenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0076] Fig.15 A fifteenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0077] Fig.16 A sixteenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0078] Fig.17 The seventeenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0079] Fig.18 The eighteenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0080] Fig.19 A nineteenth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0081] Fig. 20 The twentieth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0082] Fig.21 A schematic diagram of the state of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application is twenty-one;

[0083] Fig. 22 A schematic diagram of the state of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application is shown in FIG22;

[0084] Fig.23A schematic diagram of the state of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application is shown in FIG23;

[0085] Fig.24 A schematic diagram of the state of a method for preparing an interconnect structure based on back power supply provided in an embodiment of the present application is twenty-four;

[0086] Fig.25 The twenty-fifth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0087] Fig.26 A schematic diagram of the state of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application is as follows;

[0088] Fig. 27 The twenty-seventh state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0089] Fig.28 The twenty-eighth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0090] Fig.29 The twenty-ninth state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application;

[0091] Fig.30 The thirty-second state diagram of a method for preparing an interconnect structure based on back-side power supply provided in an embodiment of the present application.

[0092] Icons: 110-wafer substrate; 111-thinned wafer; 120-epitaxial layer; 130-first dielectric layer; 140-alignment mark; 150-first window; 160-front nano-via; 170-first isolation buffer layer; 180-front metal structure; 181-front metal pillar; 190-first insulating layer; 210-second window; 220-device structure; 230-second insulating layer; 240-first contact via; 250-signal wiring Line layer; 260-carrier wafer; 270-second dielectric layer; 271-third window; 280-back nano-via; 290-second isolation buffer layer; 310-back metal pillar; 320-power wiring layer; 330-wiring groove; 350-metal block; 360-fourth insulating layer; 371-first silicon oxide layer; 372-first silicon nitride layer; 373-second silicon oxide layer; 381-first back contact hole; 382-second back contact hole. DETAILED DESCRIPTION

[0093] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0094] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. It should be noted that, in the absence of conflict, the various features in the embodiments of the present application can be combined with each other, and the combined embodiments are still within the scope of protection of the present application.

[0095] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0096] In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and therefore cannot be understood as limiting this application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0097] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0098] In one aspect of an embodiment of the present application, a method for preparing an interconnect structure based on back-side power supply is provided, the method comprising:

[0099] S10: Select a wafer substrate having an epitaxial layer of a certain thickness.

[0100] like Figure 1As shown, a wafer substrate 110 having an epitaxial layer 120 of a certain thickness is selected. The epitaxial layer can be doped to achieve a different doping concentration from the wafer substrate during the deposition process. It is understandable that the epitaxial layer 120 will affect the final thickness of the substrate after subsequent S50 thinning (e.g. Fig.18 The thickness of the remaining epitaxial layer 120 shown in FIG. 1 is less than the thickness of the epitaxial layer 120 before thinning). Therefore, the epitaxial layer 120 with a thickness of 2 to 6 microns can be selected. The front and back surfaces of the epitaxial layer 120 are the two opposite surfaces of the epitaxial layer 120 in the thickness direction, for example Figure 1 In the figure, the side pointed by arrow a is the front side (the same applies to the subsequent figures), that is, the upper surface of the epitaxial layer 120 is the front side, and the lower surface of the epitaxial layer 120 is the back side.

[0101] S20: forming a front metal structure 180 and a device structure 220 that are spaced apart on the front side of the epitaxial layer 120 , wherein the front metal structure 180 includes a front nano-via 160 extending from the front side of the epitaxial layer 120 into the epitaxial layer 120 and a front metal column 181 filled in the front nano-via 160 .

[0102] like Figures 2 to 8 As shown, a front metal structure 180 and a device structure 220 are formed on the front side of the epitaxial layer 120 through a series of processes (such as etching, deposition, ion implantation, etc.), and the front metal structure 180 and the device structure 220 are spaced apart from each other. In other words, the front side of the epitaxial layer 120 can be divided into a first non-intersecting area and a second non-intersecting area, wherein the front metal structure 180 is located in the first area, and the device structure 220 is located in the second area.

[0103] The front metal structure 180 is buried in the epitaxial layer 120, such as Figures 2 to 4 As shown, the front metal structure 180 includes a front nano-via 160 and a front metal column 181. Specifically, the front nano-via 160 is a nano-via which opens from the front side of the epitaxial layer 120 and extends toward the back side of the epitaxial layer 120 to a certain depth inside the epitaxial layer 120 (not penetrating the epitaxial layer 120), and then the front metal column 181 is filled in the hole by metallizing the nano-via.

[0104] like Figures 5 to 8 As shown, a device structure 220 is fabricated in the second region on the front side of the epitaxial layer 120 , and the device structure 220 may be a transistor, a chip, etc. It should be understood that the present application does not limit the number of the front metal structure 180 and the device structure 220 arranged on the front side of the epitaxial layer 120 .

[0105] S30 : forming a signal wiring layer 250 covering the front metal structure 180 and the device structure 220 on the front side of the epitaxial layer 120 , wherein the signal wiring layer 250 is metal-connected to the front metal structure 180 and the device structure 220 , respectively.

[0106] like Fig. 9 and Fig.10 As shown, after the front metal structure 180 and the device structure 220 are fabricated on the front of the epitaxial layer 120 through S20, the signal wiring layer 250 is further fabricated on the front of the epitaxial layer 120. In order to facilitate interconnection, the signal wiring layer 250 can cover the front metal structure 180 and the device structure 220, and the signal wiring layer 250 is metal-connected to the front metal structure 180 and the device structure 220, respectively, so that the signal of the device structure 220 can be conveniently led out through the signal wiring layer 250.

[0107] S40 : bonding the carrier wafer 260 to the front side of the signal wiring layer 250 .

[0108] like Fig.11 As shown, in order to facilitate the construction of the power wiring layer 320 on the back of the epitaxial layer 120, a carrier wafer 260 is bonded to the front of the signal wiring layer 250, and the entire device is supported by the carrier wafer 260. Fig.11 As shown, the side pointed by arrow b is the back side (the same applies to subsequent figures).

[0109] S50: thinning at least the wafer substrate 110 to expose the epitaxial layer 120 from the back side.

[0110] like Fig.12 As shown, after S40, the device is flipped so that the carrier wafer 260 is at the bottom and the wafer substrate 110 is at the top, which facilitates the process of the wafer substrate 110. However, it should be understood that the front and back sides of the epitaxial layer 120 remain consistent with the above definition and do not change, that is, Fig.12 As shown, because it has been flipped, the upper surface of the epitaxial layer 120 is now the back surface, and the lower surface is the front surface.

[0111] Then at least the wafer substrate 110 is thinned, and finally the epitaxial layer 120 is exposed from the back side. Fig.11 and Fig.12 As shown, during the thinning process, the wafer substrate 110 is thinned. During the process, the epitaxial layer 120 can be used as an etch stop layer so that the thinning stops at the back of the epitaxial layer, thereby improving the consistency of the thinning.

[0112] After thinning the wafer substrate, the epitaxial layer 120 can be further thinned to a certain thickness from the back side of the epitaxial layer 120. The thinning can be performed by wet etching so that the exposed surface of the thinned epitaxial layer 120 serves as the back side. In this way, the epitaxial layer 120 can be exposed from the back side of the entire device. At the same time, the epitaxial layer 120 can be used to improve the consistency of silicon thickness during the thinning process.

[0113] S60 : forming a back nano-via 280 on the back side of the epitaxial layer 120 , which is connected to the front nano-via 160 .

[0114] S70 : filling the back-side metal pillars 310 in contact with the front-side metal pillars 181 in the back-side nano vias 280 .

[0115] S80 : forming a power wiring layer 320 on the back side of the epitaxial layer 120 , wherein the power wiring layer 320 is metal-connected to the back side metal pillar 310 .

[0116] like Figures 13 to 30 As shown, after the epitaxial layer 120 is exposed from the back side of the entire device, a back nano-via 280 can be formed on the back side of the epitaxial layer 120. It should be understood that the back nano-via 280 can be formed in one step or multiple steps according to the needs, for example, it can be formed by one etching or multiple etchings. There is no limit to the number of the back nano-via 280 and the front nano-via 160, which can be at least one, but it should be satisfied that the back nano-via 280 is connected to the front nano-via 160 in a one-to-one correspondence, and the back metal column 310 in contact with the front metal column 181 is filled in the back nano-via 280, so that it is convenient to use the metal columns in the back nano-via 280 and the front nano-via 160 to lead out the power wiring layer 320 for back power supply from the back of the entire device.

[0117] Then, a power wiring layer 320 is formed on the back side of the epitaxial layer 120 , wherein the power wiring layer 320 is metal-connected to the back side metal pillar 310 .

[0118] In summary, by utilizing the metallized front nanovia 160 to the metallized back nanovia 280, a power wiring layer 320 is formed on the back side of the epitaxial layer 120, that is, back side power supply is achieved. This can effectively alleviate the high voltage drop caused by the traditional arrangement of power lines and signal lines on the same side, improve power transmission performance, and reduce wiring congestion.

[0119] Optionally, S20: forming a front metal structure 180 and a device structure 220 that are spaced apart on the front side of the epitaxial layer 120, wherein the front metal structure 180 includes a front nano-via 160 extending from the front side of the epitaxial layer 120 into the epitaxial layer 120 and a front metal column 181 filled in the front nano-via 160, including:

[0120] S21 : forming a front nano-via 160 extending into the epitaxial layer 120 on the front surface of the epitaxial layer 120 .

[0121] S22 : filling the front metal pillars 181 in the front nano vias 160 .

[0122] like Figures 2 to 4 As shown, a front nano-through hole 160 extending to the inside of the epitaxial layer 120 is formed on the front side of the epitaxial layer 120 by etching, and the bottom wall of the front nano-through hole 160 is at a certain distance from the back side of the epitaxial layer 120. The front nano-through hole 160 can be formed in one step or multiple steps according to the needs, for example, by one etching or multiple etchings.

[0123] like Figure 5 As shown, the front side metal pillars 181 are filled in the front side nano vias 160 .

[0124] S23 : A device structure 220 is formed on the front side of the epitaxial layer 120 and is located next to the front nano-via 160 .

[0125] like Figures 6 to 8 As shown, a device structure 220 is formed on the front side of the epitaxial layer 120, and the device structure 220 is located beside the front nano-via 160, so that the two are spaced and distributed on the front side of the epitaxial layer 120. Since the steps of making the front metal structure 180 are earlier than the device structure 220, the method can be used to preferentially form the buried front metal structure 180 before the device structure 220 is formed, which helps to improve the flexibility of the design and is compatible with traditional and advanced processes.

[0126] Optionally, S21: forming a front nano-via 160 extending into the epitaxial layer 120 on the front side of the epitaxial layer 120 includes:

[0127] S211 : forming a first dielectric layer 130 on the front surface of the epitaxial layer 120 .

[0128] S212 : forming a first window 150 exposing the epitaxial layer 120 on the first dielectric layer 130 by photolithography.

[0129] S213 : using the first dielectric layer 130 as a mask layer, etching the epitaxial layer 120 in the first window 150 to form the front nano-via 160 .

[0130] like Figures 2 to 3As shown, the first dielectric layer 130 is first deposited on the front side of the epitaxial layer 120, and then a photoresist is coated on the front side of the first dielectric layer 130. A first window 150 is formed on the first dielectric layer 130 through a photolithography process, and the epitaxial layer 120 below the first dielectric layer 130 is exposed in the first window 150. The number of the first windows 150 corresponds to the number of the front nano-through holes 160. Then, the first dielectric layer 130 having the first windows 150 is used as a mask layer, and the epitaxial layer 120 is etched in the first windows 150 to form the front nano-through holes 160. The opening size and depth of the front nano-through holes 160 can be reasonably set according to requirements.

[0131] It should be understood that when forming a front nano-via 160 extending into the epitaxial layer 120 on the front side of the epitaxial layer 120, a one-step or multi-step forming method can be selected according to the situation. Preferably, photoresist is used as a blocking etching to form a dielectric hard mask layer on the surface of the silicon substrate, and then the dielectric is used as a hard mask to etch the silicon of the substrate portion to form a nano-TSV (nano silicon through-hole). The dielectric layer is preferably made of common semiconductor materials such as silicon nitride and silicon oxide.

[0132] The first dielectric layer 130 may be a conventional semiconductor material such as a silicon nitride layer, a silicon oxide layer or a composite thin film.

[0133] Optionally, S22: filling the front metal pillar 181 in the front nano via 160 includes:

[0134] S221 : forming a first isolation buffer layer 170 on the bottom wall and side wall of the front nano via hole 160 .

[0135] A first isolation buffer layer 170 is deposited on the bottom wall and side wall of the front nano-via 160. Figure 4 As shown, when the first dielectric layer 130 is formed on the front side of the epitaxial layer 120, the first isolation buffer layer 170 may be located on the bottom wall and sidewalls of the front nano-via 160 and the sidewalls and front side of the first dielectric layer 130. It is understood that, considering the step coverage of thin film deposition, it is preferred to use thermal oxygen or atomic layer deposition ALD to grow the first dielectric layer 130.

[0136] S222 : forming a first metal barrier layer on the surface of the first isolation buffer layer 170 .

[0137] S223: forming a front metal pillar 181 located in the front nano-via 160 on the surface of the first metal barrier layer.

[0138] like Figure 5As shown, the front nano-via 160 can be metallized. Specifically, a first metal barrier layer is first formed on the surface of the first isolation buffer layer 170. The first metal barrier layer is located in the front nano-via 160. The metal nitride of atomic layer deposition ALD is preferably used, such as tungsten nitride, titanium nitride, etc. Then, a front metal column 181 located in the front nano-via 160 is formed on the surface of the first metal barrier layer. The front metal column 181 must have high temperature stability (600°C to 1000°C). It is preferred to use metal tungsten, ruthenium, etc. of atomic layer deposition ALD or chemical vapor deposition. The first metal barrier layer can avoid the diffusion of the front metal column 181, which helps to improve the device performance.

[0139] Then, the metal formed outside the front nano-via 160 (such as the entire device surface) during the above-mentioned process of making the first metal barrier layer and the front metal column 181 is removed, leaving only the first metal barrier layer and the front metal column 181 inside the front nano-via 160. Here, chemical mechanical masking or dry etching is preferably used.

[0140] Optionally, S23: forming a device structure 220 located beside the front nano-via 160 on the front side of the epitaxial layer 120, including:

[0141] S231 : depositing a first insulating layer 190 on the front surface of the first dielectric layer 130 to cover the front metal pillars 181 .

[0142] like Figure 6 As shown, a first insulating layer 190 covering the front metal pillar 181 is first deposited on the front side of the first dielectric layer 130, so that the front metal structure 180 can be covered by the first insulating layer 190 to avoid affecting it during the subsequent preparation of the device structure 220. Usually, the first insulating layer 190 is a nitride film, such as silicon nitride. Here, the thickness of the first insulating layer 190 needs to be determined in consideration of the subsequent process requirements, and is generally about 1 micron.

[0143] S232 : etching the first insulating layer 190 and the first dielectric layer 130 in sequence to form a second window 210 exposing the epitaxial layer 120 , wherein the second window 210 is located beside the front nano-via 160 .

[0144] like Figure 7 As shown, by sequentially etching the first insulating layer 190 and the first dielectric layer 130, a second window 210 is formed in a region without the front metal structure 180, for example, the second window 210 is located beside the front nano-via 160 (or the front metal structure 180), and a portion of the front surface of the epitaxial layer 120 is exposed through the second window 210. Dry etching or wet etching with a high etching selectivity can be selected here.

[0145] S233 : forming a device structure 220 on the epitaxial layer 120 in the second window 210 .

[0146] like Figure 8 As shown, a device structure 220 is fabricated on the front side of the epitaxial layer 120 exposed in the second window 210 .

[0147] Optionally, S30: forming a signal wiring layer 250 covering the front metal structure 180 and the device structure 220 on the front side of the epitaxial layer 120, wherein the signal wiring layer 250 is metal-connected to the front metal structure 180 and the device structure 220 respectively, including: Fig. 9 As shown, a second insulating layer 230 is formed on the front side of the epitaxial layer 120, and then a first contact through hole 240 penetrating the second insulating layer 230 is formed by etching. The number of the first contact through holes 240 is multiple and can be reasonably set according to the needs. When the device structure 220 is connected through the metallized first contact through holes 240, the front metal structure 180 is also connected. Fig.10 As shown, a signal wiring layer 250 is further formed above the second insulating layer 230, and the metal lines in the signal wiring layer 250 are connected to the metallized first contact vias 240 through metal. In this way, the metal lines in the signal wiring layer 250 can be respectively connected to the front metal structure 180 and the device structure 220 through different first contact vias 240.

[0148] It should be understood that the signal wiring layer 250 may include multiple layers of stacked metal circuits, and two adjacent metal circuit layers may be separated by a third insulating layer, so that the desired wiring can be smoothly achieved.

[0149] Optionally, in S40: before bonding the carrier wafer 260 to the front side of the signal wiring layer 250 , the front side of the signal wiring layer 250 may be planarized and de-edged before bonding, and then the carrier wafer 260 may be bonded to the front side of the signal wiring layer 250 .

[0150] In addition, if Figures 2 to 30 As shown, alignment mark 140 may be formed on epitaxial layer 120 for alignment of front nano via 160 , back nano via 280 , and 2D process.

[0151] The front nano-via 160 and the back nano-via 280 in the present application are both nano-through silicon vias (nano-TSV).

[0152] Through the above steps S10 to S40, it is possible to form Fig.11On this basis, metallized back nano vias 280 and power wiring layer 320 can be prepared through S50 to S80. For ease of understanding, various preparation methods are provided below, so that the back nano vias 280 are interconnected with the front nano vias 160, thereby having the characteristics of a large process window and high process compatibility.

[0153] Example 1 (such as Figures 12 to 18 (shown)

[0154] In the process of at least thinning the wafer substrate 110 to expose the epitaxial layer 120 from the back side through S50, the thinning process can be divided into two stages: rough thinning and fine thinning, which specifically include:

[0155] S51 : roughly thinning the wafer substrate 110 from the back side of the wafer substrate 110 to form a thinned wafer 111 .

[0156] like Fig.12 As shown, the wafer substrate 110 is roughly thinned using the carrier wafer 260 as a support, so that the remaining wafer substrate 110 forms a thinned wafer 111. For example, the back side of the wafer substrate 110 is roughly thinned, and this step requires the wafer substrate 110 to be thinned from a thickness of about 775um to a thickness of 7-50um.

[0157] S52: Fine thinning the wafer 111, or, after fine thinning the wafer 111, continuing to fine thin the epitaxial layer 120 to a preset depth, so that the distance from the exposed back side of the epitaxial layer 120 to the front side nano-through hole 160 is 0.2 to 1 micrometer.

[0158] like Fig.13 As shown, after the rough thinning, the thinned wafer 111 is further thinned by fine thinning, and then the epitaxial layer 120 is finely thinned to a preset depth, so that the distance from the exposed back side of the epitaxial layer 120 to the front nano-through hole 160 is 0.2 to 1 micron. The fine thinning is usually performed by combining wet etching with a high etching selectivity ratio and chemical mechanical polishing.

[0159] S60: forming a back nano-via 280 on the back side of the epitaxial layer 120 to be connected to the front nano-via 160 correspondingly, including:

[0160] S61 : forming a second dielectric layer 270 on the back side of the epitaxial layer 120 .

[0161] like Fig.14 As shown, a second dielectric layer 270 is formed on the back side of the epitaxial layer 120 , and the dielectric layer is preferably made of common semiconductor materials such as silicon nitride and silicon oxide.

[0162] S62 : forming a third window 271 exposing the epitaxial layer 120 on the second dielectric layer 270 by photolithography.

[0163] S63 : using the second dielectric layer 270 as a mask layer, etching the epitaxial layer 120 in the third window 271 to form a back nano-via 280 , wherein the back nano-via 280 extends from the back side of the epitaxial layer 120 to the front nano-via 160 .

[0164] like Fig.15 As shown, a photoresist is coated on the front side of the second dielectric layer 270, and a third window 271 is formed on the second dielectric layer 270 through a photolithography process, and the epitaxial layer 120 below the second dielectric layer 270 is exposed in the third window 271. The number of the third windows 271 corresponds to the number of the back nano-vias 280. Then, the second dielectric layer 270 with the third window 271 is used as a mask layer, and the epitaxial layer 120 is etched from the back side of the epitaxial layer 120 in the third window 271. Here, a high etching selectivity is used to stop the etching on the first isolation buffer layer 170 in the front nano-via 160. Generally, the etching rate ratio of silicon (epitaxial layer 120) and dielectric layer (first isolation buffer layer 170, also called first insulating buffer layer) is >50:1. Thus, the back nano-via 280 is formed. The opening size and depth of the back nano-via 280 can be reasonably set according to requirements.

[0165] S70: Filling the back metal pillar 310 in the back nano via 280 and contacting the front metal pillar 181 includes:

[0166] S71 : forming a second isolation buffer layer 290 on the bottom wall and side wall of the back nano via hole 280 .

[0167] A second isolation buffer layer 290 is deposited on the bottom wall and side wall of the back nano-via 280. Fig.16 As shown, when the second dielectric layer 270 is formed on the front side of the epitaxial layer 120, the second isolation buffer layer 290 can be located on the bottom wall and sidewalls of the back nano-via 280 and the sidewalls and front side of the second dielectric layer 270. It can be understood that, considering the step coverage of thin film deposition, it is preferred to use thermal oxygen or atomic layer deposition ALD to grow the second dielectric layer 270.

[0168] S72 : etching at least the second isolation buffer layer 290 located on the bottom wall of the rear nano-via 280 to expose the front metal pillar 181 .

[0169] S73 : forming a second metal barrier layer on the surface of the second isolation buffer layer 290 .

[0170] S74: forming a back side metal pillar 310 located in the back side nano via 280 on the surface of the second metal barrier layer.

[0171] like Fig.17 As shown, the second isolation buffer layer 290 and the first isolation buffer layer 170 at the bottom of the back nano via 280 are removed by dry etching, so that the front metal pillar 181 can be exposed from the back nano via 280, and then metallized. The process of metallizing the back nano via 280 is divided into the steps of depositing the second metal barrier layer, filling the back metal pillar 310, and removing the metal outside the back nano via 280.

[0172] S80 : forming a power wiring layer 320 on the back side of the epitaxial layer 120 , wherein the power wiring layer 320 is metal-connected to the back side metal pillar 310 .

[0173] like Fig.18 As shown, after the front nano via 160 is connected to the back side of the epitaxial layer 120 by using the back nano via 280, the back power wiring layer 320 is further formed, and then the power wiring layer 320 is metal-connected to the back metal pillar 310. The power wiring layer 320 may include multiple layers of metal lines, and the multiple layers of metal lines may be separated from each other by a third insulating layer, so that the expected wiring can be smoothly achieved.

[0174] Example 2 (such as Fig.12 , Fig.13 , Figures 19 to 24 (shown)

[0175] In the process of at least thinning the wafer substrate 110 to expose the epitaxial layer 120 from the back side through S50, the thinning process can be divided into two stages: rough thinning and fine thinning, which specifically include:

[0176] S51 : roughly thinning the wafer substrate 110 from the back side of the wafer substrate 110 to form a thinned wafer 111 .

[0177] like Fig.12 As shown, the wafer substrate 110 is roughly thinned using the carrier wafer 260 as a support, so that the remaining wafer substrate 110 forms a thinned wafer 111. For example, the back side of the wafer substrate 110 is roughly thinned, and this step requires the wafer substrate 110 to be thinned from a thickness of about 775um to a thickness of 7-50um.

[0178] S52: Fine thinning the wafer 111, or, after fine thinning the wafer 111, continuing to fine thin the epitaxial layer 120 to a preset depth, so that the distance from the exposed back side of the epitaxial layer 120 to the front side nano-through hole 160 is 0.2 to 1 micrometer.

[0179] like Fig.13As shown, after the rough thinning, the wafer 111 is finely thinned, and then the epitaxial layer 120 is finely thinned to a preset depth, so that the distance from the exposed back side of the epitaxial layer 120 to the front nano-through hole 160 is 0.2 to 1 micron. The fine thinning is usually performed by combining wet etching with a high etching selectivity ratio and chemical mechanical polishing.

[0180] S60: forming a back nano-via 280 on the back side of the epitaxial layer 120 to be connected to the front nano-via 160 correspondingly, including:

[0181] S64 : forming a second dielectric layer 270 on the back side of the epitaxial layer 120 .

[0182] like Fig.19 As shown, a second dielectric layer 270 is formed on the back of the epitaxial layer 120. The dielectric layer is preferably made of common semiconductor materials such as silicon nitride and silicon oxide. The second dielectric layer 270 can be thicker than the second dielectric layer 270 in Example 1.

[0183] S65 : forming a third window 271 exposing the epitaxial layer 120 on the second dielectric layer 270 by photolithography.

[0184] S66 : using the second dielectric layer 270 as a mask layer, etching the epitaxial layer 120 in the third window 271 to form a back nano-via 280 , wherein the back nano-via 280 extends from the back side of the epitaxial layer 120 to the front nano-via 160 .

[0185] like Fig. 20 As shown, a photoresist is coated on the front side of the second dielectric layer 270, and a third window 271 is formed on the second dielectric layer 270 through a photolithography process, and the epitaxial layer 120 below the second dielectric layer 270 is exposed in the third window 271. The number of the third windows 271 corresponds to the number of the back nano-vias 280. Then, the second dielectric layer 270 with the third window 271 is used as a mask layer, and the epitaxial layer 120 is etched from the back side of the epitaxial layer 120 in the third window 271. Here, a high etching selectivity is used to stop the etching on the first isolation buffer layer 170 in the front nano-via 160. Generally, the etching rate ratio of silicon (epitaxial layer 120) and dielectric layer (first isolation buffer layer 170, also called first insulating buffer layer) is >50:1. Thus, the back nano-via 280 is formed. The opening size and depth of the back nano-via 280 can be reasonably set according to requirements.

[0186] S70: Filling the back metal pillar 310 in the back nano via 280 and contacting the front metal pillar 181 includes:

[0187] S75 : forming a second isolation buffer layer 290 on the bottom wall and sidewalls of the back nano via hole 280 and the sidewalls of the third window 271 .

[0188] A second isolation buffer layer 290 is deposited on the bottom wall and side wall of the back nano-via 280. Fig.21 As shown, when the second dielectric layer 270 is formed on the front side of the epitaxial layer 120, the second isolation buffer layer 290 can be located on the bottom wall and sidewalls of the back nano-via 280 and the sidewalls and front side of the second dielectric layer 270. It can be understood that, considering the step coverage of thin film deposition, it is preferred to use thermal oxygen or atomic layer deposition ALD to grow the second dielectric layer 270.

[0189] S76 : performing etching from the back side of the second dielectric layer 270 to form a wiring groove 330 overlapping with the third window 271 in the second dielectric layer 270 .

[0190] like Fig. 22 As shown, the second dielectric layer 270 is etched from the back side of the second dielectric layer 270 , so as to form a wiring trench 330 in the second dielectric layer 270 , and the wiring trench 330 overlaps with the third window 271 .

[0191] S77 : at least the second isolation buffer layer 290 located at the bottom wall of the rear nano-via 280 is etched to expose the front metal pillar 181 .

[0192] S78: forming a second metal barrier layer and a back metal pillar 310 on the surface of the second isolation buffer layer 290 in the wiring trench 330 and the back nano via 280 by a damascene process.

[0193] like Fig.23 As shown, the second isolation buffer layer 290 and the first isolation buffer layer 170 at the bottom of the back nano-via 280 are removed by dry etching, so that the front metal column 181 can be exposed from the back nano-via 280, and then the wiring groove 330 and the back nano-via 280 are metallized by the Damascus process. The metallization process is divided into the deposition of the second metal barrier layer and the filling of the back metal column 310. The metallization process includes processes such as electroplating and chemical mechanical polishing. The back metal column 310 includes a metal block 350 located in the wiring groove 330.

[0194] Then, a fourth insulating layer 360 is formed on the back of the second dielectric layer 270. Fig.24 As shown, the power wiring layer 320 is continuously manufactured on the fourth insulating layer 360 , and the details may refer to the related method in Example 1.

[0195] Example 3 (such as Fig.12 , Figures 25 to 30 (shown)

[0196] In the process of at least thinning the wafer substrate 110 to expose the epitaxial layer 120 from the back side through S50, the thinning process can be divided into two stages: rough thinning and fine thinning, which specifically include:

[0197] S51 : roughly thinning the wafer substrate 110 from the back side of the wafer substrate 110 to form a thinned wafer 111 .

[0198] like Fig.12 As shown, the wafer substrate 110 is roughly thinned using the carrier wafer 260 as a support, so that the remaining wafer substrate 110 forms a thinned wafer 111. For example, the back side of the wafer substrate 110 is roughly thinned, and this step requires the wafer substrate 110 to be thinned from a thickness of about 775um to a thickness of 7-50um.

[0199] S53 : Fine Thinning After the wafer 111 is thinned, the epitaxial layer 120 is further finely thinned to a preset depth, so that the first isolation buffer layer 170 in the front nano-via 160 is exposed at the back side of the epitaxial layer 120 .

[0200] like Fig.25 As shown, after the wafer 111 is finely thinned, the epitaxial layer 120 is finely thinned to a preset depth, which can be achieved by chemical mechanical grinding, wet etching, dry etching, or a combination of these processes. For example, the process of fine thinning the epitaxial layer 120 is divided into two steps: the first step is to select a combination of high-selectivity wet etching and chemical mechanical grinding to perform preliminary fine thinning on the epitaxial layer 120. When the depth of the first fine thinning is about to reach the preset depth, the second fine thinning step is performed, that is, using a high-selectivity dry etching to continue thinning the back of the epitaxial layer 120 until the first isolation buffer layer 170 in the front nano-through hole 160 is exposed from the back of the epitaxial layer 120.

[0201] S60: forming a back nano-via 280 on the back side of the epitaxial layer 120 to be connected to the front nano-via 160 correspondingly, including:

[0202] S64 : forming a composite dielectric layer on the back side of the epitaxial layer 120 .

[0203] like Fig.26 As shown, a composite dielectric layer is deposited on the back of the epitaxial layer 120 after thinning, and then the back of the composite dielectric layer is planarized to repair the height difference caused by the exposure of the first isolation buffer layer 170 during the thinning process. Fig.26 As shown, the composite dielectric layer may include a first silicon oxide layer 371 , a first silicon nitride layer 372 , and a second silicon oxide layer 373 sequentially deposited on the back side of the epitaxial layer 120 .

[0204] S65: etching to form a first back contact hole 381 on the back side of the composite dielectric layer. The first back contact hole 381 terminates at the middle layer in the composite dielectric layer.

[0205] like Fig. 27 As shown, the composite dielectric layer is etched from the back side of the composite dielectric layer to form a first back contact hole 381 extending toward the inside of the composite dielectric layer, and the first back contact hole 381 ends at an intermediate layer in the composite dielectric layer, where the intermediate layer refers to a non-outermost layer of the composite dielectric layer. Fig. 27 As shown, when the composite dielectric layer includes a first silicon oxide layer 371, a first silicon nitride layer 372 and a second silicon oxide layer 373 sequentially deposited on the back side of the epitaxial layer 120, the first back contact hole 381 terminates in the first silicon nitride layer 372, and the etching rate ratio of the second silicon oxide and the first silicon nitride is generally >5:1.

[0206] S66: Etching is performed from the back side of the composite dielectric layer to form a wiring trench 330 overlapping with the first back side contact hole 381 in the composite dielectric layer.

[0207] S67: The composite dielectric layer and the first isolation buffer layer 170 are sequentially etched in the first back contact hole 381 to form a second back contact hole 382 in the composite dielectric layer and the first isolation buffer layer 170, wherein the front metal column 181 is exposed in the second back contact hole 382, ​​and the first back contact hole 381 and the second back contact hole 382 serve as back nano-vias 280.

[0208] like Fig.28 As shown, the composite dielectric layer is etched from the back side of the composite dielectric layer, thereby forming a wiring groove 330 in the composite dielectric layer, and the wiring groove 330 overlaps with the first back contact hole 381. Then, the first silicon nitride layer 372 and the first silicon oxide layer 371 in the composite dielectric layer and the first isolation buffer layer 170 are etched, thereby forming a second back contact hole 382 in the first silicon nitride layer 372, the first silicon oxide layer 371 and the first isolation buffer layer 170, so that the front metal column 181 is exposed in the second back contact hole 382, ​​and the first back contact hole 381 and the second back contact hole 382 are connected to form a back nano-via 280 located on the back side of the epitaxial layer 120.

[0209] S70: Filling the back metal pillars 310 in the back nano vias 280 and contacting the front metal pillars 181 includes: Fig.29 As shown, a second metal barrier layer and a back metal pillar 310 are formed in the wiring trench 330 and the back nano via 280 by a damascene process. The metallization process is divided into deposition of the second metal barrier layer and filling of the back metal pillar 310. The metallization process includes processes such as electroplating and chemical mechanical polishing.

[0210] Then, a fourth insulating layer 360 is formed on the back of the composite dielectric layer. Fig.30 As shown, the power wiring layer 320 is continuously manufactured on the fourth insulating layer 360 , and the details may refer to the related method in Example 1.

[0211] Another aspect of the present application provides an interconnect structure based on back power supply, which is prepared by any of the above-mentioned methods for preparing an interconnect structure based on back power supply. The interconnect structure based on back power supply can be Fig.18 , Fig.24 or Fig.30 The structure shown.

[0212] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing an interconnection structure based on back-side power supply, It is characterized in that The method comprises: Selecting a wafer substrate having an epitaxial layer of a certain thickness; Forming a front metal structure and a device structure that are spaced apart on the front side of the epitaxial layer, wherein the front metal structure includes a front nano-via extending from the front side of the epitaxial layer into the epitaxial layer and a front metal column filled in the front nano-via; Forming a signal wiring layer covering the front metal structure and the device structure on the front side of the epitaxial layer, wherein the signal wiring layer is metal-connected to the front metal structure and the device structure respectively; Bonding a carrier wafer on the front side of the signal wiring layer; At least thinning the wafer substrate to expose the epitaxial layer from the back side; forming a back nano-through hole on the back side of the epitaxial layer, the back nano-through hole corresponding to and connected to the front nano-through hole; Filling the back-side metal pillars in contact with the front-side metal pillars in the back-side nano-vias; A power wiring layer is formed on the back side of the epitaxial layer, wherein the power wiring layer is metal-connected to the back side metal pillar.

2. The method according to claim 1, It is characterized in that The front metal structure and device structure formed on the front side of the epitaxial layer and distributed at intervals include: forming a front nano-through hole extending into the epitaxial layer on the front side of the epitaxial layer; Filling the front metal pillars in the front nano-vias; A device structure located beside the front nano-through hole is formed on the front side of the epitaxial layer.

3. The method according to claim 2, It is characterized in that The forming of a front nano-through hole extending into the epitaxial layer on the front side of the epitaxial layer comprises: forming a first dielectric layer on the front side of the epitaxial layer; Forming a first window exposing the epitaxial layer on the first dielectric layer by photolithography; The first dielectric layer is used as a mask layer to etch the epitaxial layer in the first window to form the front nano-via.

4. The method according to claim 2, It is characterized in that Filling the front metal pillars in the front nano-vias comprises: forming a first isolation buffer layer on the bottom wall and side wall of the front nano-through hole; forming a first metal barrier layer on a surface of the first isolation buffer layer; The front metal pillar located in the front nano-via is formed on the surface of the first metal barrier layer.

5. The method according to claim 3, It is characterized in that A device structure located beside the front nano-through hole is formed on the front side of the epitaxial layer, including: Depositing a first insulating layer covering the front metal column on the front side of the first dielectric layer; Sequentially etching the first insulating layer and the first dielectric layer to form a second window exposing the epitaxial layer, wherein the second window is located beside the front nano-via; The device structure is formed on the epitaxial layer in the second window.

6. The method according to any one of claims 1 to 5, It is characterized in that The step of at least thinning the wafer substrate to expose the epitaxial layer from the back side comprises: performing rough thinning on the wafer substrate from the back side of the wafer substrate to form a thinned wafer; The thinned wafer is finely thinned, or, after the thinned wafer is finely thinned, the epitaxial layer is further finely thinned to a preset depth, so that the distance from the exposed back side of the epitaxial layer to the front nano-through hole is 0.2 to 1 micron.

7. The method according to claim 6, It is characterized in that The forming of a back nano-through hole on the back side of the epitaxial layer and correspondingly communicating with the front nano-through hole comprises: forming a second dielectric layer on the back side of the epitaxial layer; forming a third window exposing the epitaxial layer on the second dielectric layer by photolithography; The second dielectric layer is used as a mask layer to etch the epitaxial layer in the third window to form the back nano-via, wherein the back nano-via extends from the back side of the epitaxial layer to the front nano-via.

8. The method according to claim 6, It is characterized in that The back metal pillars filled in the back nano-vias and contacting the front metal pillars include: forming a second isolation buffer layer on the bottom wall and side wall of the back nano-through hole; At least etching the second isolation buffer layer located at the bottom wall of the rear nano-through hole to expose the front metal column; forming a second metal barrier layer on a surface of the second isolation buffer layer; The back metal pillar located in the back nano-via is formed on the surface of the second metal barrier layer.

9. The method according to claim 7, It is characterized in that The back metal pillars filled in the back nano-vias and contacting the front metal pillars include: Forming a second isolation buffer layer on the bottom wall and side wall of the back nano-through hole and the side wall of the third window; Etching from the back side of the second dielectric layer to form a wiring groove in the second dielectric layer that overlaps with the third window; At least etching the second isolation buffer layer located at the bottom wall of the rear nano-through hole to expose the front metal column; A second metal barrier layer and the back metal column are formed on the surface of the second isolation buffer layer in the wiring trench and the back nano-via by a Damascene process.

10. The method according to claim 4, It is characterized in that The step of at least thinning the wafer substrate to expose the epitaxial layer from the back side comprises: performing rough thinning on the wafer substrate from the back side of the wafer substrate to form a thinned wafer; After fine thinning the thinned wafer, the epitaxial layer is further fine thinned to a preset depth so that the first isolation buffer layer in the front nano-through hole is exposed at the back side of the epitaxial layer.

11. The method according to claim 10, It is characterized in that The forming of a back nano-through hole on the back side of the epitaxial layer and correspondingly communicating with the front nano-through hole comprises: forming a composite dielectric layer on the back side of the epitaxial layer; Etching a first back contact hole on the back side of the composite dielectric layer, wherein the first back contact hole terminates at an intermediate layer in the composite dielectric layer; Etching from the back side of the composite dielectric layer to form a wiring groove in the composite dielectric layer that overlaps with the first back side contact hole; The composite dielectric layer and the first isolation buffer layer are sequentially etched in the first back contact hole to form a second back contact hole in the composite dielectric layer and the first isolation buffer layer, wherein the front metal column is exposed in the second back contact hole, and the first back contact hole and the second back contact hole serve as the back nanovia.

12. The method according to claim 11, It is characterized in that The back metal pillars filled in the back nano-vias and contacting the front metal pillars include: A second metal barrier layer and the back metal pillar are formed in the wiring trench and the back nano via by a damascene process.

13. An interconnection structure based on back-side power supply, It is characterized in that The method for preparing an interconnect structure based on back power supply as claimed in any one of claims 1 to 12 is used for preparation.

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