Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention relates to a semiconductor device and a manufacturing method thereof. An anode region and a cathode region of the photodiode are formed in a semiconductor substrate. At the main surface of the semiconductor substrate, a plurality of first STI regions are formed on the cathode region, and an oxide film is formed between the plurality of first STI regions. A shield electrode is formed on the plurality of first STI regions and the oxide film. A thickness of each of the plurality of first STI regions is smaller than a thickness of the second STI region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-098723 filed on June 15, 2023, including specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and can be applied to a method for manufacturing a semiconductor device including a diode and a semiconductor device including a diode, for example. Background Art

[0004] The disclosed techniques are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. Hei 04-373181.

[0006] Patent Document 1 discloses a semiconductor device including a photodiode. Summary of the invention

[0007] A semiconductor device including a photodiode includes: a semiconductor substrate, an anode region and a cathode region formed in the semiconductor substrate, a dielectric layer formed on the cathode region, and a light-transmitting electrode formed on the dielectric layer. The light-transmitting electrode is formed for noise shielding. The dielectric layer on the cathode region reduces the parasitic capacitance between the light-transmitting electrode and the cathode region. Light passing through the light-transmitting electrode and the dielectric layer thereunder enters the cathode region.

[0008] The inventors consider using an STI region formed by an STI method as a dielectric layer to electrically isolate the cathode region of the photodiode from the shielding electrode. Even in this case, it is expected to improve the performance of the semiconductor device.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0010] According to one embodiment, a method for manufacturing a semiconductor device including a photodiode includes: (a) preparing a semiconductor substrate, (b) forming a plurality of first STI regions at a main surface of the semiconductor substrate, and (c) after (b), etching the plurality of first STI regions. The method for manufacturing a semiconductor device also includes: (d) after (c), forming an oxide film between the plurality of first STI regions and at the main surface of the semiconductor substrate by thermal oxidation treatment, and (e) after (d), performing a heat treatment at 1000 degrees Celsius or higher on the semiconductor substrate. In a plan view, the plurality of first STI regions are located in a cathode region of a first conductivity type of the photodiode.

[0011] In addition, according to one embodiment, a semiconductor device including a photodiode includes: an anode region of a first conductivity type formed in a semiconductor substrate, a cathode region of a second conductivity type formed on the anode region and in the semiconductor substrate, and a first semiconductor region of the first conductivity type formed on the anode region and in the semiconductor substrate. The semiconductor device also includes: a plurality of first STI regions formed on the cathode region and at the main surface of the semiconductor substrate, an oxide film formed between the plurality of first STI regions and at the main surface of the semiconductor substrate, and electrodes formed on the plurality of first STI regions and on the oxide film. The semiconductor device also includes: a first plug electrically connected to the cathode region, a second plug electrically connected to the first semiconductor region, and a second STI region disposed between the cathode region and the first semiconductor region and at the main surface of the semiconductor substrate. The second plug is electrically connected to the anode region via the first semiconductor region. The thickness of each of the plurality of first STI regions is smaller than the thickness of the second STI region.

[0012] According to one embodiment, the performance of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a main portion cross-sectional view during a manufacturing step of a semiconductor device in one embodiment.

[0014] Figure 2 Semiconductor devices are Figure 1 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0015] Figure 3 Semiconductor devices are Figure 2 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0016] Figure 4 Semiconductor devices are Figure 3 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0017] Figure 5 Semiconductor devices are Figure 4 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0018] Figure 6 Semiconductor devices are Figure 5 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0019] Figure 7 Semiconductor devices are Figure 6 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0020] Figure 8 Semiconductor devices are Figure 7 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0021] Fig. 9 Semiconductor devices are Figure 8 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0022] Fig.10 Semiconductor devices are Fig. 9 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0023] Fig.11 Semiconductor devices are Fig.10 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0024] Fig.12 Semiconductor devices are Fig.11 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0025] Fig.13 Semiconductor devices are Fig.12 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0026] Fig.14 Semiconductor devices are Fig.13 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0027] Fig.15 Semiconductor devices are Fig.14 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0028] Fig.16 Semiconductor devices are Fig.15 Cross-sectional view of the main parts during the subsequent manufacturing steps.

[0029] Fig.17 is a plan view of a main portion of a semiconductor device in one embodiment.

[0030] Fig.18 is a plan view of a main portion of a semiconductor device in one embodiment.

[0031] Fig.19 is a cross-sectional view of a main part of a semiconductor device in one embodiment.

[0032] Fig. 20 is a main portion cross-sectional view of a semiconductor device in a first inspection example.

[0033] Fig.21 is a main portion sectional view of a semiconductor device in a second inspection example.

[0034] Fig. 22 2 is an explanatory diagram for explaining the effect of the step of forming an oxide film by thermal oxidation.

[0035] Fig.23 2 is an explanatory diagram for explaining the effect of the step of forming an oxide film by thermal oxidation.

[0036] Fig.24 2 is an explanatory diagram for explaining the effect of the step of forming an oxide film by thermal oxidation. DETAILED DESCRIPTION

[0037] In the following embodiments, when necessary, for convenience, it will be described by being divided into multiple parts or embodiments, but unless otherwise specified, the following embodiments are not independent of each other, and one embodiment relates to modified examples, details, supplementary descriptions, etc. of some or all of the other embodiments. In the following embodiments, the number of elements, etc. (including the number of elements, numerical value, amount, range, etc.) is not limited to a specific number, but may not be less than or equal to a specific number, unless the number is specifically indicated and clearly limited to the specific number in principle. In addition, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessary, unless specifically specified and in principle they are clearly considered to be necessary. Similarly, in the following embodiments, when the shape, positional relationship, etc. of the reference component, etc., it is assumed that the shape, etc. are substantially similar or similar to the shape, etc., unless specifically specified and in principle they are considered to be very clear, etc. The above numerical value and range are equally applicable.

[0038] The embodiments will be described in detail with reference to the accompanying drawings. In all the drawings used to explain the embodiments, components having the same function are represented by the same reference numerals, and their repeated description is omitted. In the following embodiments, unless particularly necessary, the description of the same or similar parts will not be repeated in principle.

[0039] In the drawings used in the embodiments, hatching may be omitted even in the case of a cross-sectional view to make the drawings easier to see. In addition, hatching may be used even in the case of a plan view to make the drawings easier to see.

[0040] In addition, the plan view corresponds to a view from a plane substantially parallel to the main surface or back surface of the semiconductor substrate SUB. In addition, the bottom surface and the lower surface have the same meaning. In addition, the height position corresponds to the distance from the back surface of the semiconductor substrate SUB.

[0041] First embodiment

[0042] Semiconductor device manufacturing steps

[0043] The manufacturing steps of the semiconductor device of the present embodiment will be described with reference to the drawings. Figures 1 to 16 is a cross-sectional view of a main portion during a manufacturing step of the semiconductor device of the present embodiment.

[0044] The semiconductor device of this embodiment includes a photodiode and a transistor element.

[0045] In the present application, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or LDMOSFET includes not only MISFET using oxide film (silicon oxide film) as gate dielectric film, but also MISFET using dielectric film other than oxide film (silicon oxide film) as gate dielectric film. LDMOSFET may also be referred to as HV-MOSFET (High Voltage Metal Oxide Semiconductor Field Effect Transistor) or DEMOSFET (Drain Extended Metal Oxide Semiconductor Field Effect Transistor).

[0046] First, if Figure 1 As shown, a semiconductor substrate SUB having a p-type substrate body SB and an n-type semiconductor layer EP is prepared. The p-type substrate body SB is formed of, for example, p-type single-crystal silicon. The n-type semiconductor layer EP is formed of n-type single-crystal silicon formed on the main surface of the substrate body SB by epitaxial growth.

[0047] The main surface of the semiconductor substrate SUB is synonymous with the main surface of the semiconductor layer EP. In addition, the back surface of the semiconductor substrate SUB is synonymous with the back surface of the substrate body SB. The main surface of the semiconductor substrate SUB and the back surface of the semiconductor substrate SUB are located on opposite sides of each other.

[0048] Here, the semiconductor substrate SUB has a photodiode forming region 1A and a transistor forming region 1B. A photodiode is formed in the photodiode forming region 1A. A transistor element is formed in the transistor forming region 1B. The photodiode forming region 1A and the transistor forming region 1B are provided at different positions on the main surface of the semiconductor substrate SUB. Figures 3 to 16 The cross-sectional view of the transistor formation region 1B in FIG. 1 shows a cross-sectional view of an active region where a transistor element is formed.

[0049] like Figure 1 As shown, in the transistor formation region 1B, an n-type buried layer NBL is formed near the interface between the substrate body SB and the semiconductor layer EP. In addition, in a portion of the photodiode formation region 1A, a p-type buried layer PBL is formed near the interface between the substrate body SB and the semiconductor layer EP. The n-type buried layer NBL and the p-type buried layer PBL may also be formed before the semiconductor layer EP is formed. For example, after forming the n-type buried layer NBL and the p-type buried layer PBL in the p-type substrate body SB by ion implantation, an n-type semiconductor layer EP may be formed on the substrate body SB using an epitaxial growth method. The p-type buried layer PBL is formed at a position that does not overlap with the n-type well region NW in a plan view, which will be formed later.

[0050] Next, if Figure 2As shown, a p-type semiconductor region PS is formed in the semiconductor layer EP in the photodiode formation region 1A. The p-type semiconductor region PS is formed so as to reach the p-type buried layer PBL from the main surface of the semiconductor substrate SUB.

[0051] The p-type semiconductor region PS can be formed by implanting p-type impurity ions into the semiconductor layer EP and then thermally diffusing the p-type impurities. The p-type semiconductor region PS is formed on the p-type buried layer PBL and in the semiconductor layer EP. In addition, the p-type semiconductor region PS is formed at a position that does not overlap with the n-type well region NW in a plan view, and the n-type well region NW will be formed later.

[0052] Next, if Figure 3 As shown, an STI region (element isolation region) 3 is formed at the main surface of a semiconductor substrate SUB using an STI (shallow trench isolation) method. The STI region 3 is formed by a dielectric film (e.g., a silicon oxide film) buried in a trench 2 formed in a semiconductor layer EP. The height position of the bottom surface of the STI region 3 is higher than the height position of the bottom surface of the semiconductor layer EP.

[0053] After the trench 2 is formed at the main surface of the semiconductor substrate SB, a dielectric film is formed on the main surface of the semiconductor substrate SB to fill the trench 2. Then, the dielectric film outside the trench 2 is removed using a method such as a CMP (chemical mechanical polishing) method. This allows the STI region 3 formed of the dielectric film buried in the trench 2 to be formed.

[0054] Next, if Figure 4 As shown, a dielectric film NT is formed on the main surface of the semiconductor substrate SUB so as to cover the STI region 3. The dielectric film NT can be formed by a CVD method (Chemical Vapor Deposition), and is formed of, for example, a silicon nitride film.

[0055] Next, if Figure 5 As shown, after a photoresist pattern (not shown) is formed on the dielectric film NT, the dielectric film NT is patterned by using the photoresist pattern as an etching mask and etching the dielectric film NT. In this patterning step, the dielectric film NT is removed in a portion of the photodiode formation region 1A and a portion of the transistor formation region 1B.

[0056] like Figure 5 As shown, in the transistor formation region 1B, a portion of the semiconductor layer EP is exposed from the dielectric film NT. Specifically, the dielectric film NT exposes the region where the field oxide film 4 is to be formed. In the transistor formation region 1B, except for the region where the field oxide film 4 is to be formed, the semiconductor layer EP and the STI region 3 are covered by the dielectric film NT.

[0057] In addition, if Figure 5As shown, in the photodiode formation region 1A, the p-type semiconductor region PS, the region where the n-type semiconductor region NC is to be formed, and the STI region 3 between the p-type semiconductor region PS and the region where the n-type semiconductor region NC is to be formed are covered by the dielectric film NT. The remaining portions of the semiconductor layer EP and the STI region 3 are exposed from the dielectric film NT. Specifically, in the photodiode formation region 1A, except for the region where the n-type semiconductor region NC is to be formed, the region where the n-type well region NW is to be formed is exposed from the dielectric film NT.

[0058] The STI region 3 has an STI region 3a and an STI region 3b. The STI region 3a is covered by the dielectric film NT, and the STI region 3b is exposed from the dielectric film NT without being covered. At this stage, the height position of the upper surface of the STI region 3a is the same as the height position of the upper surface of the STI region 3b.

[0059] In the transistor formation region 1B, the STI region 3 a covered with the dielectric film NT is formed, and the STI region 3 b not covered with the dielectric film NT is not formed.

[0060] In the photodiode formation region 1A, the STI region 3 a covered with the dielectric film NT and the STI region 3 b not covered with the dielectric film NT are formed.

[0061] Specifically, when the n-type well region NW is formed later, the STI region 3b is located in the n-type well region NW (and therefore in the n-type cathode region) in a plan view. In the photodiode formation region 1A, when the p-type well region PW1 and the n-type well region NW are formed later, the STI region 3a is located between the p-type well region PW1 and the n-type well region NW. The STI region 3a defines an active region in which a transistor element is formed in the transistor formation region 1B.

[0062] Next, Figure 6 An etching step of etching the STI region 3b is shown.

[0063] Figure 6 The etching step is performed under an etching condition in which the etching rate of the semiconductor layer EP is lower than the etching rate of the STI region 3b. Figure 6 In the etching step, the STI region 3b is etched because it is exposed from the photoresist pattern and the dielectric film NT, but the STI region 3a is not etched because it is covered by the photoresist pattern and the dielectric film NT.

[0064] However, in Figure 6 In the etching step, not all of the thickness of the STI region 3b is removed by etching, but a portion of the thickness of the STI region 3b is removed by etching, and another portion of the thickness of the STI region 3b remains. Figure 6 The etching step is performed to reduce the thickness of the STI region 3b. Figure 6After the etching step, the STI region 3b remains, but Figure 6 After the etching step, the thickness of the STI region 3b is greater than that in Figure 6 Before the etching step, the thickness of the STI region 3b is small. For example, Figure 6 After the etching step, the thickness of the STI region 3b is Figure 6 The difference between the thickness of the STI region 3b before and after the etching step is about 50nm to 200nm. The thickness of the STI region 3 is the dimension of the STI region 3 in the direction from the main surface to the back surface of the semiconductor substrate SB. In other words, the thickness of the STI region 3 is the distance from the upper surface of the STI region 3 to the bottom surface.

[0065] In addition, Figure 6 In the etching step of , the STI region 3a is not etched because it is covered by the photoresist pattern and the dielectric film NT. Therefore, the thickness of the STI region 3a is Figure 6 The etching step did not change before and after.

[0066] exist Figure 6 Before the etching step, the thickness of the STI region 3a and the thickness of the STI region 3b are the same. Figure 6 Before the etching step, the height position of the upper surface of the STI region 3a and the height position of the upper surface of the STI region 3b are the same. Figure 6 After the etching step, the thickness of the STI region 3b is smaller than the thickness of the STI region 3a. Figure 6 After the etching step, the height position of the upper surface of the STI region 3b is lower than the height position of the upper surface of the STI region 3a. Figure 6 Before and after the etching step, the height position of the bottom surface of the STI region 3 a and the height position of the bottom surface of the STI region 3 b are identical to each other.

[0067] In addition, Figure 6 Before the etching step, the height position of the upper surface of the STI region 3b is the same as or higher than the height position of the upper surface of the semiconductor layer EP, but Figure 6 After the etching step, the height position of the upper surface of the STI region 3 b is lower than the height position of the upper surface of the semiconductor layer EP.

[0068] exist Figure 6 After the etching step is completed, the photoresist pattern is removed by ashing or the like.

[0069] Figure 7 The thermal oxidation step is shown. Figure 7 As shown, the field oxide film 4 and the oxide film 5 are formed by performing a thermal oxidation process on the semiconductor substrate SUB. Figure 7The heat treatment temperature of the thermal oxidation step in is, for example, about 950 degrees Celsius to 1100 degrees Celsius. Figure 7 After the thermal oxidation step, Figure 8 As shown, the dielectric film NT is removed by etching.

[0070] pass Figure 7 In the thermal oxidation step, in the transistor formation region 1B, the surface layer (upper part) of the semiconductor layer EP exposed from the dielectric film NT is thermally oxidized, thereby forming a field oxide film 4. The field oxide film 4 is formed by a LOCOS (local oxidation of silicon) method. For example, the field oxide film 4 is made of a silicon oxide film.

[0071] In addition, through Figure 7 In the thermal oxidation step, in the photodiode formation region 1A, the surface layer (upper part) of the semiconductor layer EP exposed from the dielectric film NT is thermally oxidized, thereby forming an oxide film 5. For example, the oxide film 5 is made of a silicon oxide film. The oxide film 5 is formed on the upper surface of the semiconductor layer EP between adjacent STI regions 3b. The oxide film 5 is not formed on the bottom surface and the side surface of the trench 2 covered by the STI region 3b, but the oxide film 5 can be formed on a portion of the side surface of the trench 2 not covered by the STI region 3b. The STI region 3b and the oxide film 5 can be formed integrally. The thickness of the oxide film 5 is smaller than the thickness of the STI region 3b. In addition, the thickness of the field oxide layer 4 is the same as the thickness of the oxide layer 5.

[0072] Furthermore, the p-type semiconductor region PS and the region where the n-type semiconductor region NC is to be formed in the photodiode formation region 1A are covered with the dielectric film NT. Therefore, the oxide film 5 is not formed on the p-type semiconductor region PS and the region where the n-type semiconductor region NC is to be formed.

[0073] Fig. 9 The ion implantation step and the heat treatment step are shown. Fig. 9 As shown, in the transistor formation region 1B, an n-type drift region DF is formed in the semiconductor layer EP by ion implantation and heat treatment. In the transistor formation region 1B, the n-type drift region DF is formed to reach the n-type buried layer NBL from the main surface of the semiconductor layer EP.

[0074] A photoresist pattern formed on the semiconductor substrate SUB (not shown) is used as an ion implantation blocking mask, and n-type impurities are implanted into the semiconductor layer EP in the transistor formation region 1B. Fig. 9 At a stage after the ion implantation step, the bottom surface of the n-type drift region DF does not reach the n-type buried layer NBL, and the bottom surface of the n-type drift region DF is separated from the n-type buried layer NBL. Fig. 9 After the ion implantation step, the photoresist pattern is removed and then heat treatment is performed to diffuse the n-type impurities. Fig. 9The heat treatment step is Fig. 9 The n-type impurities implanted in the ion implantation step diffuse in the direction from the main surface to the back surface of the semiconductor substrate SUB. Fig. 9 As shown, the bottom surface of the n-type drift region DF reaches the n-type buried layer NBL. Therefore, the n-type drift region DF is formed from the main surface of the semiconductor layer EP to the n-type buried layer NBL. That is, the n-type drift region DF is formed on the n-type buried layer NBL so as to contact the n-type buried layer NBL. The n-type drift region DF is formed by ion implantation and subsequent heat treatment, and the n-type drift region DF can be formed to a deeper position of the semiconductor substrate SUB.

[0075] Fig. 9 The heat treatment temperature in the heat treatment step is 1000 degrees Celsius or higher, preferably about 1100 degrees Celsius to 1200 degrees Celsius.

[0076] Next, if Fig.10 As shown, an n-type well region NW is formed using an ion implantation method. The n-type well region NW is an n-type semiconductor region.

[0077] The n-type well region NW is formed in the semiconductor layer EP in the photodiode formation region 1A. The n-type impurity concentration of the n-type well region NW is higher than the n-type impurity concentration of the n-type semiconductor layer EP. The height position of the bottom surface of the n-type well region NW is higher than the height position of the bottom surface of the semiconductor layer EP. Therefore, the n-type semiconductor layer EP exists below the n-type well region NW, and the p-type substrate body SB exists below the n-type semiconductor layer EP.

[0078] In addition, the height position of the bottom surface of the n-type well region NW is lower than the height position of the bottom surface of the STI region 3 b. The n-type well region NW is continuously formed below the STI region 3 b and below the oxide film 5. That is, the n-type well region NW covers the bottom surface of the STI region 3 b and the bottom surface of the oxide film 5. In addition, the n-type well region NW is formed in the region where the n-type semiconductor region NC is to be formed and below the region.

[0079] The n-type well region NW can be formed by using a photoresist pattern (not shown) as an ion implantation mask and implanting n-type impurity ions into a portion of the semiconductor layer EP in the photodiode formation region 1A. At this time, the n-type well region NW is formed by the n-type impurity ions that have passed through the STI region 3 b and the oxide film 5 .

[0080] Next, if Fig.10 As shown, the p-type well region PW1 and the p-type well region PW2 are formed using an ion implantation method. The p-type well region PW1 and the p-type well region PW2 are each a p-type semiconductor region. In a plan view, the n-type well region NW and the p-type well region PW1 and the p-type well region PW2 do not overlap each other and are separated from each other.

[0081] The p-type well region PW1 is formed in the semiconductor layer EP in the photodiode formation region 1A, more specifically, in the upper portion of the p-type semiconductor region PS. That is, in a plan view, the p-type well region PW1 is included in the p-type semiconductor region PS. The height position of the bottom surface of the p-type well region PW1 is higher than the height position of the bottom surface of the p-type semiconductor region PS. The bottom surface of the p-type well region PW1 is in contact with the p-type semiconductor region PS. The p-type impurity concentration of the p-type well region PW1 is higher than the p-type impurity concentration of the p-type semiconductor region PS.

[0082] In a plan view, the n-type well region NW does not overlap with any of the p-type buried layer PBL, the p-type semiconductor region PS, and the p-type well region PW1. Therefore, the bottom surface of the n-type well region NW contacts the n-type semiconductor layer EP.

[0083] The p-type well region PW2 is formed in the semiconductor layer EP in the transistor formation region 1B, more specifically, in the n-type drift region DF. In a plan view, the p-type well region PW2 is included in the n-type drift region DF. The height position of the bottom surface of the p-type well region PW2 is higher than the height position of the bottom surface of the n-type drift region DF.

[0084] The p-type well region PW1 and the p-type well region PW2 can be formed by using a photoresist pattern (not shown) as an ion implantation mask and implanting p-type impurity ions into a portion of the semiconductor layer EP in the photodiode formation region 1A and a portion of the semiconductor layer EP in the transistor formation region 1B. The p-type well region PW1 and the p-type well region PW2 are preferably formed by the same ion implantation step, but they may be formed by separate ion implantation steps.

[0085] In the present embodiment, the p-type well region PW1 and the p-type well region PW2 are formed after the n-type well region NW is formed, but the n-type well region NW may also be formed after the p-type well region PW1 and the p-type well region PW2 are formed.

[0086] Next, if Fig.11 As shown, a gate dielectric film GF, a gate electrode GE, and a shield electrode SE are formed. The shield electrode SE and the gate electrode GE are made of a polysilicon film. The shield electrode SE and the gate electrode GE are not connected and are separated from each other. For example, the gate dielectric film GF is formed of a silicon oxide film.

[0087] A dielectric film is formed on the exposed surface of the semiconductor layer EP. Then, a polysilicon film is formed on the dielectric film, on the STI region 3a and the STI region 3b, on the field oxide film 4, and on the oxide film 5. Subsequently, by patterning the polysilicon film using photolithography and etching techniques, a shield electrode SE and a gate electrode GE made of a polysilicon film can be formed. In addition, by patterning the dielectric film using photolithography and etching techniques, the dielectric film other than the dielectric film located under the gate electrode GE is removed, and a gate dielectric film GF made of the remaining dielectric film under the gate electrode GE is formed.

[0088] In photodiode formation region 1A, shield electrode SE is continuously formed on STI region 3b and oxide film 5. In transistor formation region 1B, gate electrode GE is formed on semiconductor layer EP via gate dielectric film GF, and a portion of gate electrode GE is located on field oxide film 4.

[0089] Next, after a low impurity concentration n-type semiconductor region (not shown) for an LDD (lightly doped drain) structure is formed in the p-type well region PW2 in the transistor formation region 1B using ion implantation, sidewall dielectric films (not shown) are formed on the side walls of the gate dielectric film GF and the shielding electrode SE, respectively.

[0090] Next, if Fig.12 As shown, an n-type semiconductor region NC, an n-type source region SR, and an n-type drain region DR are formed using ion implantation. The n-type source region SR serves as a source region of the LDMOSFET. The n-type drain region DR serves as a drain region of the LDMOSFET.

[0091] For example, in the formation of Fig.12 After forming the photoresist pattern RP1 shown in FIG. 1 , an n-type semiconductor region NC, an n-type source region SR, and an n-type drain region DR can be formed by using the photoresist pattern RP1 as an ion implantation blocking mask and implanting n-type impurities into the semiconductor substrate SUB. Subsequently, the photoresist pattern RP1 is removed by ashing, etc. The n-type semiconductor region NC, the n-type source region SR, and the n-type drain region DR are preferably formed by the same ion implantation step, but may also be formed by separate ion implantation steps.

[0092] The n-type semiconductor region NC is formed in the semiconductor layer EP in the photodiode formation region 1A, more specifically, in the upper part of the n-type well region NW. In a plan view, the n-type semiconductor region NC is included in the n-type well region NW. The height position of the bottom surface of the n-type semiconductor region NC is higher than the height position of the bottom surface of the n-type well region NW. The bottom surface of the n-type semiconductor region NC contacts the n-type well region NW. The n-type impurity concentration of the n-type semiconductor region NC is higher than the n-type impurity concentration of the n-type well region NW.

[0093] In a plan view, the n-type semiconductor region NC hardly overlaps with the oxide film 5 and the STI region 3 b. In other words, most of the n-type semiconductor region NC is not covered by the oxide film 5 and the STI region 3 b. The n-type semiconductor region NC is formed in the n-type well region NW exposed from the STI region 3 b and the oxide film 5.

[0094] The n-type drain region DR is formed in the semiconductor layer EP in the transistor formation region 1B, more specifically, in the n-type drift region DF. In a plan view, the n-type drain region DR is included in the n-type drift region DF. The height position of the bottom surface of the n-type drain region DR is higher than the height position of the bottom surface of the n-type drift region DF. The bottom surface of the n-type drain region DR contacts the n-type drift region DF. The n-type impurity concentration of the n-type drain region DR is higher than the n-type impurity concentration of the n-type drift region DF.

[0095] The n-type source region SR is formed in the semiconductor layer EP in the transistor formation region 1B, more specifically, in the p-type well region PW2. In a plan view, the n-type source region SR is included in the p-type well region PW2. The height position of the bottom surface of the n-type source region SR is higher than the height position of the bottom surface of the p-type well region PW2. The bottom surface of the n-type source region SR contacts the p-type well region PW2.

[0096] In the ion implantation step for forming the n-type semiconductor region NC, the n-type source region SR and the n-type drain region DR, the field oxide film 4 and the gate electrode GE may also act as an ion implantation blocking mask. Therefore, the n-type drain region DR is self-aligned and formed near one end of the field oxide film 4. In addition, the n-type source region SR is self-aligned and formed near the sidewall dielectric film (not shown) on the sidewall near the drain side of the gate electrode GE or on the sidewall. Therefore, in a plan view, the gate electrode GE is disposed between the n-type source region SR and the n-type drain region DR. In addition, in a plan view, the field oxide film 4 is disposed between the n-type drain region DR and the source region SR, adjacent to the drain region DR. The n-type source region SR may also have an LDD structure.

[0097] Next, if Fig.13 As shown, the p-type semiconductor region PC and the p-type semiconductor region PR are formed using an ion implantation method.

[0098] For example, in the formation of Fig.13 After forming the photoresist pattern RP2 shown in FIG. 1 , the p-type semiconductor region PC and the p-type semiconductor region PR can be formed by using the photoresist pattern RP2 as an ion implantation blocking mask and implanting p-type impurities into the semiconductor substrate SUB. Subsequently, the photoresist pattern RP2 is removed by ashing, etc. The p-type semiconductor region PC and the p-type semiconductor region PR are preferably formed by the same ion implantation step, but may also be formed by separate ion implantation steps.

[0099] The p-type semiconductor region PC is formed in the semiconductor layer EP in the photodiode formation region 1A, more specifically, in the p-type well region PW1. That is, in a plan view, the p-type semiconductor region PC is included in the p-type well region PW1. The height position of the bottom surface of the p-type semiconductor region PC is higher than the height position of the bottom surface of the p-type well region PW1. The bottom surface of the p-type semiconductor region PC is in contact with the p-type well region PW1. The p-type impurity concentration of the p-type semiconductor region PC is higher than the p-type impurity concentration of the p-type well region PW1.

[0100] The p-type well region PW1 exists below the p-type semiconductor region PC, the p-type semiconductor region PS exists below the p-type well region PW1, the p-type buried layer PBL exists below the p-type semiconductor region PS, and the p-type substrate body SB exists below the p-type buried layer PBL. Therefore, the p-type semiconductor region PC, the p-type well region PW1, the p-type semiconductor region PS, the p-type buried layer PBL, and the p-type substrate body SB are electrically connected to each other.

[0101] The p-type semiconductor region PR is formed in the semiconductor layer EP in the transistor formation region 1B, more specifically, in the p-type well region PW2. In a plan view, the p-type semiconductor region PR is included in the p-type well region PW2. The height position of the bottom surface of the p-type semiconductor region PR is higher than the height position of the bottom surface of the p-type well region PW2. The bottom surface of the p-type semiconductor region PR contacts the p-type well region PW2. The p-type impurity concentration of the p-type semiconductor region PR is higher than the p-type impurity concentration of the p-type well region PW2.

[0102] The p-type semiconductor region PR and the n-type source region SR are adjacent to each other in the gate length direction of the gate electrode GE. In a plan view, the n-type source region SR is located between the p-type semiconductor region PR and the gate electrode GE.

[0103] In this embodiment, the n-type semiconductor region NC, the n-type semiconductor region SR, and the n-type semiconductor region DR are formed after the p-type semiconductor region PC and the p-type semiconductor region PR are formed, but the p-type semiconductor region PC and the p-type semiconductor region PR may also be formed after the n-type semiconductor region NC, the n-type semiconductor region SR, and the n-type semiconductor region DR are formed.

[0104] Next, if Fig.14 As shown, a dielectric film SBL is formed on the shielding electrode SE. The dielectric film SBL may be formed by forming a dielectric film on a semiconductor substrate SUB and then patterning the dielectric film by photolithography and etching techniques. The dielectric film SBL exposes a portion of the upper surface of the shielding electrode SE and covers another portion of the upper surface of the shielding electrode SE.

[0105] Next, if Fig.14As shown, a metal silicide layer SL is formed. The metal silicide layer SL may be formed using a self-aligned silicide (SALS) technique. The metal silicide layer SL is formed of cobalt silicide, nickel silicide, or nickel silicide to which platinum is added.

[0106] The metal silicide layer SL may be formed on the upper portion of each of the gate electrode GE, the p-type semiconductor region PC, the n-type semiconductor region NC, the n-type drain region DR, the n-type source region SR, and the p-type semiconductor region PR. In addition, the metal silicide layer SL is formed on a portion of the shielding electrode SE. Specifically, the metal silicide layer SL is formed on the upper surface of the shielding electrode SE exposed from the dielectric film SBL. The metal silicide layer SL is not formed on the upper surface of the shielding electrode SE covered by the dielectric film SBL.

[0107] Next, if Fig.15 As shown, a dielectric film IL1 is formed on the main surface of the semiconductor substrate SUB to cover the gate electrode GE, the shield electrode SE, and the dielectric film SBL using a CVD method or the like. For example, the dielectric film IL1 is formed of a stacked film of a silicon nitride film and a silicon oxide film thereon. After the dielectric film IL1 is formed, the upper surface of the dielectric film IL1 may be polished and flattened using a CMP method or the like.

[0108] Next, if Fig.15 As shown, by etching the dielectric film IL1 using a photoresist pattern (not shown) formed on the dielectric film IL1 as an etching mask, a contact hole (through hole) is formed in the dielectric film IL1. Subsequently, a conductive plug PG1 is formed in the contact hole.

[0109] For example, a blocking conductor film is formed on the dielectric film IL1, which includes the bottom surface and side walls of the contact hole. A main conductor film made of tungsten or the like is formed on the blocking conductor film so as to fill the contact hole. Subsequently, the main conductor film and the blocking conductor film outside the contact hole are removed by a CMP method or the like. This allows the plug PG1 to be formed.

[0110] Next, if Fig.15 As shown, the wiring M1 is formed on the dielectric film IL1. For example, a conductive film is formed on the dielectric film IL1. Subsequently, by patterning the conductive film using photolithography and etching techniques, the wiring M1 made of the conductive film can be formed. The wiring M1 is preferably an aluminum wiring, but other metal wirings such as tungsten wiring can also be applied. In addition, copper wiring formed using a damascene technique can also be used as the wiring M1.

[0111] The wiring M1 includes a source wiring M1S, a drain wiring M1D, a cathode wiring M1C, an anode wiring M1A, and a wiring M1L. The source wiring M1S is electrically connected to the n-type source region SR via a metal silicide layer SL and a plug PG1 provided on the n-type source region SR. The drain wiring M1D is electrically connected to the n-type drain region DR via a metal silicide layer SL and a plug PG1 provided on the n-type drain region DR. The cathode wiring M1C is electrically connected to the n-type semiconductor region NC via a metal silicide layer SL and a plug PG1 provided on the n-type semiconductor region NC. The anode wiring M1A is electrically connected to the p-type semiconductor region PC via a metal silicide layer SL and a plug PG1 provided on the p-type semiconductor region PC. The wiring M1L is electrically connected to the shield electrode SE via a metal silicide layer SL and a plug PG1 provided on the shield electrode SE. The source wiring M1S, the drain wiring M1D, the cathode wiring M1C, the anode wiring M1A, and the wiring M1L are not connected and are separated from each other.

[0112] The source wiring M1S is electrically connected to the p-type semiconductor region PR via the metal silicide layer SL and the plug PG1 provided on the p-type semiconductor region PR. Therefore, the source potential supplied from the source wiring M1S to the n-type source region SR via the plug PG1 is supplied from the source wiring M1S to the p-type semiconductor region PR via the plug PG1, and is also supplied from the p-type semiconductor region PR to the p-type well region PW2.

[0113] In addition, the wiring M1 may also include a gate wiring electrically connected to the gate electrode GE via the plug PG1, but the gate wiring is not Fig.15 Shown in.

[0114] Next, if Fig.16 As shown, a dielectric film IL2 is formed on the dielectric film IL1 so as to cover the wiring M1. Subsequently, a contact hole is formed in the dielectric film IL2, and a conductive plug PG2 is formed in the contact hole. Fig.16 As shown, the wiring M2 is formed on the dielectric film IL2.

[0115] The wiring M2 includes a wiring M2A that electrically connects the anode wiring M1A and the wiring M1L. The wiring M2A is electrically connected to the anode wiring M1A via a plug PG2 provided on the anode wiring M1A, and is also electrically connected to the wiring M1L via a plug PG2 provided on the wiring M1L. The shield electrode SE is electrically connected to the p-type semiconductor region PC via the wiring M1L, the wiring M2A, the anode wiring M1A, the plugs PG1, PG2, and the metal silicide layer SL. Therefore, the potential of the shield electrode SE becomes the same as the potential of the p-type semiconductor region PC.

[0116] Further upper dielectric films and wirings may be formed, but their illustration and description are omitted.

[0117] The structure of semiconductor devices

[0118] Fig.17 and Fig.18 is a plan view of the main parts of the semiconductor device of this embodiment, Fig.19 is a cross-sectional view of a main part of the semiconductor device of this embodiment. Fig.17 and Fig.18 A plan view of the above-described photodiode forming region 1A is shown. Fig.19 Corresponds to Fig.17 and Fig.18 A cross-sectional view along line AA is shown in FIG. Figures 1 to 16 The cross section of the photodiode formation region 1A in Fig.17 and Fig.18 A cross-sectional view along line AA is shown in . Fig.17 is a plan view, but for ease of understanding, hatching is applied to the STI region 3, the n-type semiconductor region NC, and the p-type semiconductor region PC. Fig.18 It is a plan view, but for ease of understanding, hatching is applied to the n-type well region NW.

[0119] The semiconductor device of this embodiment includes a semiconductor substrate SUB having a p-type substrate body SB and an n-type semiconductor layer EP, an n-type well region NW, an n-type semiconductor region NC, a p-type semiconductor region PS, a p-type well region PW1 and a p-type semiconductor region PC formed in the semiconductor layer EP, and an STI region 3 and an oxide film 5 formed at the main surface of the semiconductor substrate SUB.

[0120] The n-type well region NW is located near the center of the photodiode formation region 1A, and as Fig.18 As shown, it has a rectangular planar shape. The bottom surface of the n-type well region NW is covered by the n-type semiconductor layer EP. The n-type semiconductor layer EP exists below the n-type well region NW, and the p-type substrate body SB exists below the n-type semiconductor layer EP. The n-type well region NW and the n-type semiconductor layer EP below the n-type well region NW act as the n-type cathode region of the photodiode. And, the p-type substrate body SB acts as the p-type anode region of the photodiode. The photodiode is formed by an n-type cathode region and a p-type anode region, which are adjacent to each other in the direction from the main surface to the back surface of the semiconductor substrate SUB. A PN junction is formed at the interface between the n-type cathode region and the p-type anode region, and a depletion layer is formed near the PN junction. The interface between the n-type cathode region and the p-type anode region is the interface between the n-type semiconductor layer EP and the p-type substrate body SB.

[0121] When light enters the semiconductor device, the light passing through the dielectric film IL2, the dielectric film IL1, the dielectric film SBL, the shielding electrode SE, the STI region 3b, and the oxide film 5 enters the n-type well region NW. In addition, the light enters the aforementioned depletion layer by passing through the n-type well region NW and the n-type semiconductor layer EP below the n-type well region NW. Therefore, a large number of electron-hole pairs are generated in the depletion layer. The electrons generated in the depletion layer flow to the n-type semiconductor region NC via the n-type semiconductor layer EP and the n-type well region NW, and also flow to the cathode wiring M1C via the metal silicide layer SL and the plug PG1C on the n-type semiconductor region NC. On the other hand, the holes generated in the depletion layer flow to the p-type semiconductor region PC via the p-type substrate body SB, the p-type buried layer PBL, the p-type semiconductor region PS, and the p-type well region PW1, and also flow to the anode wiring M1A via the metal silicide layer SL and the plug PG1A on the p-type semiconductor region PC. Therefore, the current flows from the cathode wiring M1C to the anode wiring M1A via the photodiode.

[0122] The n-type impurity concentration of the n-type semiconductor region NC is higher than that of the n-type well region NW, and the plug PG1C is connected to the n-type semiconductor region NC, and the cathode wiring M1C is connected to the plug PG1C. Therefore, the n-type semiconductor region NC is an electron extraction portion for extracting electrons generated in the photodiode from the semiconductor substrate SUB to the plug PG1C. The plug PG1C is located on the metal silicide layer SL on the n-type semiconductor region NC. The plug PG1C is electrically connected to the n-type semiconductor region NC via the metal silicide layer SL on the n-type semiconductor region NC, and is electrically connected to the n-type cathode region via the n-type semiconductor region NC. The n-type semiconductor region NC is a contact portion for connecting the plug PG1C to the semiconductor substrate SUB.

[0123] In a plan view, the n-type semiconductor region NC is included in the n-type well region NW. Fig.17 and Fig.18 In the plan view, the n-type semiconductor region NC is formed along the periphery of the n-type well region NW. In the plan view, the shield electrode SE does not overlap with the n-type semiconductor region NC.

[0124] In a plan view, the p-type semiconductor region PC, the p-type well region PW1, the p-type semiconductor region PS, and the p-type buried layer PBL overlap each other. The p-type well region PW1 exists below the p-type semiconductor region PC, the p-type semiconductor region PS exists below the p-type well region PW1, the p-type buried layer PBL exists below the p-type semiconductor region PS, and the p-type substrate body SB exists below the p-type buried layer PBL. The p-type semiconductor region PE is formed by the p-type semiconductor region PC, the p-type well region PW1, the p-type semiconductor region PS, and the p-type buried layer PBL. The p-type semiconductor region PE is provided on the p-type substrate body SB as a p-type anode region, and reaches the p-type substrate body SB from the main surface of the semiconductor substrate SUB. The p-type semiconductor region PE electrically connects the plug PG1A to the p-type semiconductor substrate. The p-type semiconductor region PE is formed so as to surround the n-type cathode region configured by the n-type well region NW and the n-type semiconductor layer EP in a plan view.

[0125] The n-type impurity concentration of the p-type semiconductor region PC is higher than that of the p-type well region PW, and the plug PG1A is connected to the p-type semiconductor region PC, and the anode wiring M1A is connected to the plug PG1A. Therefore, the p-type semiconductor region PC is a hole extraction portion for extracting holes generated in the photodiode from the semiconductor substrate SUB to the plug PG1A. The plug PG1A is disposed on the metal silicide layer SL on the p-type semiconductor region PC. The plug PG1A is electrically connected to the p-type semiconductor region PC via the metal silicide layer SL on the p-type semiconductor region PC, and is further electrically connected to the p-type substrate body SB via the p-type semiconductor region PC, the p-type well region PW1, the p-type semiconductor region PS, and the p-type buried layer PBL. The p-type semiconductor region PC is a contact portion for connecting the plug PG1A to the semiconductor substrate SUB.

[0126] At the main surface of the semiconductor substrate SUB, a plurality of STI regions 3b are formed on the n-type well region NW. That is, in a plan view, the plurality of STI regions 3b are arranged in the n-type well region NW. In a plan view, preferably, the plurality of STI regions 3b are arranged in an array. Fig.17 and Fig.18 In the embodiment, each of the plurality of STI regions 3b has a planar shape of a rectangle or a square. Fig.17 and Fig.18 , 36 STI regions 3 b are arranged in an array, but the number of STI regions 3 b is not limited to 36.

[0127] At the main surface of the semiconductor substrate SUB, an oxide film 5 is formed between the plurality of STI regions 3b. That is, the oxide film 5 is formed on the surface of the n-type well region NW between adjacent STI regions 3b. The plurality of STI regions 3b and the oxide film 5 are formed at the main surface of the semiconductor substrate SUB in the photodiode formation region 1A. In a plan view, the plurality of STI regions 3b and the oxide film 5 are included in the n-type well region NW.

[0128] The shielding electrode SE for noise shielding is formed on a plurality of STI regions 3b and an oxide film 5. The shielding electrode SE does not contact the semiconductor layer EP, and a plurality of STI regions 3b and an oxide film 5 are inserted between the shielding electrode SE and the semiconductor layer EP. In a plan view, the shielding electrode SE is included in the n-type well region NW. In a plan view, although most of the n-type well region NW overlaps with the shielding electrode SE, the n-type semiconductor region NC does not overlap with the shielding electrode SE. In addition, in a plan view, each STI region 3b overlaps with the shielding electrode SE.

[0129] The shielding electrode SE has a light-transmitting property that allows light entering the semiconductor device to pass through. For example, the shielding electrode SE is made of a polysilicon film. The shielding electrode SE has the function of electromagnetically shielding the photodiode. The presence of the shielding electrode SE stabilizes the surface potential of the n-type cathode region of the photodiode. Therefore, the resistance of the photodiode to noise can be increased.

[0130] Furthermore, by inserting a plurality of STI regions 3 b and oxide film 5 between shield electrode SE and n-type well region NW, the cathode region of the photodiode can be electrically isolated from shield electrode SE and parasitic capacitance between the cathode region of the photodiode and shield electrode SE can be reduced.

[0131] The shield electrode SE is connected to the plug PG1L. The plug PG1L is disposed on the metal silicide layer SL on the shield electrode SE. The plug PG1L is electrically connected to the shield electrode SE via the metal silicide layer SL.

[0132] The shielding electrode SE is electrically connected to the p-type semiconductor region PC via the metal silicide layer SL and the plugs PG1A, PG1L, PG2 and the wirings M1A, M1L, M2A. Therefore, the same potential (preferably the ground potential) is supplied to the shielding electrode SE and the p-type semiconductor region PC. A potential higher than that of the p-type semiconductor region PC (preferably a positive potential) is supplied from the cathode wiring M1C to the n-type semiconductor region NC via the plug PG1C. Therefore, the n-type cathode region of the photodiode becomes a potential higher than the p-type anode region, and when light enters the photodiode, current flows as described above.

[0133] The STI region 3a is disposed at a boundary between an n-type cathode region configured by an n-type well region NW and an n-type semiconductor layer EP and a p-type semiconductor region PE configured by a p-type semiconductor region PC, a p-type well region PW1, a p-type semiconductor region PS, and a p-type buried layer PBL. In another view, in a plan view, the STI region 3a is disposed between the n-type semiconductor region NC and the p-type semiconductor region PC. In yet another view, in a plan view, the STI region 3a is disposed between the plug PG1C and the plug PG1A. The STI region 3a electrically isolates the n-type cathode region from the p-type semiconductor region PE. In a plan view, the STI region 3a surrounds the n-type cathode region.

[0134] As explained in relation to the manufacturing steps of the semiconductor device, the thickness of STI region 3b is less than that of STI region 3a. In another view, the height position of the upper surface of STI region 3b is lower than the height position of the upper surface of STI region 3a. The height position of the bottom surface of STI region 3a is the same as that of STI region 3b.

[0135] Background

[0136] A semiconductor device including a photodiode has: a semiconductor substrate, an anode region and a cathode region formed on the semiconductor substrate, a dielectric layer formed on the cathode region, and a noise shield having a light-transmitting property formed on the dielectric layer. The dielectric layer is formed on the cathode region to reduce the parasitic capacitance between the shielding electrode and the cathode region. Light passing through the shielding electrode and the dielectric layer below the shielding electrode enters the cathode region.

[0137] The inventors consider using the STI region formed by the STI method as a dielectric layer for electrically isolating the cathode region of the photodiode from the shielding electrode. For example, when a photodiode and a transistor element are formed together on a semiconductor substrate, it is desirable to use the STI region as an element isolation region for the transistor element. Therefore, if the STI region is used as a dielectric film for electrically isolating the cathode region of the photodiode from the shielding electrode, the number of manufacturing steps can be reduced.

[0138] Fig. 20 is a main portion cross-sectional view of a semiconductor device in a first inspection example studied by the present inventors. Fig. 20 Shown above Fig.19 However, in Fig. 20 The above is omitted from the illustration. Fig.19 The dielectric films IL1, IL2, the plugs PG1, PG2, and the wirings M1, M2 shown in FIG.

[0139] exist Fig. 20In the case of the first test example shown, one STI region 3c is formed on the n-type well region NW, and the shield electrode SE is formed on the STI region 3c. The area of ​​the STI region 3c is larger than the area of ​​each STI region 3d in the second test example described later. In the case of the first test example, the above-mentioned Figure 6 A step corresponding to the etching step in is performed, and an oxide film corresponding to the above-mentioned oxide film 5 is not formed.

[0140] exist Fig. 20 In the case of the first test example shown, by inserting the STI region 3 c between the shielding electrode SE and the n-type well region NW, the cathode region of the photodiode can be electrically isolated from the shielding electrode SE and the parasitic capacitance between the cathode region of the photodiode and the shielding electrode SE can be reduced.

[0141] However, according to the study by the present inventors, it was found that the following problems occurred in the case of the first inspection example.

[0142] That is, since the area of ​​the STI region 3c in the first inspection example is larger than the area of ​​each STI region 3d in the second inspection example described later, a recess may occur in the CMP step for forming the STI region 3c. When the recess occurs, the thickness of the central portion of the STI region 3c becomes smaller than the thickness of the peripheral portion of the STI region 3c. This may cause the performance of the semiconductor device including the photodiode to be degraded. Therefore, it is not desirable to have a recess in the STI region 3c.

[0143] Fig.21 is a main portion cross-sectional view of a semiconductor device in a second inspection example studied by the present inventors. Fig.21 Shown above Fig.19 and Fig. 20 The corresponding cross section. Fig.21 The above is also omitted from the diagram. Fig.19 The dielectric films IL1, IL2, the plugs PG1, PG2, and the wirings M1, M2 shown in FIG.

[0144] exist Fig.21 In the case of the second test example shown, a plurality of STI regions 3d are inserted between the shield electrode SE and the n-type well region NW. An oxide film 5 is formed between the plurality of STI regions 3d. However, in the case of the second test example, the above-described Figure 6 Therefore, in Fig.21 In the case of the second test example shown, each of the STI regions 3 has the same thickness.

[0145] exist Fig.21In the case of the second inspection example shown, by inserting a plurality of STI regions 3d and an oxide film 5 between the shielding electrode SE and the n-type well region NW, the cathode region of the photodiode can be electrically isolated from the shielding electrode SE and the parasitic capacitance between the cathode region of the photodiode and the shielding electrode SE can be reduced.

[0146] In the case of the second inspection example, a plurality of STI regions 3d are inserted between the shield electrode SE and the n-type well region NW. Therefore, the plane size (area) of each STI region 3d in the second inspection example can be reduced compared to the plane size (area) of the STI region 3c in the first inspection example. Therefore, in the case of the second inspection example, the occurrence of a recess when forming the STI region 3d can be suppressed or prevented.

[0147] However, according to the research of the present inventors, in the case of the second inspection example, it was found that crystal defects may occur in the semiconductor substrate SUB below the STI region 3d due to stress caused by the STI region 3d. The reason why the crystal defects occur will be described below.

[0148] The first reason is that the volume of the STI region 3d is large. If the volume of the STI region 3d is large, the stress caused by the STI region 3d tends to become large.

[0149] The second reason is that oxide film 5 is formed by thermal oxidation after STI region 3d is formed. In the thermal oxidation step for forming oxide film 5, stress attributable to STI region 3d tends to increase due to expansion of STI region 3d.

[0150] The third reason is that high temperature heat treatment (specifically, heat treatment at 1000 degrees Celsius or higher) is applied to the semiconductor substrate SUB after the oxide film 5 is formed by thermal oxidation. In a state where the stress attributable to the STI region 3d increases due to the first reason and the second reason, when the high temperature heat treatment step (specifically, heat treatment at 1000 degrees Celsius or higher) is performed, crystal defects may occur in the semiconductor substrate SUB below the STI region 3d.

[0151] Therefore, due to the first reason, the second reason, and the third reason, crystal defects may occur in the semiconductor substrate SUB below the STI region 3d. The occurrence of crystal defects in the semiconductor substrate SUB below the STI region 3d means that crystal defects occur in the cathode region or the anode region of the photodiode, resulting in reduced performance of the semiconductor device including the photodiode. Therefore, in order to improve the performance of the semiconductor device including the photodiode, the semiconductor device needs to prevent the stress caused by the STI region 3d from causing crystal defects in the semiconductor substrate SUB below the STI region 3d.

[0152] Main features and effects

[0153] The semiconductor device of the present embodiment includes a photodiode and has: a semiconductor substrate SUB, a p-type anode region (p-type substrate body SB) formed in the semiconductor substrate SUB, and an n-type cathode region (n-type well region NW and n-type semiconductor layer EP) formed on the p-type anode region in the semiconductor substrate SUB. A plurality of STI regions 3b are formed on the n-type cathode region and at the main surface of the semiconductor substrate SUB, and an oxide film 5 is formed between the plurality of STI regions 3b and at the main surface of the semiconductor substrate SUB.

[0154] The planar size of each STI region 3b in this embodiment can be reduced compared to the planar size of the STI region 3c in the first inspection example. Therefore, even in this embodiment, the occurrence of recesses when forming the STI region 3b in the photodiode formation region 1A can be suppressed or prevented.

[0155] One of the main features of this embodiment is that the manufacturing steps of the semiconductor device include Figure 6 The etching step shown is performed, and in this etching step, a plurality of STI regions 3b are etched.

[0156] In this embodiment, by Figure 6 By etching a plurality of STI regions 3b in the etching step shown, the thickness of each STI region 3b can be reduced, and thus the volume of each STI region 3b can be reduced. That is, the thickness of each STI region 3b in the present embodiment can be made smaller than the thickness of each STI region 3d in the second inspection example. Therefore, the volume of each STI region 3b in the present embodiment can be made smaller than the volume of each STI region 3d in the second inspection example.

[0157] The larger the volume of each STI region 3 is, the more likely the stress caused by the STI region 3 is to increase. Figure 6 In the etching step shown, a plurality of STI regions 3 b are etched to reduce the volume of each STI region 3 b , thereby suppressing stress caused by the STI region 3 b .

[0158] In addition, in the present embodiment, the step of etching the STI region 3b ( Figure 6 The etching step shown in FIG. 1 is performed in the step of forming the oxide film 5 ( Figure 7 The thermal oxidation for forming the oxide film 5 is performed before the thermal oxidation step (shown in FIG. 1 ). After the volume of each STI region 3 b is reduced, the thermal oxidation for forming the oxide film 5 is performed. In other words, the thermal oxidation for forming the oxide film 5 is performed in a state where the volume of each STI region 3 b is reduced. Therefore, even if the STI region 3 b expands during the thermal oxidation for forming the oxide film 5, the stress caused by the expansion of the STI region 3 b can be suppressed because the volume of the STI region 3 b is reduced.

[0159] Furthermore, in the present embodiment, after performing the steps of forming the STI region 3, etching the STI region 3b, and forming the oxide film 5, a step of performing a high temperature heat treatment (specifically, a heat treatment at 1000 degrees Celsius or higher) on the semiconductor substrate SUB is further included. For example, this high temperature heat treatment is Fig. 9 Heat treatment steps shown. Fig. 9 The heat treatment step shown is a heat treatment step after ion implantation to form the n-type drift region DF. Depending on the type of transistor element to be formed in the transistor formation region 1B, other high temperature (1000 degrees Celsius or higher) heat treatment steps may also be performed. If a high temperature heat treatment step (specifically, a heat treatment of 1000 degrees Celsius or higher) is performed in a state where the stress caused by the STI region 3b is large, crystal defects may occur in the semiconductor substrate SUB below the STI region 3b.

[0160] In contrast, in this embodiment, by Figure 6 The illustrated etching step reduces the volume of each STI region 3 b, which can suppress the stress caused by the STI region 3 b. Therefore, the occurrence of crystal defects in the semiconductor substrate SUB below the STI region 3 b can be suppressed or prevented.

[0161] Therefore, in the present embodiment, by performing an etching step ( Figure 6 The etching step shown in the figure can suppress the stress caused by the STI region 3b. Therefore, the occurrence of crystal defects in the semiconductor substrate SUB below the STI region 3b can be suppressed or prevented. Therefore, the performance of the semiconductor device including the photodiode can be improved.

[0162] Another main feature of this embodiment is Figure 6 In the etching step shown, the STI region 3 b is etched, but the STI region 3 a is not etched.

[0163] In this embodiment, Figure 6 After the illustrated etching step, the thickness of STI region 3 b becomes smaller than the thickness of STI region 3 a , and the height position of the upper surface of STI region 3 b becomes lower than the height position of the upper surface of STI region 3 a .

[0164] Specifically, at the main surface of the semiconductor substrate SUB, the STI region 3b is applied to a plurality of STI regions 3 formed on the n-type cathode region. In other words, in a plan view, the STI region 3b is applied to a plurality of STI regions 3 located in the n-type cathode region. This can suppress or prevent the occurrence of crystal defects in the n-type cathode region due to stress caused by the STI region 3. Therefore, the performance of a semiconductor device including a photodiode can be improved.

[0165] On the other hand, at the main surface of the semiconductor substrate SUB, the STI region 3a is provided between the n-type cathode region and the p-type semiconductor region PE. That is, at the main surface of the semiconductor substrate SUB, the STI region 3a is provided between the n-type semiconductor region NC and the p-type semiconductor region PC.

[0166] like Fig.19 As shown, the STI region 3a disposed between the n-type semiconductor region NC and the p-type semiconductor region PC has the function of electrically isolating the p-type region from the n-type region, the p-type region being formed by the p-type semiconductor region PC and the p-type well region PW1, and the n-type region being formed by the n-type semiconductor region NC and the n-type well region NW. However, if charges are unintentionally stored in the STI region 3a, an n-type inversion layer is formed along the sidewall of the STI region 3a adjacent to the p-type well region PW1, and there is a risk that leakage current will flow in the n-type inversion layer. That is, there is a concern that leakage current will flow between the metal silicide layer SL on the p-type semiconductor region PC and the n-type well region NW along the sidewall and bottom surface of the STI region 3a disposed between the n-type semiconductor region NC and the p-type semiconductor region PC. This leakage current degrades the performance of the semiconductor device including the photodiode, so it is desirable to suppress or prevent this leakage current.

[0167] In contrast, in this embodiment, since the STI region 3a which is thicker than the STI region 3b is provided between the n-type semiconductor region NC and the p-type semiconductor region PC, the above leakage current can be suppressed or prevented. Therefore, the performance of the semiconductor device including the photodiode can be improved.

[0168] In addition, if Figures 1 to 16 As shown, when forming a photodiode and a transistor element on a semiconductor substrate SUB, it is desirable to apply an STI region 3a to an STI region 3 defining an active region forming the transistor element. The STI region 3 defining the active region surrounds the active region in a plan view.

[0169] The STI region 3 defining the active region forming the transistor element has the function of electrically isolating the active region from other active regions. The thinner the STI region 3 is, the more difficult it is to achieve electrical isolation through the STI region 3. Therefore, the thickness of the STI region 3 defining the active region forming the transistor element needs to be set to a suitable thickness as an element isolation region. However, as described above, in order to prevent crystal defects from occurring in the n-type anode region of the photodiode due to the STI region 3, it is desirable to reduce the thickness of the STI region 3 located on the n-type anode region of the photodiode.

[0170] Therefore, in this embodiment, when forming the above Figure 3At the stage of forming the STI region 3 shown in FIG. 1 , the thickness of the STI region 3a defining the active region forming the transistor element is set to a thickness that can sufficiently achieve electrical isolation. Then, Figure 6 In the etching step, the STI region 3b is etched, and the STI region 3a is not etched. This allows the thickness of the STI region 3b located on the n-type anode region of the photodiode to be reduced while maintaining the thickness of the STI region 3a defining the active region forming the transistor element. Therefore, the performance of the semiconductor device including the photodiode and the transistor element can be improved.

[0171] Next, we will refer to Figure 22 to Figure 24 The step of forming the oxide film 5 is explained with reference to the explanatory diagram of Figure 7 of the thermal oxidation step). Figure 22 to Figure 24 A partially enlarged cross-sectional view showing a portion of the photodiode formation region 1A. Fig. 22 Corresponding to the above Figure 3 The same steps, Fig.23 Corresponding to the above Figure 6 The same steps and Fig.24 Corresponding to the above Figure 7 Same steps.

[0172] Fig. 22 2 shows a case where, when the trench 2 is formed on the semiconductor substrate SUB, a needle-shaped protrusion 6 is generated on the bottom surface of the trench 2. For example, when the trench 2 is formed by etching, the protrusion 6 may appear when foreign matter from the etching is suppressed from adhering to the main surface of the semiconductor substrate SUB. When the STI region 3 is formed in a state where the protrusion 6 is generated on the bottom of the trench 2, the protrusion 6 is covered by the STI region 3, as shown in FIG. Fig. 22 shown.

[0173] When executing the above Figure 6 When the STI region 3 b is etched by the etching step, the thickness of the STI region 3 b becomes smaller, such as Fig.23 If the protrusion 6 is generated on the bottom surface of the trench 2, when the thickness of the STI region 3b is reduced by etching, a portion of the protrusion 6 may protrude from the upper surface of the STI region 3b. Fig.23 , protrusion 6a and protrusion 6b are shown, the height of protrusion 6a is greater than the height of protrusion 6b, a part of protrusion 6a protrudes from the upper surface of STI region 3b, and protrusion 6b does not protrude from the upper surface of STI region 3b.

[0174] Then, by executing the above Figure 7 The thermal oxidation step forms an oxide film 5, such as Fig.24As shown. At this time, the protrusion 6a protruding from the upper surface of the STI region 3b can also be oxidized. This is because the protrusion 6a is made of the same material as the semiconductor layer EP. Fig.24 As shown in FIG. 1 , the height of the protrusion 6a is reduced, and the entire protrusion 6a is covered by the STI region 3b. In addition, the entire protrusion 6b is covered by the STI region 3b. Then, the reference Figures 8 to 16 Steps explained.

[0175] The shielding electrode SE is formed on the STI region 3b. If the protrusion 6 is generated on the bottom surface of the trench 2, the n-type cathode region of the photodiode is electrically connected to the shielding electrode SE when the protrusion 6 contacts the shielding electrode SE. This situation needs to be prevented because it causes the n-type cathode region to be electrically connected to the p-type anode region via the shielding electrode SE and the wirings M1L, M1A, M2A.

[0176] In the present embodiment, even when the protrusion 6 is generated on the bottom surface of the trench 2, the protrusion 6a protruding from the upper surface of the STI region 3b can be oxidized during the thermal oxidation for forming the oxide film 5. Fig.24 As shown, since all the protrusions 6 are covered by the STI region 3b, the protrusions 6 can be prevented from contacting the shielding electrode SE. Therefore, the reliability of the semiconductor device including the photodiode can be improved.

[0177] By performing the oxide film 5 forming step, even when the protrusion 6 is generated on the bottom surface of the trench 2 , the protrusion 6 can be prevented from coming into contact with the shield electrode SE.

[0178] The invention made by the present inventors has been described in detail above based on the embodiments, but the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the gist thereof.

Claims

1. A method for manufacturing a semiconductor device including a photodiode, the method comprising: (a) preparing a semiconductor substrate; (b) forming a plurality of first STI regions at the main surface of the semiconductor substrate; (c) after step (b), etching the plurality of first STI regions; (d) after (c), forming an oxide film between the plurality of first STI regions at the main surface of the semiconductor substrate by thermal oxidation treatment; and (e) after (d), performing a heat treatment at 1000 degrees Celsius or higher on the semiconductor substrate, The plurality of first STI regions are located in a cathode region of the first conductivity type of the photodiode in a plan view.

2. The method according to claim 1, Wherein in (c), the thickness of the plurality of first STI regions is reduced by etching the plurality of first STI regions.

3. The method according to claim 1, comprising: (f) forming electrodes on the plurality of first STI regions and the oxide film.

4. The method according to claim 1, wherein in said (b), a second STI region is formed at said main surface of said semiconductor substrate, The method comprises: (b1) after (b) and before (c), forming a first dielectric film on the main surface of the semiconductor substrate, the first dielectric film covering the second STI region and exposing the plurality of first STI regions, In (c), the second STI region is covered by the first dielectric film, and the plurality of first STI regions exposed from the first dielectric film are etched.

5. The method according to claim 4, comprising: (d1) After the step (d), the first dielectric film is removed.

6. The method according to claim 4, After (c), a thickness of each of the plurality of first STI regions is smaller than a thickness of the second STI region.

7. The method according to claim 4, The second STI region defines an active region in the semiconductor substrate where transistor elements are formed.

8. The method according to claim 7, comprising: (g) forming an LDMOSFET in the active region of the semiconductor substrate, The heat treatment in (e) is performed to form a semiconductor region of the LDMOSFET.

9. The method according to claim 8, In the (d), a field oxide film is formed at a portion of the surface of the active region by the heat treatment.

10. The method according to claim 4, wherein the semiconductor substrate comprises an anode region of a second conductivity type, the second conductivity type being opposite to the first conductivity type of the photodiode, The method comprises: (h) forming a first semiconductor region of the second conductivity type in the semiconductor substrate, the first semiconductor region reaching the anode region from the main surface of the semiconductor substrate, Wherein, at the main surface of the semiconductor substrate, the second STI region is arranged between the cathode region and the first semiconductor region.

11. The method according to claim 10, comprising: (i) forming a first plug on the cathode region in the semiconductor substrate, and forming a second plug on the first semiconductor region in the semiconductor substrate, the first plug being electrically connected to the cathode region, and the second plug being electrically connected to the first semiconductor region, The second plug is electrically connected to the anode region via the first semiconductor region.

12. The method according to claim 1, The plurality of first STI regions are arranged in an array in a plan view.

13. A semiconductor device comprising: Semiconductor substrate; an anode region of a first conductivity type of a photodiode, the anode region being formed in the semiconductor substrate; a cathode region of a second conductivity type, the second conductivity type being opposite to the first conductivity type of the photodiode, the cathode region being formed on the anode region and in the semiconductor substrate; a plurality of first STI regions formed on the cathode region and at the main surface of the semiconductor substrate; an oxide film formed between the plurality of first STI regions and at the main surface of the semiconductor substrate; an electrode formed on the plurality of first STI regions and on the oxide film; a first plug disposed on the cathode region and electrically connected to the cathode region; The first semiconductor region of the first conductivity type is formed on the anode region and in the semiconductor substrate; a second plug disposed on the first semiconductor region and electrically connected to the first semiconductor region; as well as a second STI region disposed between the cathode region and the first semiconductor region and at the main surface of the semiconductor substrate, wherein the second plug is electrically connected to the anode region via the first semiconductor region, and The thickness of each of the plurality of first STI regions is smaller than the thickness of the second STI region.

14. The semiconductor device according to claim 13, The height position of the upper surface of each of the plurality of first STI regions is lower than the height position of the upper surface of the second STI region.

15. The semiconductor device according to claim 14, A bottom surface of each of the plurality of first STI regions has the same height as a bottom surface of the second STI region.

16. The semiconductor device according to claim 13, The plurality of first STI regions are arranged in an array in a plan view.

17. The semiconductor device according to claim 13, comprising: a third plug disposed on the electrode and electrically connected to the electrode; as well as A wiring is provided to electrically connect the second plug and the third plug.

18. The semiconductor device according to claim 13, comprising: a third STI region formed at the main surface of the semiconductor substrate and defining an active area; as well as a transistor element formed in the active region, The thickness of each of the plurality of first STI regions is smaller than the thickness of the third STI region.

19. The semiconductor device according to claim 18, The height position of the upper surface of each of the plurality of first STI regions is lower than the height position of the upper surface of the second STI region, and is lower than the height position of the upper surface of the third STI region.

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