Semiconductor device with enhanced thermal mitigation

Abstract

A semiconductor device with enhanced thermal mitigation is provided. The semiconductor device includes: a logic die; a first plurality of stacked memory dies electrically coupled with the logic die at a first location above the backside surface of the logic die; a second plurality of stacked memory dies electrically coupled with the logic die at a second location above the backside surface of the logic die; a first dielectric material disposed over a backside surface of the logic die and between the first plurality of stacked memory dies and the second plurality of stacked memory dies; and a dummy die disposed over the first dielectric material and coupled to the first plurality of stacked memory dies and the second plurality of stacked memory dies, wherein the dummy die is coupled to back side surfaces of the first plurality of stacked memory dies and the second plurality of stacked memory dies through a second dielectric layer having a dielectric-dielectric melt bond.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices, and more particularly, to semiconductor device structures configured to enhance thermal mitigation. Background Art

[0002] Microelectronic devices typically have a die (i.e., chip) that includes an integrated circuit system with a high density of very small components. Typically, the die includes an array of very small bonding pads that are electrically coupled to the integrated circuit system. The bonding pads are external electrical contacts through which supply voltages, signals, etc. are transmitted to and from the integrated circuit system. After the die is formed, the die can be "packaged" to couple the bonding pads to a larger array of electrical terminals that can be more easily coupled to various power supply lines, signal lines, and ground lines. Conventional processes for packaging the die include electrically coupling the bonding pads on the die to an array of leads, ball pads, or other types of electrical terminals and encapsulating the die to protect them from environmental factors (e.g., moisture, particles, static electricity, and physical shock). Summary of the invention

[0003] On the one hand, the present disclosure provides a semiconductor device, comprising: a logic die; a first plurality of stacked memory dies electrically coupled to the logic die at a first position above a backside surface of the logic die; a second plurality of stacked memory dies electrically coupled to the logic die at a second position above the backside surface of the logic die; a first dielectric material disposed above the backside surface of the logic die and between the first plurality of stacked memory dies and the second plurality of stacked memory dies, the first dielectric material having a thickness similar to a height of the first plurality of stacked memory dies or the second plurality of stacked memory dies; and a dummy die disposed above the first dielectric material and coupled to the first plurality of stacked memory dies and the second plurality of stacked memory dies, wherein the dummy die is coupled to the backside surfaces of the first plurality of stacked memory dies and the second plurality of stacked memory dies through a second dielectric layer having a dielectric-to-dielectric fusion bond.

[0004] On the other hand, the present disclosure further provides a semiconductor device, comprising: a logic die; a plurality of stacked memory dies electrically coupled to the logic die; a first dielectric material disposed around the plurality of stacked memory dies, the first dielectric material having a thickness similar to a height of the plurality of stacked memory dies; and a dummy die disposed above the plurality of stacked memory dies, the dummy die being coupled to the backside surfaces of the plurality of stacked memory dies through a second dielectric layer having a dielectric-dielectric bond.

[0005] On the other hand, the present disclosure further provides a method for manufacturing a semiconductor device, which includes: providing a wafer of logic dies; providing a memory wafer having a first plurality of stacked memory dies and a second plurality of stacked memory dies; coupling the first plurality of stacked memory dies and the second plurality of stacked memory dies to the wafer of the logic die; depositing a first dielectric material at the wafer of the logic die, the first dielectric material being disposed between the first plurality of stacked memory dies and the second plurality of stacked memory dies, and the first dielectric material having a thickness similar to a height of the first plurality of stacked memory dies or the second plurality of stacked memory dies; polishing the first dielectric material disposed over backside surfaces of the first plurality of stacked memory dies and the second plurality of stacked memory dies; coupling a dummy wafer to the first plurality of stacked memory dies and the second plurality of stacked memory dies; cutting through the dummy wafer, the first dielectric material, and the wafer of the logic die; and encapsulating the semiconductor device using a molding compound material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A simplified schematic cross-sectional view illustrating a semiconductor device.

[0007] Figure 2 A simplified schematic cross-sectional view illustrating another semiconductor device in accordance with an embodiment of the present technology.

[0008] Figures 3 to 9B Simplified schematic perspective and cross-sectional views illustrating a series of steps for fabricating a semiconductor device in accordance with an embodiment of the present technology.

[0009] Fig.10 A method of manufacturing a semiconductor device according to an embodiment of the present technology is described.

[0010] Fig.11 Schematic diagrams illustrating systems including semiconductor device assemblies configured in accordance with embodiments of the present technology.

[0011] The accompanying drawings illustrate only example embodiments and therefore should not be considered limiting of scope. The elements and features shown in the accompanying drawings are not necessarily drawn to scale, instead emphasis is placed on clearly illustrating the principles of the example embodiments. In addition, certain dimensions or layouts may be exaggerated to help convey such principles visually. In the accompanying drawings, the same reference numerals used in different embodiments designate similar or corresponding but not necessarily identical elements. DETAILED DESCRIPTION

[0012] The demand for smaller and more compact semiconductor devices has led to integrated circuit designs in which components are stacked on top of each other, with the stack being disposed on a common packaging substrate to form an assembly. Specifically, a stacked semiconductor device may stack multiple semiconductor dies on top of each other to increase the number of circuit elements within a package without increasing its footprint. In order to produce a stacked semiconductor device, multiple wafers may be stacked together and cut into individual die stacks. Conventional assemblies of stacked integrated circuit components may include one or more dummy dies placed or formed on top of the stacked semiconductor die to flatten the stacked semiconductor die along with other integrated circuit components included in the same package assembly. The dummy die may be formed from a silicon wafer to a designed size in a singulation process and then coupled to the stacked semiconductor die by flowing a non-conductive fill material between the dummy die and the stacked semiconductor die. The stacked semiconductor die and one or more dummy dies may then be packaged into a packaged semiconductor device for implementation within a larger electronic device. However, due to limitations such as thermal mitigation, some technologies may have difficulty producing large stacks of semiconductor dies. One such technology is Figure 1 It is demonstrated by way of examples.

[0013] Figure 1 A semiconductor device 100 is described, which includes a first plurality of semiconductor dies 144 (e.g., memory dies) and a second plurality of semiconductor dies 144' (e.g., memory dies) assembled on a wafer 142 of semiconductor dies (e.g., logic dies). The first plurality of stacked semiconductor dies 144 and the second plurality of stacked semiconductor dies 144' can be singulated from a semiconductor wafer stack. The semiconductor wafer stack can be produced by bonding a wafer including a plurality of semiconductor dies (e.g., by wafer-wafer bonding). The wafers can be bonded in a front-to-back arrangement such that the front side (e.g., active side) of the first wafer where the circuitry of the semiconductor die is implemented is mounted to the back side (e.g., non-active side) of the second wafer. One or more of the semiconductor wafers may include through silicon vias (TSVs 134) exposed at the back side of the semiconductor wafer. The semiconductor wafers can be coupled by hybrid bonding. For example, the semiconductor wafers can be electrically coupled by interconnects (e.g., metal-metal interconnects) and bonded by dielectric materials (e.g., dielectric blocks 122 and 126). In aspects, the interconnects may be copper-copper (Cu-Cu) interconnects through contact pads 128 or 124. Dielectric materials 122 and 126 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or the like.

[0014] Once the semiconductor wafers have been bonded into a stack, the stack of semiconductor dies may be singulated from the wafer stack and assembled onto a wafer of semiconductor dies 142. In this example, the top memory die 106 may be coupled to the core memory die 104 by wafer-to-wafer bonding of the first memory wafer and the second memory wafer and singulation of the bonded wafers. The wafer of semiconductor dies 142 may include a plurality of semiconductor dies having a different arrangement than the semiconductor dies in the first plurality of stacked semiconductor dies 144 or the second plurality of stacked semiconductor dies 144'. For example, the wafer of semiconductor dies 142 may include a logic die, and the first plurality of stacked semiconductor dies 144 or the second plurality of stacked semiconductor dies 144' may include a memory die. Thus, the wafer of semiconductor dies 142 may not be bonded to the wafer stack by wafer-to-wafer bonding. Alternatively, the wafer 142 of semiconductor dies may be bonded to the carrier substrate 130 to help the device withstand processing, and the first plurality of stacked semiconductor dies 144 and the second plurality of stacked semiconductor dies 144′ may be electrically coupled to the wafer 142 of semiconductor dies. After the plurality of stacked semiconductor dies are assembled onto the wafer 142 of semiconductor dies, a mold resin 120 may be disposed on the wafer 142 of semiconductor dies around the plurality of stacked semiconductor dies 144 and the plurality of stacked semiconductor dies 144′. Additionally, solder balls 132 may be formed on the back side of the carrier substrate to provide power interconnects. Then, the stacked semiconductor dies and the various semiconductor dies on the wafer of semiconductor dies 142 may be cut, and the singulated semiconductor die stacks may be packaged into the semiconductor device 100.

[0015] The semiconductor device 100 also includes a dummy die 108 disposed above each of the first plurality of stacked semiconductor dies 144 or the second plurality of stacked semiconductor dies 144'. In this example, the dummy die 108 is coupled to each of the first plurality of stacked semiconductor dies 144 or the second plurality of stacked semiconductor dies 144' through an NCF layer 118. The NCF layer 118 may be made of an epoxy-based material, an acrylic-based material, and / or a polyimide-based material, thereby providing robust electrical insulation between the dummy die 108 and the plurality of stacked semiconductor dies 144 and 144'. Here, the NCF layer 118 may have a thickness above a threshold value (e.g., 15 μm) to ensure good adhesion. In addition, due to the type of material included in the NCF layer 118, the NCF layer 118 may have a low thermal conductivity (e.g., 0.31 to 0.36 W / (m·K)). The low thermal conductivity and thicker film profile of the NCF layer 118 makes it challenging to achieve good thermal mitigation in the semiconductor device 100 .

[0016] To address these and other shortcomings, various embodiments of the present technology provide a semiconductor device including a wafer-to-wafer (W2W) front-to-backside bonding between a dummy silicon die and a plurality of stacked semiconductor dies. A semiconductor device is provided. The semiconductor device includes: a logic die; a first plurality of stacked memory dies electrically coupled to the logic die at a first position above a backside surface of the logic die; a second plurality of stacked memory dies electrically coupled to the logic die at a second position above the backside surface of the logic die; a first dielectric material disposed above the backside surface of the logic die and between the first plurality of stacked memory dies and the second plurality of stacked memory dies; and a dummy die disposed above the first dielectric material and coupled to the first plurality of stacked memory dies and the second plurality of stacked memory dies, wherein the dummy die is coupled to the backside surfaces of the first plurality of stacked memory dies and the second plurality of stacked memory dies through a second dielectric layer having a dielectric-dielectric fusion bond. Figure 2 An example semiconductor device is shown in FIG.

[0017] Figure 2 A semiconductor device 200 is illustrated, which includes a first plurality of semiconductor dies 244 (e.g., memory dies) and a second plurality of semiconductor dies 244' (e.g., memory dies) on a wafer coupled to a semiconductor die 242 (e.g., a logic die). The first plurality of semiconductor dies 244 may be coupled (e.g., chip-wafer bonding) to a wafer of semiconductor die 206 at the first semiconductor die (e.g., at a first lateral position). The wafer of semiconductor dies 242 may be assembled onto a carrier substrate 230 (e.g., by an adhesive or dielectric material) to enable the semiconductor device 200 to withstand processing. The carrier substrate 230 may include solder balls 232 on its back side to provide electrical interconnection. Here, the first plurality of stacked semiconductor dies 244 and the second plurality of stacked semiconductor dies 244' may be singulated from a semiconductor wafer stack. The semiconductor wafer stack may be produced by bonding a wafer including a plurality of semiconductor dies (e.g., wafer-wafer bonding). The wafers may be joined in a front-to-back arrangement such that the front side (e.g., active side) of the first wafer, where the circuitry of the semiconductor die is disposed, is mounted to the back side (e.g., inactive side) of the second wafer. One or more of the semiconductor dies in the first plurality of stacked semiconductor dies 244 may include TSVs 234 exposed at the back side of the semiconductor die. The contact pads 228 may be formed at the front side of the semiconductor die and the contact pads 224 may be formed at the exposed TSVs 234 at the front side of the semiconductor die.

[0018] The semiconductor die may be electrically coupled at the contact pad 228 and the contact pad 224 by an interconnect. The semiconductor die within the first plurality of stacked semiconductor die 244 may be coupled by hybrid bonding. For example, the semiconductor die may be electrically coupled by an interconnect 234 (e.g., a metal-metal interconnect) and bonded by a dielectric material 222 or 226 (e.g., a dielectric block). In aspects, the contact pads 224 and 228 may be copper-copper (Cu-Cu) interconnects. The dielectric material 222 or 226 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or the like. Assuming that the interconnect may be formed according to wafer-wafer bonding, the interconnect between the contact pads 224 and 228 may be smaller than the interconnect formed by chip-wafer or die-wafer bonding. In this example, the plurality of stacked semiconductor die 244 includes a top semiconductor die 206 and a core semiconductor die 204, and the top semiconductor die 206 is coupled to the core semiconductor die 204. The second plurality of semiconductor dies 244' may be similarly manufactured and cut from a semiconductor wafer stack. For example, the second plurality of stacked semiconductor dies 244' may include a top semiconductor die and a core semiconductor die, the top semiconductor die being coupled to the core semiconductor die. The second plurality of semiconductor dies may be coupled to the wafer of semiconductor die 242 at a second position above the backside surface of the wafer of semiconductor die 242. The distance between the first position and the second position may be in the range of from 10 μm to 10 mm. In addition, a dielectric material 220 may be disposed on the wafer of semiconductor die 242 and between the first plurality of semiconductor dies 244 (e.g., memory dies) and the second plurality of semiconductor dies 244'. As shown, the dielectric material 220 may be filled between the plurality of stacked semiconductor dies 244 and 244' without any gaps. Furthermore, the dielectric material 220 may also be disposed over the backside surfaces of the first plurality of semiconductor dies 244 (e.g., memory dies) and the second plurality of semiconductor dies 244', thereby forming a thin dielectric layer 218 having a thickness in a range from 10 nm to 1 μm and a planarized surface thereover. Furthermore, the first dielectric material 220 may be further disposed in an edge region of the semiconductor device 200. The first dielectric material 220 may surround the outer sidewalls of the first plurality of stacked memory dies 244 and the second plurality of stacked memory dies 244' facing the edge region of the semiconductor device 200.

[0019] In this example, the semiconductor device 200 may include a dummy die 208 disposed above the first plurality of semiconductor dies 244 and the second plurality of semiconductor dies 244'. The dummy die 208 may be formed on a dummy silicon wafer coupled to the first plurality of semiconductor dies 244 and the second plurality of semiconductor dies 244' according to a singulation process. Figure 2, the dummy die 208 may be bonded to the first plurality of semiconductor die 244 and the second plurality of semiconductor die 244' by dielectric-dielectric bonding (e.g., SiO-SiO bonding) between dielectric layers 218 and 218'. The dielectric layers 218 and 218' may be made of a dielectric material including silicon oxide, silicon nitride, and / or silicon carbonitride. In this example, each of the dielectric layers 218 and 218' may have a thickness in a range from 10 nm to 1 μm. In some other examples, the dielectric layers 218 and 218' may be different from the dielectric material 220. For example, the dielectric layer 218 (e.g., silicon nitride) may be deposited over the backside surfaces of the first plurality of semiconductor die 244 and the second plurality of semiconductor die 244'. In addition, the dielectric layer 218' (e.g., silicon nitride) may be deposited on the frontside surface of the dummy silicon wafer before wafer-to-wafer bonding. The dielectric layers 218 and 218' may be bonded together by applying heat treatment and compressive pressure. A fusion bond may be formed between the dielectric layers 218 and 218' to provide strong adhesion between the dummy die 208 and the first and second plurality of semiconductor dies 244 and 244'. Compared to the NCF layer 118 disposed between the dummy die 108 and the stacked semiconductor dies 144 and 144', Figure 2 The fusion-bonded dielectric layers 218 and 218' described in have much smaller thickness and high thermal conductivity (eg, the thermal conductivity of silicon oxide is close to 1.2 W / (m·K)). Therefore, the semiconductor device 200 may exhibit better thermal mitigation performance than the semiconductor device 100.

[0020] The semiconductor device 200 may include any number of semiconductor dies in a stacked semiconductor die. For example, each of the plurality of stacked semiconductor dies 244 and 244' may include three or more semiconductor dies vertically coupled to each other. Additional semiconductor dies may be stacked by techniques similar to those described with respect to the first plurality of stacked semiconductor dies 244 and the second plurality of stacked semiconductor dies 244'. The semiconductor device 200 may further include an encapsulation material 236 (e.g., a molding resin compound or the like) that at least partially encapsulates the dummy die 208, the plurality of stacked semiconductor dies 244 and 244', the corresponding logic die 242, and the substrate 230 to prevent electrical contact therewith, and provides mechanical strength and protection to the semiconductor device 200.

[0021] Although described with a specific configuration, the semiconductor device of the present technology may include Figure 2. For example, the semiconductor device may include a different number of semiconductor die stacks, a different number of multiple stacked semiconductor dies within each stack, a different number of semiconductor dies within each stack, a different number of semiconductor dies within each multiple stacked semiconductor dies, and so on. In one embodiment, the semiconductor device 200 may include 4, 6, 8, 10, or any number of semiconductor die stacks therebetween. In another embodiment, the semiconductor device 200 may include 10, 20, 50, 100, 200, 300, 400, 500, or any number of semiconductor die stacks therebetween. In another embodiment, the semiconductor device 200 may be a dual crossbar switch random access memory (TCRAM) having 6 or more stacked semiconductor memory dies disposed on a logic die.

[0022] In one embodiment, various numbers (e.g., 4, 8, 16, 32, 48, 96, 128, 256, 512, or any number therebetween) of memory dies may be stacked vertically on top of each other to form a high bandwidth memory (HBM) with increased memory bandwidth. These memory dies may be interconnected using TSVs, which enables high-speed communication between the memory dies. Specifically, a single functional die (e.g., DRAM die) stack in the front-to-back stacking configuration described above may be surrounded by a dielectric material. In a single functional die stack, the rear surface of the top functional die (e.g., top DRAM die) may be coupled to a dummy silicon die by fusion bonding a dielectric layer disposed on the rear surface of the top functional die and the front surface of the silicon layer.

[0023] Semiconductor device 200 illustrates one type of device of the present technology. Alternatively, the front side surface of the dummy silicon die may be bonded to the front side surface of a plurality of memory stacks. In one embodiment, the front side surface of the logic die may be coupled to the front side surface of a plurality of stacked functional memory dies (e.g., a plurality of DRAM die stacks). Each of the plurality of stacked functional dies is in a B2F stacking configuration. The plurality of stacked functional dies may be surrounded by a dielectric material such as SiO2. The front side surface of the top functional die within each of the plurality of stacked functional dies may be coupled to the front side of the silicon layer by fusion bonding a SiO2 layer disposed on the front side of the top functional die (e.g., the top DRAM die) and the front side of the silicon layer.

[0024] The present disclosure now turns to a series of steps for manufacturing a semiconductor device 200 according to an embodiment of the present technology. Specifically, Figures 3 to 9B A method for manufacturing a semiconductor device (eg, Figure 2 200) is a simplified schematic perspective view and cross-sectional view of a series of steps of a semiconductor device 200 shown in FIG. For ease of description, the steps are described with respect to a specific embodiment. However, according to other embodiments, the steps may be performed with respect to Figures 3 to 9B The steps are described to manufacture a semiconductor device.

[0025] from Figure 3 Initially, at stage 300, a semiconductor wafer stack 302 is provided. The semiconductor wafer stack 302 may be bonded to a carrier wafer 304 to enable the semiconductor wafers to withstand processing. For example, a first semiconductor wafer 306 may be bonded to the carrier wafer 304 (e.g., in a face-down arrangement). The TSVs may be exposed at the back side of the first semiconductor wafer 306, and the contact pads may be disposed at the back side. A second semiconductor wafer 308 may be electrically coupled to the first semiconductor wafer 306 at the contact pads by wafer-wafer bonding (e.g., in a front-to-back arrangement). The second semiconductor wafer 308 may be electrically coupled to the first semiconductor wafer 306 by hybrid bonding to bond the wafers by dielectric materials (e.g., dielectric blocks) and metal-metal interconnects. A third semiconductor wafer 310 may be coupled to the second semiconductor wafer 308 at the contact pads on the back side of the second semiconductor wafer 308. The third semiconductor wafer 310 may be thicker than each of the other semiconductor wafers. In aspects, each of the plurality of semiconductor wafers may have a similar semiconductor die arrangement. Subsequently, the semiconductor wafer stack 302 may be removed from the carrier wafer 304 for further processing. In some other embodiments, the semiconductor wafer stack 302 may include more than two electrically coupled semiconductor wafers (e.g., three semiconductor wafers or four semiconductor wafers). These more than two semiconductor wafers may also be disposed below and coupled to the third semiconductor wafer 310.

[0026] Steering Figure 4 At stage 400, the semiconductor wafer stack 302 may be bonded to the back grinding tape 402 to enable the semiconductor wafer stack 302 to be thinned. The first semiconductor wafer 306 may be bonded to the back grinding tape 402 in a face-down position so that the back side of the third semiconductor wafer 310 is exposed for thinning. Here, the back side of the third semiconductor wafer 310 may be thinned by any suitable method (e.g., using back grinding, chemical mechanical planarization (CMP), or the like). In aspects, the back grinding process may not expose the TSVs at the back side of the third semiconductor wafer 310. After thinning, the back grinding tape 402 may be removed from the semiconductor wafer stack 302 to enable the semiconductor wafer stack 302 to be cut.

[0027] Steering Figure 5At stage 500, the semiconductor wafer stack 302 may be cut into a plurality of stacked semiconductor dies. The semiconductor wafer stack 302 may be bonded to a dicing tape 502 at the back side of the third semiconductor wafer 310. The back side of the first semiconductor wafer 306 may be exposed to enable the semiconductor wafer stack 302 to be cut between the plurality of semiconductor dies. Once cut, the plurality of stacked semiconductor dies may be singulated from each other. Subsequently, the plurality of stacked semiconductor dies may be tested and assembled into a package.

[0028] Next turn Figure 6 , at stage 600, a plurality of stacked semiconductor dies 602 are assembled onto a wafer of semiconductor dies 604 (e.g., logic dies). Here, each of the plurality of stacked semiconductor dies 602 may have the same number of semiconductor dies (e.g., two semiconductor dies in each stack). In some other embodiments, the plurality of stacked semiconductor dies 602 may have a different number of semiconductor dies. For example, the plurality of stacked semiconductor dies 602 may each have three semiconductor dies. In some other examples, the plurality of stacked semiconductor dies 602 may each have up to ten or twenty semiconductor dies. The plurality of stacked semiconductor dies 602 may be electrically coupled to the wafer of semiconductor dies 604 at the respective semiconductor dies or at the same semiconductor die (e.g., at different lateral positions) using chip-wafer bonding. The wafer of semiconductor dies 604 may be assembled onto a carrier wafer 606 to enable the semiconductor device assembly to withstand processing. The wafer of semiconductor dies 604 may have a different semiconductor die arrangement than the plurality of stacked semiconductor dies 602. A plurality of stacked semiconductor dies 602 may be selected from stacked semiconductor dies cut from a semiconductor wafer stack. The plurality of stacked semiconductor dies 602 may be selected based on the quality of the plurality of stacked semiconductor dies 602. The quality of the plurality of stacked semiconductor dies 602 may be determined by probing the stacked semiconductor dies cut from a semiconductor wafer stack. In this manner, the highest quality semiconductor die stack or “known good cube” may be selected from the stacked semiconductor dies cut from a semiconductor wafer stack to improve yield.

[0029] In some cases, the wafer 604 of semiconductor dies may be diced to produce individual semiconductor die stacks (eg, HBM devices), such as Figure 6. In other cases, the wafer of semiconductor dies 604 may be cut to produce semiconductor dies (e.g., of the wafer of semiconductor dies 604) having multiple stacks of semiconductor dies coupled thereto at multiple lateral locations. For example, a semiconductor device may include a central processing unit (CPU) or a graphics processing unit (GPU) having multiple stacks of memory dies coupled thereto. Specifically, three-dimensional integration of semiconductor devices may include stacked DRAM dies and a workstation GPU in the same package.

[0030] Next turn Fig. 7A , at stage 700a, a dielectric material 706 (e.g., silicon oxide) may be deposited between the plurality of stacked semiconductor dies 602. Each of the plurality of stacked semiconductor dies 602 may include two or more semiconductor dies vertically coupled by corresponding contact pads and interconnects. In aspects, the dielectric material layer 702 may also be disposed on the logic wafer 604. Furthermore, the dielectric material 706 may be disposed on the backside surface of the plurality of stacked semiconductor dies 602. Furthermore, the dielectric material 706 may surround the sidewalls of the plurality of stacked semiconductor dies 602. In this manner, the plurality of stacked semiconductor dies 602 may be embedded in the dielectric material 706. The plurality of stacked semiconductor dies 602 may be disposed at various locations at the backside surface of the logic wafer 604. The distance D1 between adjacent plurality of stacked semiconductor dies 602 may be in the range from 10 μm to 10 mm. In this example, the aspect ratio of the space filled by the dielectric material 706 (e.g., the ratio of the height of the plurality of stacked semiconductor dies 602 to the distance D1) may be as high as 20: 1. A gap-fill dielectric deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD)) may be used to fill the space between the adjacent plurality of stacked semiconductor dies 602. Specifically, a high-density plasma assisted chemical vapor deposition (HDPCVD) technique may be used for the dielectric gap-fill.

[0031] In some implementations, each of the plurality of stacked semiconductor dies 602 may be coupled to a dedicated logic die of the logic wafer 604. Thus, the dielectric material 706 may be disposed on the carrier wafer 606. As shown, the carrier wafer 606 may be coupled to the logic wafer 604 by fusion bonding between the dielectric layers 702 and 704. In this example, the dielectric material 706 may then be thinned using a CMP process to provide a flat dielectric layer over the backside surface of the plurality of stacked semiconductor dies 602, where an additional dummy wafer or die may be coupled. The thickness of the dielectric layer over the plurality of stacked semiconductor dies 602 may be adjusted by controlling the CMP process (e.g., using an endpoint detection technique for the CMP process), and may be in the range of from 10 nm to 1 μm. In this example, a dielectric material having a low thermal resistance may be utilized as the dielectric material 706. For example, silicon oxide has a high thermal conductivity of about 1.2 W / (m·K), and thus may be used as a gap-fill material to improve the thermal conductivity of the semiconductor device described in the present disclosure.

[0032] Alternatively, the liner layer 708 may be deposited before filling the dielectric material 706 between the plurality of stacked semiconductor dies 602. Figure 7B As shown at stage 700b in FIG. 6 , a liner layer 708 may be conformally deposited over the semiconductor device from stage 600. For example, the liner layer 708 may be deposited over the backside surfaces and sidewalls of the plurality of stacked semiconductor dies 602. In addition, the liner layer 708 may also be deposited over the logic wafer 604 and between the adjacent plurality of stacked semiconductor dies 602. The liner layer 708 may be made of a material different from the dielectric material 706, such as silicon nitride. Various thin film deposition techniques including CVD, PVD, and ALD may be utilized here to conformally deposit the liner layer 708. The thickness of the liner layer 708 may range from 10 nm to 1 μm. Once the liner layer 708 is deposited, the dielectric material 706 may be coated over the backside surfaces of the adjacent plurality of stacked semiconductor dies 602 and in the spaces between the adjacent plurality of stacked semiconductor dies. The dielectric material 706 may be further planarized using a CMP process. In this example, planarization of the dielectric material 706 may stop on a liner layer 708 disposed over backside surfaces of the plurality of stacked semiconductor dies 602 .

[0033] Next turn Fig. 8A At stage 800a, a dummy wafer may be bonded to the semiconductor wafer assembly from stage 700a. In one aspect, the front side surface of the dummy silicon wafer 804 may be bonded to the semiconductor wafer assembly from stage 700a. Fig. 7A804 can be bonded to the backside surface of the chip-to-wafer bonding assembly described in . The dummy silicon wafer 804 can be bonded using a wafer-to-wafer front-to-back melt bonding process. For example, a dielectric layer 802 made of a dielectric material 706 (e.g., silicon oxide) can be coated on the front side surface of the dummy silicon wafer 804. The dummy silicon wafer 804 can be bonded to the chip-on-wafer assembly by forming a melt bond between the dielectric layer 802 and a flat layer 706 disposed above the backside surface of the plurality of stacked semiconductor dies 602. In this example, the melt bonding process relies on chemical bonds and interactions between the interfacing surfaces of the dielectric layers 802 and 706. For example, intermolecular interactions including van der Waals forces, hydrogen bonds, and strong covalent bonds can be formed in the melt bonding process to connect dielectric-dielectric surfaces at high temperatures and / or compressive pressures. In addition, the bonding interface between the dummy silicon wafer 804 and the chip-on-wafer assembly may be affected by thermal cycles (e.g., annealing temperatures) applied during the melt bonding process. Fusion bonding techniques can help semiconductor die manufacturers meet the demand to reduce the volume occupied by semiconductor die assemblies.

[0034] Alternatively, a dielectric layer made of a material different from the dielectric material 706 may be deposited to assist in bonding the dummy wafer to the chip-on-wafer assembly from stage 700b. In one aspect, once the dielectric material 706 is planarized and the pad layer 708 over the backside surfaces of the plurality of stacked semiconductor dies 602 is exposed, a dielectric layer 806 may be deposited over the planarized dielectric material 706 and the exposed pad layer 708. The dielectric layer 806 may be made of a material different from the dielectric material 706 (e.g., silicon oxide), such as silicon nitride or silicon carbonitride. Additionally, another dielectric layer 808 may be coated on the frontside surface of the dummy silicon wafer 804. The dielectric layer 808 may be made of the same material as the dielectric layer 806 (e.g., silicon nitride or silicon carbonitride). Each of the dielectric layers 806 and 808 may have a thickness in the range from 100 nm to 1 μm. In this example, the dummy silicon wafer 804 may be bonded to the chip-on-wafer assembly by fusion bonding the dielectric layers 806 and 808. In this example, compressive pressure and / or a thermal annealing process may be applied to achieve a high-strength dielectric-to-dielectric bond (e.g., SiCN-SiCN fusion bonding) between the dummy silicon wafer 804 and the plurality of stacked semiconductor dies 602.

[0035] Fig.9AA simplified schematic semiconductor device manufacturing stage 900a according to an embodiment of the present technology is illustrated. As shown, the carrier wafer 606 from stage 800a can be removed from the semiconductor device using a backside polishing or wafer grinding process. In addition, a semiconductor device assembly including a dummy wafer 804, a plurality of stacked semiconductor dies 602, and a logic wafer 604 can be assembled onto a package-level substrate 904 (e.g., a printed circuit board (PCB), a semiconductor substrate, etc.). Here, one or more of the plurality of stacked semiconductor dies 602 can be singulated through the dummy wafer 804, the dielectric material 706, and the logic die 604. The dielectric material 706 can surround the one or more plurality of singulated stacked semiconductor dies for power isolation. In this example, the dummy silicon die 804 can be bonded to a plurality of corresponding stacked semiconductor dies by a dielectric layer 908, which is formed at stage 800a by fusion bonding the dielectric layers 706 and 802. The dielectric layer 908 can have a thickness in the range from 100 nm to 1 μm. Here, the dielectric layer 908 disposed between the stacked semiconductor die 602 and the dummy die 804 may be much thinner than Figure 1 and used in conventional semiconductor device assemblies. Fig.9A The semiconductor device shown in the invention can provide enhanced heat conduction performance.

[0036] like Fig.9A , the substrate 904 may further include package-level contact pads that provide external connectivity (e.g., via solder balls 902) to the plurality of stacked semiconductor dies 602 and corresponding logic dies 604 (e.g., power, ground, and I / O signals) through traces, lines, vias, and other electrical connection structures in the substrate 904 that electrically connect the package-level contact pads to contact pads at the upper surface of the substrate 904. The semiconductor device may further include an encapsulant material 906 (e.g., a molding resin compound or the like) that at least partially encapsulates the dummy wafer die 804, the semiconductor die stack 602, the corresponding logic die 604, and the substrate 904 to prevent electrical contact therewith and to provide mechanical strength and protection to the semiconductor device.

[0037] Next turn Fig. 9B, at stage 900b, the stacked semiconductor die can be assembled in a semiconductor device. In aspect, the carrier wafer 606 can be removed from the front side of the logic wafer 604. In addition, a semiconductor device assembly including a dummy wafer 804, one or more stacked semiconductor dies 602, a pad layer 708, and a logic wafer 604 can be assembled onto a package-level substrate 904 (e.g., a printed circuit board (PCB), a semiconductor substrate, etc.). In this example, the dummy silicon die 804 can be bonded to a plurality of corresponding stacked semiconductor dies via a dielectric layer 910, which is formed at stage 800b by melt bonding dielectric layers 806 and 808. The dielectric layer 910 can have a thickness in the range from 100nm to 1μm. Here, the dielectric layer 910 disposed between the stacked semiconductor die 602 and the dummy die 804 can be much thinner than the NCF layer included in a conventional semiconductor device assembly. Therefore, Fig. 9B The semiconductor device shown in can exhibit enhanced thermal conductivity performance.

[0038] At stage 900b, one or more of the plurality of stacked semiconductor dies 602 may be singulated through the dummy wafer 804, the dielectric material 706, the liner layer 708, and the logic die 604. The dielectric material 706 may surround the liner layer 708 disposed on the sidewalls of the one or more plurality of singulated stacked semiconductor dies for power isolation. In this example, the substrate 904 may further include package-level contact pads that provide external connectivity (e.g., via solder balls 902) to the plurality of stacked semiconductor dies 602 and corresponding logic dies 604. In addition, the semiconductor device may further include an encapsulant material 906 that encapsulates the dummy wafer die 804, the semiconductor die stack 602, the corresponding logic die 604, and the substrate 904 to prevent electrical contact therewith and provide mechanical strength and protection to the semiconductor device.

[0039] Steering Fig.10 , Fig.10 1 is a flow chart of a method 1000 of processing a semiconductor memory device according to an embodiment of the present technology. The method 1000 includes providing a wafer of logic dies at 1002. For example, a wafer 604 of logic dies may be provided for a semiconductor device assembly. In particular, the logic dies included in the wafer 604 may be cut to produce a single semiconductor die stack for HBM device applications, or to produce a semiconductor die having a plurality of other semiconductor die stacks coupled thereto at various lateral locations.

[0040] In addition, method 1000 includes providing a memory wafer having a first plurality of stacked memory dies and a second plurality of stacked memory dies at 1004. For example, a plurality of stacked semiconductor dies 602 may be provided for a semiconductor device assembly. Each of the plurality of stacked semiconductor dies may be coupled to an adjacent semiconductor die by interconnects and contact pads for electrical connection. In addition, each plurality of stacked semiconductor dies may include two or more semiconductor dies vertically coupled in a corresponding stack.

[0041] The method 1000 also includes coupling the first plurality of stacked memory dies and the second plurality of stacked memory dies to the wafer of logic dies at 1006. For example, the plurality of stacked semiconductor dies 602 can be electrically coupled to the wafer of semiconductor dies 604 at respective semiconductor dies or at the same semiconductor die (e.g., at different lateral locations) using chip-wafer bonding techniques, such as Figure 6 As shown in .

[0042] In addition, method 1000 includes depositing a first dielectric material at the wafer of logic die at 1008, the first dielectric material being disposed between the first plurality of stacked memory die and the second plurality of stacked memory die, and the first dielectric material having a thickness similar to the height of the first plurality of stacked memory die or the second plurality of stacked memory die. For example, dielectric material 706 may be deposited between the plurality of stacked semiconductor die 602. Dielectric material 706 may be disposed above the backside surfaces of the plurality of stacked semiconductor die 602 and around the sidewalls of the plurality of stacked semiconductor die 602. Dielectric material 706 may have a thickness similar to the height of the plurality of stacked semiconductor die 602. Dielectric material 706 may also be disposed above logic wafer 604, such as Fig. 7A In some other examples, the liner 708 can be conformally coated over the plurality of stacked semiconductor dies 602 and on the logic die 604. Figure 7B As shown in , dielectric material 706 may be further deposited over liner layer 708 .

[0043] The method 1000 also includes polishing the first dielectric material disposed over the backside surfaces of the first plurality of stacked memory dies and the second plurality of stacked memory dies at 1010. For example, a CMP process may be utilized to planarize the dielectric material 706 disposed over the backside surfaces of the plurality of stacked semiconductor dies 602. Fig. 7A As shown in FIG. 7 , a planar dielectric layer 706 having a thickness in a range from 10 nm to 1 μm can be formed. Figure 7B, the dielectric material 706 can be polished until the underlying dielectric liner layer 708 is exposed. Here, the liner layer 708 disposed over the backside surfaces of the plurality of stacked semiconductor dies 602 can act as a polish stop layer and be coplanar with the polished dielectric material 706.

[0044] In addition, method 1000 includes coupling a dummy wafer to the first plurality of stacked memory dies and the second plurality of stacked memory dies at 1012. For example, dummy silicon wafer 804 may be coupled to plurality of stacked semiconductor dies 602 by fusion bonding between dielectric layer 802 and planar layer 706, as shown in FIG. Fig. 8A . In another example, dielectric layers 806 and 808 may be deposited over the exposed liner layer 708 and the backside surface of the dummy silicon wafer 804, respectively. Furthermore, the dummy silicon wafer 804 may be coupled to the plurality of stacked semiconductor dies 602 by fusion bonding (e.g., SiCN-SiCN fusion bonding) between the dielectric layers 806 and 808.

[0045] The method 1000 also includes cutting through the wafer of the dummy wafer, the first dielectric material, and the logic die at 1014. For example, the one or more plurality of stacked semiconductor dies 602 may be singulated by a wafer dicing process, such as cutting through the dummy silicon wafer 804, the dielectric layer 706, and the logic wafer 604. Additionally, the carrier wafer 606 may be removed by a wafer grinding or polishing process. The one or more plurality of singulated stacked semiconductor dies 602 may be assembled onto a package-level substrate 904, which provides external connectivity via solder balls 902.

[0046] Finally, method 1000 includes encapsulating the semiconductor device using a molding compound material at 1016. For example, encapsulant material 906 may be applied to at least partially encapsulate dummy wafer die 804, one or more plurality of stacked semiconductor dies 602, corresponding logic die 604, and substrate 904 so as to prevent electrical contact therewith and provide mechanical strength and protection to the semiconductor device in the present disclosure.

[0047] Although in the foregoing example embodiments, the semiconductor device assembly has been illustrated and described as including a specific configuration of semiconductor dies, in other embodiments, the assembly may have a different configuration of semiconductor dies. For example, after appropriate modification, the semiconductor device assembly illustrated in any of the foregoing examples may be implemented using, for example, a vertical stack of semiconductor dies, multiple semiconductor dies, or a single semiconductor die.

[0048] According to one aspect of the present disclosure, Figures 1 to 10The semiconductor device illustrated in the assembly of may be a memory die, such as a dynamic random access memory (DRAM) die, a NAND memory die, a NOR memory die, a magnetic random access memory (MRAM) die, a phase change memory (PCM) die, a ferroelectric random access memory (FeRAM) die, a static random access memory (SRAM) die, or the like. In embodiments where multiple dies are provided in a single assembly, the semiconductor device may include the same kind of memory dies (e.g., all NAND, all DRAM, etc.) or different kinds of memory dies (e.g., one DRAM and one NAND, etc.). According to another aspect of the present disclosure, the semiconductor die of the assembly illustrated and described above may be a logic die (e.g., a controller die, a processor die, etc.) or a mix of logic dies and memory dies (e.g., a memory controller die and a memory die controlled by it).

[0049] References Figures 1 to 10 Any of the described semiconductor devices and semiconductor device assemblies may be incorporated into any of a larger and / or more complex system, a representative example of which is Fig.11 The system 1100 is schematically shown in FIG. Figures 1 to 10 The stack of semiconductor dies provided in the system 1100 may communicate with one or more devices within the system 1100 using one or more standard protocols. For example, the stacked semiconductor dies may communicate using the HBM protocol. Alternatively, the stacked semiconductor dies may communicate using a suitable protocol. The system 1100 may include a semiconductor device 1110 (e.g., a discrete semiconductor device), a power supply 1120, a driver 1130, a processor 1140, and / or other subsystems or components 1150. The semiconductor device 1110 may include the semiconductor device 1110 described above with reference to Figures 1 to 10 The features of the semiconductor device assembly described are generally similar features. The resulting system 1100 can perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, the representative system 1100 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of the system 1100 may be housed in a single unit or distributed over multiple interconnected units (e.g., via a communication network). The components of the system 1100 may also include any of a variety of computer-readable media and remote devices.

[0050] Specific details of several embodiments of semiconductor devices and associated systems and methods are described above. Depending on the context in which it is used, the term "substrate" may refer to a wafer-level substrate or a singulated die-level substrate. In addition, unless the context indicates otherwise, conventional semiconductor manufacturing techniques may be used to form the structures disclosed herein. For example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques may be used to deposit materials. Similarly, materials may be removed, for example, using plasma etching, wet etching, CMP, or other suitable techniques.

[0051] The technology disclosed herein relates to semiconductor devices, systems having semiconductor devices, and related methods for manufacturing semiconductor devices. The term "semiconductor device" generally refers to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. In addition, the term "semiconductor device" may refer to a finished device or an assembly or other structure at various processing stages before becoming a finished device. Depending on the context in which it is used, the term "substrate" may refer to a structure that supports an electronic component (e.g., a die), such as a PCB or wafer-level substrate, a die-level substrate, or another die for die stacking or 3DI applications.

[0052] The devices discussed herein, including memory devices, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation or any other doping means during the initial formation or growth of the substrate.

[0053] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the present disclosure and the appended claims. Features implementing the functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0054] As used herein (including in the claims), "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

[0055] As used herein, the terms "vertical," "lateral," "up," "down," "above," and "below" may refer to the relative direction or positioning of features in a semiconductor device in view of the orientation shown in the figure. For example, "upper" or "topmost" may refer to a feature that is closer to the top of the page than another feature. However, these terms should be broadly interpreted to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, over / under, over / under, up / down, and left / right may be interchanged depending on the orientation.

[0056] It will be appreciated from the foregoing that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present invention. On the contrary, in the foregoing description, numerous specific details are discussed to provide a comprehensive and feasible description of embodiments of the present technology. However, those skilled in the relevant art will recognize that the present disclosure may be implemented without one or more of the specific details. In other examples, well-known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid obscuring other aspects of the present technology. In general, it should be understood that various other devices, systems and methods other than those specific embodiments disclosed herein may also be within the scope of the present technology.

Claims

1. A semiconductor device, include: Logic die; a first plurality of stacked memory dies electrically coupled to the logic die at a first location above a backside surface of the logic die; a second plurality of stacked memory die electrically coupled to the logic die at a second location above the backside surface of the logic die; a first dielectric material disposed over the backside surface of the logic die and between the first plurality of stacked memory dies and the second plurality of stacked memory dies, the first dielectric material having a thickness similar to a height of the first plurality of stacked memory dies or the second plurality of stacked memory dies; and A dummy die is disposed over the first dielectric material and coupled to the first plurality of stacked memory die and the second plurality of stacked memory die, wherein the dummy die is coupled to backside surfaces of the first plurality of stacked memory die and the second plurality of stacked memory die through a second dielectric layer having a dielectric-to-dielectric fusion bond. 2 . The semiconductor device of claim 1 , wherein the first dielectric material is silicon oxide, and the second dielectric layer is made of silicon oxide. 3 . The semiconductor device according to claim 1 , wherein the second dielectric layer is made of a material different from the first dielectric material. 4 . The semiconductor device according to claim 3 , wherein the first dielectric material is silicon oxide, and the second dielectric layer is made of a material including silicon nitride and / or silicon carbonitride.

5. The semiconductor device of claim 1, further comprising a third dielectric layer disposed on sidewalls and backside surfaces of the first plurality of stacked memory dies and the second plurality of stacked memory dies, wherein the third dielectric layer is made of silicon nitride. 6 . The semiconductor device according to claim 1 , wherein the second position is spaced apart from the first position by a distance, and the distance is in a range from 10 μm to 10 mm.

7. The semiconductor device of claim 1 , wherein each of the first plurality of stacked memory dies and the second plurality of stacked memory dies comprises a top memory die and a plurality of core memory dies, the top memory die being disposed above the plurality of core memory dies, and the top memory die being thicker than each of the plurality of core memory dies.

8. The semiconductor device of claim 7 , wherein each of the first plurality of stacked memory dies and the second plurality of stacked memory dies includes an interconnect coupling the top memory die and the plurality of core memory dies, and the interconnect is electrically coupled between contact pads of the top memory die and an adjacent memory die of the plurality of core memory dies.

9. The semiconductor device of claim 1, wherein the first dielectric material is further disposed in an edge region of the semiconductor device, and the first dielectric material surrounds outer sidewalls of the first and second plurality of stacked memory dies that face the edge region of the semiconductor device.

10. The semiconductor device of claim 1, further comprising an encapsulant material disposed over a backside surface and sidewalls of the dummy die, the encapsulant material extending horizontally to surround sidewalls of the first and second plurality of stacked memory dies and sidewalls of the logic die.

11. A semiconductor device, include: Logic die; a plurality of stacked memory dies electrically coupled to the logic die; a first dielectric material disposed around the plurality of stacked memory dies, the first dielectric material having a thickness similar to a height of the plurality of stacked memory dies; and A dummy die is disposed over the plurality of stacked memory dies, the dummy die being coupled to backside surfaces of the plurality of stacked memory dies through a second dielectric layer having a dielectric-to-dielectric bond. 12 . The semiconductor device of claim 11 , wherein the first dielectric material and the second dielectric layer are made of the same dielectric material including silicon oxide. 13 . The semiconductor device of claim 11 , wherein the first dielectric material is silicon oxide, and the second dielectric layer is made of a material including silicon nitride and / or silicon carbonitride.

14. The semiconductor device of claim 11, further comprising a third dielectric layer disposed on sidewalls and backside surfaces of the plurality of stacked memory dies, wherein the third dielectric layer is made of a material including silicon nitride. 15 . The semiconductor device of claim 11 , further comprising an encapsulant material disposed over a backside surface and sidewalls of the dummy die, the encapsulant material extending horizontally to surround sidewalls of the plurality of stacked memory dies and sidewalls of the logic die.

16. A method for manufacturing a semiconductor device, wherein include: Wafers that provide logic dies; providing a memory wafer having a first plurality of stacked memory dies and a second plurality of stacked memory dies; coupling the first plurality of stacked memory dies and the second plurality of stacked memory dies to the wafer of logic dies; depositing a first dielectric material at the wafer of the logic die, the first dielectric material disposed between the first plurality of stacked memory dies and the second plurality of stacked memory dies, and the first dielectric material having a thickness similar to a height of the first plurality of stacked memory dies or the second plurality of stacked memory dies; polishing the first dielectric material disposed over backside surfaces of the first plurality of stacked memory dies and the second plurality of stacked memory dies; coupling a dummy wafer to the first plurality of stacked memory dies and the second plurality of stacked memory dies; cutting through the dummy wafer, the first dielectric material, and the wafer of the logic die; and The semiconductor device is encapsulated using a molding compound material.

17. The method of claim 16 further comprises depositing a second dielectric layer on a backside surface of the dummy wafer prior to coupling the dummy wafer, wherein coupling the dummy wafer to the first plurality of stacked memory dies and the second plurality of stacked memory dies comprises forming a dielectric-to-dielectric fusion bond between the first dielectric material and the second dielectric layer.

18. The method of claim 17, wherein the first dielectric material and the second dielectric layer are made of the same dielectric material including silicon oxide.

19. The method of claim 17, further comprising depositing a third dielectric layer over the first dielectric material and the first and second plurality of stacked memory dies after polishing the first dielectric material, the third and second dielectric layers being made of the same second dielectric material that is different from the first dielectric material, The first dielectric material comprises silicon oxide, the second dielectric layer is made of a material comprising silicon nitride and / or silicon carbonitride, and Wherein coupling the dummy wafer to the first plurality of stacked memory die and the second plurality of stacked memory die includes forming a dielectric-dielectric fusion bond between the third dielectric layer and the second dielectric layer.

20. The method of claim 19, further comprising depositing a fourth dielectric layer on the sidewalls and backside surfaces of the first plurality of stacked memory dies and the second plurality of stacked memory dies before depositing the first dielectric material, wherein the fourth dielectric layer is made of a material comprising silicon nitride and the first dielectric material is disposed above the fourth dielectric layer.

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