Capacitor device and method of forming the same

Abstract

A capacitor device and a method of forming the same, wherein the structure comprises: a plurality of first electrode layers arranged in a stack, a second electrode layer between any two adjacent first electrode layers, and a first dielectric layer between any two adjacent first electrode layer and second electrode layer, each upper first electrode layer is on a first sidewall and a part of a top surface of a lower second electrode layer, a first included angle is between the first sidewall of the second electrode layer and the top surface of the second electrode layer, the first included angle is an obtuse angle, each upper second electrode layer is on a second sidewall and a part of a top surface of a lower first electrode layer, a second included angle is between the second sidewall of the first electrode layer and the top surface of the first electrode layer, the second included angle is an obtuse angle; a first conductive plug on a first region, the first conductive plug connects each first electrode layer; a second conductive plug on a third region, the second conductive plug connects each second electrode layer, which is conducive to improving the reliability of the capacitor.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a capacitor device and a forming method thereof. BACKGROUND

[0002] In a semiconductor integrated circuit, integrated capacitors fabricated on the same chip as transistor circuits are widely used. The forms mainly include metal-insulator-metal (MIM) capacitors and metal-oxide-metal (MOM) capacitors.

[0003] Among them, the MIM capacitor uses the upper and lower metal as the capacitor electrode plate. For the traditional MIM capacitor, there is only a single dielectric layer between the capacitor electrode plates, and the equivalent capacitance density is limited by the thickness of the dielectric layer and the dielectric constant of the dielectric layer. Therefore, a multi-layer electrode plate capacitor structure is introduced to obtain a higher equivalent capacitance density.

[0004] However, the performance of the multi-layer electrode plate capacitor structure still needs to be further improved. SUMMARY

[0005] The technical problem solved by the present application is to provide a capacitor device and a forming method thereof to improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical scheme of the present application provides a capacitor device, comprising: a substrate, the substrate comprising a first region, a second region and a third region arranged along a first direction, the second region being located between the first region and the third region; a metal layer structure located on the substrate, the metal layer structure comprising a plurality of first electrode layers stacked, a second electrode layer located between any two adjacent first electrode layers, and a first dielectric layer located between any adjacent first electrode layer and second electrode layer, each first electrode layer being located on the second region and extending to the first region, each second electrode layer being located on the second region and extending to the third region, each upper first electrode layer being located on the first side wall and part of the top surface of the lower second electrode layer, the first side wall of the second electrode layer and the top surface of the second electrode layer having a first included angle, the first included angle being an obtuse angle, each upper second electrode layer being located on the second side wall and part of the top surface of the lower first electrode layer, the second side wall of the first electrode layer and the top surface of the first electrode layer having a second included angle, the second included angle being an obtuse angle; a first conductive plug located on the first region, the first conductive plug connecting each first electrode layer; a second conductive plug located on the third region, the second conductive plug connecting each second electrode layer.

[0007] Optionally, the first included angle ranges from 100 degrees to 130 degrees; the second included angle ranges from 100 degrees to 130 degrees.

[0008] Optionally, the capacitor further comprises: a first lower metal layer in the first region and a second lower metal layer in the third region in the substrate; a second dielectric layer on the surface of the metal layer structure; a first upper metal layer and a second upper metal layer on the second dielectric layer and separated from each other; the first conductive plug further connects the first lower metal layer and the first upper metal layer; and the second conductive plug further connects the second lower metal layer and the second upper metal layer.

[0009] Optionally, the number of layers of the metal layer structure is odd, and the first electrode layer is located at the lowermost layer; the capacitor further comprises: a dummy electrode layer on the second electrode layer at the uppermost layer in the third region, and the dummy electrode layer is separated from the first electrode layer; the number of layers of the metal layer structure is odd, and the second electrode layer is located at the lowermost layer; the capacitor further comprises: a dummy electrode layer on the first electrode layer at the uppermost layer in the first region, and the dummy electrode layer is separated from the second electrode layer.

[0010] Optionally, the material of the first electrode layer comprises one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; and the material of the second electrode layer comprises one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0011] Optionally, the material of the first dielectric layer comprises one or more of HfO, AlO, ZrO and LaO.

[0012] Optionally, the thickness of the first electrode layer ranges from 300 angstroms to 800 angstroms; and the thickness of the second electrode layer ranges from 300 angstroms to 800 angstroms.

[0013] Correspondingly, the technical scheme of the application also provides a forming method of a capacitor device, comprising: providing a substrate, the substrate comprising a first region, a second region and a third region arranged along a first direction, the second region being located between the first region and the third region; forming a metal layer structure on the substrate, the metal layer structure comprising a plurality of first electrode layers arranged in a stack, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between the adjacent first electrode layer and the second electrode layer, each first electrode layer being located on the second region and extending to the first region, each second electrode layer being located on the second region and extending to the third region, each upper first electrode layer being located on a first side wall and a part of a top surface of a lower second electrode layer, a first included angle being formed between the first side wall of the second electrode layer and the top surface of the second electrode layer, the first included angle being an obtuse angle, each upper second electrode layer being located on a second side wall and a part of a top surface of a lower first electrode layer, a second included angle being formed between the second side wall of the first electrode layer and the top surface of the first electrode layer, the second included angle being an obtuse angle; after the metal layer structure is formed, a first conductive plug connecting the first electrode layers and a second conductive plug connecting the second electrode layers are formed, the first conductive plug being located on the first region, and the second conductive plug being located on the third region.

[0014] Optionally, the forming method of the adjacent first electrode layer and the second electrode layer comprises: forming a first electrode material layer on the substrate, or forming a first dielectric layer and a first electrode material layer located on the first dielectric layer on the upper second electrode layer; patterning the first electrode material layer to form the first electrode layer; forming a first dielectric layer and a second electrode material layer located on the first dielectric layer on the first electrode layer; and patterning the second electrode material layer to form the second electrode layer.

[0015] Optionally, the patterning process of the first electrode material layer comprises a dry etching process.

[0016] Optionally, the patterning process of the second electrode material layer comprises a dry etching process.

[0017] Optionally, the forming process of the first electrode material layer comprises a physical vapor deposition process; and the forming process of the second electrode material layer comprises a physical vapor deposition process.

[0018] Optionally, the substrate has a first lower metal layer located in the first region and a second lower metal layer located in the third region; the first conductive plug also connects the first lower metal layer; and the second conductive plug also connects the second lower metal.

[0019] Optionally, the method for forming the first conductive plug and the second conductive plug comprises: forming a second dielectric layer on the surface of the metal layer structure; forming a first contact hole in the first region and in the metal layer structure and the second dielectric layer above the first region, the bottom of the first contact hole exposing the first lower metal layer; forming a second contact hole in the third region and in the metal layer structure and the second dielectric layer above the third region, the bottom of the second contact hole exposing the second lower metal layer; forming the first conductive plug in the first contact hole; and forming the second conductive plug in the second contact hole.

[0020] Optionally, after the second dielectric layer is formed, a first upper metal layer and a second upper metal layer are formed, the first conductive plug is further connected to the first upper metal layer, and the second conductive plug is further connected to the second upper metal layer.

[0021] Optionally, the method for forming the first conductive plug, the second conductive plug, the first upper metal layer and the second upper metal layer further comprises: after the first contact hole and the second contact hole are formed, forming a conductive material layer on the surface of the second dielectric layer and in the first contact hole and the second contact hole; and etching the conductive material layer until the surface of the second dielectric layer is exposed, thereby forming the first conductive plug and the first upper metal layer on the first conductive plug, and forming the second conductive plug and the second upper metal layer on the second conductive plug.

[0022] Optionally, the number of layers of the metal layer structure is odd, and the first electrode layer is located at the lowermost layer, and the method further comprises: when the first electrode layer at the uppermost layer is formed, a dummy electrode layer is further formed on the second electrode layer at the uppermost layer above the third region, and the dummy electrode layer is separate from the first electrode layer; or the number of layers of the metal layer structure is odd, and the second electrode layer is located at the lowermost layer, and the method further comprises: when the second electrode layer at the uppermost layer is formed, a dummy electrode layer is further formed on the first electrode layer at the uppermost layer above the first region, and the dummy electrode layer is separate from the second electrode layer.

[0023] Optionally, the first included angle ranges from 100 degrees to 130 degrees; and the second included angle ranges from 100 degrees to 130 degrees.

[0024] Compared with the prior art, the technical scheme of the embodiment of the application has the following beneficial effects:

[0025] In the capacitor device provided by the technical scheme, the first electrode layer of each upper layer is located on the first side wall and part of the top surface of the second electrode layer of the lower layer, the first side wall of the second electrode layer and the top surface of the second electrode layer have a first included angle, the first included angle is obtuse, and the first included angle is large, so that the sharpness of the corner of the second electrode layer adjacent to the first electrode layer is reduced, which is beneficial to reducing the electric field strength between the corner of the second electrode layer and the first electrode layer, thereby improving the reliability of the capacitor; similarly, the included angle between the second side wall of the first electrode layer and the top surface of the first electrode layer is also obtuse, which is also beneficial to improving the reliability of the capacitor.

[0026] The method for forming the capacitor device provided by the technical scheme has a first included angle between the first sidewall of the second electrode layer and the top surface of the second electrode layer, the first included angle is an obtuse angle, and the first included angle is relatively large, so that the sharpness of the corner of the second electrode layer adjacent to the first electrode layer is reduced, the electric field intensity between the corner of the second electrode layer and the first electrode layer is reduced, and the reliability of the capacitor is improved; similarly, the included angle between the second sidewall of the first electrode layer and the top surface of the first electrode layer is an obtuse angle, which is also conducive to improving the reliability of the capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 FIG. 1 is a structural schematic diagram of a capacitor device.

[0028] Figures 2 to 4 FIG. 1 is a structural schematic diagram of a capacitor device. DETAILED DESCRIPTION

[0029] It should be noted that the "surface", "upper", in the specification, are used to describe the relative position relationship in space, and are not limited to whether they are in direct contact.

[0030] As the background, the performance of the capacitor device formed in the prior art needs to be improved. Now, a capacitor device will be described and analyzed.

[0031] Figure 1 FIG. 1 is a structural schematic diagram of a capacitor device.

[0032] Please refer to Figure 1The capacitor device comprises a substrate 100, the substrate 100 comprises a first region I, a second region II and a third region III arranged along a first direction X, the second region II is located between the first region I and the third region II, the first region I has a first lower metal layer 101, and the third region III has a second lower metal layer 102; a plurality of first electrode structures and a plurality of second electrode structures are arranged on the substrate 100 in a stack, the first electrode structure comprises a first lead-out end 103 located on the first region I and a first electrode layer 104 located on the second region II, the second electrode structure comprises a second lead-out end 105 located on the third region III and a second electrode layer 106 located on the second region II, and each first electrode layer 104 on the second region II is located between adjacent second electrode layers 106; a first dielectric layer 107 is located between adjacent first electrode layers 104 and second electrode layers 106; a dummy electrode layer 108 is located on the plurality of first electrode structures on the first region I; a second dielectric layer 109 is located on the surfaces of the first electrode structure and the second electrode structure; a first upper metal layer 110 and a second upper metal layer 111 are located on the second dielectric layer 109 and separated from each other; a first conductive plug 112 is located in the second dielectric layer 109, and the first conductive plug 112 connects the first lower metal layer 101, the first upper metal layer 110 and each first lead-out end 103; a second conductive plug 113 is located in the second dielectric layer 109, and the second conductive plug 113 connects the second lower metal layer 102, the second upper metal layer 111 and each second lead-out end 105.

[0033] In the above-mentioned MIM capacitor device, each adjacent first electrode layer 104, second electrode layer 106 and first dielectric layer 107 therebetween form a single capacitor, the first lead-out end 103 is used to electrically lead out the first electrode layer 104, and the second lead-out end 105 is used to electrically lead out the second electrode layer 106, thereby forming a plurality of parallel capacitors to obtain a larger equivalent capacitance density. However, since the first lead-out end 103 is located on the side wall of the adjacent second electrode layer 106, the side wall of the second electrode layer 106 adjacent to the first lead-out end 103 and the top portion thereof have an approximately right-angled corner A, which causes a local larger electric field area between the first electrode structure and the second electrode structure, thereby affecting the reliability of the capacitor. Similarly, the approximately right-angled corner of the first electrode layer 104 adjacent to the second lead-out end 105 also reduces the reliability of the capacitor.

[0034] To solve the above problems, the application provides a capacitor device and a forming method thereof, each upper first electrode layer is located on the first side wall and part of the top surface of the lower second electrode layer, the first side wall of the second electrode layer and the top surface of the second electrode layer have a first included angle, the first included angle is an obtuse angle, and the first included angle is large, so that the sharpness of the corner of the second electrode layer adjacent to the first electrode layer is reduced, which is beneficial to reducing the electric field intensity between the corner of the second electrode layer and the first electrode layer, thereby improving the reliability of the capacitor; similarly, the included angle between the second side wall of the first electrode layer and the top surface of the first electrode layer is an obtuse angle, which is also beneficial to improving the reliability of the capacitor.

[0035] In order to make the above-mentioned purposes, features and advantages of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the drawings.

[0036] Figures 2 to 4 is the structure diagram corresponding to each step in the forming method of the capacitor device of the embodiment of the application.

[0037] Please refer to Figure 4 , a substrate 200 is provided, the substrate 200 includes a first region I, a second region II and a third region III arranged along a first direction Y, the second region II is located between the first region I and the third region III.

[0038] In the embodiment, the substrate 200 has a first lower metal layer 201 located in the first region I and a second lower metal layer 202 located in the third region III.

[0039] In the embodiment, the substrate 200 further includes a substrate (not shown in the figure), a device layer (not shown in the figure) located on the substrate, and a metal interconnection layer located on the device layer, the metal interconnection layer includes a third dielectric layer (not shown in the figure), the first lower metal layer 201 and the second lower metal layer 202 located in the third dielectric layer, and the metal interconnection layer and the device layer are electrically connected.

[0040] Please refer to Figure 3A metal layer structure is formed on the substrate 200, which includes a plurality of first electrode layers 203, a plurality of second electrode layers 204 located between two adjacent first electrode layers, and a plurality of first dielectric layers 205 between adjacent first electrode layers 203 and second electrode layers 204. Each first electrode layer 203 extends to the first region I from the second region II. Each second electrode layer 204 extends to the third region III from the second region II. The first sidewall 204a of the second electrode layer 204 and the top surface of the second electrode layer 204 form a first included angle α, which is an obtuse angle. The second sidewall 203a of the first electrode layer 203 and the top surface of the first electrode layer 203 form a second included angle β, which is an obtuse angle.

[0041] The first included angle α between the first sidewall 204a of the second electrode layer 204 and the top surface of the second electrode layer 204 is an obtuse angle, which is large, so that the sharpness of the corner of the second electrode layer 204 adjacent to the first electrode layer 203 is reduced, which is beneficial to reduce the electric field intensity between the corner of the second electrode layer 204 and the first electrode layer 203, thereby improving the reliability of the capacitor. Similarly, the second included angle β between the second sidewall 203a of the first electrode layer 203 and the top surface of the first electrode layer 203 is an obtuse angle, which is also beneficial to improve the reliability of the capacitor.

[0042] In this embodiment, the first included angle α ranges from 100 degrees to 130 degrees, and the second included angle β ranges from 100 degrees to 130 degrees.

[0043] In this embodiment, the method for forming the adjacent first electrode layer 203 and second electrode layer 204 includes: forming a first electrode material layer (not shown in the figure) on the substrate 200, or forming a first dielectric layer 205 and a first electrode material layer (not shown in the figure) on the first dielectric layer 205 on the upper second electrode layer 204; patterning the first electrode material layer to form the first electrode layer 203; forming a first dielectric layer and a second electrode material layer (not shown in the figure) on the first electrode layer 203; and patterning the second electrode material layer to form the second electrode layer 204.

[0044] In this embodiment, the process of patterning the first electrode material layer includes a dry etching process.

[0045] In this embodiment, the process of patterning the second electrode material layer includes a dry etching process.

[0046] In the embodiment, the forming process of the first electrode material layer includes a physical vapor deposition process; and the forming process of the second electrode material layer includes a physical vapor deposition process.

[0047] In the embodiment, the material of the first electrode layer 203 includes a combination of one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; and the material of the second electrode layer 204 includes a combination of one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0048] In the embodiment, the material of the first dielectric layer 205 includes a combination of one or more of HfO, AlO, ZrO and LaO.

[0049] It should be noted that each first electrode layer 203 and the adjacent second electrode layer 204 and the first dielectric layer 205 therebetween form a single capacitor device, the metal layer structure includes a plurality of parallel capacitor devices, and the material of the first dielectric layer 205 in each capacitor device can be the same or different.

[0050] In the embodiment, the thickness of the first electrode layer 203 ranges from 300 angstroms to 800 angstroms; and the thickness of the second electrode layer 204 ranges from 300 angstroms to 800 angstroms.

[0051] In the embodiment, the number of layers of the metal layer structure is odd and the first electrode layer 203 is located at the lowermost layer, and the method further includes: when the first electrode layer 203 at the uppermost layer is formed, a dummy electrode layer 211 is also formed on the second electrode layer 204 at the uppermost layer on the third region III, and the dummy electrode layer 211 is separate from the first electrode layer 203. The dummy electrode layer 211 is used to balance the thickness of the metal layer structure on the first region I and the third region III when the first contact hole and the second contact hole are formed, and to reduce the etching difference in forming the first contact hole and the second contact hole.

[0052] In another embodiment, the number of layers of the metal layer structure is odd and the second electrode layer is located at the lowermost layer, and the method further includes: when the second electrode layer at the uppermost layer is formed, a dummy electrode layer is also formed on the first electrode layer at the uppermost layer on the first region, and the dummy electrode layer is separate from the second electrode layer.

[0053] In other embodiments, the number of layers of the metal layer structure is even, i.e., the thickness of the metal layer structure on the first region and the thickness of the metal layer structure on the third region are consistent, and no dummy electrode layer is provided.

[0054] For reference Figure 4After the metal layer structure is formed, the first conductive plug 206 connecting the first electrode layers 203 and the second conductive plug 207 connecting the second electrode layers 204 are formed, the first conductive plug 206 is located on the first region I, and the second conductive plug 207 is located on the third region III.

[0055] In this embodiment, the first conductive plug 206 also connects the first lower metal layer 201, and the second conductive plug 207 also connects the second lower metal layer 202.

[0056] In this embodiment, the forming method of the first conductive plug 206 and the second conductive plug 207 includes: forming the second dielectric layer 208 on the surface of the metal layer structure; forming the first contact hole (not shown in the figure) in the first region I and in the metal layer structure and the second dielectric layer 208 on the first region I, the bottom of the first contact hole exposing the first lower metal layer 201; forming the second contact hole (not shown in the figure) in the third region III and in the metal layer structure and the second dielectric layer 208 on the third region III, the bottom of the second contact hole exposing the second lower metal layer 202; forming the first conductive plug 206 in the first contact hole; and forming the second conductive plug 207 in the second contact hole.

[0057] In this embodiment, after the second dielectric layer 208 is formed, the first upper metal layer 209 and the second upper metal layer 210 are formed separately, the first conductive plug 206 also connects the first upper metal layer 209, and the second conductive plug 207 also connects the second upper metal layer 210.

[0058] In this embodiment, the forming method of the first conductive plug 206, the second conductive plug 207, the first upper metal layer 209 and the second upper metal layer 210 further includes: after the first contact hole and the second contact hole are formed, forming the conductive material layer (not shown in the figure) in the second dielectric layer 208, the first contact hole and the second contact hole; etching the conductive material layer until the surface of the second dielectric layer 208 is exposed, forming the first conductive plug 206 and the first upper metal layer 209 on the first conductive plug 206, and forming the second conductive plug 207 and the second upper metal layer 210 on the second conductive plug 207.

[0059] Correspondingly, the embodiment of the present application also provides a capacitor device formed by the above method, please continue to refer to Figure 4The capacitor device comprises a substrate 200, the substrate 200 comprising a first region I, a second region II and a third region III arranged along a first direction Y, the second region II being located between the first region I and the third region III; a metal layer structure located on the substrate 200, the metal layer structure comprising a plurality of first electrode layers 203 arranged in a stack, a second electrode layer 204 located between any two adjacent first electrode layers 203, and a first dielectric layer 205 between any adjacent first electrode layer 203 and second electrode layer 204, each first electrode layer 203 being located on the second region II and extending to the first region I, each second electrode layer 204 being located on the second region II and extending to the third region III, each upper first electrode layer 203 being located on a first side wall 204a and part of a top surface of a lower second electrode layer 204, the first side wall 204a of the second electrode layer 204 and the top surface of the second electrode layer 204 having a first included angle a, the first included angle a being an obtuse angle, each upper second electrode layer 204 being located on a second side wall 203a and part of a top surface of a lower first electrode layer 203, the second side wall 203a of the first electrode layer 203 and the top surface of the first electrode layer 203 having a second included angle β, the second included angle β being an obtuse angle; a first conductive plug 206 located on the first region I, the first conductive plug 206 connecting each first electrode layer 203; a second conductive plug 207 located on the third region III, the second conductive plug 207 connecting each second electrode layer 204.

[0060] At this point, the first side wall 204a of the second electrode layer 204 and the top surface of the second electrode layer 204 have a first included angle a, the first included angle a being an obtuse angle, and the first included angle a being relatively large, so that the sharpness of the corner of the second electrode layer 204 adjacent to the first electrode layer 203 is reduced, which is beneficial to reducing the electric field strength between the corner of the second electrode layer 204 and the first electrode layer 203, thereby improving the reliability of the capacitor.

[0061] In the embodiment, the first included angle a ranges from 100 degrees to 130 degrees; and the second included angle β ranges from 100 degrees to 130 degrees.

[0062] In the embodiment, the capacitor device further comprises: a first lower metal layer 201 located in the first region I and a second lower metal layer 202 located in the third region III in the substrate 200; a second dielectric layer 208 located on the surface of the metal layer structure; a first upper metal layer 209 and a second upper metal layer 210 located on the second dielectric layer 208 and separated from each other; the first conductive plug 206 further connects the first lower metal layer 201 and the first upper metal layer 209; and the second conductive plug 207 further connects the second lower metal layer 202 and the second upper metal layer 210.

[0063] In the embodiment, the number of layers of the metal layer structure is odd, and the first electrode layer 203 is located at the lowermost layer, and the capacitor device further comprises a dummy electrode layer 211 located on the uppermost second electrode layer 204 on the third region III, and the dummy electrode layer 211 and the first electrode layer 203 are separate from each other.

[0064] In another embodiment, the number of layers of the metal layer structure is odd, and the second electrode layer is located at the lowermost layer, and the capacitor device further comprises a dummy electrode layer located on the uppermost first electrode layer on the first region, and the dummy electrode layer and the second electrode layer are separate from each other.

[0065] In other embodiments, the number of layers of the metal layer structure is even, that is, the thickness of the metal layer structure on the first region and the thickness of the metal layer structure on the third region are consistent, and no dummy electrode layer is arranged.

[0066] In the embodiment, the material of the first electrode layer 203 comprises one or more combinations of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; and the material of the second electrode layer 204 comprises one or more combinations of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0067] In the embodiment, the material of the first dielectric layer 205 comprises one or more combinations of HfO, AlO, ZrO and LaO.

[0068] In the embodiment, the thickness of the first electrode layer 203 ranges from 300 angstroms to 800 angstroms; and the thickness of the second electrode layer 204 ranges from 300 angstroms to 800 angstroms.

[0069] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and therefore the protection scope of the present application should be subject to the range defined by the claims.

Claims

1. A capacitor component, characterized in that, include: A substrate, the substrate comprising a first region, a second region, and a third region arranged along a first direction, wherein the second region is located between the first region and the third region; A metal layer structure located on the substrate includes a plurality of first electrode layers stacked together, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers. Each first electrode layer is located on a second region and extends to the first region. Each second electrode layer is located on the second region and extends to the third region. Each upper first electrode layer is located on the first sidewall and part of the top surface of the second electrode layer below it. There is a first included angle between the first sidewall and the top surface of the second electrode layer. The first included angle is an obtuse angle. Each upper second electrode layer is located on the second sidewall and part of the top surface of the first electrode layer below it. There is a second included angle between the second sidewall and the top surface of the first electrode layer. The second included angle is an obtuse angle. A first conductive plug located on the first region, the first conductive plug being connected to each of the first electrode layers; A second conductive plug is located on the third region, and the second conductive plug is connected to each of the second electrode layers; The metal layer structure has an odd number of layers, and the bottommost layer is the first electrode layer. The capacitor also includes a dummy electrode layer on the topmost second electrode layer in the third region, and the dummy electrode layer is separate from the first electrode layer. Alternatively, the number of layers in the metal layer structure is odd, and the bottommost layer is the second electrode layer. The capacitor also includes a dummy electrode layer located on the topmost first electrode layer in the first region, and the dummy electrode layer is separate from the second electrode layer.

2. The capacitor as described in claim 1, characterized in that, The first included angle ranges from 100 degrees to 130 degrees; the second included angle ranges from 100 degrees to 130 degrees.

3. The capacitor as described in claim 1, characterized in that, Also includes: The substrate has a first lower metal layer located in the first region and a second lower metal layer located in the third region; a second dielectric layer located on the surface of the metal layer structure. A first upper metal layer and a second upper metal layer are located on the second dielectric layer and are separate from each other; the first conductive plug is also connected to the first lower metal layer and the first upper metal layer; the second conductive plug is also connected to the second lower metal layer and the second upper metal layer.

4. The capacitor as claimed in claim 1, characterized in that, The material of the first electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

5. The capacitor as claimed in claim 1, characterized in that, The material of the first dielectric layer includes one or more of HfO, AlO, ZrO and LaO.

6. The capacitor as claimed in claim 1, characterized in that, The thickness of the first electrode layer ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer ranges from 300 angstroms to 800 angstroms.

7. A method for forming a capacitor element, characterized in that, include: A substrate is provided, the substrate including a first region, a second region and a third region arranged along a first direction, wherein the second region is located between the first region and the third region; A metal layer structure is formed on the substrate. The metal layer structure includes a plurality of first electrode layers stacked together, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers. Each first electrode layer is located on a second region and extends to the first region. Each second electrode layer is located on the second region and extends to the third region. Each upper first electrode layer is located on the first sidewall and part of the top surface of the second electrode layer below it. A first included angle, which is an obtuse angle, is formed between the first sidewall and the top surface of the second electrode layer below it. Each upper second electrode layer is located on the second sidewall and part of the top surface of the first electrode layer below it. A second included angle, which is an obtuse angle, is formed between the second sidewall and the top surface of the first electrode layer below it. After the metal layer structure is formed, a first conductive plug is formed to connect each of the first electrode layers and a second conductive plug is formed to connect each of the second electrode layers. The first conductive plug is located on the first region and the second conductive plug is located on the third region. The number of layers in the metal layer structure is odd, and the bottommost layer is the first electrode layer. The method further includes: when forming the topmost first electrode layer, a dummy electrode layer is also formed on the topmost second electrode layer in the third region, and the dummy electrode layer is separate from the first electrode layer. Alternatively, the number of layers in the metal layer structure is odd, and the bottommost layer is the second electrode layer. The method further includes: when forming the topmost second electrode layer, a dummy electrode layer is also formed on the topmost first electrode layer in the first region, and the dummy electrode layer is separate from the second electrode layer.

8. The method for forming a capacitor element as described in claim 7, characterized in that, The method for forming adjacent first electrode layers and second electrode layers includes: forming a first electrode material layer on the substrate, or forming a first dielectric layer and a first electrode material layer located on the first dielectric layer on an upper second electrode layer; patterning the first electrode material layer to form the first electrode layer; forming the first dielectric layer and a second electrode material layer located on the first dielectric layer on the first electrode layer; and patterning the second electrode material layer to form the second electrode layer.

9. The method for forming a capacitor element as described in claim 8, characterized in that, The process of patterning the first electrode material layer includes a dry etching process.

10. The method for forming a capacitor element as described in claim 8, characterized in that, The process for patterning the second electrode material layer includes a dry etching process.

11. The method for forming a capacitor element as described in claim 8, characterized in that, The formation process of the first electrode material layer includes physical vapor deposition; the formation process of the second electrode material layer includes physical vapor deposition.

12. The method for forming a capacitor element as described in claim 7, characterized in that, The substrate has a first lower metal layer located in the first region and a second lower metal layer located in the third region; the first conductive plug is also connected to the first lower metal layer; the second conductive plug is also connected to the second lower metal layer.

13. The method for forming a capacitor element as described in claim 12, characterized in that, The method for forming the first conductive plug and the second conductive plug includes: forming a second dielectric layer on the surface of the metal layer structure; forming a first contact hole in the first region and in the metal layer structure and the second dielectric layer on the first region, the bottom of the first contact hole exposing the first lower metal layer; forming a second contact hole in the third region and in the metal layer structure and the second dielectric layer on the third region, the bottom of the second contact hole exposing the second lower metal layer; forming the first conductive plug in the first contact hole; and forming the second conductive plug in the second contact hole.

14. The method for forming a capacitor element as described in claim 13, characterized in that, After the second dielectric layer is formed, a first upper metal layer and a second upper metal layer are also formed, which are separate from each other. The first conductive plug is also connected to the first upper metal layer, and the second conductive plug is also connected to the second upper metal layer.

15. The method for forming a capacitor element as described in claim 14, characterized in that, The method for forming the first conductive plug, the second conductive plug, the first upper metal layer, and the second upper metal layer further includes: after forming the first contact hole and the second contact hole, forming a conductive material layer on the surface of the second dielectric layer, in the first contact hole, and in the second contact hole; etching the conductive material layer until the surface of the second dielectric layer is exposed, forming the first conductive plug and the first upper metal layer on the first conductive plug, and forming the second conductive plug and the second upper metal layer on the second conductive plug.

16. The method for forming a capacitor element as described in claim 7, characterized in that, The first included angle ranges from 100 degrees to 130 degrees; the second included angle ranges from 100 degrees to 130 degrees.

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