Capacitor device and method of forming the same

Abstract

A capacitor device and a method for forming the same. The structure includes: a metal layer structure on a substrate, the metal layer structure including a plurality of first electrode layers arranged in a stack, a second electrode layer between two adjacent first electrode layers, and a first dielectric layer between the adjacent first electrode layer and the second electrode layer, each first electrode layer being on a second region and extending to a first region, and each second electrode layer being on the second region and extending to a third region; a first conductive plug on the first region, the first conductive plug including a first portion and a second portion on the first portion, the first portion penetrating each first electrode layer along a normal direction of a surface of the substrate and connecting each first electrode layer, a sidewall of the first portion having a first included angle with the normal direction of the surface of the substrate, a sidewall of the second portion having a second included angle with the normal direction of the surface of the substrate, the first included angle being greater than the second included angle, which is conducive to reducing the contact resistance between the first conductive plug and each first electrode layer and improving the performance of the capacitor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a capacitor and a method for forming the same. Background Technology

[0002] In semiconductor integrated circuits, integrated capacitors, fabricated on the same chip as transistor circuits, are widely used. They mainly come in two forms: metal-insulator-metal (MIM) capacitors and metal-oxide-metal (MOM) capacitors.

[0003] MIM capacitors use upper and lower metal layers as capacitor plates. In traditional MIM capacitors, there is only a single dielectric layer between the capacitor plates, and its equivalent capacitance density is limited by the thickness and dielectric constant of the dielectric layer. Therefore, a multi-layer capacitor structure is introduced to achieve a higher equivalent capacitance density.

[0004] However, the performance of multilayer plate capacitor structures still needs further improvement. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a capacitor device and a method for forming the same, so as to improve the performance of semiconductor structures.

[0006] To solve the above-mentioned technical problems, the present invention provides a capacitor device, comprising: a substrate, the substrate including a first region, a second region, and a third region arranged along a first direction, the second region being located between the first region and the third region; a metal layer structure on the substrate, the metal layer structure including a plurality of first electrode layers stacked thereon, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers, each first electrode layer being located on the second region and extending into the first region, and each second electrode layer being located on the second region and extending into the third region; and a first conductive plug located on the first region, the first conductive plug including a first portion The first part and the second part located on the first part, the first part penetrates each first electrode layer along the normal direction of the substrate surface and connects each first electrode layer, the sidewall of the first part has a first angle with the normal direction of the substrate surface, the sidewall of the second part has a second angle with the normal direction of the substrate surface, the first angle is greater than the second angle; the second conductive plug located on the third region, the second conductive plug includes a third part and a fourth part located on the third part, the third part penetrates each second electrode layer along the normal direction of the substrate surface and connects each second electrode layer, the sidewall of the third part has a third angle with the normal direction of the substrate surface, the sidewall of the fourth part has a fourth angle with the normal direction of the substrate surface, the third angle is greater than the fourth angle.

[0007] Optionally, the first included angle ranges from 10 degrees to 40 degrees; the third included angle ranges from 10 degrees to 40 degrees.

[0008] Optionally, the substrate further includes a first lower metal layer located in the first region and a second lower metal layer located in the third region; the first conductive plug further includes a fifth part, which is located between the surface of the first lower metal layer and the first part, and the sidewall of the fifth part has a fifth angle with the normal direction of the substrate surface, and the first angle is greater than the fifth angle; the second conductive plug further includes a sixth part, which is located between the surface of the second lower metal layer and the third part, and the sidewall of the sixth part has a sixth angle with the normal direction of the substrate surface, and the third angle is greater than the sixth angle.

[0009] Optionally, it also includes: a second dielectric layer located on the metal layer structure, with the second part and the fourth part located within the second dielectric layer; a first upper metal layer and a second upper metal layer located on the second dielectric layer, which are mutually separate, with the first conductive plug also connected to the first upper metal layer and the second conductive plug also connected to the second upper metal layer.

[0010] Optionally, it includes: the first electrode layer of each upper layer is located on the sidewall and part of the top surface of the second electrode layer below it; the second electrode layer of each upper layer is located on the sidewall and part of the top surface of the first electrode layer below it.

[0011] Optionally, the number of metal layer structures is odd, and the bottom layer is the first electrode layer. The capacitor device also includes: a dummy electrode layer on the topmost second electrode layer in the third region, the dummy electrode layer being separate from the first electrode layer; the number of metal layer structures is odd, and the bottom layer is the second electrode layer. The capacitor device also includes: a dummy electrode layer on the topmost first electrode layer in the first region, the dummy electrode layer being separate from the second electrode layer.

[0012] Optionally, the material of the first electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0013] Optionally, the material of the first dielectric layer includes one or a combination of HfO, AlO, ZrO and LaO.

[0014] Optionally, the thickness of the first electrode layer ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer ranges from 300 angstroms to 800 angstroms.

[0015] Accordingly, the technical solution of the present invention also provides a method for forming a capacitor, comprising: providing a substrate, the substrate including a first region, a second region and a third region arranged along a first direction, the second region being located between the first region and the third region; forming a metal layer structure on the substrate, the metal layer structure including a plurality of first electrode layers stacked thereon, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers, each first electrode layer being located on the second region and extending into the first region, and each second electrode layer being located on the second region and extending into the third region; forming a first conductive plug on the first region, the first conductive plug including a first... The first part and a second part are located on the first part. The first part penetrates each first electrode layer along the normal direction of the substrate surface and connects each first electrode layer. The sidewall of the first part has a first angle with the normal direction of the substrate surface, and the sidewall of the second part has a second angle with the normal direction of the substrate surface. The first angle is greater than the second angle. A second conductive plug is formed on the third region. The second conductive plug includes a third part and a fourth part located on the third part. The third part penetrates each second electrode layer along the normal direction of the substrate surface and connects each second electrode layer. The sidewall of the third part has a third angle with the normal direction of the substrate surface, and the sidewall of the fourth part has a fourth angle with the normal direction of the substrate surface. The third angle is greater than the fourth angle.

[0016] Optionally, the first included angle ranges from 10 degrees to 40 degrees; the third included angle ranges from 10 degrees to 40 degrees.

[0017] Optionally, before forming the first conductive plug and the second conductive plug, a second dielectric layer is formed on the metal layer structure, and the second portion of the first conductive plug and the fourth portion of the second conductive plug are located within the second dielectric layer; the method for forming the first conductive plug and the second conductive plug includes: etching a portion of the second dielectric layer located on the first region and the third region using a first etching process until the surface of the metal layer structure is exposed; etching the exposed metal layer structure using a second etching process until the substrate is exposed, so as to form a first contact hole on the first region and a second contact hole on the third region, wherein the sidewall of the first contact hole in the metal layer structure has a first angle with the normal direction of the substrate surface, the sidewall of the first contact hole in the second dielectric layer has a second angle with the normal direction of the substrate surface, the sidewall of the second contact hole in the metal layer structure has a third angle with the normal direction of the substrate surface, and the sidewall of the second contact hole in the second dielectric layer has a fourth angle with the normal direction of the substrate surface; forming the first conductive plug in the first contact hole; and forming the second conductive plug in the second contact hole.

[0018] Optionally, the substrate has a first lower metal layer located in a first region and a second lower metal layer located in a third region; the first conductive plug further includes a fifth portion located between the surface of the first lower metal layer and the first portion, the sidewall of the fifth portion having a fifth angle with the normal direction of the substrate surface, the first angle being greater than the fifth angle; the second conductive plug further includes a sixth portion located between the surface of the second lower metal layer and the third portion, the sidewall of the sixth portion having a sixth angle with the normal direction of the substrate surface, the third angle being greater than the sixth angle; the first contact hole is also located within the substrate, and the bottom of the first contact hole exposes the first lower metal layer; the second contact hole is also located within the substrate, and the bottom of the second contact hole exposes the second lower metal layer.

[0019] Optionally, the method for forming the first contact hole and the second contact hole further includes: after the second etching process, using a third etching process to continue etching the exposed substrate until the top surfaces of the first lower metal layer and the second lower metal layer are exposed.

[0020] Optionally, after forming the second dielectric layer, a first upper metal layer and a second upper metal layer, which are mutually independent, are also formed. The first conductive plug is also connected to the first upper metal layer, and the second conductive plug is also connected to the second upper metal layer. The method for forming the first conductive plug, the second conductive plug, the first upper metal layer, and the second upper metal layer further includes: after forming the first contact hole and the second contact hole, forming a conductive material layer on the surface of the second dielectric layer and inside the first contact hole and the second contact hole; planarizing the conductive material layer; after the planarization process, etching the conductive material layer until the surface of the second dielectric layer is exposed, forming the first conductive plug and the first upper metal layer located on the first conductive plug, and forming the second conductive plug and the second upper metal layer located on the second conductive plug.

[0021] Optionally, the number of metal layer structures is odd, and the bottommost layer is the first electrode layer. The method further includes: when forming the topmost first electrode layer, a dummy electrode layer is also formed on the topmost second electrode layer in the third region, and the dummy electrode layer is separate from the first electrode layer; the number of metal layer structures is odd, and the bottommost layer is the second electrode layer. The method further includes: when forming the topmost second electrode layer, a dummy electrode layer is also formed on the topmost first electrode layer in the first region, and the dummy electrode layer is separate from the second electrode layer.

[0022] Optionally, the method for forming adjacent first electrode layers and second electrode layers includes: forming a first electrode material layer on a substrate, or forming a first dielectric layer and a first electrode material layer on the upper second electrode layer; patterning the first electrode material layer to form a first electrode layer; forming a first dielectric layer and a second electrode material layer on the first dielectric layer; and patterning the second electrode material layer to form a second electrode layer.

[0023] Optionally, the first electrode layer of each upper layer is located on the sidewall and part of the top surface of the second electrode layer of the lower layer; the second electrode layer of each upper layer is located on the sidewall and part of the top surface of the first electrode layer of the lower layer.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0025] In the capacitor device provided by the present invention, a first conductive plug located in a first region includes a first part and a second part located on the first part. The first part penetrates each first electrode layer along the normal direction of the substrate surface and connects each first electrode layer. The sidewall of the first part has a first angle with the normal direction of the substrate surface, and the sidewall of the second part has a second angle with the normal direction of the substrate surface. The first angle is greater than the second angle, which makes the inclination of the contact surface between the first conductive plug and each first electrode layer larger, thereby increasing the contact area between the first conductive plug and each first electrode layer. This helps to reduce the contact resistance between the first conductive plug and each first electrode layer and improves the performance of the capacitor device. Similarly, the contact surface between the second conductive plug and each second electrode layer is increased, which helps to improve the performance of the capacitor device.

[0026] In the method for forming a capacitor provided by the present invention, a first conductive plug is formed on a first region. The first conductive plug includes a first part and a second part located on the first part. The first part penetrates each first electrode layer along the normal direction of the substrate surface and connects each first electrode layer. The sidewall of the first part has a first angle with the normal direction of the substrate surface, and the sidewall of the second part has a second angle with the normal direction of the substrate surface. The first angle is greater than the second angle, which makes the inclination of the contact surface between the first conductive plug and each first electrode layer larger, thereby increasing the contact area between the first conductive plug and each first electrode layer. This helps to reduce the contact resistance between the first conductive plug and each first electrode layer and improves the performance of the capacitor. Similarly, the contact surface between the second conductive plug and each second electrode layer is increased, which helps to improve the performance of the capacitor. Attached Figure Description

[0027] Figure 1 This is a structural schematic diagram of a capacitor device;

[0028] Figures 2 to 6 This is a schematic diagram of the structure corresponding to each step in the capacitor device forming method of the present invention. Detailed Implementation

[0029] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0030] As mentioned in the background section, the performance of capacitors in the prior art needs improvement. A capacitor will now be described and analyzed in conjunction with this example.

[0031] Figure 1 This is a schematic diagram of the structure of a capacitor.

[0032] Please refer to Figure 1 The capacitor device includes: a substrate 100, which includes a first region I, a second region II, and a third region III arranged along a first direction X, wherein the second region II is located between the first region I and the third region II; the first region I has a first lower metal layer 101, and the third region III has a second lower metal layer 102; and a plurality of first electrode structures and a plurality of second electrode structures stacked on the substrate 100. The first electrode structures include a first lead-out terminal 103 located on the first region I and a first electrode layer 104 located on the second region II; the second electrode structures include a second lead-out terminal 105 located on the third region III and a second electrode layer 106 located on the second region II; and each first electrode layer 104 on the second region II is located between adjacent second electrode layers 106. The following are components: a first dielectric layer 107 located between adjacent first electrode layers 104 and second electrode layers 106; a dummy electrode layer 108 located on several first electrode structures in the first region I; a second dielectric layer 109 located on the surfaces of several first electrode structures and several second electrode structures; a first upper metal layer 110 and a second upper metal layer 111 located on the second dielectric layer 109, which are mutually separate; a first conductive plug 112 located within the second dielectric layer 109, the first conductive plug 112 connecting the first lower metal layer 101, the first upper metal layer 110 and each first lead-out terminal 103; and a second conductive plug 113 located within the second dielectric layer 109, the second conductive plug 113 connecting the second lower metal layer 102, the second upper metal layer 111 and each second lead-out terminal 105.

[0033] In the above-mentioned MIM capacitor, each adjacent first electrode layer 104, second electrode layer 106 and the first dielectric layer 107 between them form a single capacitor. The first conductive plug 112 is connected to each first lead-out terminal 103 for electrically leading out each first electrode layer 104, and the second conductive plug 113 is connected to each second lead-out terminal 105 for electrically leading out each second electrode layer 106, thereby forming multiple parallel capacitors to obtain a larger equivalent capacitance density. However, the first conductive plug 112 is connected to each first lead-out terminal 103 by passing through each first lead-out terminal 103 vertically. The side wall of the first conductive plug 112 located inside the first lead-out terminal 103 is approximately perpendicular to the bottom surface of the first lead-out terminal 103. The contact surface A between each first lead-out terminal 103 and the first conductive plug 112 is small, resulting in a large contact resistance between the first conductive plug 112 and each first lead-out terminal 103. Similarly, the contact resistance between the second conductive plug 113 and each second lead-out terminal 105 is also large, thereby affecting the performance of the capacitor.

[0034] To address the aforementioned problems, this invention provides a capacitor and its forming method. A first sidewall of a first conductive plug has a first angle with the normal direction of the substrate surface, and a second sidewall has a second angle with the normal direction of the substrate surface. The first angle is greater than the second angle, resulting in a larger inclination of the contact surface between the first conductive plug and each first electrode layer. This increases the contact area between the first conductive plug and each first electrode layer, which helps reduce the contact resistance between the first conductive plug and each first electrode layer, thus improving the performance of the capacitor. Similarly, the increased contact surface between the second conductive plug and each second electrode layer further enhances the performance of the capacitor.

[0035] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figures 2 to 6 This is a schematic diagram of the structure corresponding to each step in the capacitor device forming method of the present invention.

[0037] Please refer to Figure 2 A substrate 200 is provided, the substrate 200 includes a first region I, a second region II and a third region III arranged along a first direction Y, the second region II being located between the first region I and the third region III.

[0038] In this embodiment, the substrate 200 has a first lower metal layer 201 located in the first region I and a second lower metal layer 202 located in the third region III.

[0039] In this embodiment, the substrate 200 further includes a substrate (not shown in the figure), a device layer (not shown in the figure) located on the substrate, and a metal interconnect layer located on the device layer. The metal interconnect layer includes a third dielectric layer (not shown in the figure), a first lower metal layer 201 and a second lower metal layer 202 located within the third dielectric layer, and the metal interconnect layer and the device layer are electrically connected.

[0040] Please refer to Figure 3 A metal layer structure is formed on the substrate 200. The metal layer structure includes a plurality of first electrode layers 203 stacked together, a second electrode layer 204 located between two adjacent first electrode layers 203, and a first dielectric layer 205 located between adjacent first electrode layers 203 and second electrode layers 204. Each first electrode layer 203 is located on a second region II and extends to a first region I, and each second electrode layer 204 is located on a second region II and extends to a third region III.

[0041] In this embodiment, the first electrode layer 203 of each upper layer is located on the sidewall and part of the top surface of the second electrode layer 204 below it; the second electrode layer 204 of each upper layer is located on the sidewall and part of the top surface of the first electrode layer 203 below it.

[0042] In this embodiment, the method for forming adjacent first electrode layer 203 and second electrode layer 204 includes: forming a first electrode material layer (not shown in the figure) on a substrate 200, or forming a first dielectric layer 205 and a first electrode material layer located on the first dielectric layer 205 on the upper second electrode layer 204; patterning the first electrode material layer to form the first electrode layer 203; forming a first dielectric layer and a second electrode material layer (not shown in the figure) located on the first dielectric layer 205 on the first electrode layer; and patterning the second electrode material layer to form the second electrode layer 204.

[0043] In this embodiment, the formation process of the first electrode material layer includes physical vapor deposition; the formation process of the second electrode material layer includes physical vapor deposition.

[0044] In this embodiment, the material of the first electrode layer 203 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer 204 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0045] In this embodiment, the material of the first dielectric layer 205 includes one or more of HfO, AlO, ZrO and LaO.

[0046] It should be noted that each first electrode layer 203, the adjacent second electrode layer 204, and the first dielectric layer 205 between them form a single capacitor element. The metal layer structure includes multiple capacitor elements connected in parallel. The material of the first dielectric layer 205 in each capacitor element can be the same or different.

[0047] In this embodiment, the thickness of the first electrode layer 203 ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer 204 ranges from 300 angstroms to 800 angstroms.

[0048] In this embodiment, the number of metal layer layers is odd, and the bottommost layer is the first electrode layer 203. The method further includes forming a dummy electrode layer 206 on the topmost second electrode layer 204 in the third region III when forming the topmost first electrode layer 203. The dummy electrode layer 206 is separate from the first electrode layer 203. Specifically, the patterned topmost second electrode material layer is also used to form the dummy electrode layer 206.

[0049] The dummy electrode layer 206 is used to balance the thickness of the metal layer structure on the first region I and the third region III when forming the first contact hole and the second contact hole, thereby reducing the etching difference between the first contact hole and the second contact hole.

[0050] In another embodiment, the number of metal layer structures is odd, and the bottommost layer is the second electrode layer. The method further includes: when forming the topmost second electrode layer, a dummy electrode layer is also formed on the topmost first electrode layer in the first region, and the dummy electrode layer and the second electrode layer are separate from each other.

[0051] In other embodiments, the number of metal layer structures is even, that is, the thickness of the metal layer structure on the first region is the same as the thickness of the metal layer structure on the third region, then no dummy electrode layer is provided.

[0052] Please refer to Figures 4 to 6 , Figure 5 for Figure 4 A magnified view of the first conductive plug in the middle section. Figure 6 for Figure 4 A partially enlarged view of the second conductive plug shows that a first conductive plug 207 is formed on the first region I. The first conductive plug 207 includes a first part a1 and a second part a2 located on the first part a1. The first part a1 penetrates each first electrode layer 203 along the normal direction of the substrate 200 surface and connects each first electrode layer 203. The sidewall of the first part a1 has a first angle β1 with the normal direction of the substrate 200 surface, and the sidewall of the second part a2 has a second angle β2 with the normal direction of the substrate 200 surface. The first angle β1 is greater than the second angle β2. A second conductive plug 208 is formed on the third region III. The second conductive plug 208 includes a third part a3 and a fourth part a4 located on the third part a3. The third part a3 penetrates each second electrode layer 204 along the normal direction of the substrate 200 surface and connects each second electrode layer 204. The sidewall of the third part a3 has a third angle β3 with the normal direction of the substrate 200 surface, and the sidewall of the fourth part a4 has a fourth angle β4 with the normal direction of the substrate 200 surface. The third angle β3 is greater than the fourth angle β4.

[0053] Thus, the first part a1 sidewall has a first angle β1 with the normal direction of the substrate 200 surface, and the second part a2 sidewall has a second angle β2 with the normal direction of the substrate 200 surface. The first angle β1 is greater than the second angle β2, which makes the contact surface of the first conductive plug 207 and each first electrode layer 203 more inclined, increasing the contact area between the first conductive plug 207 and each first electrode layer 203. This helps to reduce the contact resistance between the first conductive plug 207 and each first electrode layer 203, and improves the performance of the capacitor. Similarly, the contact surface between the second conductive plug 208 and each second electrode layer 204 is increased, which helps to improve the performance of the capacitor.

[0054] In this embodiment, the range of the first included angle β1 is 10 degrees to 40 degrees; the range of the third included angle β3 is 10 degrees to 40 degrees.

[0055] In this embodiment, before forming the first conductive plug 207 and the second conductive plug 208, a second dielectric layer 209 is formed on the metal layer structure, and the second part a2 of the first conductive plug 207 and the fourth part a4 of the second conductive plug 208 are located in the second dielectric layer 209.

[0056] In this embodiment, the method for forming the first conductive plug 207 and the second conductive plug 208 includes: etching a portion of the second dielectric layer 209 located in the first region I and the third region III using a first etching process until the surface of the metal layer structure is exposed; etching the exposed metal layer structure using a second etching process until the substrate 200 is exposed, so as to form a first contact hole (not shown in the figure) in the first region I and a second contact hole (not shown in the figure) in the third region III, wherein the sidewall of the first contact hole in the metal layer structure has a first angle β1 with the normal direction of the surface of the substrate 200, the sidewall of the first contact hole in the second dielectric layer 209 has a second angle β2 with the normal direction of the surface of the substrate 200, the sidewall of the second contact hole in the metal layer structure has a third angle β3 with the normal direction of the surface of the substrate 200, and the second contact hole in the second dielectric layer 209 has a fourth angle β4 with the normal direction of the surface of the substrate 200; forming the first conductive plug 207 in the first contact hole; and forming the second conductive plug 208 in the second contact hole.

[0057] In this embodiment, the first conductive plug 207 further includes a fifth part a5, which is located in the first lower metal layer 201 (e.g., Figure 2 As shown, the fifth part a5 has a fifth included angle β5 between its sidewall and the normal direction of the substrate 200 surface, and the first included angle β1 is greater than the fifth included angle β5; the second conductive plug 208 also includes a sixth part, which is located in the second lower metal layer 202 (as shown). Figure 2 As shown, between the surface and the third part a3, the sidewall of the sixth part a6 has a sixth included angle β6 with the normal direction of the surface of the substrate 200, and the third included angle β3 is greater than the sixth included angle β6; the first contact hole is also located inside the substrate 200, and the bottom of the first contact hole exposes the first lower metal layer 201; the second contact hole is also located inside the substrate 200, and the bottom of the second contact hole exposes the second lower metal layer 202.

[0058] In this embodiment, the method for forming the first contact hole and the second contact hole further includes: after the second etching process, using a third etching process to continue etching the exposed substrate 200 until the first lower metal layer 201 and the top surface 202 of the second lower metal layer are exposed.

[0059] In this embodiment, after the second dielectric layer 209 is formed, a first upper metal layer 210 and a second upper metal layer 211 that are mutually independent are also formed. The first conductive plug 207 is also connected to the first upper metal layer 210, and the second conductive plug 208 is also connected to the second upper metal layer 211.

[0060] In this embodiment, the method for forming the first conductive plug 207, the second conductive plug 208, the first upper metal layer 210, and the second upper metal layer 211 further includes: after forming the first contact hole and the second contact hole, forming a conductive material layer (not shown in the figure) on the surface of the second dielectric layer 209 and inside the first contact hole and the second contact hole; planarizing the conductive material layer; after the planarization process, etching the conductive material layer until the surface of the second dielectric layer 209 is exposed, forming the first conductive plug 207 and the first upper metal layer 210 located on the first conductive plug 207, and forming the second conductive plug 208 and the second upper metal layer 211 located on the second conductive plug 208.

[0061] Accordingly, embodiments of the present invention also provide a capacitor device formed by the above method; please refer to further details. Figures 4 to 6 The system includes: a substrate 200, which includes a first region I, a second region II, and a third region III arranged along a first direction Y, wherein the second region II is located between the first region I and the third region III; a metal layer structure on the substrate 200, which includes a plurality of first electrode layers 203 stacked together, a second electrode layer 204 located between two adjacent first electrode layers 203, and a first dielectric layer 205 located between adjacent first electrode layers 203 and second electrode layers 204, wherein each first electrode layer 203 is located on the second region II and extends to the first region I, and each second electrode layer 204 is located on the second region II and extends to the third region III; and a first conductive plug 207 located on the first region I, wherein the first conductive plug 207 includes a first part a1 and a second part a2 located on the first part a1. 1. A portion a1 penetrates each first electrode layer 203 along the normal direction of the substrate 200 surface and connects each first electrode layer 203. The sidewall of the first portion a1 has a first angle β1 with the normal direction of the substrate 200 surface, and the sidewall of the second portion a2 has a second angle β2 with the normal direction of the substrate 200 surface. The first angle β1 is greater than the second angle β2. A second conductive plug 208 is located on the third region III. The second conductive plug 208 includes a third portion a3 and a fourth portion a4 located on the third portion a3. The third portion a3 penetrates each second electrode layer 204 along the normal direction of the substrate 200 surface and connects each second electrode layer 204. The sidewall of the third portion a3 has a third angle β3 with the normal direction of the substrate 200 surface, and the sidewall of the fourth portion a4 has a fourth angle β4 with the normal direction of the substrate 200 surface. The third angle β3 is greater than the fourth angle β4.

[0062] Thus, the first part a1 sidewall has a first angle β1 with the normal direction of the substrate 200 surface, and the second part a2 sidewall has a second angle β2 with the normal direction of the substrate 200 surface. The first angle β1 is greater than the second angle β2, which makes the contact surface of the first conductive plug 207 and each first electrode layer 203 more inclined, increasing the contact area between the first conductive plug 207 and each first electrode layer 203. This helps to reduce the contact resistance between the first conductive plug 207 and each first electrode layer 203, and improves the performance of the capacitor. Similarly, the contact surface between the second conductive plug 208 and each second electrode layer 204 is increased, which helps to improve the performance of the capacitor.

[0063] In this embodiment, the range of the first included angle β1 is 10 degrees to 40 degrees; the range of the third included angle β3 is 10 degrees to 40 degrees.

[0064] In this embodiment, the substrate 200 further includes a first lower metal layer 201 located in the first region I and a second lower metal layer 202 located in the third region III; the first conductive plug 207 further includes a fifth part a5, which is located between the surface of the first lower metal layer 201 and the first part a1, and the sidewall of the fifth part a5 has a fifth angle β5 with the normal direction of the surface of the substrate 200, and the first angle β1 is greater than the fifth angle β5; the second conductive plug 208 further includes a sixth part a6, which is located between the surface of the second lower metal layer 202 and the third part a3, and the sidewall of the sixth part a6 has a sixth angle β6 with the normal direction of the surface of the substrate 200, and the third angle β3 is greater than the sixth angle β6.

[0065] In this embodiment, the capacitor further includes: a second dielectric layer 209 located on the metal layer structure, with the second part a2 and the fourth part a4 located within the second dielectric layer 209; a first upper metal layer 210 and a second upper metal layer 211 located on the second dielectric layer 209, with the first conductive plug 207 also connected to the first upper metal layer 210 and the second conductive plug 208 also connected to the second upper metal layer 211.

[0066] In this embodiment, the capacitor further includes: each upper first electrode layer 203 is located on the sidewall and part of the top surface of the lower second electrode layer 204; each upper second electrode layer 204 is located on the sidewall and part of the top surface of the lower first electrode layer 203.

[0067] In this embodiment, the number of metal layer structures is odd, and the bottommost layer is the first electrode layer 203. The capacitor also includes a dummy electrode layer 206 on the topmost second electrode layer 204 located in the third region III. The dummy electrode layer 206 is separate from the first electrode layer 203.

[0068] In another embodiment, the number of metal layer structures is odd, and the bottommost layer is the second electrode layer. The capacitor also includes a dummy electrode layer located on the topmost first electrode layer in the first region, and the dummy electrode layer and the second electrode layer are separate from each other.

[0069] In other embodiments, the number of metal layer structures is even, that is, the thickness of the metal layer structure on the first region is the same as the thickness of the metal layer structure on the third region, then no dummy electrode layer is provided.

[0070] In this embodiment, the material of the first electrode layer 203 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer 204 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0071] In this embodiment, the material of the first dielectric layer 205 includes one or more of HfO, AlO, ZrO and LaO.

[0072] In this embodiment, the thickness of the first electrode layer 203 ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer 204 ranges from 300 angstroms to 800 angstroms.

[0073] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A capacitor component, characterized in that, include: A substrate, the substrate comprising a first region, a second region, and a third region arranged along a first direction, wherein the second region is located between the first region and the third region; A metal layer structure located on the substrate, the metal layer structure including a plurality of first electrode layers stacked together, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers, each first electrode layer being located on a second region and extending to the first region, and each second electrode layer being located on a second region and extending to the third region; A first conductive plug located on the first region, the first conductive plug including a first part and a second part located on the first part, the first part penetrating each of the first electrode layers along the normal direction of the substrate surface and connecting each of the first electrode layers, the sidewall of the first part having a first angle with the normal direction of the substrate surface, the sidewall of the second part having a second angle with the normal direction of the substrate surface, the first angle being greater than the second angle; A second conductive plug located on the third region, the second conductive plug including a third part and a fourth part located on the third part, the third part penetrating each of the second electrode layers along the normal direction of the substrate surface and connecting each of the second electrode layers, the sidewall of the third part having a third angle with the normal direction of the substrate surface, the sidewall of the fourth part having a fourth angle with the normal direction of the substrate surface, the third angle being greater than the fourth angle; Wherein, the number of layers in the metal layer structure is odd, and the bottommost layer is the first electrode layer. The capacitor device also includes: a dummy electrode layer on the topmost second electrode layer in the third region, wherein the dummy electrode layer is separate from the first electrode layer. Alternatively, the number of layers in the metal layer structure is odd, and the bottommost layer is the second electrode layer. The capacitor also includes a dummy electrode layer located on the topmost first electrode layer in the first region, and the dummy electrode layer is separate from the second electrode layer.

2. The capacitor as described in claim 1, characterized in that, The first included angle ranges from 10 degrees to 40 degrees; the third included angle ranges from 10 degrees to 40 degrees.

3. The capacitor as described in claim 1, characterized in that, The substrate further comprises a first lower metal layer located in the first region and a second lower metal layer located in the third region; the first conductive plug further comprises a fifth portion located between the surface of the first lower metal layer and the first portion, the sidewall of the fifth portion having a fifth angle with the normal direction of the substrate surface, the first angle being greater than the fifth angle; the second conductive plug further comprises a sixth portion located between the surface of the second lower metal layer and the third portion, the sidewall of the sixth portion having a sixth angle with the normal direction of the substrate surface, the third angle being greater than the sixth angle.

4. The capacitor as claimed in claim 1, characterized in that, Also includes: A second dielectric layer is located on the metal layer structure, and the second part and the fourth part are located within the second dielectric layer; A first upper metal layer and a second upper metal layer are located on the second dielectric layer and are mutually separate. The first conductive plug is also connected to the first upper metal layer, and the second conductive plug is also connected to the second upper metal layer.

5. The capacitor as claimed in claim 1, characterized in that, include: The first electrode layer of each upper layer is located on the sidewall and part of the top surface of the second electrode layer below it; the second electrode layer of each upper layer is located on the sidewall and part of the top surface of the first electrode layer below it.

6. The capacitor as claimed in claim 1, characterized in that, The material of the first electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

7. The capacitor as claimed in claim 1, characterized in that, The material of the first dielectric layer includes one or more of HfO, AlO, ZrO and LaO.

8. The capacitor as claimed in claim 1, characterized in that, The thickness of the first electrode layer ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer ranges from 300 angstroms to 800 angstroms.

9. A method for forming a capacitor element, characterized in that, include: A substrate is provided, the substrate including a first region, a second region and a third region arranged along a first direction, wherein the second region is located between the first region and the third region; A metal layer structure is formed on the substrate. The metal layer structure includes a plurality of first electrode layers stacked together, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers. Each first electrode layer is located on a second region and extends to the first region, and each second electrode layer is located on the second region and extends to the third region. A first conductive plug is formed on the first region. The first conductive plug includes a first part and a second part located on the first part. The first part penetrates each of the first electrode layers along the normal direction of the substrate surface and connects each of the first electrode layers. The sidewall of the first part has a first angle with the normal direction of the substrate surface, and the sidewall of the second part has a second angle with the normal direction of the substrate surface. The first angle is greater than the second angle. A second conductive plug is formed on the third region. The second conductive plug includes a third part and a fourth part located on the third part. The third part penetrates each of the second electrode layers along the normal direction of the substrate surface and connects each of the second electrode layers. The sidewall of the third part has a third angle with the normal direction of the substrate surface, and the sidewall of the fourth part has a fourth angle with the normal direction of the substrate surface. The third angle is greater than the fourth angle. Wherein, the number of layers in the metal layer structure is odd, and the bottommost layer is the first electrode layer. The method further includes: when forming the topmost first electrode layer, a dummy electrode layer is also formed on the topmost second electrode layer in the third region, and the dummy electrode layer is separate from the first electrode layer. Alternatively, the number of layers in the metal layer structure is odd, and the bottommost layer is the second electrode layer. The method further includes: when forming the topmost second electrode layer, a dummy electrode layer is also formed on the topmost first electrode layer in the first region, and the dummy electrode layer is separate from the second electrode layer.

10. The method for forming a capacitor element as described in claim 9, characterized in that, The first included angle ranges from 10 degrees to 40 degrees; the third included angle ranges from 10 degrees to 40 degrees.

11. The method for forming a capacitor element as described in claim 9, characterized in that, Before forming the first conductive plug and the second conductive plug, a second dielectric layer is formed on the metal layer structure, wherein the second portion of the first conductive plug and the fourth portion of the second conductive plug are located within the second dielectric layer; The method for forming the first conductive plug and the second conductive plug includes: etching a portion of the second dielectric layer located on the first region and the third region using a first etching process until the surface of the metal layer structure is exposed; etching the exposed metal layer structure using a second etching process until the substrate is exposed to form a first contact hole on the first region and a second contact hole on the third region, wherein the sidewall of the first contact hole in the metal layer structure has a first angle with the normal direction of the substrate surface, the sidewall of the first contact hole in the second dielectric layer has a second angle with the normal direction of the substrate surface, the sidewall of the second contact hole in the metal layer structure has a third angle with the normal direction of the substrate surface, and the sidewall of the second contact hole in the second dielectric layer has a fourth angle with the normal direction of the substrate surface; forming the first conductive plug in the first contact hole; and forming the second conductive plug in the second contact hole.

12. The method for forming a capacitor element as claimed in claim 11, characterized in that, The substrate has a first lower metal layer located in the first region and a second lower metal layer located in the third region; the first conductive plug further includes a fifth portion, the fifth portion being located between the surface of the first lower metal layer and the first portion, the sidewall of the fifth portion having a fifth angle with the normal direction of the substrate surface, the first angle being greater than the fifth angle; the second conductive plug further includes a sixth portion, the sixth portion being located between the surface of the second lower metal layer and the third portion, the sidewall of the sixth portion having a sixth angle with the normal direction of the substrate surface, the third angle being greater than the sixth angle; the first contact hole is also located within the substrate, and the bottom of the first contact hole exposes the first lower metal layer; the second contact hole is also located within the substrate, and the bottom of the second contact hole exposes the second lower metal layer.

13. The method for forming a capacitor element as described in claim 12, characterized in that, The method for forming the first contact hole and the second contact hole further includes: after the second etching process, using a third etching process to continue etching the exposed substrate until the top surfaces of the first lower metal layer and the second lower metal layer are exposed.

14. The method for forming a capacitor element as claimed in claim 11, characterized in that, After the second dielectric layer is formed, a first upper metal layer and a second upper metal layer are also formed, which are separate from each other. The first conductive plug is also connected to the first upper metal layer, and the second conductive plug is also connected to the second upper metal layer. The method for forming the first conductive plug, the second conductive plug, the first upper metal layer, and the second upper metal layer further includes: after forming the first contact hole and the second contact hole, forming a conductive material layer on the surface of the second dielectric layer, in the first contact hole, and in the second contact hole; planarizing the conductive material layer; and after the planarization process, etching the conductive material layer until the surface of the second dielectric layer is exposed, thereby forming the first conductive plug and the first upper metal layer on the first conductive plug, and forming the second conductive plug and the second upper metal layer on the second conductive plug.

15. The method for forming a capacitor element as described in claim 9, characterized in that, The method for forming adjacent first electrode layers and second electrode layers includes: forming a first electrode material layer on the substrate, or forming a first dielectric layer and a first electrode material layer located on the first dielectric layer on an upper second electrode layer; patterning the first electrode material layer to form the first electrode layer; forming the first dielectric layer and a second electrode material layer located on the first dielectric layer on the first electrode layer; and patterning the second electrode material layer to form the second electrode layer.

16. The method for forming a capacitor element as described in claim 9, characterized in that, The first electrode layer of each upper layer is located on the sidewall and part of the top surface of the second electrode layer below it; the second electrode layer of each upper layer is located on the sidewall and part of the top surface of the first electrode layer below it.

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