Semiconductor device and forming method thereof

Abstract

An embodiment includes a device including a first die including a first surface and a second surface opposite the first surface. The first die includes a plurality of through substrate vias (TSVs) exposed from a second surface of the first die. The device also includes a guard ring surrounding the plurality of TSVs. The device also includes a dummy metallization pattern surrounding the guard ring. The device also includes an active metallization pattern connected to an active device in the first die. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, the improvement in integration density stems from the iterative reduction of the minimum component size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, there is a demand for smaller and more creative packaging technologies for semiconductor die. An example of such a packaging system is package-on-package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor device, comprising: a first die, comprising a first surface and a second surface opposite to the first surface, wherein the first die comprises: a plurality of through substrate vias (TSVs) exposed from the second surface of the first die; a guard ring surrounding the plurality of through substrate vias; and a dummy metallization pattern surrounding the guard ring. In some embodiments, the guard ring extends between the plurality of through substrate vias.

[0004] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first tube core including a first surface and a second surface opposite to the first surface, wherein forming the first tube core includes: forming a first interconnect structure above a first substrate, the first interconnect structure including an active metallization pattern, a guard ring and a dummy metallization pattern; forming a substrate through via (TSV) passing through the first interconnect structure and the first substrate, the guard ring surrounding the substrate through via in the first interconnect structure, and the dummy metallization pattern surrounding the guard ring; and forming a bonding pad connected to the substrate through via and the active metallization pattern of the first interconnect structure above the first interconnect structure, the bonding pad being located on the first surface of the first tube core, and the substrate through via being exposed at the second surface of the first tube core; forming a second tube core including a first surface and a second surface opposite to the first surface; and bonding the first surface of the first tube core to the first surface of the second tube core.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first tube core including a first surface and a second surface opposite to the first surface, wherein forming the first tube core includes: forming a first interconnect structure above a first substrate, the first interconnect structure including an active metallization pattern, a guard ring, and a dummy metallization pattern; forming a substrate through via (TSV) passing through the first interconnect structure and the first substrate, the guard ring being a continuous structure surrounding the substrate through via in the first interconnect structure and extending between the substrate through vias in the first interconnect structure, the dummy metallization pattern surrounding the guard ring; and forming a second interconnect structure on the first substrate, the second interconnect structure being located on a side of the first substrate opposite to the first interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1A , Figure 1B , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Figure 7 , Figure 8 and Fig. 9 Cross-sectional and plan views illustrate intermediate stages in the formation of a die in accordance with an embodiment.

[0008] Figures 10 to 14 A cross-sectional view illustrating an intermediate stage in the formation of a package in accordance with an embodiment.

[0009] Fig.15A , Fig. 15B , Fig. 15C and Fig.15D Cross-sectional and plan views illustrate intermediate stages in the formation of a die in accordance with an embodiment.

[0010] Fig.16 A cross-sectional view of a package according to an embodiment is shown.

[0011] Fig.17 A cross-sectional view of a package according to an embodiment is shown. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] Embodiments discussed herein may be discussed in a specific context, namely, a through-substrate via (TSV) cluster with reduced spacing between adjacent TSVs. In some embodiments, the TSV cluster has a merged guard ring wall between adjacent TSVs. In some embodiments, a dummy interconnect structure is located between adjacent TSVs of the TSV cluster in place of the merged guard ring wall. By having a merged guard ring wall or a dummy interconnect structure between adjacent TSVs of the TSV cluster, the spacing between adjacent TSVs can be reduced. Therefore, the total area consumed by the TSV cluster is reduced, and more area can be used for other functions of the device, or the device size can be reduced. In some embodiments, the disclosed TSV cluster may be applicable to a device (e.g., a chip or die) or a package (e.g., a system on an integrated chip (SoIC), a chip on wafer (CoW) packaging structure, or a wafer on wafer (WoW) packaging structure). By reducing the spacing between adjacent TSVs in a TSV cluster, the performance, power, and area cost of the device are improved. For example, in a 2×2 TSV cluster, the area cost of the disclosed TSV cluster is reduced by 25%-35% compared to a conventional TSV structure.

[0015] In addition, the teachings of the embodiments of the present disclosure are applicable to any device or package having a TSV cluster. Other embodiments contemplate other applications, such as different package types or different configurations, which will be apparent to a person of ordinary skill in the art after reading the embodiments of the present disclosure. It should be noted that the embodiments discussed herein may not necessarily show every component or part that may be present in the structure. For example, multiples of components may be omitted from the accompanying drawings, such as when a discussion of one of the components is sufficient to convey various aspects of the embodiment. In addition, the method embodiments discussed herein may be discussed as being implemented in a particular order; however, other method embodiments may be implemented in any logical order.

[0016] Figure 1A , Figure 1B , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Figure 7 , Figure 8 and Fig. 9 Cross-sectional and plan views are shown of intermediate stages in the formation of a die in accordance with some embodiments.

[0017] Figure 1A A cross section of an integrated circuit die 20 is shown in accordance with some embodiments. Figure 1B Shows Figure 1B The plan view of the structure, where Figure 1A along Figure 1B Line AA in. The integrated circuit die 20 will be packaged in a subsequent process to form an integrated circuit package. The integrated circuit die 20 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof.

[0018] The integrated circuit die 20 can be formed in a wafer, which can include different device regions that are segmented in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 20 can be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die 20 includes a substrate 22 (such as doped or undoped silicon) or an active layer of a semiconductor on insulator (SOI) substrate. The substrate 22 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The substrate 22 has an active surface (e.g., Figure 1A the upward-facing surface) (sometimes referred to as the front side) and the inactive surface (e.g. Figure 1A The downward-facing surface (sometimes called the dorsal side) is the central surface of the brain.

[0019] Device 21 may be formed at the front side of substrate 22. Device 21 may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, etc., or a combination thereof. An interlayer dielectric (ILD) (not shown separately) is located over the front side of substrate 22. The ILD surrounds and may cover device 21. The ILD may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0020] A conductive plug (not shown separately) extends through the ILD to electrically and physically couple the device 21. For example, when the device 21 is a transistor, the conductive plug can couple the gate and source / drain regions of the transistor. The conductive plug can be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or a combination thereof.

[0021] The active surface of substrate 22 includes portions 22A between substrate 22 and dummy metallization pattern 28 and guard ring 30. These portions 22A may be patterned portions of substrate 22, or may be structures formed on top of substrate 22. These portions extend as high as the front-end processing of substrate 22. In some embodiments, the front-end processing ends after the gate, ILD, and conductive plug are formed.

[0022] The interconnect structure 24 is located above the ILD and the conductive plug. The interconnect structure 24 can be formed by, for example, metallization patterns 26, 28, 30 in the dielectric layer 23 on the ILD. In these embodiments, the metallization patterns 26, 28, 30 are formed in the middle of the line process and the back end of the line process. The metallization patterns 26, 28, 30 include metal lines and vias formed in one or more low-k dielectric layers 23. The metallization patterns can be formed using any suitable process, such as a single damascene process, a dual damascene process, a plating process, a combination thereof, etc.

[0023] The metallization patterns 26, 28, 30 include an active metallization pattern 26, a dummy metallization pattern 28, and a guard ring 30. The active metallization pattern 26 of the interconnect structure 24 interconnects the devices to form an integrated circuit. The active metallization pattern 26 is electrically coupled to the device through a conductive plug. The dummy metallization pattern 28 is electrically isolated from the device of the die 20.

[0024] like Figure 1A and Figure 1B As shown in FIG, a dummy metallization pattern 28 and a guard ring 30 are formed around the TSV region 27. Figure 1B , four groups of TSV regions 27 are shown and may be referred to as TSV clusters 46. The dummy metallization pattern 28 and the guard ring 30 are formed simultaneously and by the same process as the active metallization pattern 26. The guard ring 30 may reduce leakage current between subsequently formed TSVs and other structures in the substrate 22 and the interconnect structure 24. In addition, during the manufacture and operation of the device, the TSV may introduce mechanical stress, and the guard ring 30 may provide stress relief. In addition, the guard ring 30 may provide electrical isolation between the TSV and nearby active devices and the metallization pattern. The dummy metallization pattern 28 is included to provide a more uniform pattern density in the interconnect structure 24, which may aid in planarization and process consistency, such as during a chemical mechanical polishing (CMP) process.

[0025] In some embodiments, guard ring 30 surrounds each of TSV regions 27 and is located between TSV regions 27, and dummy metallization pattern 28 surrounds guard ring 30 and is not located between TSV regions 27 (see, e.g., Figure 1B and Figure 6B In some embodiments, the dummy metallization pattern is located between TSV regions 27, and the guard ring surrounds TSV regions 27 and is not located between TSV regions 27 (see, for example, Fig. 15B , Fig. 15C and Fig.15D). In some embodiments, the guard ring 30 is formed to have a width W1, and the dummy metallization pattern is formed to have a width W2. In some embodiments, the width W1 is in a range from 0.5 μm to 1.5 μm. In some embodiments, the width W2 is at least 0.5 μm and may be a width required by the design of the device. For example, the width W2 of the dummy metallization pattern 28 may be limited only by the distance between the guard ring 30 and the nearest active metallization pattern 26, so that the dummy metallization pattern 28 has a width that fills the distance. In some embodiments, the width W2 may be greater than 10 μm or greater than 40 μm.

[0026] After forming the interconnect structure 24, as shown in FIG. Figure 2 As shown in FIG. 1 , a mask 32 is formed and patterned on the interconnect structure 24. In some embodiments, the mask 32 is a photoresist and may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to a through substrate via (TSV) 44 (see, e.g., FIG. 1 ) subsequently formed in the TSV region 27. Fig. 6A ). At least one opening is patterned through the photoresist 32 to expose the interconnect structure 24. In some embodiments, before the mask 32, a stop layer (not shown) such as a chemical mechanical polishing (CMP) stop layer is deposited over the top surface of the interconnect structure 24. The CMP stop layer can be used to prevent the subsequent CMP process from removing too much material by resisting the subsequent CMP process and / or by providing a detectable stop point for the subsequent CMP process. In some embodiments, the CMP stop layer may include one or more dielectric material layers. Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, etc.), nitrides (such as SiN, etc.), oxynitrides (such as SiON, etc.), oxycarbides (such as SiOC, etc.), carbonitrides (such as SiCN, etc.), carbides (such as SiC, etc.), combinations thereof, etc., and may be formed using spin coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), etc., or combinations thereof.

[0027] exist Figure 3In the embodiment of the present invention, the remaining mask 32 is used as a mask during the etching process to remove the exposed and underlying portions of the dielectric layer 23 and the substrate 22 of the interconnect structure 24. A single etching process can be used to etch the opening 34 in the TSV region 27 of the interconnect structure 24 and the substrate 22, or a first etching process can be used to etch the interconnect structure 24, and a second etching process can be used to etch the substrate 22. In some embodiments, the opening 34 is formed using a plasma dry etching process and a reactive ion etching (RIE) process, such as a deep RIE (DRIE) process. In some embodiments, the DRIE process includes an etching cycle and a passivation cycle, wherein the etching cycle uses, for example, SF6, and the passivation cycle uses, for example, C4F8. A highly anisotropic etching process can be achieved using a DRIE process with a passivation cycle and an etching cycle. In some embodiments, the etching process can be any acceptable etching process, such as by wet etching or dry etching.

[0028] like Figure 4 As shown in FIG. 1 , after forming the opening 34, the photoresist 32 is removed. The photoresist 32 may be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like.

[0029] In addition, Figure 4 In the embodiment of the present invention, a liner layer 38 is conformally deposited on the interconnect structure 24 and on the bottom surface and sidewalls of the opening 34. In some embodiments, the liner layer 38 includes one or more dielectric material layers and can be used to physically and electrically isolate the subsequently formed via from the substrate 22. Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, etc.), nitrides (such as SiN, etc.), oxynitrides (such as SiON, etc.), combinations thereof, etc. The liner layer 38 can be formed using CVD, PECVD, ALD, etc., or combinations thereof.

[0030] In subsequent steps, Figure 4 As shown in , a seed layer 40 is formed over the pad layer 38. In some embodiments, the seed layer 40 is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer 40 includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD) or the like. In some embodiments, a barrier layer (not shown) can be formed on the pad layer 38 before forming the seed layer 40. The barrier layer can include Ti, TiN, etc., or a combination thereof.

[0031] exist Figure 5 In the embodiment, a conductive material 42 filling the opening 34 is formed on the seed layer 40. The conductive material 42 may be formed by plating, such as electroplating including electrochemical plating, chemical plating, etc. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, etc.

[0032] After forming conductive material 42, an annealing process is then performed. The annealing process may be performed to prevent subsequent extrusion of the conductive material of TSV 44 (sometimes referred to as TSV pumping). TSV pumping is caused by a coefficient of thermal expansion (CTE) mismatch between conductive material 42 and substrate 22, and may cause damage to structures above the TSV (e.g., metallization patterns).

[0033] After the annealing process, a planarization process is performed to remove the conductive material 42, the seed layer 40, and the portion of the liner layer 38 located outside the opening 34 to form a TSV 44. Fig. 6A As shown in . The top surface of TSV 44 and the topmost dielectric layer of interconnect structure 24 are coplanar within process variations after a planarization process. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, the upper portion of TSV 44 (formed in interconnect structure 24) has a greater width than the lower portion of TSV 44 (formed in substrate 22). In some embodiments, the width of TSV 44 is constant through interconnect 24 and substrate 22. In some embodiments, TSV 44 is formed to have a width W3. In some embodiments, width W3 is in a range from 2 μm to 4.5 μm. In some embodiments, TSV 44 in TSV cluster 46 is formed to have a pitch P1. In some embodiments, pitch P1 is in a range from (1×W3) to (2×W3). In some embodiments, pitch P1 is in a range from 4 μm to 5 μm.

[0034] Figure 6B Shows Fig. 6A The plan view of the structure in which Fig. 6A along Figure 6B Line AA in. Figure 6C A plan view of a plurality of TSV clusters 46 is shown. In the illustrated embodiment, guard rings 30 surround each of TSVs 44 and are located between TSVs 44, and dummy metallization patterns 28 surround guard rings 30 and are not located between TSVs 44. Figure 6B The guard ring 30 in the embodiment of the present invention may be referred to as a merged guard ring 30 because the guard rings are connected together and are not separate guard ring structures. In other words, the guard ring 30 surrounding each of the TSVs 44 in the TSV cluster 46 is a continuous guard ring 30. In some embodiments, the TSV clusters 46 are separated by a distance D1. In some embodiments, the distance D1 is a minimum of 6 μm. In some embodiments, the distance D1 is in a range from 6 μm to 150 μm. The merged guard ring 30 allows for a smaller distance D1 than a conventional TSV structure.

[0035] Although Figure 6B A TSV cluster 46 having four TSVs 44 is shown, and Figure 6CA TSV cluster 46 having seven TSVs 44 is shown, but the embodiments are not limited to those numbers of TSVs 44 per TSV cluster 46 and each may have more or fewer TSVs 44 per TSV cluster.

[0036] refer to Figure 7 ,exist Fig. 6A The interconnect structure 50 is formed above the structure. The interconnect structure 50 includes a dielectric layer 52, a metallization pattern and a via 54, and a top metal 56. Figure 7 The interconnect structure 50 is connected to the active metallization pattern 26 and TSV 44 of the interconnect structure 24 through the metallization pattern and the via formed in the dielectric layer 52. The metallization pattern and the via can be formed by similar processes and materials as the interconnect structure 24, and will not be described again here. In some embodiments, there is more than one top metal 56 layer, such as two top metal layers.

[0037] In some embodiments, dielectric layer 52 is the same material as dielectric layer 23 of interconnect structure 24, for example, a low-k dielectric. In other embodiments, dielectric layer 52 is formed of a silicon-containing material (which may or may not include oxygen). For example, dielectric layer 52 may include an oxide such as silicon oxide, a nitride such as silicon nitride, etc.

[0038] The metallization pattern and the via 54 and the top metal 56 can be formed using any suitable process, such as a single damascene process, a dual damascene process, a plating process, a combination thereof, and the like. Examples of forming the metallization pattern and the via 54 and the top metal 56 by a damascene process include: etching the dielectric layer 52 to form an opening; depositing a conductive barrier layer in the opening; plating a metal material, such as copper or a copper alloy; and performing planarization to remove excess portions of the metal material. In other embodiments, the formation of the dielectric layer 52, the metallization pattern and the via 54 and the top metal 56 may include: forming the dielectric layer 52; patterning the dielectric layer 52 to form an opening; forming a metal seed layer (not shown); forming a patterned plating mask (such as a photoresist) to cover some portions of the metal seed layer, leaving other portions exposed; plating the metallization pattern and the via 54 and the top metal 56; removing the plating mask; and etching undesired portions of the metal seed layer. The metallization pattern and the via 54 and the top metal 56 may be made of tungsten, cobalt, nickel, copper, silver, gold, aluminum, and the like, or a combination thereof. In some embodiments, top metal 56 is thicker than metallization pattern 54 , such as three times thicker, five times thicker, or any suitable thickness ratio between metallization layers.

[0039] Figure 7A passivation layer 58 is also shown formed over the dielectric layer 52 and the top metal 56. In some embodiments, the passivation layer 58 is formed of the same material as the dielectric layer 52. In some embodiments, the passivation layer 58 can be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.; a nitride such as silicon nitride, etc.; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; etc.; or a combination thereof. The passivation layer 58 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. The passivation layer 58 can have a flush upper surface within process variations.

[0040] Although Figure 7 TSVs 44 are shown connected directly to interconnect structure 50 , but in some embodiments, one or more of TSVs 44 may be connected directly to interconnect structure 24 .

[0041] exist Figure 8 In the embodiment, dielectric layers 72, 74 and 76 are formed over passivation layer 58. Figure 8 Three dielectric layers 72, 74, and 76 are shown, but more or less than three dielectric layers may be formed. Dielectric layer 72 is separated from top metal 56 by passivation layer 58. Dielectric layer 72 provides a flat top surface to form dielectric layers 74 and 76 on planarization dielectric layer 72, and may be considered planarization dielectric layer 72. Dielectric layer 74 may provide an etch stop function during the subsequent formation of bonding pads and bonding vias, and may be considered an etch stop layer 74. Dielectric layer 76 may provide a dielectric bonding function, and may be considered a bonding dielectric layer 76.

[0042] In some embodiments, dielectric layers 72, 74, and 76 are formed of a silicon-containing material. For example, dielectric layers 72, 74, and 76 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, or a combination thereof.

[0043] Figure 8 Also shown are bond pad vias 86 and bond pads 88 formed in dielectric layers 72, 74, and 76. Bond pad vias 86 and bond pads 88 are connected to top metal 56. Bond pad vias 86 and bond pads 88 may be formed using any suitable process, such as a single damascene process, a dual damascene process, combinations thereof, etc. A dual damascene process will be described.

[0044] In some embodiments, a photoresist (not shown) is formed and patterned on the dielectric layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the opening of the bonding pad 88. In addition, the dielectric layer 76 is patterned using the patterned photoresist as a mask to form an opening, wherein the patterning process stops on the dielectric layer 74. The exposed portion of the dielectric layer 76 can be removed, such as by using an acceptable etching process, such as by wet etching and / or dry etching.

[0045] The photoresist is removed and may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Next, another photoresist (not shown) is formed and patterned on the patterned dielectric layer 76 and in the openings through the dielectric layer 76. The photoresist may be formed by spin coating, etc., and may be exposed to light for patterning. The pattern of the photoresist corresponds to the opening for the bonding pad via 86. The dielectric layers 74 and 72 are patterned using the patterned photoresist as a mask to form openings, wherein the patterning process exposes portions of the top metal 56. The exposed portions of the dielectric layers 74 and 72 may be removed, such as by using an acceptable etching process, such as by wet etching and / or dry etching.

[0046] The photoresist is removed, and a barrier layer 84, a bonding pad via 86, and a bonding pad 88 are formed in the opening. The barrier layer 84 may be formed in the opening before forming the bonding pad via 86 and the bonding pad 88. In some embodiments, the barrier layer 84 may include Ti, TiN, etc., or a combination thereof. The bonding pad via 86 and the bonding pad 88 may be formed by processes and materials similar to the top metal 56 and the via 54, and are not repeated here. For example, the bonding pad 88 may be formed of or include copper. Adjacent bonding pads 88 have a spacing P2. In some embodiments, the spacing P2 is as small as 3.0 μm. In some embodiments, the spacing P2 is in the range of from 3.0 μm to 9.0 μm.

[0047] The top surface of the bond pad 88 is coplanar (within process variations) with the top surface of the uppermost dielectric layer 76. Planarization is achieved by a chemical mechanical polishing (CMP) process or a mechanical grinding process.

[0048] exist Fig. 9 In the embodiment of the present invention, the integrated circuit die 20 is thinned by thinning the substrate 22 before the subsequent singulation process. The thinning may be performed by a planarization process such as a mechanical grinding process or a CMP process. The thinning process exposes the TSVs 44 and the liner layer 38. After thinning, the TSVs 44 provide electrical connections from the back side of the substrate 22 to the front side of the substrate 22 (e.g., the interconnect structures 24 and 50 and the bonding pads 88).

[0049] Fig.10A package structure 100 is shown. The package structure 100 includes a substrate 102 (similar to substrate 22 of integrated circuit die 20) and an interconnect structure 104 including bonding pads 106. The interconnect structure 104 and bonding pads 106 may be similar to the interconnect structures 24 and 50 and bonding pads 88 described above, respectively, and are not described again here. The package structure 100 may be referred to as a die 100.

[0050] exist Fig.11 In the embodiment of the present invention, the integrated circuit die 20 is bonded to the package structure 100. The bonding of the integrated circuit die 20 to the package structure 100 can be achieved by direct bonding, wherein a metal-to-metal direct bond (between the bonding pads 88 and 106) and a dielectric-to-dielectric bond (such as a Si-O-Si bond between the integrated circuit die 20 and the surface dielectric layer of the package structure 100) are formed. In addition, there can be a single integrated circuit die 20 or multiple dies 20 bonded to the same package structure 100. The multiple dies 20 bonded to the same package structure 100 can be completely identical to each other or different from each other to form a homogeneous or heterogeneous structure. In some embodiments, the package structure includes multiple package structures 100 and multiple integrated circuit dies 20.

[0051] The die 20 is arranged facing upward, so that the front side of the die 20 faces the package structure 100, and the back side of the die 20 faces away from the package structure 100. The die 20 is bonded to the package structure 100 at the interface 108. Fig.11 As shown, the direct bonding process directly bonds the topmost dielectric layer of the interconnect structure 104 of the package structure 100 to the topmost dielectric layer 76 of the die 20 at the interface 108 by fusion bonding. In an embodiment, the bond between the topmost dielectric layer of the interconnect structure 104 and the topmost dielectric layer 76 of the die 20 can be an oxide-to-oxide bond. The direct bonding process also directly bonds the bond pad 88 of the die 20 to the bond pad 106 of the package structure 100 at the interface 108 by direct metal-to-metal bonding. Therefore, the electrical connection between the die 20 and the package structure 100 is provided by the physical connection of the bond pad 88 to the bond pad 106.

[0052] As an example, the direct bonding process begins by aligning die 20 with package structure 100, for example, by aligning bond pads 88 with bond pads 106. When die 20 and package structure 100 are aligned, bond pads 88 may overlap corresponding bond pads 106. Next, the direct bonding includes a pre-bonding step during which die 20 is placed in contact with package structure 100. The direct bonding process continues with an anneal, for example, at a temperature between 150° C. and 400° C. for a duration between 0.5 hours and 3 hours, such that the copper in bond pads 88 and bond pads 106 interdiffuse into each other and thereby form a direct metal-to-metal bond.

[0053] Next, if Fig.12 As shown in , a gap filling process is performed to seal the package structure 100 in the sealant 110. After formation, the sealant 110 seals the package structure 100 and the interconnect structure 104. The sealant 110 may include an oxide. Alternatively, the sealant may be a molding compound, a molded underfill, a resin, an epoxy resin, etc. The sealant 110 may be applied by compression molding, transfer molding, etc., and may be applied in a liquid or semi-liquid form and then subsequently cured.

[0054] In some embodiments (not shown separately), the encapsulant 110 seals the integrated circuit die 20 instead of the package structure 100. In these embodiments, a gap filling process is performed to seal the integrated circuit die 20 in the encapsulant 110. After formation, the encapsulant 110 seals the integrated circuit die 20, the interconnect structure 50, and the dielectric layers 72, 74, 76. After depositing the encapsulant 110, a planarization process is performed to make the backside surface of the integrated circuit die 20 flush with the top surface of the encapsulant 110 and expose the TSV 44. The surfaces of the TSV 44, the substrate 22, and the encapsulant 110 are substantially coplanar within process variations after the planarization process. The planarization process can be, for example, chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, planarization can be omitted, for example, if the TSV 44 is already exposed.

[0055] exist Fig.13 In the embodiment of the present invention, a redistribution structure 112 is formed on the TSV 44 and the die 20. The redistribution structure 112 may include a redistribution line (RDL) such as a metal trace (or metal line) and a via located under the metal trace and connected to the metal trace. The redistribution line of the redistribution structure 112 is physically and electrically connected to the TSV 44 of the die 20.

[0056] According to some embodiments of the present disclosure, the RDL is formed by a plating process, wherein each of the RDLs includes a seed layer (not shown) and a metallized material above the seed layer. The seed layer can be formed using, for example, PVD, etc. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the RDL. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating, etc. The seed layer and the metallized material can be formed of the same material or different materials. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the seed layer are removed on which the conductive material is not formed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching and / or dry etching. The seed layer and the remaining portion of the conductive material form the RDL.

[0057] A dielectric layer or passivation layer may be formed over each layer of metal traces. In some embodiments, the dielectric layer or passivation layer is formed of a polymer, which may be a photosensitive material that can be patterned using a photolithography mask, such as PBO, polyimide, BCB, etc. In other embodiments, the dielectric layer or passivation layer is formed of: a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG; etc. The dielectric layer or passivation layer may be formed by spin coating, lamination, CVD, etc., or a combination thereof.

[0058] A patterning process may be used to form openings in the top dielectric layer or passivation layer, exposing part or all of the top metal layer of the redistribution structure 112. The patterning process may be an acceptable process, such as by exposing the dielectric layer or passivation layer to light when the dielectric layer is a photosensitive material, or by etching using, for example, anisotropic etching.

[0059] The redistribution structure 112 is shown as an example. More or fewer dielectric layers and metallization layers than shown may be formed in the redistribution structure 112 by repeating or omitting previously described steps.

[0060] exist Fig.13In the embodiment, an under bump metal (UBM) 114 is formed for external connection to the redistribution structure 112. The UBM 114 has a bump portion located on the top surface of the upper dielectric layer of the redistribution structure 112 and extending along the top surface of the upper dielectric layer of the redistribution structure 112, and has a through hole portion extending through the upper dielectric layer of the redistribution structure 112 to physically and electrically couple the upper metallization layer of the redistribution structure 112. Therefore, the UBM 114 is electrically connected to the die 20 (e.g., the interconnect structure 50 and the TSV 44). The UBM 114 can be formed of the same material as the metallization layer of the redistribution structure 112, and can be formed by a similar process. In some embodiments, the UBM 114 has a different size (such as a larger size) than the metallization layer of the redistribution structure 112.

[0061] Conductive connector 116 is formed on UBM 114. Conductive connector 116 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), etc. Conductive connector 116 can include conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, conductive connector 116 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape. In another embodiment, conductive connector 116 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process.

[0062] In some embodiments, passive devices (not shown) (eg, surface mount devices (SMDs)) may be attached to the package assembly (eg, bonded to the metallization layers of UBM 114 or redistribution structure 112 ). The passive devices may be bonded to the same surface of the package assembly as conductive connectors 116 .

[0063] In some embodiments, the integrated circuit die 20 includes a backside interconnect structure 120 (see, e.g., Fig.16 and Fig.17 ).exist Fig.16 and Fig.171 , the backside interconnect structure 120 includes a metallization pattern in one or more dielectric layers and is similar to the interconnect structure 24 described above. In these embodiments, the backside interconnect structure 120 can be formed on the back side of the thinned substrate 22 and connected to the TSV 44 or other conductive elements extending into the substrate 22. The backside interconnect structure can be electrically connected to the active devices 21 of the integrated circuit die 20 and the metallization pattern of the interconnect structure 50 through the TSV 44 or other conductive elements extending into the substrate 22. For example, the backside interconnect structure 120 can be electrically connected to the source / drain region of the active device 21. In some embodiments, the TSV 44 can be directly connected to the RDL 112. The interconnect structure 120 and the TSV 44 can be connected to the RDL 112, respectively, and further electrically connected to the conductive connector 116.

[0064] Fig.13 The embodiment shown in includes dies 20 and 100 bonded together in a face-to-face configuration. Other embodiments are also contemplated in the present disclosure. For example, in Fig.17 In the embodiment of the present invention, the interconnect structure 50 and the bonding pad via 86 and the bonding pad 88 are omitted and replaced with a heat dissipation structure 130. The heat dissipation structure 130 may include one or more layers of high thermal conductivity materials (having a thermal conductivity greater than 10 Watts / meter Kelvin (W / m·K), also referred to as high-k materials or high-k materials), such as suitable nitrides (e.g., AlN, BN, etc.), suitable metal oxides (e.g., Y2O2, Y3Al5O 12 (yttrium aluminum garnet, YAG), Al2O2, BeO, etc.), suitable carbides (e.g., SiC, graphene, diamond-like carbon (DLC), diamond, etc.), combinations thereof, etc. TSVs 44 and guard rings 30 can be connected to heat dissipation structure 130. In addition, integrated circuit die 20 can be coupled to external devices (e.g., die 100) through backside interconnect structure 120 (when present). In some embodiments, a cover or heat sink structure can be located above and / or attached to heat dissipation structure 130.

[0065] In some embodiments, the signal may be transmitted through the back side of the die 20 through the TSV 44. In some embodiments, the back side interconnect structure 120 may be directly connected to the device 21. In addition, the signal may be transmitted to the back side of the die 20 using various paths. In some embodiments, the signal may be transmitted through the path (front side interconnect structure 24 / 26-->TSV 44-->redistribution structure 112-->connection 114 / 116). In some embodiments, the signal may be transmitted through the path (back side interconnect structure 120-->redistribution structure 112-->connection 114 / 116).

[0066] In each of the above-described embodiments, the redistribution structure 112 may be omitted, and the TSV 44 may be directly connected to the UBM 114. The UBM 114 may be formed to directly contact the exposed ends of the TSV 44.

[0067] exist Fig.14 middle, Fig.13 The package assembly is attached to the package substrate 420 using a conductive connector 116 to form a package structure 400. The package substrate 420 includes a substrate core 422, which can be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, etc. can also be used. In addition, the substrate core 422 can be an SOI substrate. Typically, the SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In another embodiment, the substrate core 422 is an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Optional materials for the core material include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. A laminate film such as Ajinomoto built-up film (ABF) or other laminate materials may be used for the substrate core 422 .

[0068] The substrate core 422 may include active devices and passive devices (not shown separately). Devices such as transistors, capacitors, resistors, combinations thereof, etc. may be used to generate the structural and functional requirements of the design for the system. The devices may be formed using any suitable method.

[0069] The substrate core 422 may also include metallization layers and vias and bonding pads 424 over the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers may be formed of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper) (where the vias interconnect the conductive material layers) and may be formed by any suitable process (such as deposition, damascene, etc.). In some embodiments, the substrate core 422 is substantially free of active and passive devices.

[0070] The conductive connectors 116 are reflowed to attach the UBM 114 to the bonding pads 424. The conductive connectors 116 connect the package assembly (including the RDL 112 and the interconnect structure 50) to the package substrate 420 (including the metallization layers of the substrate core 422). Thus, the package substrate 420 is electrically connected to the die 20. In some embodiments, passive devices 426 (e.g., SMDs) can be attached to the package substrate 420, for example, to the bonding pads 424.

[0071] In some embodiments, an underfill (not shown) is formed between the package assembly and the package substrate 420, surrounding the conductive connectors 116. The underfill may be formed by a capillary flow process after attaching the package assembly, or may be formed by any suitable deposition method before attaching the package assembly.

[0072] Fig.15A , Fig. 15B , Fig. 15C and Fig.15D A cross-sectional view and a plan view of an integrated circuit die 20 according to some embodiments are shown. These embodiments include dummy metallization patterns 28 between adjacent TSVs 44 in a TSV cluster 46. Details about this embodiment similar to those of previously described embodiments will not be repeated here.

[0073] In these embodiments, dummy metallization pattern 28 is located between adjacent TSVs 44 in TSV cluster 46. Fig. 15B , the dummy metallization pattern 28 extends in a “+” shape between four TSVs 44. In this example, the guard ring 30 extends on the outer edge of the TSV cluster 46 and does not extend between the TSVs 44 of the TSV cluster 46. In this embodiment, the dummy metallization pattern 28 extends from the guard ring 30 with no gap between the guard ring 30 and the dummy metallization pattern 28.

[0074] Fig. 15C Similar to Fig. 15B , and it also has gaps 502 between the guard ring 30 and the dummy metallization pattern 28 and at the intersections of the dummy metallization pattern 28. In this embodiment, there are two gaps 502 at the intersections of the dummy metallization pattern 28. By having gaps 502 where the dummy metallization pattern 28 will intersect other structures (e.g., 28 or 30) at right angles, the uniformity of the dummy metallization pattern 28 is improved because it is difficult for the plating process to grow structures accurately in corners or right angles.

[0075] Fig.15D Similar to Fig. 15C , and it has a single gap 502 in the middle of the "+" shape between portions of the dummy metallization pattern 28. In this embodiment, the gap 502 is located where the dummy metallization pattern 28 will intersect the structure at a right angle.

[0076] Although FIG. 15B to FIG. 15D TSV clusters 46 are shown with four TSVs 44 , but the embodiments are not limited to those numbers of TSVs 44 per TSV cluster 46 , and each may have more or fewer TSVs 44 per TSV cluster.

[0077] Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that incorporates intermediate verification of known good dies to increase yield and reduce costs.

[0078] Embodiments discussed herein may be discussed in a specific context, namely, a through-substrate via (TSV) cluster with reduced spacing between adjacent TSVs. In some embodiments, the TSV cluster has a merged guard ring wall between adjacent TSVs. In some embodiments, a dummy interconnect structure is located between adjacent TSVs of the TSV cluster in place of the merged guard ring wall. By having a merged guard ring wall or a dummy interconnect structure between adjacent TSVs of the TSV cluster, the spacing between adjacent TSVs can be reduced. Therefore, the total area consumed by the TSV cluster is reduced, and more area can be used for other functions of the device, or the device size can be reduced. In some embodiments, the disclosed TSV cluster may be applicable to a device (e.g., a chip or die) or a package (e.g., a system on an integrated chip (SoIC), a chip on wafer (CoW) packaging structure, or a wafer on wafer (WoW) packaging structure). By reducing the spacing between adjacent TSVs in a TSV cluster, the performance, power, and area cost of the device are improved. For example, in a 2×2 TSV cluster, the area cost of the disclosed TSV cluster is reduced by 25%-35% compared to a conventional TSV structure.

[0079] Embodiments include a device, the device including: a first die including a first surface and a second surface opposite to the first surface. The first die includes a plurality of through substrate vias (TSVs) exposed from the second surface of the first die. The device also includes a guard ring surrounding the plurality of TSVs. The device also includes a dummy metallization pattern surrounding the guard ring.

[0080] Embodiments may include one or more of the following features. A device wherein a guard ring extends between a plurality of TSVs. A guard ring surrounding a plurality of TSVs and extending between a plurality of TSVs is a continuous guard ring. The device further includes an active metallization pattern connected to an active device in a first die. The first die includes: a substrate, a first surface located on a first side of the substrate; a first interconnect structure located on a first side of the substrate, a guard ring, a dummy metallization pattern, and an active metallization pattern located in the first interconnect structure; and a second interconnect structure located on a second side of the substrate, the metallization pattern of the second interconnect structure being electrically coupled to at least one of the plurality of TSVs. A device wherein the first die further includes: a high-k material located on the first interconnect structure and the plurality of TSVs. The device further includes a second die bonded to a first surface of the first die, the first surface including a bonding pad. The dummy metallization pattern extends between the plurality of TSVs. The dummy metallization pattern extending between the plurality of TSVs is physically connected to a guard ring surrounding the plurality of TSVs. A gap separates the dummy metallization pattern extending between the plurality of TSVs and the guard ring. The gap separates the dummy metallization pattern at the intersection between the plurality of TSVs. The guard ring does not extend between the multiple TSVs.

[0081] An embodiment includes a method, the method including: forming a first tube core including a first surface and a second surface opposite to the first surface, wherein forming the first tube core includes: forming a first interconnect structure above a first substrate, the first interconnect structure including an active metallization pattern, a guard ring, and a dummy metallization pattern. The method also includes: forming a substrate through via (TSV) passing through the first interconnect structure and the first substrate, the guard ring surrounding the TSV in the first interconnect structure, and the dummy metallization pattern surrounding the guard ring. The method also includes: forming a bonding pad connected to the TSV and the active metallization pattern of the first interconnect structure above the first interconnect structure, the bonding pad being located on the first surface of the first tube core, and the TSV being exposed at the second surface of the first tube core. The method also includes: forming a second tube core including a first surface and a second surface opposite to the first surface. The method also includes: bonding the first surface of the first tube core to the first surface of the second tube core.

[0082] Embodiments may include one or more of the following features. A method wherein a guard ring extends between TSVs. A guard ring surrounding the TSVs and extending between the TSVs is a continuous guard ring. A dummy metallization pattern extends between the TSVs. A gap separates the dummy metallization pattern extending between the TSVs and the guard ring. The guard ring does not extend between the TSVs. The method further includes: forming a redistribution structure on a second surface of the first die, the redistribution structure electrically connected to the TSVs; forming a conductive connector on the redistribution structure; and bonding the first die to a package substrate with the conductive connector.

[0083] An embodiment includes a method, the method including: forming a first tube core including a first surface and a second surface opposite to the first surface, wherein forming the first tube core includes: forming a first interconnect structure above a first substrate, the first interconnect structure including an active metallization pattern, a guard ring, and a dummy metallization pattern. The method also includes: forming a through substrate via (TSV) passing through the first interconnect structure and the first substrate, the guard ring is a continuous structure surrounding the TSV in the first interconnect structure and extending between the TSVs in the first interconnect structure, and the dummy metallization pattern surrounds the guard ring. The method also includes: forming a second interconnect structure on the first substrate, the second interconnect structure being located on a side of the first substrate opposite to the first interconnect structure.

[0084] Embodiments may include one or more of the following features. A method wherein the active metallization pattern is connected to active devices in the first die.

[0085] Some embodiments of the present application provide a semiconductor device, comprising: a first die, comprising a first surface and a second surface opposite to the first surface, wherein the first die comprises: a plurality of through substrate vias (TSVs) exposed from the second surface of the first die; a guard ring surrounding the plurality of through substrate vias; and a dummy metallization pattern surrounding the guard ring. In some embodiments, the guard ring extends between the plurality of through substrate vias.

[0086] In some embodiments, the guard ring surrounding the plurality of substrate through vias and extending between the plurality of substrate through vias is a continuous guard ring. In some embodiments, the first die further comprises: an active metallization pattern connected to active devices in the first die; a substrate, the first surface being located on a first side of the substrate; a first interconnect structure located on the first side of the substrate, the guard ring, the dummy metallization pattern, and the active metallization pattern being located in the first interconnect structure; and a second interconnect structure located on the second side of the substrate, the metallization pattern of the second interconnect structure being electrically coupled to at least one of the plurality of substrate through vias. In some embodiments, the first die further comprises: a high-k material located on the first interconnect structure and the plurality of substrate through vias. In some embodiments, the semiconductor device further comprises: a second die bonded to the first surface of the first die, the first surface comprising a bonding pad. In some embodiments, the dummy metallization pattern extends between the plurality of substrate through vias. In some embodiments, the dummy metallization pattern extending between the plurality of substrate through vias is physically connected to the guard ring surrounding the plurality of substrate through vias. In some embodiments, a gap separates the dummy metallization pattern extending between the plurality of substrate through vias and the guard ring. In some embodiments, gaps will separate the dummy metallization pattern at intersections between the plurality of through substrate vias. In some embodiments, the guard ring does not extend between the plurality of through substrate vias.

[0087] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first tube core including a first surface and a second surface opposite to the first surface, wherein forming the first tube core includes: forming a first interconnect structure above a first substrate, the first interconnect structure including an active metallization pattern, a guard ring and a dummy metallization pattern; forming a substrate through via (TSV) passing through the first interconnect structure and the first substrate, the guard ring surrounding the substrate through via in the first interconnect structure, and the dummy metallization pattern surrounding the guard ring; and forming a bonding pad connected to the substrate through via and the active metallization pattern of the first interconnect structure above the first interconnect structure, the bonding pad being located on the first surface of the first tube core, and the substrate through via being exposed at the second surface of the first tube core; forming a second tube core including a first surface and a second surface opposite to the first surface; and bonding the first surface of the first tube core to the first surface of the second tube core.

[0088] In some embodiments, the guard ring extends between the substrate through holes. In some embodiments, the guard ring surrounding the substrate through holes and extending between the substrate through holes is a continuous guard ring. In some embodiments, the pseudo-metallization pattern extends between the substrate through holes. In some embodiments, a gap separates the pseudo-metallization pattern extending between the substrate through holes and the guard ring. In some embodiments, the guard ring does not extend between the substrate through holes. In some embodiments, the method further includes: forming a redistribution structure on the second surface of the first die, the redistribution structure being electrically connected to the substrate through holes; forming a conductive connector on the redistribution structure; and bonding the first die to a package substrate with the conductive connector.

[0089] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first tube core including a first surface and a second surface opposite to the first surface, wherein forming the first tube core includes: forming a first interconnect structure above a first substrate, the first interconnect structure including an active metallization pattern, a guard ring, and a dummy metallization pattern; forming a substrate through via (TSV) passing through the first interconnect structure and the first substrate, the guard ring being a continuous structure surrounding the substrate through via in the first interconnect structure and extending between the substrate through vias in the first interconnect structure, the dummy metallization pattern surrounding the guard ring; and forming a second interconnect structure on the first substrate, the second interconnect structure being located on a side of the first substrate opposite to the first interconnect structure.

[0090] In some embodiments, the active metallization pattern is connected to active devices in the first die.

[0091] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising: A first tube core includes a first surface and a second surface opposite to the first surface, wherein the first tube core includes: a plurality of through substrate vias (TSVs) exposed from the second surface of the first die; a guard ring surrounding the plurality of through substrate vias; and A dummy metallization pattern surrounds the guard ring.

2. The semiconductor device according to claim 1, wherein The guard ring extends between the plurality of through substrate vias.

3. The semiconductor device according to claim 2, wherein: The guard ring surrounding the plurality of through substrate vias and extending between the plurality of through substrate vias is a continuous guard ring.

4. The semiconductor device according to claim 1, wherein: The first die also includes: an active metallization pattern connected to active devices in the first die; a substrate, the first surface being located on a first side of the substrate; a first interconnect structure located on the first side of the substrate, the guard ring, the dummy metallization pattern, and the active metallization pattern being located in the first interconnect structure; and A second interconnect structure is located on a second side of the substrate, a metallization pattern of the second interconnect structure being electrically coupled to at least one of the plurality of through substrate vias.

5. The semiconductor device according to claim 4, wherein: The first die also includes: A high-k material is disposed on the first interconnect structure and the plurality of substrate through vias.

6. The semiconductor device according to claim 1, further comprising: A second die is bonded to the first surface of the first die, the first surface including bonding pads.

7. The semiconductor device according to claim 1, wherein The dummy metallization pattern extends between the plurality of substrate through vias.

8. The semiconductor device according to claim 7, wherein: The dummy metallization pattern extending between the plurality of through substrate vias is physically connected to the guard ring surrounding the plurality of through substrate vias.

9. A method of forming a semiconductor device, comprising: forming a first die including a first surface and a second surface opposite to the first surface, wherein forming the first die includes: forming a first interconnect structure over a first substrate, the first interconnect structure comprising an active metallization pattern, a guard ring, and a dummy metallization pattern; forming a through substrate via (TSV) passing through the first interconnect structure and the first substrate, the guard ring surrounding the through substrate via in the first interconnect structure, and the dummy metallization pattern surrounding the guard ring; and forming a bonding pad connected to the through substrate via and the active metallization pattern of the first interconnect structure over the first interconnect structure, the bonding pad being located on the first surface of the first die, the through substrate via being exposed at the second surface of the first die; forming a second die including a first surface and a second surface opposite the first surface; and The first surface of the first die is bonded to the first surface of the second die.

10. A method of forming a semiconductor device, comprising: forming a first die including a first surface and a second surface opposite to the first surface, wherein forming the first die includes: forming a first interconnect structure over a first substrate, the first interconnect structure comprising an active metallization pattern, a guard ring, and a dummy metallization pattern; forming a through substrate via (TSV) passing through the first interconnect structure and the first substrate, the guard ring being a continuous structure surrounding the substrate via in the first interconnect structure and extending between the substrate vias in the first interconnect structure, the dummy metallization pattern surrounding the guard ring; and A second interconnect structure is formed on the first substrate, the second interconnect structure being located on an opposite side of the first substrate from the first interconnect structure.

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