Semiconductor device and forming method thereof

Abstract

An embodiment is a device including a first die, and a substrate includes a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to a second surface of the substrate, the through substrate via electrically coupled to the metallization pattern in the first interconnect structure. The device also includes one or more material-filled trench structures extending into the substrate from the second surface of the substrate, the one or more material-filled trench structures being electrically isolated from the substrate vias. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from the iterative reduction of the minimum component size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, there is a demand for smaller and more creative packaging technologies for semiconductor dies. An example of such a packaging system is package-on-package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables the production of semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor device, comprising: a first die, comprising: a substrate, comprising a first surface and a second surface opposite to the first surface; an active device, located on the first surface of the substrate; a first interconnect structure, located on the first surface of the substrate; a substrate through hole, extending through the first interconnect structure and the substrate to the second surface of the substrate, the substrate through hole being electrically coupled to a metallization pattern in the first interconnect structure; and one or more material-filled trench structures, extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the substrate through hole.

[0004] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first tube core including a substrate, the substrate including a first surface and a second surface opposite to the first surface; forming an active device on the first surface of the substrate; forming a first interconnect structure on the first surface of the substrate; forming a substrate through hole extending through the first interconnect structure and the substrate to the second surface of the substrate, the substrate through hole being electrically coupled to a metallization pattern in the first interconnect structure; and forming one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the substrate through hole.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first tube core including a first surface and a second surface opposite to the first surface, wherein forming the first tube core includes: forming a first interconnect structure above a first substrate, the first interconnect structure including a metallization pattern; forming a substrate through hole passing through the first interconnect structure and the first substrate; forming a bonding pad above the first interconnect structure and the substrate through hole, the bonding pad being located on the first surface of the first tube core; forming a groove in the second surface of the first tube core; filling the groove in the second surface of the first tube core with a first material; recessing the second surface of the first tube core to expose the substrate through hole; and forming a bonding pad on the recessed second surface of the first tube core; and directly bonding the bonding pad of the first tube core to the bonding pad of the second tube core. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figures 1 to 13 , Fig.14A , Fig. 14B , Fig. 14C and Figures 15 to 18 Cross-sectional and plan views illustrate intermediate stages in the formation of structures according to embodiments.

[0008] Figures 19 to 22 A cross-sectional view illustrating an intermediate stage in the formation of a package in accordance with an embodiment.

[0009] Figure 23 to Figure 25 A cross-sectional view is shown of an intermediate stage in the formation of a die in accordance with an embodiment.

[0010] Fig.26 and Fig. 27 A cross-sectional view of a TSV according to an embodiment is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] The embodiments discussed herein may be discussed in a specific context, namely a warpage adjustment process that can control die warpage. In some embodiments, the warpage adjustment process is applied to the back side of the die. For example, the warpage adjustment structure may include one or more substrate through vias (TSVs) in the back side of the die. The warpage adjustment TSV does not necessarily extend completely through the substrate or die, but in some embodiments, partially extends into the back side of the substrate. In some embodiments, the warpage adjustment TSV may be filled with a tensile material, such as a conductive material. In some embodiments, the warpage adjustment TSV may be filled with a compressive material, such as a dielectric material. Compressive materials may be used for dies with a convex warpage (sometimes referred to as a crying or frowning warpage) on the back side. Tensile materials may be used for dies with a concave warpage (sometimes referred to as a smiling warpage) on the back side. By having a warpage adjustment TSV, the warpage control of the die is improved, which may improve the warpage control for a packaging structure, such as a 3DIC including a die. In addition, in embodiments having a conductive TSV as a warpage adjustment TSV, the heat dissipation of the die may be improved.

[0014] In addition, the teachings of the embodiments of the present disclosure are applicable to any device or package that requires warpage control. Other embodiments contemplate other applications, such as different packaging types or different configurations that are apparent to a person of ordinary skill in the art reading the embodiments of the present disclosure. It should be noted that the embodiments discussed herein may not necessarily show every component or part that may be present in the structure. For example, multiple components may be omitted from the accompanying drawings, such as when a discussion of one of the components may be sufficient to convey various aspects of the embodiment. In addition, the method embodiments discussed herein may be discussed as being implemented in a particular order; however, other method embodiments may be implemented in any logical order.

[0015] Figures 1 to 13 , Fig.14A , Fig. 14B , Fig. 14C and Figures 15 to 18 Cross-sectional and plan views are shown of intermediate stages in forming a structure / die 20 in a prior TSV process in accordance with some embodiments.

[0016] Figure 1 A cross-sectional view of a structure 20 according to some embodiments is shown. The structure 20 will be packaged in a subsequent process to form an integrated circuit package. The structure 20 may include a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof.

[0017] The structure 20 may be formed in a wafer that may include different device regions that are segmented in subsequent steps to form multiple integrated circuit dies. The structure 20 may be processed according to an applicable manufacturing process to form an integrated circuit. For example, the structure 20 includes a substrate 22 (such as doped or undoped silicon) or an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 22 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates may also be used, such as multilayer or gradient substrates. The substrate 22 has an active surface (e.g., Figure 1 the upward-facing surface) (sometimes referred to as the front side) and the inactive surface (e.g. Figure 1 The downward-facing surface (sometimes called the dorsal side) is the central surface of the brain.

[0018] Device 23 may be formed at the front side of substrate 22. Device 23 may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, etc., or a combination thereof. An interlayer dielectric (ILD) (not shown separately) is located over the front side of substrate 22. The ILD surrounds and may cover device 23. The ILD may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0019] A conductive plug (not shown separately) extends through the ILD to electrically and physically couple the device. For example, when the device is a transistor, the conductive plug can couple the gate and source / drain regions of the transistor. The conductive plug can be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or a combination thereof.

[0020] The interconnect structure 24 is located above the ILD and the conductive plug. The interconnect structure 24 can be formed by, for example, metallization patterns 28, 30 in a dielectric layer 26 on the ILD. In these embodiments, the metallization patterns 28, 30 are formed in the middle of the line process and the back end of the line process. The metallization patterns 28, 30 include metal lines and vias formed in one or more low-k dielectric layers 26. The metallization patterns can be formed using any suitable process, such as a single damascene process, a dual damascene process, a plating process, a combination thereof, etc.

[0021] The metallization patterns 28, 30 include active metallization patterns 28 and guard rings 30. The active metallization patterns 28 of the interconnect structure 24 interconnect the devices to form an integrated circuit. The active metallization patterns 28 are electrically coupled to the devices through conductive plugs. The metallization patterns may also include dummy metallization patterns (not shown) electrically isolated from the devices 23 of the structure 20.

[0022] The guard ring 30 is formed around the area of ​​the subsequently formed through substrate via (TSV) (see, for example, the opening 32 discussed below). The guard ring 30 is formed simultaneously and by the same process as the active metallization pattern 28. The guard ring 30 can reduce the leakage current between the subsequently formed TSV and the substrate 22 and other structures in the interconnect structure 24. In addition, the TSV can introduce mechanical stress, and the guard ring 30 can provide stress relief during the manufacture and operation of the device. In addition, the guard ring 30 can provide electrical isolation between the TSV and nearby active devices and metallization patterns. The dummy metallization pattern can provide a more uniform pattern density in the interconnect structure 24, which helps with planarization and process consistency, such as during a chemical mechanical polishing (CMP) process.

[0023] After forming interconnect structure 24, a mask (not shown) is formed and patterned on interconnect structure 24. In some embodiments, the mask is a photoresist and may be formed by spin coating, etc., and may be exposed to light for patterning. The pattern of the photoresist corresponds to a through substrate via (TSV) 36 (see, e.g., FIG. 1 ) that is subsequently formed. Figure 4 ). Patterning forms at least one opening through the photoresist to expose the interconnect structure 24. In some embodiments, before masking, a stop layer (not shown), such as a chemical mechanical polishing (CMP) stop layer, is deposited over the top surface of the interconnect structure 24. The CMP stop layer can be used to prevent the subsequent CMP process from removing too much material by resisting the subsequent CMP process and / or by providing a detectable stop point for the subsequent CMP process. In some embodiments, the CMP stop layer may include one or more dielectric material layers. Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, etc.), nitrides (such as SiN, etc.), oxynitrides (such as SiON, etc.), oxycarbides (such as SiOC, etc.), carbonitrides (such as SiCN, etc.), carbides (such as SiC, etc.), combinations thereof, etc., and may be formed using spin coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), etc., or combinations thereof.

[0024] In addition, Figure 1 In the embodiment of the present invention, the patterned mask is used as a mask during the etching process to remove the exposed and underlying portions of the dielectric layer 26 of the interconnect structure 24 and the substrate 22. A single etching process can be used to etch the opening 32 in the interconnect structure 24 and the substrate 22, or a first etching process can be used to etch the interconnect structure 24, and a second etching process can be used to etch the substrate 22. In some embodiments, the opening 32 is formed using a plasma dry etching process and a reactive ion etching (RIE) process (such as a deep RIE (DRIE) process). In some embodiments, the DRIE process includes an etching cycle and a passivation cycle, wherein the etching cycle uses, for example, SF6, and the passivation cycle uses, for example, C4F8. A highly anisotropic etching process can be achieved using a DRIE process with a passivation cycle and an etching cycle. In some embodiments, the etching process can be any acceptable etching process, such as by wet etching or dry etching.

[0025] After forming the opening 32, the photoresist is removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like.

[0026] exist Figure 2, a conductive material 34 is formed on the interconnect structure 24 and in the opening 32. In some embodiments, before forming the conductive material 34, a liner layer (not shown separately) and a seed layer (not shown separately) are formed on the interconnect structure and in the opening 32. For example, the liner layer is conformally deposited on the interconnect structure 24 and on the bottom surface and sidewalls of the opening 32. In some embodiments, the liner layer includes one or more dielectric material layers and can be used to physically and electrically isolate the subsequently formed through-hole 36 from the substrate 22. Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, etc.), nitrides (such as SiN, etc.), oxynitrides (such as SiON, etc.), combinations thereof, etc. The liner layer can be formed using CVD, PECVD, ALD, etc., or combinations thereof.

[0027] In a subsequent step, a seed layer is formed over the pad layer. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. In some embodiments, a barrier layer (not shown) may be formed on the pad layer before forming the seed layer. The barrier layer may include Ti, TiN, or the like, or a combination thereof.

[0028] Conductive material 34 is formed on the seed layer and fills opening 32. Conductive material 34 may be formed by plating, such as electroplating including electrochemical plating, electroless plating, etc. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc.

[0029] After forming conductive material 34, an annealing process is then performed. The annealing process may be performed to prevent subsequent extrusion (sometimes referred to as TSV pumping) of the conductive material of TSV 36. TSV pumping is caused by a coefficient of thermal expansion (CTE) mismatch between conductive material 34 and substrate 22, and may cause damage to structures above the TSV (e.g., metallization patterns).

[0030] After the annealing process, a planarization process is performed to remove the conductive material 34, the seed layer, and the portion of the liner layer outside the opening 32 to form a TSV 36. Figure 3 . The top surface of TSV 36 and the topmost dielectric layer 26 of interconnect structure 24 are coplanar after a planarization process within process variations. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, the upper portion of TSV 36 (formed in interconnect structure 24) has a greater width than the lower portion of TSV 36 (formed in substrate 22). In some embodiments, the width of TSV 36 is constant through interconnect structure 24 and substrate 22.

[0031] refer to Figure 4 ,exist Figure 3 The interconnect structure 40 is formed above the structure. The interconnect structure 40 includes a dielectric layer 42, a metallization pattern and a via 44, and a top metal 46. In some embodiments, the metallization pattern 44 can be a top metal metallization pattern, and the top metal 46 can be omitted or include multiple top metal layers. Figure 4 4. The interconnect structure 40 is connected to the active metallization pattern 28 and TSV 36 of the interconnect structure 24 through the metallization pattern and via formed in the dielectric layer 42. The metallization pattern and via can be formed using similar processes and materials as the interconnect structure 24, and will not be described again here. In some embodiments, there is more than one top metal 46 layer, such as two top metal layers.

[0032] In some embodiments, dielectric layer 42 is the same material as dielectric layer 26 of interconnect structure 24, e.g., a low-k dielectric. In other embodiments, dielectric layer 42 is formed of a silicon-containing material (which may or may not include oxygen). For example, dielectric layer 42 may include an oxide such as silicon oxide, a nitride such as silicon nitride, etc.

[0033] The metallization pattern and the via 44 and the top metal 46 can be formed using any suitable process, such as a single damascene process, a dual damascene process, a plating process, a combination thereof, and the like. Examples of forming the metallization pattern and the via 44 and the top metal 46 by a damascene process include: etching the dielectric layer 42 to form an opening; depositing a conductive barrier layer into the opening; plating a metal material, such as copper or a copper alloy; and performing planarization to remove excess portions of the metal material. In other embodiments, the formation of the dielectric layer 42, the metallization pattern and the via 44 and the top metal 46 may include: forming the dielectric layer 42; patterning the dielectric layer 42 to form an opening; forming a metal seed layer (not shown); forming a patterned plating mask (such as a photoresist) to cover some portions of the metal seed layer while leaving other portions exposed; plating the metallization pattern and the via 44 and the top metal 46; removing the plating mask; and etching undesired portions of the metal seed layer. The metallization pattern and the via 44 and the top metal 46 may be made of tungsten, cobalt, nickel, copper, silver, gold, aluminum, and the like, or a combination thereof. In some embodiments, top metal 46 is thicker than metallization pattern 44 , such as three times thicker, five times thicker, or any suitable thickness ratio between metallization layers.

[0034] Figure 5A dielectric layer 50 is shown formed over dielectric layer 42 and top metal 46, and pad vias 52 are formed in dielectric layer 50 and contact pads 56 are formed in passivation layer 54. In some embodiments, dielectric layer 50 is formed of the same material as dielectric layer 42. In some embodiments, dielectric layer 50 may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.; a nitride such as silicon nitride, etc.; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; etc.; or a combination thereof. Dielectric layer 50 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. Dielectric layer 50 may have a flush upper surface within process variations.

[0035] Although Figure 5 TSVs 36 are shown connected directly to interconnect structure 40 , but in some embodiments, one or more of TSVs 36 may be connected directly to interconnect structure 24 .

[0036] In addition, Figure 5 In the embodiment of the present invention, a passivation layer 54 is formed over the dielectric layer 50. In some embodiments, the passivation layer 54 is formed of the same material as the dielectric layer 42. In some embodiments, the passivation layer 54 may be a polymer such as (PBO), polyimide (BCB), etc.; a nitride such as silicon nitride, etc.; an oxide such as silicon oxide, (PSG), (BSG), (BPSG), etc.; etc.; or a combination thereof. The passivation layer 54 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. The passivation layer 54 may have a flush upper surface within process variations.

[0037] Figure 5 Also shown is a pad via 52 formed in dielectric layer 50 and a contact pad 56 formed in passivation layer 54. Pad via 52 and contact pad 56 are connected to top metal 46. Pad via 52 and contact pad 56 may be formed using any suitable process, such as a single damascene process, a dual damascene process, a combination thereof, etc. A dual damascene process will be described.

[0038] In some embodiments, a photoresist (not shown) is formed and patterned on the dielectric layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the opening for the contact pad 56. In addition, the passivation layer 54 is patterned using the patterned photoresist as a mask to form an opening, wherein the patterning process stops on the dielectric layer 50 (or the etch stop layer, if present). The exposed portion of the passivation layer 54 can be removed, such as by using an acceptable etching process, such as by wet etching and / or dry etching.

[0039] The photoresist is removed and can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Next, another photoresist (not shown) is formed and patterned on the patterned passivation layer 54 and in the opening through the passivation layer 54. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the opening for the pad via 52. The dielectric layer 50 is patterned using the patterned photoresist as a mask to form an opening, wherein the patterning process exposes a portion of the top metal 46. The exposed portion of the dielectric layer 50 can be removed, such as by using an acceptable etching process, such as by wet etching and / or dry etching.

[0040] The photoresist is removed, and pad vias 52 and contact pads 56 are formed in the openings. In some embodiments, a barrier layer may be formed in the openings before forming pad vias 52 and contact pads 56. In some embodiments, the barrier layer may include Ti, TiN, etc., or a combination thereof. Pad vias 52 and contact pads 56 may be formed by processes and materials similar to top metal 46 and vias 44, and are not described again herein. For example, contact pads 56 may be formed of or include copper, aluminum, or an alloy thereof.

[0041] The top surface of contact pad 56 is coplanar (within process variations) with the top surface of passivation layer 54. Planarization is achieved by a chemical mechanical polishing (CMP) process or a mechanical grinding process.

[0042] exist Figure 6 In the embodiment, the grooves 60 are formed by an etching process. These grooves 60 can be used in a cutting process to separate the structure 20 into a plurality of dies 20A and 20B (see, for example, Fig.12 ). In some embodiments, trench 60 is formed through passivation layer 54, dielectric layer 50, interconnect structures 40 and 24, and partially into substrate 22. In some embodiments, the etching process is a plasma etching process or the like.

[0043] exist Figure 7 middle, Figure 6 The structure 20 is flipped over and attached to a substrate 70. The substrate 70 may be referred to as a carrier substrate 70. The carrier substrate 70 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 70 may be a wafer so that a plurality of structures 20 may be attached to the carrier substrate 70 at the same time. The structure 20 may be attached by a bottom anti-reflective coating (BARC) 72 between the structure 20 and the carrier substrate 70. The BARC 72 may fill the trench 60. The BARC 72 may be a polymer-based material.

[0044] In some embodiments, a release layer (not shown) is formed on the carrier substrate 70, and the structure 20 and the BARC 72 are attached to the release layer. The release layer can be formed of a polymer-based material that can be removed from the upper structure to be formed in a subsequent step together with the carrier substrate 70. In some embodiments, the release layer is a thermal release material based on epoxy resin that loses its viscosity when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer can be an ultraviolet (UV) glue that loses its viscosity when exposed to UV light. The release layer can be dispensed and cured as a liquid, can be a laminated film laminated to the carrier substrate 70, or can be similar. The top surface of the release layer can be flush and substantially planar within process variations.

[0045] exist Figure 8 In the embodiment of the present invention, trenches 78 are formed in the back side of the substrate 22 of the structure 20. These trenches 78 will be subsequently filled with material to form a warpage adjustment structure (see, e.g., Fig.11 ). Grooves 78 may be formed in a similar manner as openings 32, and the process is not repeated here. In some embodiments, grooves 78 have different widths and shapes depending on the warpage adjustment characteristics of structure 20, as discussed further below. In some embodiments, grooves 78 are formed partially but not completely through substrate 22.

[0046] exist Fig. 9 In the embodiment of the present invention, a warpage adjustment material 80 is formed on the back side of the substrate 22 and in the trench 78. In some embodiments, the warpage adjustment material 80 includes a liner layer and a seed layer as discussed above for the TSV 36, and is not repeated here. In some embodiments, the warpage adjustment material 80 is a tensile material, such as a conductive material, and in some embodiments, the warpage adjustment material 80 is a compressive material, such as a dielectric material. In embodiments with tensile warpage adjustment material 80, the warpage adjustment material 80 includes a conductive material, such as gold, silver, copper, iron, tin, aluminum, etc., or alloys thereof. In embodiments with compressive warpage adjustment material 80, the warpage adjustment material 80 includes a dielectric material, such as an oxide (such as silicon oxide, aluminum oxide, etc.), a nitride (such as SiN, etc.), an oxynitride (such as SiON, etc.), an oxycarbide (such as SiOC, etc.), a carbonitride (such as SiCN, etc.), a carbide (such as SiC, etc.), combinations thereof, etc.

[0047] Compression materials can be used for structures with a backside having a convex warp profile or tendency (sometimes called a cry or frown warp). Stretch materials can be used for structures with a backside having a concave warp profile or tendency (sometimes called a smile warp). In some embodiments, a combination of stretch materials and compression materials are used for some structures.

[0048] exist Fig.10In the process, a planarization process is performed to remove portions of the warpage adjustment material 80 (and other layers present, such as a seed layer and a liner layer) located outside the trench 78 to form a warpage adjustment structure 82 (also referred to as a warpage adjustment TSV 82). In some embodiments, some of the warpage adjustment structures 82 are filled with a tensile material (e.g., a conductive material) while other warpage adjustment structures are filled with a compressive material (e.g., a dielectric material). The top surface of the warpage adjustment structure 82 and the backside surface of the substrate 22 are coplanar after the planarization process within process variations. The planarization process may be, for example, a chemical mechanical polishing (CMP), a grinding process, etc.

[0049] Warp tuning structures 82 are electrically isolated from TSVs 36 of die 20A / 20B and interconnect structures 24 and 40. As discussed above and below, warp tuning structures are used to help control die warpage and are not used for electrical connection within die 20A / 20B and subsequent packaging structures.

[0050] By having the warpage adjustment structure 82, the warpage control of the die 20A / 20B is improved. Therefore, the yield of the die is improved. In addition, due to the improved planarity of the die 20A / 20B, the reliability of the electrical connection between the die 20A / 20B and other components in the package structure is improved. Therefore, the reliability and performance of the package structure are improved.

[0051] exist Fig.11 In the embodiment of the present invention, the structure 20 is thinned by thinning the substrate 22 before subsequent singulation. The thinning may be performed by a planarization process such as a mechanical grinding process or a CMP process. The thinning process thins the substrate 22 and the warpage adjustment structure 82 and exposes the saw trench 60 and the potential BARC 72 in the saw trench 60. After thinning, the saw trench 60 extends through the substrate 22.

[0052] exist Fig.12 , the substrate 22 is further thinned, and the structure 20 is shown to be segmented into integrated circuit dies 20A and 20B. The cut trenches 60, BARC 72, and the remaining substrate 22 between the trenches 60 are removed. These structures can be removed by a patterning process such as an etching process. After the etching process, the segmented dies 20A and 20B can be removed from the carrier substrate 70 and placed on a carrier substrate 90. The carrier substrate 90 can be similar to the carrier substrate 70, and will not be described again here.

[0053] After the thinning step and the singulation process, warpage adjustment structures 82 remain in the backside of dies 20A and 20B. Warpage adjustment structures 82 extend from the backside of substrate 22 to overlap TSVs 36 extending from the frontside of substrate 22. In other words, the sum of the depths of one of TSVs 36 and one of warpage adjustment structures 82 is greater than the thickness of the thinned substrate 22.

[0054] Next, if Fig.13 As shown in , a gap filling process is performed to seal the separated tube core 20A and 20B in the sealant 98. After formation, the sealant 98 seals the tube core 20A and 20B. The sealant 98 may include an oxide. Alternatively, the sealant 98 may be a molding compound, a molded underfill, a resin, an epoxy resin, etc. The sealant 98 can be applied by compression molding, transfer molding, etc., and can be applied in a liquid or semi-liquid form, and then subsequently cured.

[0055] Fig.14A , Fig. 14B and Fig. 14C 1 and 2 show plan views of various shapes of the warpage adjustment structure 82. Fig.14A In the embodiment, the warpage adjustment structure 82 is a groove shape having a width W1. In some embodiments, the width W1 is in a range from 0.36 μm to 10.8 μm. Fig. 14B In the embodiment, the warpage adjustment structure 82 is a circular shape having a width (or diameter) W2. In some embodiments, the width W2 is in the range from 0.3 μm to 5 μm. Fig. 14C , the warpage adjustment structure 82 is a cross shape having a width W3. In some embodiments, the width W3 is in a range from 0.36 μm to 10.8 μm.

[0056] Fig.15 Shows Fig.13 A plan view of the structure, where Fig.13 A cross-sectional view along Fig.15 Line AA. Fig.15 Various shapes of the warpage adjustment structures 82 adjacent to the TSVs 36 in the dies 20A and 20B are shown. Fig.15 3 and 32. However, in some embodiments, the dies 20A and 20B may have different configurations. In addition, in some embodiments, the dies 20A and 20B may have more or fewer TSVs 36 and warpage adjustment structures 82.

[0057] exist Fig.16 In the embodiment of the present invention, the back side of the substrate 22 is recessed to expose the sidewalls of the TSV 36 and the warpage adjustment structure 82. The recessing process forms a groove 102 on the back side of the dies 20A and 20B around the TSV 36 and the warpage adjustment structure 82. The recessing process can be performed by an acceptable etching process, such as by wet etching and / or dry etching.

[0058] exist Fig.17In the embodiment, an isolation layer 106 is formed in the groove 102 and on the sidewalls of the TSV 36 and the warpage adjustment structure 82. In some embodiments, the isolation layer 106 includes an oxide such as silicon oxide, a nitride such as silicon nitride, etc. In some embodiments, the isolation layer 106 can be a polymer-based material. In embodiments where the isolation layer 106 covers the TSV 36 or the warpage adjustment structure 82, a planarization process can be performed to re-expose the TSV 36.

[0059] exist Fig.18 In the embodiment, dielectric layer 110 is formed over isolation layer 106, encapsulant 98, TSV 36, and warpage adjustment structure 82. Fig.18 One dielectric layer 110 is shown, but more dielectric layers may be formed, such as, for example, three dielectric layers. Dielectric layer 110 may provide a dielectric bonding function and may be considered a bonding dielectric layer 110. In some embodiments, more dielectric layers, such as a planarization dielectric layer and an etch stop layer, may be formed before bonding layer 110, so that bonding layer 110 is formed on these layers.

[0060] In some embodiments, the dielectric layer 110 is a silicon-containing material. For example, the dielectric layer 110 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, or a combination thereof.

[0061] In addition, Fig.18 In the embodiment, a bonding pad 112 is formed in the dielectric layer 110. The formation process and materials of the bonding pad 112 may be similar to those of the contact pad 56 described above, and will not be described again herein.

[0062] Figures 19 to 22 A cross-sectional view of a package structure formed in accordance with some embodiments is shown. Fig.19 A package structure 200 is shown. Package structure 200 includes: a substrate 202, similar to substrate 22 of structure 20; and an interconnect structure 204, including bonding pads 206. Interconnect structure 204 and bonding pads 206 may be similar to interconnect structures 24 and 40 and pads 56 and 112 described above, respectively, and are not described again herein. Package structure 200 may be referred to as die 200.

[0063] exist Fig. 20In the embodiment of the present invention, the integrated circuit die 20A / 20B is bonded to the package structure 200. Bonding the integrated circuit die 20A / 20B to the package structure 200 can be achieved by direct bonding, wherein a metal-to-metal direct bond (between the bonding pads 112 and 206) and a dielectric-to-dielectric bond (such as a Si-O-Si bond between the integrated circuit die 20A / 20B and the surface dielectric layer of the package structure 200) are formed. In addition, there can be a single integrated circuit die 20A / 20B or multiple dies 20A / 20B bonded to the same package structure 200. The multiple dies 20A / 20B bonded to the same package structure 200 can be exactly the same as each other or different from each other to form a homogeneous or heterogeneous structure. In some embodiments, the package structure includes multiple package structures 200 and multiple integrated circuit dies 20A / 20B.

[0064] The die 20A / 20B is arranged to face downward so that the back side of the die 20A / 20B faces the package structure 200 and the front side of the die 20A / 20B faces away from the package structure 200. The die 20A / 20B is bonded to the package structure 200 at the interface 208. Fig. 20 As shown, the direct bonding process directly bonds the topmost dielectric layer of the interconnect structure 204 of the package structure 200 to the topmost dielectric layer 110 of the die 20A / 20B at the interface 208 by fusion bonding. In an embodiment, the bond between the topmost dielectric layer of the interconnect structure 204 and the topmost dielectric layer 110 of the die 20A / 20B can be an oxide-to-oxide bond. The direct bonding process also directly bonds the bond pad 112 of the die 20A / 20B to the bond pad 206 of the package structure 200 at the interface 108 by direct metal-to-metal bonding. Therefore, the electrical connection between the die 20A / 20B and the package structure 200 is provided by the physical connection of the bond pad 112 to the bond pad 206.

[0065] As an example, the direct bonding process begins by aligning the die 20A / 20B with the package structure 200, for example by aligning the bond pads 112 with the bond pads 206. When the die 20A / 20B and the package structure 200 are aligned, the bond pads 112 may overlap with the corresponding bond pads 206. Next, the direct bonding includes a pre-bonding step during which the die 20A / 20B is placed in contact with the package structure 200. The direct bonding process continues with an anneal, for example, at a temperature between 150° C. and 400° C. for a duration between 0.5 hours and 3 hours, so that the copper in the bond pads 112 and the bond pads 206 interdiffuse with each other and thereby form a direct metal-to-metal bond.

[0066] In addition, Fig. 20In the embodiment of the present invention, die 220 is bonded to the back side of the adjacent package structure 200 of die 20A / 20B. In some embodiments, die 20A / 20B is a memory structure, such as a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.). In some embodiments, die 220 is a dummy structure. For example, dummy structure 220 can be used to improve the warpage control of the package structure. In some embodiments, die 220 includes substrate 220A and bonding structure 220B. Die 220 can be formed in a process similar to die 20, and will not be described again here.

[0067] Next, if Fig. 20 As shown in , a gap filling process is performed to seal the package structure 200 and the tube core 220 in the sealant 224. After formation, the sealant 224 seals the package structure 200 and the tube core 220. The sealant 224 may include an oxide. Alternatively, the sealant 224 may be a molding compound, a molded underfill, a resin, an epoxy resin, etc. The sealant 224 can be applied by compression molding, transfer molding, etc., and can be applied in a liquid or semi-liquid form, and then subsequently cured.

[0068] exist Fig.21 In some embodiments, the backside structure 300 is attached to the backside of the package structure 200 and the backside of the die 220. In some embodiments, the backside structure 300 is attached to the backside of the package structure 200 and the backside of the die 220 with an adhesive 230. Fig. 20 The back side of the structure of the package structure 200 is provided with a thermal structure 310. The adhesive 230 may be a thermal interface material (TIM), a die attach film (DAF), or the like. For example, the adhesive 230 may be formed of a TIM such as a solder paste, a polymeric material, or the like, which may be dispensed on the back side of the package structure 200 and the back side of the die 220 and / or on the back side structure 300. The back side package 300 includes a substrate 302, a thermal structure 310, and a back side metal 320. The substrate 302 may be similar to the substrate 22, 70, or 90 described above, and is not described again herein. The thermal structure 310 may include a dielectric layer and a thermally conductive structure configured to thermally dissipate heat from the package structure 200 and the die 220.

[0069] exist Fig.21, a backside metal 320 is formed along the backside surface of the backside structure 300. The backside metal 320 is formed by one or more layers. The backside metal 320 may include multiple layers, each of which has a different composition and function, such as an adhesion layer, a diffusion barrier layer, and an anti-oxidation layer. In some embodiments, at least one of the layers is formed of a material having high thermal conductivity. One or more layers of the backside metal 320 may be formed of a metal or a metal nitride, such as aluminum, titanium, titanium nitride, nickel, nickel vanadium, silver, gold, copper, combinations thereof, etc., which may be conformally formed by a PVD process such as sputtering or evaporation, a plating process such as chemical plating or electroplating, a printing process such as inkjet printing, etc.

[0070] exist Fig. 22 In the embodiment of the present invention, a front side redistribution structure and a conductive connector 350 are formed to connect to the contact pad 56 of the die 20A / 20B. In some embodiments, dielectric or passivation layers 340 and 342 are formed over the passivation layer 54 and the contact pad 56. In some embodiments, the dielectric or passivation layer 340 / 342 is formed of a polymer that can be patterned using a photolithography mask, which can be a photosensitive material such as PBO, polyimide, BCB, etc. In other embodiments, the dielectric or passivation layer 340 / 342 is formed of: a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG; etc. The dielectric or passivation layer 340 / 342 can be formed by spin coating, lamination, CVD, etc., or a combination thereof.

[0071] A patterning process may be used to form openings in dielectric or passivation layer 340 / 342, exposing some or all of contact pads 56. The patterning process may be an acceptable process, such as by exposing the dielectric or passivation layer to light when the dielectric layer is a photosensitive material, or by etching using, for example, anisotropic etching.

[0072] The front side redistribution structure is shown as an example. In some embodiments, the front side redistribution structure may include redistribution lines (RDLs) such as metal traces (or metal lines) and vias located under and connected to the metal traces. The redistribution lines of the redistribution structure may be physically and electrically connected to the contact pads 56.

[0073] According to some embodiments of the present disclosure, the RDL is formed by a plating process, wherein each of the RDLs includes a seed layer (not shown) and a metallized material above the seed layer. The seed layer can be formed using, for example, PVD, etc. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the RDL. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating, etc. The seed layer and the metallized material can be formed of the same material or different materials. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the seed layer are removed on which the conductive material is not formed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching and / or dry etching. The seed layer and the remaining portion of the conductive material form the RDL.

[0074] More or fewer dielectric and metallization layers than shown may be formed in the redistribution structure by repeating or omitting previously described steps.

[0075] An under-bump metal (UBM) (not shown separately) may be formed for external connection to contact pad 56. The UBM has a bump portion located on and extending along the top surface of upper layer 342, and has a via portion extending through upper layer 342 to physically and electrically couple contact pad 56. Thus, the UBM is electrically connected to die 20A / 20B (e.g., interconnect structure 40 and TSV 36). The UBM may be formed of the same material as the metallization layer and may be formed by a similar process.

[0076] Conductive connector 350 is formed on contact pad 56 (or UBM, if present). Conductive connector 350 can be ball grid array (BGA) connector, solder ball, metal column, controlled collapse chip connection (C4) bump, micro bump, bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG) and the like. Conductive connector 350 can include conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin and the like or a combination thereof. In some embodiments, conductive connector 350 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement and the like. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape. In another embodiment, conductive connector 350 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD and the like. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process.

[0077] Although Fig. 22 Two dielectric or passivation layers 340 and 342 are shown, but more or fewer layers may be included. In some embodiments, passive devices (not shown) (e.g., surface mount devices (SMDs)) may be attached to the package assembly (e.g., bonded to the UBM, contact pads 56, or metallization layers of the redistribution structure). The passive devices may be bonded to the same surface of the package assembly as the conductive connector 350.

[0078] In some embodiments, Fig. 22 The structure may undergo a subsequent singulation process to singulate it into packaged components. Fig. 22 The package assembly can be attached to the package substrate using conductive connectors 350 to form a package structure.

[0079] Figure 23 to Figure 25 A cross-sectional view of an intermediate stage in forming a structure / die 20 in a post-TSV process is shown in accordance with some embodiments. Details regarding this embodiment similar to those for previously described embodiments will not be repeated here.

[0080] In these embodiments, the TSVs 36 are formed after the warpage adjustment structures 82 . Fig.23 shows the process described above Figure 6 Similar steps are described in detail below and will not be repeated here. Figure 6 Compared to the prior TSV embodiment, the TSV 36 has not been formed.

[0081] Fig.24 Shows Fig.23 The structure is similar to the above Figures 7 to 13 The further processing of the processing steps shown and described in the above description will not be repeated here. Fig.24 As shown in FIG. 8 , warpage adjustment structures 82 are formed in the backsides of dies 20A and 20B, but TSVs 36 have not yet been formed.

[0082] Fig.25 2 shows the formation of TSV 36 from the back side of die 20A and 20B. The formation process of TSV 36 is similar to that described above in Figures 1 to 3 The process described in and will not be repeated here.

[0083] Fig.25 The die 20A / 20B may be included in Fig. 22 The packaging structure is shown in FIG. The description of the packaging structure will not be repeated here.

[0084] Fig.26 A detailed view of TSV 36 in a first TSV embodiment is shown. Fig. 27 A detailed view of TSV 36 in a rear TSV embodiment is shown. Fig.26 and Fig. 27 The liner layer 402 and the barrier layer 404 are formed on the sidewalls of the TSV 36. Fig. 27 In the TSV-last embodiment, the barrier layer 404 is located between and separates the metallization / top metal 44 / 46 and the conductive material of the TSV 36, while in Fig.26 In the first TSV embodiment, the barrier layer 404 is not located between the metallization / top metal 44 / 46 and the conductive material of the TSV 36 because it has been removed during the TSV backside exposure step (see, e.g. Fig.11 and / or Fig.16 ). In addition, the tapered direction of TSV 36 changes in the TSV-first and TSV-last embodiments. Fig.26 In FIG. 1 , TSV 36 tapers from metallization / top metal 44 / 46 to bonding pad 112 . Fig. 27 , TSV 36 tapers from bond pad 112 to metallization / top metal 44 / 46 .

[0085] Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that incorporates intermediate verification of known good dies to increase yield and reduce costs.

[0086] The embodiments discussed herein may be discussed in a specific context, namely a warpage adjustment process that can control die warpage. In some embodiments, the warpage adjustment process is applied to the back side of the die. For example, the warpage adjustment structure may include one or more substrate through vias (TSVs) in the back side of the die. The warpage adjustment TSV does not necessarily extend completely through the substrate or die, but in some embodiments, partially extends into the back side of the substrate. In some embodiments, the TSV may be filled with a tensile material, such as a conductive material. In some embodiments, the TSV may be filled with a compressive material, such as a dielectric material. Compressive materials may be used for dies with convex warpage (sometimes referred to as crying or frowning warpage) on the back side. Tensile materials may be used for dies with concave warpage (sometimes referred to as smiling warpage) on the back side. By having a warpage adjustment TSV, the warpage control of the die is improved, which can improve the warpage control for a packaging structure, such as a 3DIC including a die. In addition, in embodiments having a conductive TSV as a warpage adjustment TSV, the heat dissipation of the die may be improved.

[0087] An embodiment is a device including a first die, and a substrate including a first surface and a second surface opposite to the first surface. The device also includes an active device located on the first surface of the substrate. The device also includes a first interconnect structure located on the first surface of the substrate. The device also includes a substrate through hole extending through the first interconnect structure and the substrate to the second surface of the substrate, the substrate through hole being electrically coupled to a metallization pattern in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the substrate through hole.

[0088] Embodiments may include one or more of the following features. A device wherein the one or more material-filled trench structures include a dielectric material. The one or more material-filled trench structures include a conductive material. The device further includes: a dielectric layer located above the one or more material-filled trench structures and the second surface of the substrate; and a bonding pad located in the dielectric layer. The device further includes a second die bonded to the bonding pad of the first die. The device further includes: a contact pad located above the first interconnect structure and electrically coupled to the first interconnect structure; and a conductive connector electrically coupled to the contact pad. The one or more material-filled trench structures form a warpage adjustment structure. Moving from the first surface of the substrate to the second surface, the width of the substrate through-hole decreases. Moving from the first surface of the substrate to the second surface, the width of the substrate through-hole increases.

[0089] An embodiment is a method comprising: forming a first die comprising a substrate, the substrate comprising a first surface and a second surface opposite the first surface. The method also comprises forming an active device on the first surface of the substrate. The method also comprises forming a first interconnect structure on the first surface of the substrate. The method also comprises forming a substrate through-hole extending through the first interconnect structure and the substrate to the second surface of the substrate, the substrate through-hole electrically coupled to a metallization pattern in the first interconnect structure. The method also comprises forming one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the substrate through-hole.

[0090] Embodiments may include one or more of the following features. A method wherein the one or more material-filled trench structures include at least two material-filled trench structures, wherein the first of the material-filled trench structures includes a dielectric material, and wherein the second of the material-filled trench structures includes a conductive material. Forming one or more material-filled trench structures extending from a second surface of the substrate into the substrate includes etching a trench in the second surface of the substrate, filling the trench with a material, and thinning the second surface of the substrate to expose a substrate through-hole. The method also includes: forming a dielectric layer over the one or more material-filled trench structures and the thinned second surface of the substrate; and forming a bonding pad in the dielectric layer that is electrically coupled to the substrate through-hole. The method also includes: directly bonding a second die bonded to the bonding pad of the first die. The substrate through-hole is formed before the material-filled trench structure. The substrate through-hole is formed after the material-filled trench structure. The method also includes: forming a contact pad electrically coupled to the first interconnect structure over the first interconnect structure; and forming a conductive connector electrically coupled to the contact pad.

[0091] An embodiment is a method comprising: forming a first die comprising a first surface and a second surface opposite to the first surface, wherein forming the first die comprises forming a first interconnect structure over a first substrate, the first interconnect structure comprising a metallization pattern. The method also comprises: forming a substrate through hole passing through the first interconnect structure and the first substrate. The method also comprises: forming a contact pad over the first interconnect structure and the substrate through hole, the bonding pad being located on the first surface of the first die. The method also comprises: forming a groove in the second surface of the first die. The method also comprises: filling the groove in the second surface of the first die with a first material. The method also comprises: recessing the second surface of the first die to expose the substrate through hole. The method also comprises: forming a bonding pad on the recessed second surface of the first die. The method also comprises: directly bonding the bonding pad of the first die to the bonding pad of the second die.

[0092] Embodiments may include one or more of the following features. A method wherein the first material is a conductive material. The method further comprises: forming a contact pad electrically coupled to the first interconnect structure over the first interconnect structure; and forming a solder connection electrically coupled to the contact pad.

[0093] Some embodiments of the present application provide a semiconductor device, comprising: a first die, comprising: a substrate, comprising a first surface and a second surface opposite to the first surface; an active device, located on the first surface of the substrate; a first interconnect structure, located on the first surface of the substrate; a substrate through hole, extending through the first interconnect structure and the substrate to the second surface of the substrate, the substrate through hole being electrically coupled to a metallization pattern in the first interconnect structure; and one or more material-filled trench structures, extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the substrate through hole.

[0094] In some embodiments, the one or more material-filled trench structures include a dielectric material. In some embodiments, the one or more material-filled trench structures include a conductive material. In some embodiments, the semiconductor device further includes: a dielectric layer located above the one or more material-filled trench structures and the second surface of the substrate; and a bonding pad located in the dielectric layer. In some embodiments, the semiconductor device further includes: a second die bonded to the bonding pad of the first die. In some embodiments, the semiconductor device further includes: a contact pad located above the first interconnect structure and electrically coupled to the first interconnect structure; and a conductive connector electrically coupled to the contact pad. In some embodiments, the one or more material-filled trench structures form a warpage adjustment structure. In some embodiments, the width of the substrate through-hole decreases as the substrate moves from the first surface to the second surface. In some embodiments, the width of the substrate through-hole increases as the substrate moves from the first surface to the second surface.

[0095] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first tube core including a substrate, the substrate including a first surface and a second surface opposite to the first surface; forming an active device on the first surface of the substrate; forming a first interconnect structure on the first surface of the substrate; forming a substrate through hole extending through the first interconnect structure and the substrate to the second surface of the substrate, the substrate through hole being electrically coupled to a metallization pattern in the first interconnect structure; and forming one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the substrate through hole.

[0096] In some embodiments, the one or more material-filled trench structures include at least two material-filled trench structures, wherein a first of the material-filled trench structures includes a dielectric material, and wherein a second of the material-filled trench structures includes a conductive material. In some embodiments, forming the one or more material-filled trench structures extending from the second surface of the substrate into the substrate includes: etching a trench in the second surface of the substrate; filling the trench with a material; and thinning the second surface of the substrate to expose the substrate through-hole. In some embodiments, the method further includes: forming a dielectric layer over the one or more material-filled trench structures and the thinned second surface of the substrate; and forming a bonding pad in the dielectric layer electrically coupled to the substrate through-hole. In some embodiments, the method further includes: directly bonding a second die to the bonding pad of the first die. In some embodiments, the substrate through-hole is formed before the material-filled trench structure. In some embodiments, the substrate through-hole is formed after the material-filled trench structure. In some embodiments, the method further includes: forming a contact pad electrically coupled to the first interconnect structure over the first interconnect structure; and forming a conductive connector electrically coupled to the contact pad.

[0097] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first tube core including a first surface and a second surface opposite to the first surface, wherein forming the first tube core includes: forming a first interconnect structure above a first substrate, the first interconnect structure including a metallization pattern; forming a substrate through hole passing through the first interconnect structure and the first substrate; forming a bonding pad above the first interconnect structure and the substrate through hole, the bonding pad being located on the first surface of the first tube core; forming a groove in the second surface of the first tube core; filling the groove in the second surface of the first tube core with a first material; recessing the second surface of the first tube core to expose the substrate through hole; and forming a bonding pad on the recessed second surface of the first tube core; and directly bonding the bonding pad of the first tube core to the bonding pad of the second tube core.

[0098] In some embodiments, the first material is a conductive material. In some embodiments, the method further comprises: forming a contact pad electrically coupled to the first interconnect structure over the first interconnect structure; and forming a solder connection electrically coupled to the contact pad.

[0099] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, include: The first die comprises: a substrate comprising a first surface and a second surface opposite to the first surface; an active device located on the first surface of the substrate; a first interconnect structure located on the first surface of the substrate; a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to a metallization pattern in the first interconnect structure; and One or more material-filled trench structures extend from the second surface of the substrate into the substrate, and the one or more material-filled trench structures are electrically isolated from the through-substrate via.

2. The semiconductor device according to claim 1, in, The one or more material-filled trench structures include a dielectric material.

3. The semiconductor device according to claim 1, in, The one or more material-filled trench structures include a conductive material.

4. The semiconductor device according to claim 1, further comprising: include: a dielectric layer located over the one or more material-filled trench structures and the second surface of the substrate; as well as A bonding pad is located in the dielectric layer.

5. The semiconductor device according to claim 4, further comprising: include: A second die is bonded to the bonding pad of the first die.

6. The semiconductor device according to claim 5, further comprising: include: a contact pad located above and electrically coupled to the first interconnect structure; as well as A conductive connector is electrically coupled to the contact pad.

7. The semiconductor device according to claim 1, in, The one or more material-filled trench structures form a warpage adjusting structure.

8. The semiconductor device according to claim 1, in, Moving from the first surface to the second surface of the substrate, the width of the through substrate via decreases.

9. A method of forming a semiconductor device, include: forming a first die including a substrate including a first surface and a second surface opposite the first surface; forming an active device on the first surface of the substrate; forming a first interconnect structure on the first surface of the substrate; forming a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to a metallization pattern in the first interconnect structure; as well as One or more material-filled trench structures are formed extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.

10. A method of forming a semiconductor device, include: forming a first die including a first surface and a second surface opposite to the first surface, wherein forming the first die includes: forming a first interconnect structure over a first substrate, the first interconnect structure comprising a metallization pattern; forming a through substrate via passing through the first interconnect structure and the first substrate; forming a bonding pad over the first interconnect structure and the through substrate via, the bonding pad being located on the first surface of the first die; forming a trench in the second surface of the first die; filling the trench in the second surface of the first die with a first material; recessing the second surface of the first die to expose the through substrate via; and forming bonding pads on the recessed second surface of the first die; and directly bonding the bonding pads of the first die to bonding pads of a second die.

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