Semiconductor structure and method for manufacturing the same

Abstract

The present invention relates to a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises a substrate and a source structure, a gate structure, a protection structure, a discharge structure and a cutting path located on the substrate; the gate structure surrounds the source structure; the gate structure has a convex portion on one side facing the source structure; the protection structure surrounds the gate structure; the discharge structure surrounds the protection structure; the discharge structure comprises a connection layer, which is connected to the convex portion; and the cutting path surrounds the discharge structure. The discharge structure comprises a connection layer, which is connected to the convex portion, thereby forming a discharge loop, which does not occupy too much area of ​​the structure, thereby eliminating the antenna effect of the gate structure during the preparation of the semiconductor structure. When the semiconductor structure is tested, it is only necessary to apply a voltage to the gate structure. Since the diode formed by the discharge structure is forward-conducted, the discharge structure is blown, and the discharge loop is cut off, thereby ensuring that the subsequent semiconductor structure can be tested normally.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] During chip manufacturing, exposed conductors such as metal wires or polysilicon will collect charges generated during the manufacturing process (such as charged particles generated by plasma etching), resulting in increased potential. The larger the area of ​​conductors such as metal wires or polysilicon, the more charges are collected, and the higher the voltage. This effect is called the antenna effect.

[0003] If the above conductor is connected to the gate of the transistor, although the generated charge will not cause direct breakdown of the gate dielectric layer under normal circumstances, it will cause the test data of the insulated gate silicon-controlled rectifier (IGSS) of the transistor to be unstable. Summary of the invention

[0004] Based on this, an embodiment of the present application provides a semiconductor structure and a method for preparing the same, which can effectively avoid the antenna effect.

[0005] According to some embodiments, the present application provides a semiconductor structure, which includes a substrate and a source structure, a gate structure, a protection structure, a discharge structure and a cutting path located on the substrate; the gate structure surrounds the source structure; the gate structure has a protruding portion on the side facing the source structure; the protection structure surrounds the gate structure; the discharge structure surrounds the protection structure; the discharge structure includes a connecting layer, which is connected to the protruding portion; and the cutting path surrounds the discharge structure.

[0006] In the semiconductor structure of the above embodiment, the discharge structure is located between the protection structure and the cutting path, and the discharge structure includes a connection layer, which is connected to the protruding portion, thereby forming a discharge loop, which does not occupy too much area of ​​the structure, thereby eliminating the antenna effect of the gate structure during the preparation of the semiconductor structure. The connection layer of the discharge structure is connected to the protruding portion of the gate structure. When the semiconductor structure is tested, only a voltage of nearly 1V needs to be applied to the gate structure. Since the diode formed by the discharge structure is forward-conducted, the discharge structure is blown, and the discharge loop is cut off, thereby ensuring that the subsequent semiconductor structure can be tested normally.

[0007] In some embodiments, a connection groove is provided in the protection structure, and the connection groove is located outside the protruding portion; the connection layer is at least located in the connection groove and extends along the first direction.

[0008] In some embodiments, the discharge structure further includes a first doping layer and a second doping layer located on the substrate, the first doping layer covers the outer surface of the first doping layer; the first doping layer and the second doping layer have the same doping type, and the doping concentration of the second doping layer is greater than the doping concentration of the first doping layer.

[0009] In some embodiments, the discharge structure also includes a first contact structure and a first isolation layer, the top surface of the first contact structure is flush with the top surface of the first isolation layer; the first isolation layer is located on the top surface of the first doped layer, and the first contact structure penetrates the first isolation layer and a portion of the first doped layer and extends to the top surface of the second doped layer; the connecting layer is at least located on the top surface of the first contact structure and the top surface of the first isolation layer.

[0010] In some embodiments, the semiconductor structure further includes an epitaxial layer located on the substrate, and the discharge structure is located on a top surface of the epitaxial layer.

[0011] In some embodiments, the gate structure includes a first gate and a second gate stacked along a second direction, and a doped stack located on both sides of the second gate, the doped stack is located on the epitaxial layer, and the second direction is perpendicular to the first direction; the first gate is located in the epitaxial layer and is insulated from the second gate.

[0012] In some embodiments, the gate structure also includes a second contact structure and a second isolation layer, the top surface of the second contact structure is flush with the top surface of the second isolation layer, the second isolation layer covers the outer surface of the first gate and the outer surface of the second gate; the second contact structure penetrates the second isolation layer and extends into the second gate.

[0013] In some embodiments, the gate structure further includes a conductive layer located on a top surface of the second contact structure and a top surface of the second isolation layer; the conductive layer is connected to the connection layer.

[0014] In some embodiments, the protection structure is a field limiting ring terminal structure or a terminal extension structure.

[0015] According to some embodiments, the present application also provides a method for preparing a semiconductor structure, comprising:

[0016] Providing a substrate, on which a source structure is formed;

[0017] forming a gate structure, wherein the gate structure surrounds the source structure; and a side of the gate structure facing the source structure has a convex portion;

[0018] forming a protection structure, the protection structure surrounding the gate structure;

[0019] A discharge structure is formed, the discharge structure surrounds the protection structure; the discharge structure includes a connection layer, and the connection layer is connected to the protruding portion of the gate structure;

[0020] A cutting path is formed, and the cutting path surrounds the discharge structure.

[0021] In the method for preparing the semiconductor structure of the above embodiment, a discharge structure is formed, the discharge structure is located between the protection structure and the cutting path, and the discharge structure includes a connection layer, and the connection layer is connected to the protruding portion, thereby forming a discharge loop, which will not occupy too much area of ​​the structure, thereby eliminating the antenna effect of the gate structure during the preparation of the semiconductor structure. The connection layer of the discharge structure is connected to the protruding portion of the gate structure. When the semiconductor structure is tested, only a voltage of nearly 1V needs to be applied to the gate structure. Since the diode formed by the discharge structure is forward-conducted, the discharge structure is blown, and the discharge loop is cut off, thereby ensuring that the subsequent semiconductor structure can be tested normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic top view of a semiconductor structure;

[0023] Figure 2 A schematic diagram of a flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present application;

[0024] Figure 3 A schematic top view of a semiconductor structure provided in one embodiment of the present application;

[0025] Figure 4 An equivalent circuit diagram of a discharge structure in a semiconductor structure provided in one embodiment of the present application;

[0026] Figure 5 A schematic cross-sectional view of a semiconductor structure provided in one embodiment of the present application.

[0027] Description of reference numerals:

[0028] 10. Substrate; 20. Source structure; 21. Conductive connection layer; 30. Gate structure; 301. Raised portion; 31. First gate; 32. Second gate; 33. Doped stack; 331. First sub-doped layer; 332. Second sub-doped layer; 34. Second contact structure; 35. Second isolation layer; 36. Conductive layer; 40. Protection structure; 41. Connection groove; 50. Discharge structure; 51. Connection layer; 52. First doped layer; 53. Second doped layer; 54. First contact structure; 55. First isolation layer; 60. Cutting road; 70. Epitaxial layer. DETAILED DESCRIPTION

[0029] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0031] The term "and / or" used herein includes any and all combinations of one or more of the related listed items. In the case of using "including", "having", and "comprising" described herein, another component may be added unless a clear limiting term such as "only", "consisting of", etc. is used. Unless mentioned to the contrary, a term in the singular form may include a plural form and cannot be understood as having one number.

[0032] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0033] In the description of the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0034] In addition, in order to clearly indicate the multiple layers and regions in the drawings, the thickness of each layer and each region in the drawings are enlarged to clearly illustrate the relative positions between the layers and the distribution of each region. When a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, the expression includes not only the case where it is "directly" above the other part, but also the case where there are other layers in between. And, it is understood that when a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, it generally refers to the side located directly above the other part.

[0035] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0036] See also Figure 1 In a traditional semiconductor structure, the source structure is surrounded by a gate structure, a protection structure, and a cutting path in sequence, and the gate structure usually includes a conductive material. However, in the chip manufacturing process, the conductive material in the gate structure is usually an exposed metal wire or a conductor such as polysilicon. The above conductors will collect the charges generated during the manufacturing process (such as charged particles generated by plasma etching), resulting in an increase in potential. The larger the area of ​​a conductor such as a metal wire or polysilicon, the more charges are collected, and the higher the voltage. This effect is called the antenna effect. If the above conductor is connected to the gate of the transistor, although the charges generated under normal circumstances will not cause direct breakdown of the gate dielectric layer, it will cause the test data of the insulated gate silicon-controlled rectifier (IGSS) of the transistor to be unstable.

[0037] In view of the above-mentioned deficiencies in the prior art, the present disclosure aims to provide a semiconductor structure and a method for preparing the semiconductor structure, the details of which will be described in subsequent embodiments.

[0038] See also Figure 2 According to some embodiments, the present application provides a method for preparing a semiconductor structure, and the method for preparing a semiconductor structure includes the following steps.

[0039] S10: providing a substrate, on which a source structure is formed;

[0040] S30: forming a gate structure, wherein the gate structure surrounds the source structure; and a side of the gate structure facing the source structure has a convex portion;

[0041] S50: forming a protection structure, wherein the protection structure surrounds the gate structure;

[0042] S70: forming a discharge structure, the discharge structure surrounding the protection structure; the discharge structure includes a connection layer, the connection layer is connected to the protruding portion of the gate structure;

[0043] S90: forming a cutting path, wherein the cutting path surrounds the discharge structure.

[0044] In the method for preparing the semiconductor structure of the above embodiment, a discharge structure is formed, the discharge structure is located between the protection structure and the cutting path, and the discharge structure includes a connection layer, and the connection layer is connected to the protruding portion, thereby forming a discharge loop, which will not occupy too much area of ​​the structure, thereby eliminating the antenna effect of the gate structure during the preparation of the semiconductor structure. The connection layer of the discharge structure is connected to the protruding portion of the gate structure. When the semiconductor structure is tested, only a voltage of nearly 1V needs to be applied to the gate structure. Since the diode formed by the discharge structure is forward-conducted, the discharge structure is blown, and the discharge loop is cut off, thereby ensuring that the subsequent semiconductor structure can be tested normally.

[0045] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0046] The embodiments of the present application do not specifically limit the constituent materials of the substrate. As an example, the substrate may be composed of semiconductor materials, insulating materials, conductor materials, or any combination of their material types. The substrate may be a single-layer structure or a multi-layer structure. For example, the substrate may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI), or a silicon germanium on an insulator. A person skilled in the art may select the type of substrate according to the type of transistor formed on the substrate, so the type of substrate should not limit the scope of protection of the present disclosure.

[0047] For example, in step S10, an ion implantation process may be used to implant P-type ions into the substrate to form a first type doped well region (not shown), and the P-type ions may include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions. Alternatively, an ion implantation process may be used to implant N-type ions into the substrate to form a second type doped well region (not shown), and the N-type ions may include, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions. In an embodiment where the substrate includes a P-type substrate, an active region may be formed by implanting N-type ions; correspondingly, in an embodiment where the substrate includes an N-type substrate, an active region may be formed by implanting P-type ions. Accordingly, the active region may be a P-type active region or an N-type active region.

[0048] The present application also provides a semiconductor structure, which can be prepared by using the above-mentioned semiconductor structure preparation method. Figures 3 to 5 It is understood that the present application provides specific embodiments of the semiconductor structure.

[0049] As an example, the semiconductor structure can be used to form a semiconductor device. For example, the semiconductor structure can be used to form a power metal oxide semiconductor device (Power MOSFET), but it is not limited thereto. The semiconductor structure provided in the embodiment of the present disclosure can also be used as other structures.

[0050] Figure 3 FIG. 1 is a schematic diagram of a top view of a semiconductor structure in an embodiment. Figure 3 The semiconductor structure includes a substrate 10 and a source structure 20, a gate structure 30, a protection structure 40, a discharge structure 50 and a cutting path 60 located on the substrate 10; the gate structure 30 surrounds the source structure 20; the gate structure 30 has a protruding portion 301 on the side facing the source structure 20; the protection structure 40 surrounds the gate structure 30; the discharge structure 50 surrounds the protection structure 40; the discharge structure 50 includes a connecting layer 51, and the connecting layer 51 is connected to the protruding portion 301; the cutting path 60 surrounds the discharge structure 50.

[0051] In the semiconductor structure of the above embodiment, the discharge structure 50 is located between the protection structure 40 and the cutting path 60. The discharge structure 50 includes a connection layer 51, and the connection layer 51 is connected to the protruding portion 301, thereby forming a discharge loop, which does not occupy too much area of ​​the structure, thereby eliminating the antenna effect of the gate structure 30 during the preparation of the semiconductor structure. The connection layer 51 of the discharge structure 50 is connected to the protruding portion 301 of the gate structure 30. When the semiconductor structure is tested, only a voltage of nearly 1V needs to be applied to the gate structure 30. Since the diode formed by the discharge structure 50 is forward-conducted, the discharge structure 50 is blown, and the discharge loop is cut off, thereby ensuring that the subsequent semiconductor structure can be tested normally.

[0052] In some embodiments, adjacent surfaces of the source structure 20 , the gate structure 30 , the protection structure 40 , the discharge structure 50 and the cutting path 60 may have insulating gaps to avoid leakage caused by direct electrical contact, thereby improving the stability and reliability of the semiconductor structure.

[0053] In some embodiments, an interlayer dielectric layer may be provided between adjacent surfaces of the source structure 20, the gate structure 30, the protection structure 40, the discharge structure 50, and the cutting path 60, and the interlayer dielectric layer can provide electrical insulation to prevent current leakage between different film layers. In addition, the interlayer dielectric layer can also provide mechanical support for the upper structure and enhance the stability of the structure. For example, the interlayer dielectric layer can be made of an insulating material. For example, the material of the interlayer dielectric layer includes at least one of silicon oxide, silicon nitride, low-k dielectrics, and high-k dielectrics.

[0054] In some embodiments, Figure 3 As shown, the discharge structure 50 is located on the side of the cutting path 60 facing the source structure 20, and the outer surface of the discharge structure 50 is in contact with the inner surface of the cutting path 60. In this way, the discharge structure 50 can form a physical protection ring to protect the internal structure of the discharge structure 50, and when the semiconductor structure is cut and diced along the cutting path 60, it can avoid damage to the semiconductor structure and isolate water vapor from entering the semiconductor structure.

[0055] In some embodiments, the orthographic projections of the gate structure 30, the protection structure 40, the discharge structure 50, and the cutting path 60 can all be set as rectangular ring structures, and the surfaces of the gate structure 30, the protection structure 40, the discharge structure 50, and the cutting path 60 relative to each other are parallel to each other, thereby improving the distribution density of semiconductor structures on the same wafer. For example, the orthographic projections of the gate structure 30, the protection structure 40, the discharge structure 50, and the cutting path 60 are all set as square ring structures to further improve the distribution density of semiconductor structures on the same wafer.

[0056] In some embodiments, the raised portion 301 of the gate structure 30 is located on at least one of the four sidewalls of the rectangular gate structure 30. For example, the raised portion 301 of the gate structure 30 is located on the symmetry axis of the sidewall of the gate structure 30. The symmetrical design of the gate structure 30 can ensure uniform distribution of the electric field inside the device, thereby improving the performance and stability of the device, and the symmetrical gate structure 30 helps to ensure that the device exhibits consistent electrical characteristics under different working conditions, reducing performance fluctuations caused by asymmetry.

[0057] For example, the connecting layer 51 is located on the symmetry axis of the raised portion 301 of the gate structure 30 as a possible implementation method, thereby improving the symmetry of the semiconductor structure. The symmetrical design can simplify the manufacturing process, reduce variability in production, and improve the yield. The symmetrical structure helps to reduce defects that may occur in the manufacturing process, thereby improving the overall quality of the product.

[0058] By way of example, the constituent materials of the connection layer 51 include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0059] In some embodiments, the orthographic projection of the raised portion 301 of the gate structure 30 may be arranged in a rectangular shape.

[0060] In some embodiments, the semiconductor structure further includes a conductive connection layer 21 , which is located on the source structure 20 and extends along the first direction. For example, the extension direction of the conductive connection layer 21 is located on the symmetry axis of the protruding portion 301 of the gate structure 30 .

[0061] In some embodiments, the source structure 20 has an accommodating groove, the protruding portion 301 of the gate structure 30 is located in the accommodating groove, and the surfaces opposite to each other between the protruding portion 301 of the gate structure 30 and the accommodating groove are parallel to each other.

[0062] See also Figure 3 and Figure 4 In some embodiments, the protection structure 40 has a connection groove 41, and the connection groove 41 is located outside the protruding portion 301; the connection layer 51 is at least located in the connection groove 41 and extends along the first direction. For example, the discharge structure 50 includes a main ring structure and a connection layer 51, and the main ring structure is connected to the protruding portion 301 of the gate structure 30 through the connection layer 51. It should be noted that the first direction is as follows Figure 3 y direction shown.

[0063] Figure 4 An equivalent circuit diagram of a discharge structure 50 in an embodiment is shown. The main ring structure of the discharge structure 50 can form a PN junction, so that the discharge structure 50 can form a discharge circuit equivalent to a diode. When the semiconductor structure is tested, it is only necessary to apply a voltage of approximately 1V to the gate structure 30. Since the diode formed by the discharge structure 50 is forward-conducted, the discharge structure 50 is blown, and the above-mentioned discharge circuit is cut off, thereby ensuring that the subsequent semiconductor structure can be tested normally.

[0064] See also Figure 3 and Figure 5 In some embodiments, the discharge structure 50 further includes a first doping layer 52 and a second doping layer 53 located on the substrate 10, wherein the first doping layer 52 covers an outer surface of the first doping layer 52; the first doping layer 52 and the second doping layer 53 have the same doping type, and the doping concentration of the second doping layer 53 is greater than the doping concentration of the first doping layer 52.

[0065] In a specific embodiment, the doping type of the first doping layer 52 and the doping type of the second doping layer 53 are both P-type.

[0066] In some embodiments, the discharge structure 50 further includes a first contact structure 54 and a first isolation layer 55, the top surface of the first contact structure 54 is flush with the top surface of the first isolation layer 55; the first isolation layer 55 is located on the top surface of the first doped layer 52, the first contact structure 54 penetrates the first isolation layer 55 and a portion of the first doped layer 52 and extends to the top surface of the second doped layer 53; the connection layer 51 is at least located on the top surface of the first contact structure 54 and the top surface of the first isolation layer 55.

[0067] Illustratively, the first contact structure 54 is trapezoidal in shape.

[0068] For example, the material of the first contact structure 54 may include titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride silicon or a combination thereof. For example, ruthenium, tungsten, gold or silver are all low-resistance metals, which can further reduce the resistance of the first contact structure 54 and increase the operating speed of the device.

[0069] In some embodiments, the semiconductor structure further includes an epitaxial layer 70 located on the substrate 10 , and the discharge structure 50 is located on a top surface of the epitaxial layer 70 .

[0070] In some embodiments, the gate structure 30 includes a first gate 31 and a second gate 32 stacked along a second direction, and a doped stack 33 located on both sides of the second gate 32, the doped stack 33 is located on the epitaxial layer 70, and the second direction is perpendicular to the first direction; the first gate 31 is located in the epitaxial layer 70 and is insulated from the second gate 32. It should be noted that the second direction is as follows Figure 5 The z direction shown is the thickness direction of the substrate 10 .

[0071] For example, the bottom surface of the doped stack 33 is flush with the bottom surface of the first doped layer 52 , and the top surface of the doped stack 33 is flush with the top surface of the first doped layer 52 .

[0072] By way of example, the constituent materials of the first gate 31 and the second gate 32 include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0073] In some embodiments, the doped stack 33 includes a stacked first sub-doped layer 331 and a second sub-doped layer 332, the first doped sublayer is located on the epitaxial layer 70, the top surface of the first gate 31 is not higher than the top surface of the first doped sublayer, and the top surface of the second gate 32 is not higher than the top surface of the second doped sublayer.

[0074] In some embodiments, the doping type of the first sub-doping layer 331 is different from the doping type of the second sub-doping layer 332. For example, the doping type of the first sub-doping layer 331 is P-type, and the doping type of the second sub-doping layer 332 is N-type. Alternatively, the doping type of the first sub-doping layer 331 is N-type, and the doping type of the second sub-doping layer 332 is P-type.

[0075] In some embodiments, the doping type of the first sub-doping layer 331 is the same as the doping type of the first doping layer 52. For example, the doping type of the first sub-doping layer 331 and the doping type of the first doping layer 52 are both P-type.

[0076] In some embodiments, the gate structure 30 also includes a second contact structure 34 and a second isolation layer 35, the top surface of the second contact structure 34 is flush with the top surface of the second isolation layer 35, and the second isolation layer 35 covers the outer surface of the first gate 31 and the outer surface of the second gate 32; the second contact structure 34 penetrates the second isolation layer 35 and extends into the second gate 32.

[0077] Illustratively, the second contact structure 34 is trapezoidal in shape.

[0078] For example, the material of the second contact structure 34 may include titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride silicon or a combination thereof. For example, ruthenium, tungsten, gold or silver are all low-resistance metals, which can further reduce the resistance of the second contact structure 34 and increase the operating speed of the device.

[0079] In some embodiments, the gate structure 30 further includes a conductive layer 36 located on the top surface of the second contact structure 34 and the top surface of the second isolation layer 35 ; the conductive layer 36 is connected to the connection layer 51 .

[0080] In some embodiments, the conductive layer 36 is made of the same material as the connection layer 51. For example, the conductive layer 36 and the connection layer 51 are formed simultaneously based on a single process.

[0081] In some embodiments, the protection structure 40 is a field limiting ring terminal structure or a terminal extension structure.

[0082] It can be understood that the field limiting ring terminal structure is a design that controls the electric field distribution by introducing an additional electric field adjustment layer (usually a metal or doped layer) in the terminal area of ​​the semiconductor device. This structure can effectively reduce the electric field strength, prevent breakdown and improve the voltage resistance of the device. The field limiting ring terminal structure is formed by injecting doped ions into the ring junction at a certain distance from the main junction. The main junction and the ring junction are diffused at the same time, which increases the curvature radius of the depletion layer and increases the breakdown voltage. By introducing the field limiting ring, the electric field distribution can be smoothed, the electric field concentration phenomenon can be reduced, and the breakdown voltage can be effectively reduced, thereby improving the voltage resistance of the device. The electric field distribution optimized by the field limiting ring terminal structure can reduce leakage current and improve the efficiency of the device.

[0083] The terminal extension structure is a design that improves the electric field distribution and reduces the electric field strength by extending the terminal area of ​​the device. This structure usually involves adding additional doping or material layers to the edge or terminal area of ​​the device. The terminal extension structure is to inject a certain amount of impurities into the PN junction area. When the depth of the terminal extension area is greater than or equal to the main junction depth, it can effectively improve the electric field distribution at the bend, thereby increasing the breakdown voltage. By extending the terminal area, the electric field strength is reduced, the electric field concentration is reduced, and the reduction of the electric field strength can reduce the risk of device failure under high voltage and improve long-term reliability. In addition, the terminal extension structure can help dissipate heat and reduce the operating temperature of the device.

[0084] In the embodiment where the protection structure 40 is a field limiting ring terminal structure or a terminal extension structure, the field limiting ring terminal structure or the terminal extension structure affects the surface electric field structure by ion implantation diffusion. Since the field limiting ring terminal structure and the terminal extension structure affect the surface electric field structure by ion implantation, the arrangement structure of the connection layer 51 will not affect the surface electric field, and thus the withstand voltage of the protection structure 40 will not be affected.

[0085] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate and a source structure located on the substrate; a gate structure surrounding the source structure; The gate structure has a convex portion on one side facing the source structure; A protection structure surrounding the gate structure; A discharge structure surrounding the protection structure; the discharge structure includes a connection layer, and the connection layer is connected to the protruding portion; a cutting path surrounding the discharge structure; The protective structure has a connecting groove therein, and the connecting groove is located outside the raised portion; The connection layer is at least located in the connection groove and extends along a first direction.

2. The semiconductor structure according to claim 1, characterized in that: The discharge structure further includes a first doping layer and a second doping layer located on the substrate, wherein the first doping layer covers an outer surface of the first doping layer; The first doping layer and the second doping layer have the same doping type, and the doping concentration of the second doping layer is greater than the doping concentration of the first doping layer.

3. The semiconductor structure according to claim 2, characterized in that: The discharge structure further includes a first contact structure and a first isolation layer, wherein the top surface of the first contact structure is flush with the top surface of the first isolation layer; The first isolation layer is located on the top surface of the first doping layer, and the first contact structure penetrates the first isolation layer and a portion of the first doping layer and extends to the top surface of the second doping layer; The connection layer is at least located on a top surface of the first contact structure and a top surface of the first isolation layer.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: It also includes an epitaxial layer located on the substrate, and the discharge structure is located on the top surface of the epitaxial layer.

5. The semiconductor structure according to claim 4, characterized in that: The gate structure comprises a first gate and a second gate stacked along a second direction, and doped stacks located on both sides of the second gate, the doped stacks are located on the epitaxial layer, and the second direction is perpendicular to the first direction; The first gate is located in the epitaxial layer and is insulated from the second gate.

6. The semiconductor structure according to claim 5, characterized in that: The gate structure further includes a second contact structure and a second isolation layer, the top surface of the second contact structure is flush with the top surface of the second isolation layer, and the second isolation layer covers the outer surface of the first gate and the outer surface of the second gate; The second contact structure penetrates the second isolation layer and extends into the second gate.

7. The semiconductor structure according to claim 6, characterized in that: The gate structure further includes a conductive layer located on a top surface of the second contact structure and a top surface of the second isolation layer; The conductive layer is connected to the connecting layer.

8. The semiconductor structure according to claim 7, characterized in that: The protection structure is a field limiting ring terminal structure or a terminal extension structure.

9. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, on which a source structure is formed; forming a gate structure, wherein the gate structure surrounds the source structure; and the gate structure has a convex portion on a side facing the source structure; forming a protection structure, the protection structure surrounding the gate structure; the protection structure having a connection groove therein, the connection groove being located outside the protruding portion; forming a discharge structure, wherein the discharge structure surrounds the protection structure; the discharge structure comprises a connection layer, and the connection layer is connected to the protruding portion of the gate structure; The connection layer is at least located in the connection groove and extends along a first direction; A scribe line is formed, the scribe line surrounding the discharge structure.

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