Semiconductor packaging structure and packaging method

Abstract

The present disclosure relates to a semiconductor packaging structure and packaging method. The semiconductor packaging structure includes: a substrate, multiple chips and multiple insulating dielectric layers; multiple chips are stacked layer by layer on the substrate; multiple insulating dielectric layers are simultaneously filled in the gap between the bottom chip and the substrate, as well as the gap between adjacent chips; wherein at least part of the edge of each chip is provided with a chamfer; multiple insulating dielectric layers all extend to the inclined surface formed by the chamfer. In this way, in the process of forming the insulating dielectric layer, the filling material can more easily fill the gap between the chip and the substrate, as well as between adjacent chips. At the same time, it can increase the contact area between the insulating dielectric layer and the chip, improve the bonding force between the chip and the insulating dielectric layer, reduce the risk of delamination of the semiconductor packaging structure, and improve the reliability of the packaging structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor packaging structure and a packaging method. Background Art

[0002] Molded underfill technology integrates underfill and injection molding processes, offering high throughput and low costs. However, as integration and I / O density increase, the gaps between adjacent bumps decrease, posing significant challenges to molded underfill performance. This can lead to defects such as voids and flow marks.

[0003] For example, the bump space of high-bandwidth memory (HBM) products is already less than 20μm, and the number of bumps in HBM products typically reaches tens of thousands. Related art solutions primarily balance the flow resistance caused by the dense bump packing by increasing the mold pressure during the compression mold process. However, increasing the mold pressure also increases the risk of wafer cracking. Therefore, increasing the mold pressure is not a safe and effective solution. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor packaging structure and a packaging method to improve the filling capability of the bottom filling technology and enhance the reliability of the packaging.

[0005] The technical solution of the present invention is achieved as follows:

[0006] An embodiment of the present disclosure discloses a semiconductor packaging structure, comprising: a substrate, multiple chips and multiple insulating dielectric layers; the multiple chips are stacked layer by layer on the substrate; the multiple insulating dielectric layers are simultaneously filled in the gap between the bottom chip and the substrate, as well as the gap between adjacent chips; wherein at least part of the edge of each chip is provided with a chamfer; the multiple insulating dielectric layers all extend to the inclined surface formed by the chamfer.

[0007] In the above solution, the linear dimension of the chamfer along the stacking direction is less than or equal to the thickness of the chip.

[0008] In the above solution, for each chip, the inclined surface formed by the chamfer faces the substrate.

[0009] In the above solution, for the chip at the bottom, the inclined surface formed by the chamfer faces away from the substrate;

[0010] For the remaining chips, the inclined surfaces formed by the chamfers all face the substrate.

[0011] In the above scheme, the semiconductor packaging structure also includes: multiple connection structures; the chip and substrate located at the bottom, and every two adjacent chips are connected through multiple connection structures; wherein the volume of the connection structure between the chip at the bottom and the substrate is larger than the volume of the connection structure between adjacent chips.

[0012] In the above solution, each chip includes: a first region and a second region; the distribution density of the connection structure in the first region is greater than the distribution density in the second region; for each chip, a chamfer is set at the edge corresponding to the first region.

[0013] In the above solution, the chamfer angle ranges from 50 to 70 degrees.

[0014] In the above scheme, among the multiple chips, the front side of the 2n-1th chip is bonded to the front side of the 2nth chip, and the back side of the 2nth chip is bonded to the back side of the 2n+1th chip; n is a positive integer; and the back side of the 1st chip is bonded to the substrate.

[0015] The present disclosure also discloses a semiconductor packaging method, including: providing a substrate and a wafer; cutting the wafer to obtain multiple chips; wherein at least part of the edge of each chip is formed with a chamfer; stacking multiple chips layer by layer on the substrate; and simultaneously filling the gap between the bottom chip and the substrate, as well as the gap between adjacent chips, to form multiple insulating dielectric layers; wherein the multiple insulating dielectric layers extend to the inclined surface formed by the chamfer.

[0016] In the above scheme, the wafer is cut to obtain multiple chips, including: cutting the chip along the front side of the wafer; the front side of the chip and the chamfered bevel have the same orientation; or, cutting the chip along the back side of the wafer; the front side of the chip and the chamfered bevel have opposite orientations.

[0017] In the above scheme, the wafer is cut to obtain multiple chips, which also includes: using a narrow knife to cut the wafer; wherein the cutting depth of the narrow knife corresponds to the linear dimension of the chamfer; using a flat knife to cut the wafer to obtain multiple chips.

[0018] In the above scheme, the semiconductor packaging method also includes: stacking multiple chips layer by layer on a substrate; connecting the bottom chip and the substrate, as well as adjacent chips, through multiple partially welded connection structures; simultaneously filling the gaps between the bottom chip and the substrate, as well as the gaps between adjacent chips, to form multiple insulating dielectric layers; performing reflow soldering on the multiple partially welded connection structures to form multiple fully welded connection structures; wherein the length of the partially welded connection structure is greater than the length of the fully welded connection structure.

[0019] In the above solution, the heating peak temperature of the reflow soldering process is higher than the heating temperature for forming the partially soldered connection structure; and the heating time of the reflow soldering process is longer than the heating time for forming the partially soldered connection structure.

[0020] In the above scheme, each chip includes: a first area and a second area; the distribution density of the connection structure in the first area is greater than the distribution density in the second area; the wafer is cut to obtain multiple chips, and it also includes: removing the metal and dielectric layers in the cutting area on the wafer; forming a patterned hard mask on the front or back of the wafer to expose the edge corresponding to the first area to form an etching window; performing wet etching according to the patterned hard mask to form a chamfer at the position corresponding to the etching window; and cutting the wafer along the cutting area to obtain multiple chips.

[0021] The present disclosure discloses a semiconductor packaging structure, comprising: a substrate, a plurality of chips, and a plurality of insulating dielectric layers; the plurality of chips are stacked layer by layer on the substrate; the plurality of insulating dielectric layers are simultaneously filled in the gaps between the bottom chip and the substrate, as well as the gaps between adjacent chips; wherein at least a portion of the edge of each chip is provided with a chamfer; and the plurality of insulating dielectric layers extend to the inclined surface formed by the chamfer. In this way, during the formation of the insulating dielectric layer, the flared structure formed by the chamfer of the chip in the present disclosure and the chamfer of the substrate or the adjacent chip can add thrust to the filling material when the filling material of the insulating dielectric layer flows, thereby, when the external mold pressure remains unchanged, the filling material can more easily fill the gaps between the chip and the substrate, as well as between adjacent chips, thereby improving the filling effect of the semiconductor packaging structure. At the same time, due to the setting of the chamfer, the contact area between the insulating dielectric layer and the chip in the stacking direction is larger, thereby increasing the bonding force between the chip and the insulating dielectric layer, thereby reducing the risk of delamination of the semiconductor packaging structure and improving the reliability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the semiconductor package structure provided in the embodiment of the present disclosure Figure 1 ;

[0023] Figure 2 A schematic structural diagram of a compression mold provided in an embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of the semiconductor package structure provided in the embodiment of the present disclosure Figure 2 ;

[0025] Figure 4A A schematic structural diagram of a semiconductor packaging structure in related art;

[0026] Figure 4BA schematic diagram of the semiconductor package structure provided in the embodiment of the present disclosure Figure 3 ;

[0027] Figure 5 A fourth structural diagram of a semiconductor package structure provided by an embodiment of the present disclosure;

[0028] Figure 6 A schematic diagram of the structure of a chip provided in an embodiment of the present disclosure;

[0029] Figure 7 The process of the semiconductor packaging method provided by the embodiment of the present disclosure Figure 1 ;

[0030] Figure 8 Schematic diagram of the structure of the wafer provided in the embodiment of the present disclosure Figure 1 ;

[0031] Figure 9 Schematic diagram of the semiconductor packaging method provided by the embodiment of the present disclosure Figure 1 ;

[0032] Figure 10A Schematic diagram of the semiconductor packaging method provided by the embodiment of the present disclosure Figure 2 ;

[0033] Figure 10B Schematic diagram of the semiconductor packaging method provided by the embodiment of the present disclosure Figure 3 ;

[0034] Figure 11A Schematic diagram 4 of a semiconductor packaging method provided by an embodiment of the present disclosure;

[0035] Figure 11B Schematic diagram of the semiconductor packaging method provided by the embodiment of the present disclosure Figure 5 ;

[0036] Figure 12A Schematic diagram of the semiconductor packaging method provided by the embodiment of the present disclosure Figure 6 ;

[0037] Figure 12B Schematic diagram of the semiconductor packaging method provided by the embodiment of the present disclosure Figure 7 ;

[0038] Figure 13 The process of the semiconductor packaging method provided by the embodiment of the present disclosure Figure 2 ;

[0039] Figure 14A Schematic diagram of the semiconductor packaging method provided by the embodiment of the present disclosure Figure 8 ;

[0040] Figure 14BSchematic diagram of the semiconductor packaging method provided by the embodiment of the present disclosure Figure 9 ;

[0041] Figure 15 Schematic diagram of the structure of the wafer provided in the embodiment of the present disclosure Figure 2 ;

[0042] Figure 16A Schematic diagram 10 of a semiconductor packaging method provided by an embodiment of the present disclosure;

[0043] Figure 16B Schematic diagram 11 of a semiconductor packaging method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0045] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0046] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0048] Figure 1 is a schematic structural diagram of an optional semiconductor package structure 10 provided in an embodiment of the present disclosure, with reference to Figure 1The semiconductor package structure 10 includes: multiple chips 100, a substrate 200, and multiple insulating dielectric layers 300. The multiple chips 100 are stacked layer by layer on the substrate 200. The multiple insulating dielectric layers 300 simultaneously fill the gaps between the bottom chip 100 and the substrate 200, as well as the gaps between adjacent chips 100. At least part of the edge of each chip 100 is chamfered. The multiple insulating dielectric layers 300 extend to the inclined surface formed by the chamfer.

[0049] In the embodiments of the present disclosure, reference Figure 1 The chip 100 may be a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). The substrate 200 may be a printed circuit board (PCB) or an interposer substrate.

[0050] Figure 2 This is a structural schematic diagram of an optional compression mold provided in an embodiment of the present disclosure. It should be noted that the filling material 30 can be a molded underfill (MUF) material. In some embodiments, the filling material 30 can be any one of materials such as BPA epoxy resin, BPF epoxy resin and aliphatic epoxy resin.

[0051] It should be noted that, in the embodiments of the present disclosure, Figure 1 and Figure 2 In the process of forming the insulating dielectric layer 300 , a compression mold 20 or other equipment is usually used to apply mold pressure to press the filling material 30 along the edge of each chip 100 into the gap between the chip 100 and the substrate 200 and the adjacent chips 100.

[0052] Figure 3 More specifically, Figure 1 The chip 100 and substrate 200 at the bottom, it should be noted that, Figure 3 Omitted Figure 1 The insulating dielectric layer in the

[0053] Furthermore, in the embodiment of the present disclosure, Figure 2 and Figure 3Because the edge of each chip 100 is chamfered, the thrust applied to the filling material 30 will increase when the mold clamping pressure remains unchanged. Take the example of filling the gap between the chip 100 at the bottom and the substrate 200: the chamfer of the bottom chip 100 forms a bell mouth with the substrate 200. The cross-sectional area of ​​the bell mouth section S1 is much larger than the cross-sectional area of ​​the bell mouth section S2, and the flow rate of the filling material 30 at section S1 will be much lower than that at section S2. Since the pressure at low flow rates of a continuous fluid is higher than that at high flow rates, the pressure at section S1 will be much higher than that at section S2. Therefore, according to Bernoulli's principle, as the filling material 30 flows from section S1 to section S2, a thrust is generated that is applied to the filling material 30, pressing the filling material 30 into the gap between the chip 100 and the substrate 200. In other words, the bell mouth structure formed by the chamfer of the chip and the chamfer of the substrate or adjacent chip in the embodiment of the present disclosure can add thrust to the filling material when the filling material forming the insulating layer and dielectric layer flows. In this way, when the external mold clamping pressure remains unchanged, the filling material 30 can more easily fill the gaps between the chip 100 and the substrate 200 and between adjacent chips 100 , thereby improving the filling effect of the semiconductor package structure 10 .

[0054] It should be noted that, in the embodiments of the present disclosure, reference Figure 1 The coefficients of thermal expansion (CTE) of the materials in the semiconductor package structure 10 are usually mismatched, and if the bonding force between the chip 100 and the insulating dielectric layer 300 is too weak, the semiconductor package structure 10 may be easily delaminated.

[0055] It should also be noted that, in the embodiments of the present disclosure, Figure 1 As temperature changes, stress and strain are generated in the semiconductor package structure, and are mainly concentrated at the edges of the chip 100, which may cause the chip 100 to warp. Therefore, at the edges of the chip 100, it is necessary to increase the contact area between the chip 100 and the insulating dielectric layer 300 in the stacking direction X, and to increase the bonding force between the chip 100 and the insulating dielectric layer 300 in the stacking direction X to offset the effects of stress and strain at the edges of the chip 100.

[0056] Furthermore, if Figure 4A In the semiconductor package structure of the related art shown, the front side (or back side) of the chip contacts the insulating dielectric layer in the stacking direction X. That is, the contact area between the chip and the insulating dielectric layer in the stacking direction X is S4. Figure 4BIn the embodiment of the present disclosure shown, the edge of the chip 100 is chamfered in the stacking direction X, and the multiple insulating dielectric layers 300 all extend to the chamfered inclined surface 111. The contact area between the chip 100 and the insulating dielectric layer 300 is S5, which is greater than the contact area S4 of the related art. This increases the contact area between the insulating dielectric layer 300 and the chip 100 in the stacking direction X, thereby increasing the bonding strength between the insulating dielectric layer 300 and the chip 100. This reduces the risk of delamination of the semiconductor package structure 10 and improves the reliability of the semiconductor package structure 10.

[0057] In some embodiments of the present disclosure, reference Figure 3 , the linear dimension b of the chamfer along the stacking direction X is less than or equal to the thickness of the chip 100 .

[0058] In the present disclosure, continue to refer to Figure 3 In the stacking direction X, the linear dimension b of the chamfer can be smaller than the thickness of the chip 100 or can be equal to the thickness of the chip 100. In this way, the edges of the chip 100 at the bottom and the substrate 200, as well as the edges of the adjacent chips 100, all form a flared shape, making it easier for the filling material to fill the gaps between the chip 100 and the substrate 200, as well as between the adjacent chips 100, thereby improving the filling effect of the semiconductor package structure 10.

[0059] In some embodiments of the present disclosure, reference Figure 1 For each chip 100 , the inclined surface 111 formed by the chamfer faces the substrate 200 .

[0060] In the embodiments of the present disclosure, reference Figure 1 For each chip 100, the chamfered inclined surface 111 faces the substrate 200. In this way, the edges of the chip 100 at the bottom and the substrate 200, as well as the edges of the adjacent chips 100, form a flared shape, making it easier for the filling material to fill the gaps between the chip 100 and the substrate 200, as well as between the adjacent chips 100, thereby improving the filling effect of the semiconductor package structure 10.

[0061] Figure 5 is a structural diagram of another optional semiconductor package structure 10 provided in an embodiment of the present disclosure. It should be noted that: Figure 5 Only the first chip 110 and the second chip 120 are illustrated. In the stacking direction X, the first chip 110 is the chip located at the bottom; the remaining chips included in the semiconductor package structure 10 can be understood with reference to the second chip 120.

[0062] In some embodiments of the present disclosure, for the bottom chip, the inclined surface formed by the chamfer faces away from the substrate, while for the remaining chips, the inclined surfaces formed by the chamfer face toward the substrate.

[0063] It should be noted that, in the embodiments of the present disclosure, reference Figure 5 In some cases, the connection structure 410 used to connect the bottom chip (first chip 110) and the substrate 200 in the semiconductor package structure 10 may be larger than the connection structure 420 used to connect adjacent chips. In other words, the bump gap between the connection structure 410 is larger than that between the connection structure 420. This makes it easier to fill the gap between the bottom chip (first chip 110) and the substrate 200, and thus, the flared structure may not be provided at the edge of the bottom chip (first chip 110) and the substrate 200.

[0064] Further, in the embodiments of the present disclosure, reference is made to Figure 5 In the stacking direction X, the inclined surface 1201 corresponding to the second chip 120 faces the substrate 200, and the inclined surface 1101 corresponding to the first chip 110 faces away from the substrate 200. In this way, the chamfer of the second chip 120 and the chamfer of the first chip 110 form a bell-mouth structure. The flow rate difference of the filling material 30 at the cross section S3 and the cross section S2 of the bell-mouth structure is greater, and the pressure difference at the cross section S3 and the cross section S2 is greater. In this way, when the external mold pressure remains unchanged, the filling material 30 can more easily fill the gap between the first chip 110 and the second chip 120, thereby further improving the filling effect of the semiconductor packaging structure 10.

[0065] In some embodiments of the present disclosure, reference Figure 1 The semiconductor package structure 10 further includes a plurality of connection structures 400 . The chip 100 at the bottom is connected to the substrate 200 , and every two adjacent chips 100 are connected via the plurality of connection structures 400 .

[0066] In the embodiments of the present disclosure, reference Figure 1 Each connection structure 400 includes a bump and a pad. During the stacking of chips 100, the bumps are soldered to corresponding pads to form the connection structure 400. The volume of the connection structure 400 between the bottom chip 100 and the substrate 200 can be equal to the volume of the connection structure 400 between adjacent chips 100.

[0067] In the embodiments of the present disclosure, reference Figure 3The volume of the connection structure 410 between the bottom chip 100 and the substrate 200 is larger than the volume of the connection structure 420 between adjacent chips. For example, the semiconductor package structure 10 may be a package structure of a three-dimensional stack (3DS) product. In a 3DS package structure, the connection structure connecting the bottom chip and the substrate generally uses larger bumps. Therefore, in a 3DS package structure, the volume of the connection structure between the bottom chip and the substrate is larger than the volume of the connection structure between adjacent chips.

[0068] Figure 6 This is a schematic diagram of the structure of an optional chip provided in an embodiment of the present disclosure.

[0069] In some embodiments of the present disclosure, reference Figure 6 Each chip 100 includes: a first area 121 and a second area 122; the distribution density of the connection structure in the first area 121 is greater than the distribution density in the second area 122; for each chip 100, a chamfer is set at the edge corresponding to the first area 121.

[0070] In the embodiments of the present disclosure, reference Figure 6 For chip 100, the bumps 131 are distributed more densely in first region 121 than in second region 122. Correspondingly, in the stacked semiconductor package structure, the connection structures are distributed more densely in first region 121 than in second region 122. In other words, the bump spacing in first region 121 of chip 100 is smaller than the bump spacing in second region 122. Thus, chip 100 in the semiconductor package structure can be chamfered only on the edges corresponding to first region 121. This further simplifies the chip structure while ensuring effective fillet filling.

[0071] In some embodiments of the present disclosure, the chamfer angle ranges from 50 to 70 degrees.

[0072] In the embodiments of the present disclosure, reference Figure 3 The chamfer angle is a, and the range of a is 50 to 70 degrees. This ensures that the chip 100 has a larger chamfer at the edge, increasing the area difference between the cross section S1 and the cross section S2. As a result, the filling material can more easily fill the gap between the chip at the bottom (the first chip 110) and the substrate 200, as well as between adjacent chips, thereby further improving the filling effect of the semiconductor package structure 10.

[0073] Figure 7 This is an optional flow chart of the semiconductor packaging method provided by the embodiment of the present disclosure, which will be combined with Figure 7 The steps shown are explained.

[0074] S101. Provide a substrate and a wafer.

[0075] S102 , cutting the wafer to obtain a plurality of chips; wherein at least a portion of the edge of each chip is chamfered.

[0076] Figure 8 It is an optional structural diagram of the wafer provided in the embodiment of the present disclosure.

[0077] In the embodiments of the present disclosure, reference Figure 8 , a wafer 500 usually forms a plurality of chips 100. Therefore, it is usually necessary to cut the wafer 500 along the cutting path 511 of the wafer 500, thereby obtaining a plurality of chips 100. Among them, at least part of the edge of each chip 100 is formed with a chamfer. In this way, the trumpet-mouth structure formed by the chamfer of the chip in the embodiment of the present disclosure and the chamfer of the substrate or the adjacent chip can add thrust to the filling material when the filling material forming the insulating layer and the dielectric layer flows; when the external mold pressure remains unchanged, the filling material can more easily fill the gap between the chip 100 and the substrate and the adjacent chips 100, thereby improving the filling effect of the semiconductor packaging structure.

[0078] S103 , stacking multiple chips layer by layer on the substrate.

[0079] Figure 9 This is an optional structural diagram of the semiconductor packaging method provided by the embodiment of the present disclosure. It should be noted that: Figure 9 In the description, the semiconductor package structure 10 includes four chips as an example. The number of chips included in the semiconductor package structure 10 can also be greater than 4 or less than 4, which is not limited here.

[0080] In the embodiments of the present disclosure, reference Figure 9 On a substrate 200, multiple chips are stacked layer by layer along a stacking direction X. For example, along the stacking direction X, a first chip 110, a second chip 120, a third chip 130, and a fourth chip 140 are stacked in sequence. The first chip 110 and the substrate 200, as well as adjacent chips, are connected via a connection structure 400.

[0081] S104 , simultaneously filling the gap between the bottom chip and the substrate, as well as the gap between adjacent chips, to form multiple insulating dielectric layers; wherein the multiple insulating dielectric layers extend to the inclined surface formed by the chamfer.

[0082] In the embodiments of the present disclosure, reference Figure 9 , while filling the gap between the bottom chip 110 and the substrate 200, as well as the gap between adjacent chips, to form multiple insulating dielectric layers; thereby, forming Figure 1In the illustrated semiconductor package structure 10, multiple insulating dielectric layers 300 extend to the chamfered inclined surface 111. This extension of the multiple insulating dielectric layers 300 to the chamfered inclined surface 111 increases the contact area between the insulating dielectric layers 300 and the chip in the stacking direction X. This, in turn, increases the bonding strength between the chip and the insulating dielectric layers 300, reduces the risk of delamination in the semiconductor package structure 10, and improves the reliability of the semiconductor package structure 10.

[0083] In some embodiments of the present disclosure, reference Figure 9 Among the multiple chips, the front side of the 2n-1th chip is bonded to the front side of the 2nth chip, and the back side of the 2nth chip is bonded to the back side of the 2n+1th chip; n is a positive integer; and the back side of the first chip is bonded to the substrate.

[0084] In the present disclosure, continue to refer to Figure 9 , taking a semiconductor package structure 10 including four chips as an example for explanation: in the stacking direction X, the first chip 110, the second chip 120, the third chip 130, and the fourth chip 140 are stacked in sequence. The first chip 110 is the chip located at the bottom. In the process of stacking the chips layer by layer, the substrate 200 can be bonded to the back surface of the first chip 110, the front surface of the first chip 110 can be bonded to the front surface of the second chip 120, the back surface of the second chip 120 can be bonded to the back surface of the third chip 130, and the front surface of the third chip 130 can be bonded to the front surface of the fourth chip 140.

[0085] In some embodiments of the present disclosure, it can be achieved through S201 or S202 Figure 7 S102 shown will be described in conjunction with each step.

[0086] S201, cutting out chips along the front side of the wafer; the front side of the chip and the chamfered surface have the same orientation.

[0087] Figure 10A and Figure 10B It is a schematic structural diagram of an optional wafer cutting method provided by an embodiment of the present disclosure.

[0088] in, Figure 10A The positional relationship between the wafer 500 and the narrow blade 610 is shown. Figure 10B Shown Figure 10A The dicing method shown corresponds to the formed chip 100 .

[0089] In the embodiment of the present disclosure, Figure 10A and Figure 10B The present disclosure can use a narrow knife 610 to cut the wafer 500 along the front side 510 of the wafer 500 to obtain the following Figure 10BThe plurality of chips 100 are shown. The chamfered bevel 111 faces the front surface 112 of the chip 100 and faces away from the back surface 113 of the chip 100. Therefore, in the semiconductor package structure, the chamfered bevel 111 and the front surface 112 of the chip 100 have the same orientation.

[0090] S202 , cutting chips along the back side of the wafer; the front side of the chip and the chamfered surface have opposite directions.

[0091] Figure 11A and Figure 11B This is a schematic diagram of another optional structure of a wafer cut according to an embodiment of the present disclosure. Figure 11A The positional relationship between the wafer 500 and the narrow blade 610 is shown. Figure 11B Shown Figure 11A The dicing method shown corresponds to the formed chip 100 .

[0092] In the embodiment of the present disclosure, Figure 11A and Figure 11B The present disclosure can use a narrow knife 610 to cut the wafer 500 along the back side 520 of the wafer 500 to obtain the following Figure 11B The plurality of chips 100 are shown. The chamfered inclined surface 111 faces the back surface 113 of the chip 100 and faces away from the front surface 112 of the chip 100. Therefore, in the semiconductor package structure, the front surface 112 of the chip 100 and the chamfered inclined surface 111 have opposite directions.

[0093] That is, the chips in the semiconductor package structure may have different chamfers. The embodiments of the present disclosure can, according to the orientation of the chamfered surface of the specific chip in the semiconductor package structure, cut the wafer from the front or back of the wafer corresponding to the chip during the process of cutting to form the chip, and obtain the chamfer with the corresponding orientation. For example, Figure 5 In the semiconductor package structure 10 shown, the first chip 110 can be cut along the back side of the corresponding wafer, and the second chip 120 can be cut along the front side of the corresponding wafer.

[0094] In some embodiments of the present disclosure, S301 to S302 can be used to implement Figure 7 S102 shown will be described in conjunction with each step.

[0095] S301, using a narrow knife to cut the wafer; wherein the cutting depth of the narrow knife corresponds to the linear dimension of the chamfer.

[0096] Figure 12A and Figure 12B This is a schematic diagram of another optional structure of a wafer cut according to an embodiment of the present disclosure. Figure 12A The positional relationship between the wafer 500 and the narrow blade 610 is shown. Figure 12B The positional relationship between the wafer 500 and the flat blade 620 is shown.

[0097] In the embodiment of the present disclosure, Figure 10A and Figure 12A , the present disclosure can select different cutting depths according to the linear dimensions of the chamfer preset. The cutting depth of the narrow knife 610 corresponds to the linear dimensions of the chamfer. For example, Figure 10A The cutting depth of the medium narrow blade 610 is h1. Figure 12A The cutting depth of the medium narrow blade 610 is h2, which is smaller than h1.

[0098] S302: Use a flat knife to cut the wafer to obtain multiple chips.

[0099] It should be noted that the reference Figure 10A If a narrow blade 610 is used to cut through the wafer 500 , the sharp corners of the narrow blade 610 may cause chipping on the product surface.

[0100] Furthermore, in the embodiment of the present disclosure, Figure 12A and Figure 12B The present disclosure can adopt a step-cut method, first cutting with a narrow blade 610, and then cutting through with a flat blade 620 to obtain multiple chips 100. In this way, while ensuring that the chip can improve the filling effect, the problem of product surface chipping can be avoided, which can further improve the product yield.

[0101] Figure 13 This is another optional flow chart of the semiconductor packaging method provided by the embodiment of the present disclosure, which is combined with Figure 13 The steps shown are explained.

[0102] It should be noted that Figure 13 and Figure 7 S101 and S102 are the same and will not be described here.

[0103] S105 , stacking a plurality of chips layer by layer on a substrate; connecting the bottom chip to the substrate, and adjacent chips to each other, through a connection structure with multiple partial welds.

[0104] Figure 14A and Figure 14B This is a schematic diagram of an optional connection structure provided by an embodiment of the present disclosure. Figure 14A A partially welded connection structure 430 is shown, Figure 14B A fully welded connection 440 is shown.

[0105] It should also be noted that Figure 14A and Figure 14BThe semiconductor package structure 10 includes two chips as an example for description. The number of chips included in the semiconductor package structure 10 can also be greater than or less than two, which is not limited here.

[0106] In the disclosed embodiment, referring to FIG14 , multiple chips are stacked layer by layer on a substrate 200. For example, in stacking direction X, a first chip 110 and a second chip 120 are sequentially stacked on the substrate 200. The bottom chip 110 is connected to the substrate 200, as well as to adjacent chips, via a plurality of partially welded connection structures 430.

[0107] S106 , simultaneously filling the gap between the bottom chip and the substrate, as well as the gap between adjacent chips, to form multiple insulating dielectric layers.

[0108] In the embodiment of the present disclosure, Figure 14A and Figure 14B , simultaneously filling the gap between the bottom chip 110 and the substrate 200, as well as the gaps between adjacent chips, to form multiple insulating dielectric layers. The length L1 of the partially welded connection structure 430 is greater than the length L2 of the fully welded connection structure 440. This increases the gap between the chip and the substrate, as well as the gaps between adjacent chips, making it easier for the filler material to fill the gaps between the chip and the substrate, as well as the gaps between adjacent chips; thereby, further improving the filling effect of the semiconductor package structure 10.

[0109] S107 , performing reflow soldering on the plurality of partially soldered connection structures to form a plurality of completely soldered connection structures; wherein the length of the partially soldered connection structure is greater than the length of the completely soldered connection structure.

[0110] In the embodiment of the present disclosure, Figure 14A and Figure 14B After forming the insulating dielectric layer, the partially welded connection structures 430 are subjected to a mass reflow process to form a plurality of fully welded connection structures 440. Thus, the connection structures between the bottom chip and the substrate and between adjacent chips can have good electrical conductivity.

[0111] It is understood that the disclosed embodiments utilize a partially soldered connection structure to connect the chip and substrate, then fill the gaps between the bottom chip and substrate, as well as between adjacent chips. Finally, the partially soldered connection structure is reflowed to form a fully soldered connection structure. This further improves the filling effect of the semiconductor package structure while ensuring the conductive performance of the connection structure.

[0112] In some embodiments of the present disclosure, the peak heating temperature of the reflow soldering process is higher than the heating temperature for forming the partially soldered connection structure; and the heating time of the reflow soldering process is longer than the heating time for forming the partially soldered connection structure.

[0113] In the embodiment of the present disclosure, Figure 14A and Figure 14B Multiple chips are stacked layer by layer on a substrate 200 along a stacking direction X, with adjacent chips connected by partially soldered connection structures 430. A reflow soldering process is performed on the multiple partially soldered connection structures 430 to form corresponding fully soldered connection structures 440. The peak heating temperature of the reflow soldering process is higher than the heating temperature for forming the partially soldered connection structures; and the heating time of the reflow soldering process is longer than the heating time for forming the partially soldered connection structures.

[0114] In some embodiments of the present disclosure, S401 to S404 can be used to implement Figure 7 S102 shown will be described in conjunction with each step.

[0115] S401, clearing the metal and dielectric layers in the sawing area on the wafer.

[0116] Figure 15 It is a schematic structural diagram of another optional wafer provided in an embodiment of the present disclosure.

[0117] In the embodiments of the present disclosure, reference Figure 15 , the metal and dielectric layers in the scribe line area 511 on the wafer 500 are removed. Thus, the metal and dielectric layers can be prevented from interfering with the subsequent wafer dicing steps.

[0118] S402 , forming a patterned hard mask on the front side or the back side of the wafer to expose an edge corresponding to the first region to form an etching window.

[0119] Figure 16A and Figure 16B It is a schematic structural diagram of an optional wafer cutting method provided by an embodiment of the present disclosure.

[0120] in, Figure 16A shows the wafer before dicing, Figure 16B The wafer after sawing is shown.

[0121] In the embodiment of the present disclosure, the chamfers of the specific chips in the semiconductor packaging structure have different bevel directions. During the process of cutting the wafer to form the chips, a patterned hard mask can be formed on the front or back side of the wafer; thus, after the subsequent cutting step is completed, a chamfer with a corresponding bevel direction is formed. For example, Figure 16A In the embodiment, a hard mask 710 is formed on the front side 510 of the wafer 500 so that the inclined surface formed by the chamfer of the chip faces the front side of the chip.

[0122] It should be noted that, in the embodiments of the present disclosure, Figure 15 Each chip 100 includes a first region 121 and a second region 122. The bumps 131 are distributed more densely in the first region 121 than in the second region 122. Correspondingly, in the stacked semiconductor package structure, the connection structures are distributed more densely in the first region 121 than in the second region 122. Therefore, the chips 100 in the semiconductor package structure can be chamfered only at the edges corresponding to the first region 121.

[0123] Furthermore, in the embodiment of the present disclosure, Figure 15 and Figure 16A A patterned hard mask 710 is formed on the front surface 510 of the wafer 500 to expose the edge corresponding to the first region 121 to form an etching window 512. Therefore, in subsequent steps, chamfers can be formed only at positions corresponding to the etching windows 512.

[0124] S403 , performing wet etching according to the patterned hard mask to form chamfers at positions corresponding to the etching windows.

[0125] It should be noted that the hard mask can be a photoresist (PR). When etching, a hard mask can be set on either the front or back side of the wafer, and correspondingly, an etching fixture is set on the other side of the wafer. For example, Figure 16A The intermediate hard mask 710 is disposed on the front side 510 of the wafer 500 , and the etching fixture 720 is disposed on the back side of the wafer 500 .

[0126] In the embodiment of the present disclosure, Figure 16A and Figure 16B The wafer 500 is wet-etched according to the patterned hard mask 710 to form chamfers on the wafer 500 corresponding to the etching window. The wet etching agent can be KOH, the etching angle can be 54.74°, and the width of the dicing street on the wafer 500 can be greater than 120 μm.

[0127] S404 , cutting the wafer along the dicing lanes to obtain a plurality of chips.

[0128] In the embodiment of the present disclosure, after the chamfer is formed, a flat knife or a narrow knife can be used to cut the wafer to obtain multiple chips.

[0129] It is understandable that the disclosed embodiment forms an etch window at a location corresponding to the area with small bump gaps, and then uses wet etching to create a chamfer at the etch window. This can reduce the chamfer range while ensuring the filling effect, further simplifying the chip structure.

[0130] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0131] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0132] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor packaging structure, characterized in that: include: A substrate, a plurality of chips and a plurality of insulating dielectric layers; A plurality of the chips are stacked layer by layer on the substrate; The plurality of insulating dielectric layers are simultaneously filled in the gap between the bottom chip and the substrate, and the gap between adjacent chips; wherein, At least part of the edge of each chip is provided with a chamfer; the plurality of insulating dielectric layers extend to the inclined surface formed by the chamfer; For the chip at the bottom, the inclined surface formed by the chamfer faces away from the substrate; For the remaining chips, the inclined surfaces formed by the chamfers all face the substrate.

2. The semiconductor package structure according to claim 1, wherein: A linear dimension of the chamfer along the stacking direction is less than or equal to the thickness of the chip.

3. The semiconductor package structure according to claim 1 or 2, wherein: The semiconductor package structure further includes: a plurality of connection structures; The chip at the bottom and the substrate, as well as every two adjacent chips, are connected via a plurality of the connection structures; wherein the volume of the connection structure between the chip at the bottom and the substrate is greater than the volume of the connection structure between adjacent chips.

4. The semiconductor package structure according to claim 3, wherein: Each of the chips includes: a first region and a second region; The distribution density of the connection structures in the first area is greater than that in the second area; For each of the chips, the chamfer is set at an edge corresponding to the first area.

5. The semiconductor package structure according to claim 1, wherein: The chamfer angle ranges from 50 to 70 degrees.

6. The semiconductor package structure according to claim 1, wherein: Among the plurality of chips, the front surface of the 2n-1th chip is bonded to the front surface of the 2nth chip, and the back surface of the 2nth chip is bonded to the back surface of the 2n+1th chip; n is a positive integer; The reverse side of the first chip is bonded to the substrate.

7. A semiconductor packaging method, characterized in that: include: Provide substrates and wafers; Cutting the wafer to obtain a plurality of chips; wherein at least a portion of an edge of each chip is chamfered; On the substrate, stacking a plurality of the chips layer by layer; At the same time, the gap between the bottom chip and the substrate, as well as the gap between adjacent chips, is filled to form a plurality of insulating dielectric layers; wherein the plurality of insulating dielectric layers extend to the inclined surface formed by the chamfer; For the chip at the bottom, the inclined surface formed by the chamfer faces away from the substrate; For the remaining chips, the inclined surfaces formed by the chamfers all face the substrate.

8. The semiconductor packaging method according to claim 7, wherein: Cutting the wafer to obtain a plurality of chips comprises: The chip is cut out along the front side of the wafer; the front side of the chip and the chamfered surface have the same orientation; or, The chip is cut out along the back side of the wafer; the front side of the chip and the chamfered slope have opposite directions.

9. The semiconductor packaging method according to claim 8, wherein: Cutting the wafer to obtain a plurality of chips further comprises: Cutting the wafer using a narrow blade; wherein the cutting depth of the narrow blade corresponds to the linear dimension of the chamfer; The wafer is cut using a flat knife to obtain a plurality of the chips.

10. The semiconductor packaging method according to claim 7, wherein: The semiconductor packaging method further includes: On the substrate, a plurality of the chips are stacked layer by layer; the bottom chip and the substrate, as well as adjacent chips, are connected via a plurality of partially welded connection structures; Simultaneously filling the gap between the chip and the substrate at the bottom, as well as the gap between adjacent chips, to form multiple insulating dielectric layers; A reflow soldering process is performed on the plurality of partially soldered connection structures to form a plurality of completely soldered connection structures; wherein the length of the partially soldered connection structures is greater than the length of the completely soldered connection structures.

11. The semiconductor packaging method according to claim 10, wherein: The heating peak temperature of the reflow soldering process is higher than the heating temperature of the partially soldered connection structure; and the heating time of the reflow soldering process is longer than the heating time of the partially soldered connection structure.

12. The semiconductor packaging method according to claim 10, wherein: Each of the chips comprises: a first region and a second region; the distribution density of the connection structures in the first region is greater than the distribution density in the second region; Cutting the wafer to obtain a plurality of chips further comprises: removing the metal and dielectric layers in the scribe line area on the wafer; forming a patterned hard mask on the front side or the back side of the wafer to expose an edge corresponding to the first region to form an etching window; Performing wet etching according to the patterned hard mask to form the chamfer at a position corresponding to the etching window; The wafer is cut along the dicing area to obtain a plurality of chips.

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