Semiconductor device

Abstract

Provided is a semiconductor device in which a chip can be arranged more appropriately. According to one embodiment, a semiconductor device includes a substrate, a first laminate, a second laminate, a first adhesive layer, a second adhesive layer, a first conductive line, and a second conductive line. The substrate has a first surface. The first laminated body has a plurality of first semiconductor chips. The second laminate is provided at a position different from that of the first laminate in the in-plane direction of the first surface, and has a plurality of second semiconductor chips. The first adhesive layer is provided on a lower portion of each of the plurality of first semiconductor chips. The second adhesive layer is provided on a lower portion of each of the plurality of second semiconductor chips. The first conductive line electrically connects the first semiconductor chip and the second semiconductor chip to each other. The second conductive line electrically connects the substrate and the second semiconductor chip. The thickness of the first adhesive layer provided on the lower portion of the first semiconductor chip on the lowermost layer is different from the thickness of the other first adhesive layers.

Description

Related Applications

[0001] This application claims the priority of Japanese Patent Application No. 2023-098725 (filing date: June 15, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0002] This embodiment relates to a semiconductor device. Background Art

[0003] In the package structure of a semiconductor device, a semiconductor chip having a high ratio of the width of the long side to the width of the short side (aspect ratio) may be mounted. A semiconductor chip having a high aspect ratio may be difficult to arrange appropriately in a semiconductor package. Summary of the invention

[0004] Provided is a semiconductor device capable of more appropriately arranging chips.

[0005] The semiconductor device of the present embodiment comprises a substrate, a first stack, a second stack, a first adhesive layer, a second adhesive layer, a first wire and a second wire. The substrate has a first surface. The first stack has a plurality of first semiconductor chips. The second stack is arranged at a position different from the first stack in the in-plane direction of the first surface and has a plurality of second semiconductor chips. The first adhesive layer is arranged at the lower part of each of the plurality of first semiconductor chips. The second adhesive layer is arranged at the lower part of each of the plurality of second semiconductor chips. The first wire electrically connects the first semiconductor chip and the second semiconductor chip to each other. The second wire electrically connects the substrate and the second semiconductor chip. The thickness of the first adhesive layer arranged at the lower part of the first semiconductor chip at the lowermost layer is different from the thickness of the other first adhesive layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment. Figure 2 It is a plan view showing an example of the structure of the semiconductor device according to the first embodiment. Figure 3 This is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first comparative example of the first embodiment. Figure 4 This is a cross-sectional view showing an example of the configuration of a semiconductor device according to a second comparative example of the first embodiment. Figure 5 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a first modification of the first embodiment. Figure 6 It is a cross-sectional view showing an example of the structure of the semiconductor device according to the second embodiment. Figure 7 It is a plan view showing an example of the structure of the semiconductor device according to the second embodiment. Figure 8 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a first modification of the second embodiment. Fig. 9 It is a plan view showing an example of the structure of a semiconductor device according to a first modification of the second embodiment. Fig.10 It is a plan view showing an example of the structure of a semiconductor device according to a second modification of the second embodiment. Fig.11 It is a plan view showing an example of connection of bonding wires in the second modification example of the second embodiment. Fig.12 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a third modification of the second embodiment. Fig.13 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a fourth modification of the second embodiment. Fig.14 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a fifth modification of the second embodiment. Fig.15 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a sixth modification of the second embodiment. Fig.16 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a seventh modification of the second embodiment. Fig.17 This is a cross-sectional view showing an example of the structure of a semiconductor device according to an eighth modification of the second embodiment. Fig.18 It is a cross-sectional view showing an example of the structure of the semiconductor device according to the third embodiment. Fig.19 It is a plan view showing an example of the structure of a semiconductor device according to the third embodiment. Fig. 20 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a first modification of the third embodiment. Fig.21 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a second modification of the third embodiment. Fig. 22 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a third modification of the third embodiment. Fig.23 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a fourth modification of the third embodiment. Fig.24This is a cross-sectional view showing an example of the structure of a semiconductor device according to a fifth modification of the third embodiment. DETAILED DESCRIPTION

[0007] The following describes the embodiments of the present invention with reference to the accompanying drawings. The embodiments do not limit the present invention. The accompanying drawings are schematic or conceptual, and the proportions of the various parts may not be the same as the actual ones. In the specification and the accompanying drawings, the same reference numerals are given to the elements that are the same as the elements described above with respect to the accompanying drawings that have appeared, and the detailed description is appropriately omitted.

[0008] (First Embodiment) Figure 1 It is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the first embodiment. Figure 2 It is a plan view showing an example of the structure of the semiconductor device 1 according to the first embodiment. Figure 2 The AA line represents the cross-sectional view of Figure 1 The corresponding cross section.

[0009] The semiconductor device 1 includes a wiring substrate 10, laminated bodies S1a, S1b, S2a, and S2b, a semiconductor chip 40, bonding wires 81 and 82, and a sealing resin 91. The semiconductor device 1 is, for example, a NAND flash memory package.

[0010] in addition, Figure 1 The X direction and the Y direction are parallel to the surface of the substrate (wiring substrate 10) and perpendicular to each other, and the Z direction is perpendicular to the surface of the substrate (wiring substrate 10). In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not be consistent with the gravity direction.

[0011] The wiring substrate 10 may be a printed circuit board or an interposer including a wiring layer (not shown) and an insulating layer (not shown). The wiring layer may be made of a low-resistance metal such as copper (Cu), nickel (Ni) or an alloy thereof. The insulating layer may be made of an insulating material such as glass epoxy resin. The wiring substrate 10 may also have a multilayer wiring structure formed by stacking a plurality of wiring layers and a plurality of insulating layers. The wiring substrate 10 may also have a through electrode that penetrates the front and back surfaces thereof, such as an interposer.

[0012] A solder resist layer is provided on the wiring layer on the surface (surface F10a) of the wiring substrate 10. The solder resist layer is also used as an insulating layer to protect the wiring layer and suppress short circuit failure. Pads 17 and 18 are provided on the surface of the wiring substrate 10. Pads 17 and 18 are wiring layers exposed from the solder resist layer. Pad 17 is electrically connected to the laminate S1a. Pad 18 is electrically connected to the laminate S2b. Pads 17 and 18 are, for example, gold-plated (Au) electrodes. In addition, pads (not shown) connected to the metal material 70 described later are also provided on the surface of the wiring substrate 10.

[0013] A solder resist layer provided on the wiring layer is provided on the back surface (surface F10b) of the wiring substrate 10. Connection bumps 13 are provided on the wiring layer exposed from the solder resist layer. The connection bumps 13 are provided to electrically connect other components (not shown) to the wiring substrate 10.

[0014] The stacked bodies S1a and S1b have semiconductor chips 20 and adhesive layers 21. The adhesive layer 21 is, for example, DAF (Die Attachment Film) or NCP (Non Conductive Paste). The stacked body S1a is a stacked body in which a plurality of semiconductor chips 20 are stacked in a direction (e.g., -X direction) perpendicular to the stacking direction (Z direction). The stacked body S1b is a stacked body in which a plurality of semiconductor chips 20 are stacked in a direction (e.g., +X direction) perpendicular to the stacking direction (Z direction). In addition, the stacked bodies S1a and S1b are arranged on the surface F10a.

[0015] The semiconductor chip 20 is, for example, a memory chip including a NAND flash memory. The semiconductor chip 20 has a semiconductor element (not shown) on its surface (upper surface, surface F20a). The semiconductor element may be, for example, a memory cell array and its peripheral circuit (CMOS (Complementary Metal Oxide Semiconductor) circuit). The memory cell array may be a three-dimensional memory cell array in which a plurality of memory cells are arranged in three dimensions. Figure 1 In the embodiment, each of the stacked bodies S1a and S1b has two stacked semiconductor chips 20 as memory chips. However, the number of stacked semiconductor chips may be three or more.

[0016] The stacked bodies S2a and S2b have semiconductor chips 30 and adhesive layers 31. The adhesive layer 31 is, for example, DAF (Die Attachment Film) or NCP (Non Conductive Paste). The stacked body S2a is a stacked body formed by staggering a plurality of semiconductor chips 30 in a direction (for example, -X direction) perpendicular to the stacking direction (Z direction). The stacked body S2b is a stacked body formed by staggering a plurality of semiconductor chips 30 in a direction (for example, +X direction) perpendicular to the stacking direction (Z direction). In addition, the stacked bodies S2a and S2b are arranged at positions in the X direction that are roughly parallel to the surface F10a from the position of the stacked body S1 on the surface F10a.

[0017] The semiconductor chip 30 is, for example, a memory chip including a NAND flash memory. The semiconductor chip 30 has a semiconductor element (not shown) on its surface (upper surface, surface F30a). The semiconductor element may be, for example, a memory cell array and its peripheral circuit (CMOS circuit). The memory cell array may be a three-dimensional memory cell array in which a plurality of memory cells are arranged in three dimensions. Figure 1 In the embodiment, each of the stacked bodies S2a and S2b has two stacked semiconductor chips 30 as memory chips. However, the number of stacked semiconductor chips may be three or more.

[0018] The semiconductor chip 40 is, for example, a controller chip for controlling a memory chip. A semiconductor element (not shown) is provided on the surface F40b of the semiconductor chip 40 facing the wiring substrate 10. The semiconductor element may be, for example, a CMOS (Complementary Metal Oxide Semiconductor) circuit constituting a controller. An electrode column (not shown) electrically connected to the semiconductor element is provided on the surface F40b which is the back (lower surface) of the semiconductor chip 40. The electrode column is made of, for example, a low-resistance metal material such as copper, nickel, or an alloy thereof.

[0019] In addition, the semiconductor chip 40 is provided on the surface F10a. The semiconductor chip 40 is provided between the laminated bodies S1a and S2b, for example.

[0020] A metal material 70 is provided around the electrode column as the connection bump. The electrode column is electrically connected to the wiring layer exposed in the opening of the solder resist layer via the metal material 70. The metal material 70 uses a low-resistance metal material such as solder, silver, copper, etc. The metal material 70 electrically connects the electrode column of the semiconductor chip 40 to the wiring layer of the wiring substrate 10.

[0021] A resin layer 80 is provided in the area around the metal material 70 and in the area between the semiconductor chip 40 and the wiring substrate 10. The resin layer 80 is formed by curing an underfill resin, for example, and covers and protects the area around the semiconductor chip 40.

[0022] The bonding wire 81 is connected to any pad of the wiring substrate 10 and the semiconductor chip 20. The bonding wire 82 is connected to any pad of the wiring substrate 10 and the semiconductor chip 30. The bonding wires 81 and 82 are, for example, gold (Au) wires. In order to connect with the bonding wires 81 and 82, the semiconductor chips 20 and 30 are stacked with the pads 20p and 30p offset.

[0023] The sealing resin 91 seals the laminated bodies S1a, S1b, S2a, S2b, the semiconductor chip 40, the bonding wires 81, 82, etc. Thus, the semiconductor device 1 forms a semiconductor package including the laminated bodies S1a, S1b, S2a, S2b and the semiconductor chip 40 on the wiring substrate 10.

[0024] Next, the configurations of the stacked bodies S1a, S1b, S2a, S2b and the semiconductor chip 40 will be described in detail.

[0025] like Figure 2 As shown, the semiconductor chip 20 is arranged in such a manner that the short side is substantially parallel to the X direction and the long side is substantially parallel to the Y direction. Therefore, the plurality of semiconductor chips 20 are stacked staggered in the short side direction of the semiconductor chip 20. The semiconductor chip 20 is an elongated shape when viewed from above. Alternatively, the short side of the semiconductor chip 20 may be substantially parallel to the Y direction and the long side may be substantially parallel to the X direction.

[0026] like Figure 1 As shown, the stacked bodies S1 a and S1 b are arranged side by side in the short-side direction of the semiconductor chip 20 .

[0027] Each of the stacked bodies S1a and S1b has two stacked layers of semiconductor chips 20. The semiconductor chips 20 at the bottom of the stacked bodies S1a and S1b are provided at different positions on the surface F10a. The number of stacked semiconductor chips 20 may be three or more.

[0028] The plurality of bonding wires 81 electrically connect the plurality of semiconductor chips 20 to each other. The stacked bodies S1a and S1b are electrically connected to each other via the bonding wires 81. The bonding wires 81 electrically connect the plurality of semiconductor chips 20 to each other in a single stroke, for example.

[0029] The thickness of the adhesive layer 21 below the semiconductor chip 20 in the lowermost layer of the stacked body S1b is different from the thickness of other adhesive layers 21. More specifically, the adhesive layer 21 below the semiconductor chip 20 in the lowermost layer of the stacked body S1b is thicker than other adhesive layers 21.

[0030] The adhesive layer 21 provided under the semiconductor chip 20 of the lowermost layer of the stacked body S1b covers at least a portion of the semiconductor chip 40. Thus, the stacked body S1b and the semiconductor chip 40 can be arranged close to each other, and the packaging area can be further reduced.

[0031] The adhesive layer 21 provided below the bottom semiconductor chip 20 of the stack S1b covers at least a portion of the bonding wire 81 electrically connecting the bottom semiconductor chip 20 of the stack S1a to the wiring substrate 10. Thus, the stacks S1a and S1b can be arranged close to each other, and the packaging area can be further reduced.

[0032] like Figure 2 As shown, the semiconductor chip 30 is arranged in such a manner that the short side is substantially parallel to the X direction and the long side is substantially parallel to the Y direction. Therefore, the plurality of semiconductor chips 30 are stacked staggered in the short side direction of the semiconductor chip 30. The semiconductor chip 30 is an elongated shape when viewed from above. Alternatively, the short side of the semiconductor chip 30 may be substantially parallel to the Y direction and the long side may be substantially parallel to the X direction.

[0033] like Figure 1 As shown, the stacked bodies S2 a and S2 b are arranged side by side in the short-side direction of the semiconductor chip 30 .

[0034] Each of the stacked bodies S2a and S2b has two stacked layers of semiconductor chips 30. The semiconductor chips 30 at the bottom of the stacked bodies S2a and S2b are provided at different positions on the surface F10a. In addition, the number of stacked semiconductor chips 30 may be three or more.

[0035] The plurality of bonding wires 82 electrically connect the plurality of semiconductor chips 30 to each other. The stacked bodies S2a and S2b are electrically connected to each other via the bonding wires 82. The bonding wires 82 electrically connect the plurality of semiconductor chips 30 to each other in a single stroke, for example.

[0036] The thickness of the adhesive layer 31 below the semiconductor chip 30 in the lowermost layer of the stacked body S2a is different from the thickness of other adhesive layers 31. More specifically, the adhesive layer 31 below the semiconductor chip 30 in the lowermost layer of the stacked body S2a is thicker than other adhesive layers 31.

[0037] The adhesive layer 31 provided under the semiconductor chip 30 of the lowermost layer of the stacked body S2a covers at least a portion of the semiconductor chip 40. Thus, the stacked body S2a and the semiconductor chip 40 can be arranged close to each other, and the packaging area can be further reduced.

[0038] The adhesive layer 31 provided below the semiconductor chip 30 of the lowest layer of the stack S2a covers at least a portion of the bonding wire 82 electrically connecting the semiconductor chip 30 of the lowest layer of the stack S2b to the wiring substrate 10. Thus, the stacks S2a and S2b can be arranged close to each other, and the packaging area can be further reduced.

[0039] As described above, according to the first embodiment, the thickness of the adhesive layer 21 disposed under the semiconductor chip 20 of the lowest layer of the stacked body S1b is different from the thickness of the other adhesive layers 21. The thickness of the adhesive layer 31 disposed under the semiconductor chip 30 of the lowest layer of the stacked body S2a is different from the thickness of the other adhesive layers 31. Thus, the semiconductor chips 20 and 30 can be more appropriately arranged in the package.

[0040] In the first embodiment, the plurality of stacked bodies S1a and S1b arranged at different positions on the surface F10a are electrically connected to each other via the bonding wire 81. The plurality of stacked bodies S2a and S2b arranged at different positions on the surface F10a are electrically connected to each other via the bonding wire 82. Thus, multiple layers are not stacked, but a plurality of stacked bodies of a lower layer are provided that are electrically connected.

[0041] In addition, if Figure 2 As shown, semiconductor chips 20 and 30 having a high ratio of the width of the long side to the width of the short side (aspect ratio) may be used. As described later, even when semiconductor chips 20 and 30 having a high aspect ratio are used, the semiconductor chips 20 and 30 can be more appropriately arranged in the package. Figure 2 The aspect ratios of the semiconductor chips 20 and 30 shown are merely examples.

[0042] The ratio of the width of the long side to the width of the short side of the semiconductor chips 20 and 30 (aspect ratio) is greater than a predetermined value. The predetermined value is, for example, 3. For example, the smaller the width of the short side, the larger the aspect ratio. The predetermined value may also be, for example, 5 or 10.

[0043] The pads of the semiconductor chip 20 constituting the stack S1a are located on the right side of the chip (one side of the long side) when viewed from above. The pads of the semiconductor chip 20 constituting the stack S1b are located on the left side of the chip (the side of the long side closer to the stack S1a) when viewed from above.

[0044] To arrange the semiconductor chips in this way, when the same semiconductor chips are used in the laminate S1a and the laminate S1b, the orientation of the semiconductor chips in the laminate S1a and the laminate S1b needs to be reversed. Specifically, the semiconductor chips need to be rotated 180 degrees in the in-plane direction.

[0045] Therefore, the semiconductor chip 20 constituting the stacked body S1a and the semiconductor chip 20 constituting the stacked body S1b may be different chips. In this case, the semiconductor chip 20 constituting the stacked body S1b and the semiconductor chip 20 constituting the stacked body S1a may have the same internal structure but different pad arrangements.

[0046] The same applies to the stacked bodies S2a and S2b.

[0047] Alternatively, the thick adhesive layer 21 , 31 may be provided under at least one of the lowermost semiconductor chips 20 , 30 .

[0048] In addition, the semiconductor chip 40 is not limited to the flip chip connection, and can also be connected by wire bonding. In this case, the thick adhesive layers 21 and 31 bury the wires.

[0049] Figure 3 1 is a cross-sectional view showing an example of the structure of a semiconductor device 1a according to a first comparative example of the first embodiment. The first comparative example of the first embodiment is different from the first embodiment in that the thickness of the adhesive layer 21 is the same. Figure 3 In order to explain the laminate S1 in detail, the Figure 1 FIG. 1 is a diagram of the configuration other than the wiring substrate 10 and the laminate S1.

[0050] The semiconductor device 1 a includes a stacked body S1 . The stacked body S1 includes four layers of stacked semiconductor chips 20 .

[0051] The smaller the width of the short side (X direction) of the semiconductor chip 20, that is, the higher the aspect ratio, the more likely the semiconductor chip 20 at a higher layer is to tilt relative to the wiring substrate 10. This is because, during chip bonding of the semiconductor chips 20, the area of ​​the lower semiconductor chip 20 supporting the upper semiconductor chip 20 becomes smaller. As a result, it is difficult to stack the semiconductor chips 20 in a higher layer.

[0052] In contrast, in the first embodiment, Figure 3 Compared with the stacked body S1 of the embodiment shown in FIG. 1 , the stacked bodies S1a, S1b, S2a, and S2b of the lower layers are arranged side by side in the short side direction of the semiconductor chips 20 and 30. Thus, even when semiconductor chips 20 and 30 with a high aspect ratio are used, the semiconductor chips 20 and 30 can be arranged more appropriately. Therefore, the semiconductor chips 20 and 30 can be arranged more appropriately in the package.

[0053] Figure 4 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1b according to a second comparative example of the first embodiment. The second comparative example of the first embodiment is different from the first embodiment in that the aspect ratio of the semiconductor chips 20 and 30 is relatively low.

[0054] The semiconductor device 1b includes stacked bodies S1 and S2. The stacked body S1 includes four stacked semiconductor chips 20. The stacked body S2 includes four stacked semiconductor chips 30. The stacked body S1 is provided above the semiconductor chip 40, and the stacked body S2 is provided on the stacked body S1.

[0055] Since the aspect ratio of the semiconductor chips 20 and 30 is relatively low, the width of the short side of the semiconductor chips 20 and 30 is relatively large. The semiconductor chip 40 is buried in the adhesive layer 21 provided below the semiconductor chip 20 .

[0056] In contrast, in the first embodiment, since the aspect ratio of the semiconductor chips 20 and 30 is relatively high, the semiconductor chip 40 is not completely buried by the adhesive layer 21 and 31. A portion of the semiconductor chip 40 is covered by the plurality of semiconductor chips 20 and 30. Thus, the semiconductor chips 20 and 30 can be more appropriately arranged in the package.

[0057] (First Modification of First Embodiment) Figure 5 1 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the first modification of the first embodiment. The first modification of the first embodiment is different from the first embodiment in that a spacer 110 is provided above the semiconductor chip 40 .

[0058] The semiconductor device 1 further includes a spacer 110 and an adhesive layer 111 .

[0059] The spacer 110 is provided above the semiconductor chip 40. The spacer 110 may include, for example, Si or a resin such as PI (Polyimide).

[0060] The adhesive layer 111 is disposed at a lower portion of the spacer 110 .

[0061] The laminated bodies S1b and S2a are provided on the spacer 110. The laminated bodies S1b and S2a are arranged so as to overlap with at least a part of the semiconductor chip 40 when viewed from the Z direction.

[0062] The semiconductor chip 40 is provided on the surface F10 a so as to be covered (buried) with the adhesive layer 111 .

[0063] As in the first modification of the first embodiment, a spacer 110 may be provided above the semiconductor chip 40. The semiconductor device 1 of the first modification of the first embodiment can obtain the same effects as those of the first embodiment.

[0064] (Second Embodiment) Figure 6It is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the second embodiment. Figure 7 It is a plan view showing an example of the structure of the semiconductor device 1 according to the second embodiment. Figure 7 The BB line represents the cross-sectional view of Figure 6 The second embodiment is different from the first embodiment in that a spacer 110 is provided and the semiconductor chips 20 are arranged in parallel on the spacer 110 .

[0065] In addition, Figure 6 and Figure 7 In the example shown, the semiconductor chip 30 is not shown.

[0066] The semiconductor device 1 further includes a spacer 110 , an adhesive layer 111 , and a bonding wire 81 a .

[0067] The spacer 110 is provided on the surface F10a. The spacer 110 may contain Si or a resin such as PI, for example.

[0068] The adhesive layer 111 is disposed at a lower portion of the spacer 110 .

[0069] The bonding wire 81a will Figure 6 The semiconductor chip 20 at the center left end is electrically connected to the wiring substrate 10 . Figure 6 The semiconductor chip 20 at the center left end receives supply of a reference voltage (power supply / ground) from the bonding wire 81 a .

[0070] Figure 6 The semiconductor chip 20 at the middle right end receives a signal and a reference voltage (power supply / ground) from the wiring substrate 10 via a bonding wire 81. The semiconductor chip 20 at the left end is away from the connection point between the semiconductor chip 20 at the right end and the wiring substrate 10. By providing a bonding wire 81a capable of supplying a reference voltage, the power supply can be strengthened.

[0071] The plurality of semiconductor chips 20 are provided at different positions on the spacer 110. That is, the plurality of semiconductor chips 20 are arranged in parallel on the spacer 110. The plurality of semiconductor chips 20 are provided in contact with the upper surface (on the same surface) of the spacer 110 via the adhesive layer 21.

[0072] The semiconductor chip 20 has a plurality of pads 20 p to which the bonding wires 81 are connected.

[0073] The bonding wires 81 electrically connect the plurality of semiconductor chips 20 that are in contact with the spacer 110 via the adhesive layer 21 .

[0074] The semiconductor chip 40 is provided on the surface F10 a so as to be covered (buried) with the adhesive layer 111 .

[0075] exist Figure 7In the example shown, the four semiconductor chips 20 are arranged in the same direction when viewed from the Z direction. That is, the plurality of semiconductor chips 20 are arranged in such a way that the arrangement of the pads 20p is the same when viewed from the Z direction. Figure 7 There are 8 pads on the left and 8 pads on the right, but not all of them are shown in the figure. These pads are for I / O (Input / Output) (IO_0 to IO_7). Other power pads are omitted. For example, Figure 7 The pads 17 are arranged in order from IO_0 to IO_7 from the top. Figure 7 The number of the connection bumps 13 indicated by the dotted lines may range from several tens to more than 100, but since not all of them can be recorded, they are omitted from the drawing.

[0076] The eight connection bumps 13 are used as I / O (Input / Output) (IO_0 to IO_7). For example, the connection bump 13 for IO_0 is only connected to the Figure 7 The pad 17 for IO_0 on the left is connected. At this time, the connection bumps 13 of IO_1 to IO_7 are only connected to the pads 17 on the left. Figure 7 IO_1 to IO_7 on the left are connected by pads 17 . For example, the connection bump 13 for IO_0 is only connected to the Figure 7 The connection bumps 13 of IO_1 to IO_7 are connected to the pads 17 of IO_0 on the right. Figure 7 IO_1 to IO_7 on the right are connected by pad 17. For example, the connection bump 13 for IO_0 may also be branched in the wiring substrate 10 and connected to the connection bump 13 for IO_0. Figure 7 The connection bumps 13 of IO_1 to IO_7 are connected to the pads 17 on the left and right sides of IO_0. Figure 7 The left and right sides of IO_1 to IO_7 are connected with pad 17. Such connections from the connection bumps 13 to the corresponding pads 17 may also be combined. For example, the connection bumps 13 for IO_0 may be connected only to the pads 17 located at Figure 7 The pad 17 for IO_0 on the left is connected, and the connection bump 13 for IO_1 is only connected to the pad 17 on the left. Figure 7 The connection bump 13 for IO_2 is branched in the wiring substrate 10 and connected to the pad 17 for IO_1 on the right side. Figure 7 The left and right sides of IO_1 are connected with pad 17.

[0077] As described above, according to the second embodiment, the plurality of semiconductor chips 20 are provided at different positions on the spacer 110. The bonding wires 81 electrically connect the plurality of semiconductor chips 20 in contact with the spacer 110 via the adhesive layer 21. Thus, the semiconductor chips 20 and 30 can be more appropriately arranged in the package.

[0078] like Figure 7 As shown, a semiconductor chip 20 with a relatively high aspect ratio is sometimes used. Figure 3 As described above, it is sometimes difficult to stack multiple semiconductor chips 20 having a relatively high aspect ratio.

[0079] In contrast, in the second embodiment, the semiconductor chips 20 are not stacked. Therefore, even when semiconductor chips 20 and 30 with a high aspect ratio are used, the semiconductor chips 20 and 30 can be more appropriately arranged. Therefore, the semiconductor chips 20 and 30 can be more appropriately arranged in the package.

[0080] In addition, since the semiconductor chips 20 are not stacked, it is not necessary to thin the semiconductor chips 20 and 30, and the semiconductor chips 20 and 30 can be made thicker. As a result, the pick-up performance can be improved, and chip cracks during pick-up can be reduced. In addition, since the cross-sectional structure in the package is simplified, the package warpage shape is simplified. As a result, the package warpage can be more easily controlled.

[0081] Furthermore, since the width of the semiconductor chip 20 in the short-side direction is short, it is possible to suppress the bonding wire 81 connecting the semiconductor chips 20 from becoming longer.

[0082] (First Modification of Second Embodiment) Figure 8 It is a cross-sectional view showing an example of the structure of a semiconductor device 1 according to a first modification of the second embodiment. Fig. 9 It is a plan view showing an example of the configuration of a semiconductor device 1 according to a first modification of the second embodiment. Fig. 9 The CC line represents the cross-sectional view of Figure 8 The first modification of the second embodiment is different from the second embodiment in that the orientation of a part of the semiconductor chips 20 is different.

[0083] exist Figure 8 In the example shown, a portion of the four semiconductor chips 20 is arranged in different orientations when viewed from the Z direction. More specifically, a portion of the four semiconductor chips 20 is arranged in a manner in which the arrangement of the pads 20p is reversed when viewed from the Z direction. The two semiconductor chips 20 on the left are arranged so that the orientation of the semiconductor chips 20 as viewed from the Z direction is rotated (reversed) by 180° compared to the two semiconductor chips 20 on the right. The pads 17 are arranged in a manner in which the arrangement of the pads 20p is reversed when viewed from the Z direction. Fig. 9There are 8 pads on the left and 8 pads on the right, but not all of them are shown in the figure. These pads are for I / O (Input / Output) (IO_0 to IO_7). Other power pads are omitted. For example, Fig. 9 The pads 17 are arranged in order from IO_0 to IO_7 from the top. Fig. 9 The number of the connection bumps 13 indicated by the dotted lines may range from several tens to more than 100, but since not all of them can be recorded, they are omitted from the drawing.

[0084] 16 of the connection bumps 13 are used as connection bumps 13 for I / O. In the first variant of the second embodiment, the connection for I / O is divided between the two semiconductor chips 20 on the left and the two semiconductor chips 20 on the right. In more detail, 8 connection bumps 13 are connected to the pads 17 for IO_0 to IO_7 on the left, respectively. The remaining 8 connection bumps 13 are connected to the pads 17 for IO_0 to IO_7 on the right, respectively. In this case, compared with the second embodiment in which 4 semiconductor chips 20 are connected, twice the connection bumps for I / O are provided. As a result, the semiconductor chips 20 can be operated in parallel. For example, although the power consumption is doubled, the operation speed can be doubled.

[0085] As in the first modification of the second embodiment, the orientation of some semiconductor chips 20 may be different. The semiconductor device 1 according to the first modification of the second embodiment can obtain the same effects as those of the second embodiment.

[0086] (Second Modification of Second Embodiment) Fig.10 1 is a plan view showing an example of the configuration of a semiconductor device 1 according to a second modification of the second embodiment. The second modification of the second embodiment differs from the first modification of the second embodiment in that a bonding wire 81b is provided to connect pads 20p for reference voltage.

[0087] The semiconductor device 1 further includes a bonding wire 81b. The bonding wire 81b electrically connects the pads 20p of the semiconductor chips 20 arranged in a manner rotated (reversed) by 180 degrees. The bonding wire 81b is not connected to the pads 20p for signals such as I / O and DQ / DQS, but is connected to the pads 20p for reference voltage (power supply / ground).

[0088] exist Fig.10 In the example shown, the pad 20p for the reference voltage (ground VSS) is electrically connected between the two left semiconductor chips 20 and the two right semiconductor chips 20 via the bonding wire 81b. On the other hand, the pad 20p (IO_0) for the signal is not connected between the two left semiconductor chips 20 and the two right semiconductor chips 20.

[0089] Fig.11 FIG. 1 is a top view showing an example of connection of the bonding wires 81 and 81b in the second modification of the second embodiment. Fig.11 2 shows the pads 20p for reference voltage (power supply VEXT / ground VSS), and omits the pads 20p for signals. Although not shown in the figure, the pads 20p for signals are arranged between the pads 20p for power supply VEXT / ground VSS.

[0090] like Fig.11 As shown, depending on the configuration of the pad 20p, it is sometimes difficult to connect using the bonding wire 81b. For example, sometimes the pad 20p for power supply VEXT of the semiconductor chip 20 on the left is not configured at a position opposite to the pad 20p for power supply VEXT of the semiconductor chip 20 on the right. For example, the semiconductor chips 20 on the right and left use the same chip, and the semiconductor chip 20 on the right is obtained by rotating the semiconductor chip 20 on the left by 180 degrees. In this case, the pad 20p for power supply VEXT of the semiconductor chip 20 on the right is sometimes not connected by the bonding wire 81b. Similarly, sometimes the pad 20p for ground VSS of the semiconductor chip 20 on the left is not configured at a position opposite to the pad 20p for ground VSS of the semiconductor chip 20 on the right. In this case, the pad 20p for ground VSS of the semiconductor chip 20 on the right is sometimes not connected by the bonding wire 81b.

[0091] A bonding wire 81b connecting the pads 20p for reference voltage to each other may be provided as in the second modification of the second embodiment. The semiconductor device 1 of the second modification of the second embodiment can obtain the same effects as those of the first modification of the second embodiment.

[0092] (Third Modification of Second Embodiment) Fig.12 1 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the third modification of the second embodiment. The third modification of the second embodiment is different from the first modification of the second embodiment in that a member 120 is provided between the semiconductor chips 20 .

[0093] In addition, Fig.12 In the example shown, some semiconductor chips 20 have different orientations. However, all semiconductor chips 20 may have the same orientation.

[0094] The semiconductor device 1 further includes a member 120. The member 120 is provided so as to fill the space between the semiconductor chips 20. The member 120 is made of resin, for example.

[0095] As in the third modification of the second embodiment, the member 120 may be provided between the semiconductor chips 20. The semiconductor device 1 of the third modification of the second embodiment can obtain the same effects as those of the first modification of the second embodiment.

[0096] (Fourth Modification of Second Embodiment) Fig.13 This is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a fourth modification of the second embodiment. The fourth modification of the second embodiment is different from the first modification of the second embodiment in that some semiconductor chips 20 are not cut (individualized).

[0097] Fig.13 The two semiconductor chips 20 on the left side are not cut apart. Similarly, the two semiconductor chips 20 on the right side are not cut apart. The two semiconductor chips 20 are cut out from the wafer while being connected, and are mounted on the wiring substrate 10. This can further simplify the process.

[0098] Some semiconductor chips 20 may not be cut (individualized) as in the fourth modification of the second embodiment. The semiconductor device 1 of the fourth modification of the second embodiment can obtain the same effects as the first modification of the second embodiment.

[0099] (Fifth Modification of Second Embodiment) Fig.14 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a fifth modification of the second embodiment. The fifth modification of the second embodiment is different from the second embodiment in that a semiconductor chip 20 a is further provided on the wiring substrate 10 .

[0100] The semiconductor device 1 further includes a semiconductor chip 20a. The semiconductor chip 20a is provided at a position on a surface F10a different from the spacer 110. The semiconductor chip 20a is provided, for example, adjacent to the spacer 110. The shape of the semiconductor chip 20a is, for example, substantially the same as that of the semiconductor chip 20.

[0101] The bonding wire 81 electrically connects the semiconductor chip 20 and the semiconductor chip 20 a that are in contact with the spacer 110 via the adhesive layer 21 .

[0102] Furthermore, since the width of the semiconductor chip 20 a in the short-side direction is short, it is possible to suppress the bonding wire 81 connecting the semiconductor chips 20 and 20 a from becoming longer.

[0103] As in the fifth modification of the second embodiment, a semiconductor chip 20a may be further provided on the wiring substrate 10. The semiconductor device 1 of the fifth modification of the second embodiment can obtain the same effects as those of the second embodiment.

[0104] (Sixth Modification of Second Embodiment) Fig.15 2 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a sixth modification of the second embodiment. The sixth modification of the second embodiment is different from the fifth modification of the second embodiment in that the semiconductor chip 20 a is thicker.

[0105] The height of the upper surface of the semiconductor chip 20a is substantially the same as that of the upper surface of the semiconductor chip 20. Thus, the lengths of the bonding wires 81 connecting the semiconductor chips 20 and 20a and the bonding wires 81 connecting the semiconductor chips 20 to each other can be made substantially the same.

[0106] The semiconductor chip 20a may be thicker as in the sixth modification of the second embodiment. The semiconductor device 1 of the sixth modification of the second embodiment can obtain the same effects as those of the fifth modification of the second embodiment.

[0107] (Seventh Modification of Second Embodiment) Fig.16 2 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a seventh modification of the second embodiment. The seventh modification of the second embodiment is different from the sixth modification of the second embodiment in that no bonding wire 81 a is provided.

[0108] The bonding wire 81a may not be provided as in the seventh modification of the second embodiment. The semiconductor device 1 according to the seventh modification of the second embodiment can obtain the same effects as those of the sixth modification of the second embodiment.

[0109] (Eighth Modification of Second Embodiment) Fig.17 1 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the eighth modification of the second embodiment. The eighth modification of the second embodiment is different from the first modification of the second embodiment in that a semiconductor chip 20 b is further provided on the semiconductor chip 20 .

[0110] The semiconductor device 1 further includes a semiconductor chip 20b. The semiconductor chip 20b is provided on the semiconductor chip 20. The semiconductor chip 20b is arranged, for example, so as to span across a plurality of semiconductor chips 20. The shape of the semiconductor chip 20b is, for example, substantially the same as that of the semiconductor chip 20.

[0111] The bonding wires 81 electrically connect the semiconductor chip 20 and the semiconductor chip 20 b.

[0112] As in the eighth modification of the second embodiment, a semiconductor chip 20b may be further provided on the semiconductor chip 20. The semiconductor device 1 of the eighth modification of the second embodiment can obtain the same effects as those of the first modification of the second embodiment.

[0113] (Third Embodiment) Fig.18 It is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the third embodiment. Fig.19 It is a plan view showing an example of the structure of the semiconductor device 1 according to the third embodiment. Fig.19 The DD line represents the cross-sectional view of Fig.18 The corresponding cross section.

[0114] The semiconductor device 1 includes stacked bodies S1 and S2. The stacked body S1 includes four stacked semiconductor chips 20. The stacked body S2 includes four stacked semiconductor chips 30. The stacked bodies S1 and S2 are provided at different positions on the plane F10a. More specifically, the bottom semiconductor chips 20 and 30 are provided at different positions on the plane F10a.

[0115] The semiconductor chip 40 is provided on the surface F10a so that at least a portion thereof is covered by the plurality of adhesive layers 21. Fig.19 In the example shown, since the aspect ratio of the semiconductor chips 20 and 30 is relatively high, the long sides (X direction) of the semiconductor chip 40 extend in the X direction from both sides of the stacked body S1 when viewed in the Z direction.

[0116] The adhesive layers 21, 31 provided under the bottom semiconductor chips 20, 30 covering the semiconductor chip 40 may be thicker or made of different materials than other adhesive layers 21, 31. The adhesive layers 21, 31 provided under the bottom semiconductor chips 20, 30 are preferably softer, for example, to easily cover the semiconductor chip 40.

[0117] As described above, according to the third embodiment, the semiconductor chip 40 is provided on the surface F10a so that at least a part thereof is covered by the plurality of adhesive layers 21 and 31. Thus, the semiconductor chips 20 and 30 can be more appropriately arranged in the package. In addition, the package area can be further reduced.

[0118] In addition, the semiconductor chip 40 is rectangular when viewed from the Z direction. Compared with a square, a rectangle has a longer periphery even if the area is the same. Therefore, when the semiconductor chip 40 is connected to the wiring substrate 10 by wire bonding, the semiconductor chip 40 is preferably rectangular when viewed from the Z direction.

[0119] As reference Figure 4As described above, when the aspect ratio of the semiconductor chip 20 is relatively low, the semiconductor chip 40 is buried in the adhesive layer 21 provided below the semiconductor chip 20 .

[0120] In contrast, in the third embodiment, since the aspect ratio of the semiconductor chips 20 and 30 is relatively high, a portion of the semiconductor chip 40 is covered by the plurality of stacked bodies S1 and S2 . This allows the semiconductor chips 20 and 30 to be more appropriately arranged in the package.

[0121] (First Modification of the Third Embodiment) Fig. 20 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a first modification of the third embodiment. The first modification of the third embodiment is different from the third embodiment in that the width of the long side of a semiconductor chip 40 is different.

[0122] exist Fig. 20 In the example shown, as viewed in the Z direction, the long sides (X direction) of the semiconductor chip 40 extend in the X direction from both sides of the stacked bodies S1 and S2 .

[0123] As in the first modification of the third embodiment, the width of the long side of the semiconductor chip 40 may be varied. The semiconductor device 1 according to the first modification of the third embodiment can obtain the same effects as those of the third embodiment.

[0124] (Second Modification of the Third Embodiment) Fig.21 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a second modification of the third embodiment. The second modification of the third embodiment is different from the third embodiment in that semiconductor chips 20 c and 30 c are further provided on a wiring substrate 10 .

[0125] In addition, Fig.21 In the example shown, the semiconductor chips 20 and 30 are each provided in one layer.

[0126] The semiconductor device 1 further includes semiconductor chips 20c and 30c. The semiconductor chips 20c and 30c are provided at positions on the surface F10a different from the semiconductor chips 20, 30, and 40. The shapes of the semiconductor chips 20c and 30c are substantially the same as those of the semiconductor chips 20 and 30, for example.

[0127] The semiconductor chip 20c is electrically connected to the semiconductor chip 20 via the bonding wire 81. The semiconductor chip 20c is provided, for example, adjacent to the semiconductor chip 20. Since the aspect ratio of the semiconductor chips 20 and 20c is relatively high, the semiconductor chips 20 and 20c can be easily arranged side by side.

[0128] The semiconductor chip 30c is electrically connected to the semiconductor chip 30 via the bonding wire 82. The semiconductor chip 30c is provided, for example, adjacent to the semiconductor chip 30. Since the aspect ratio of the semiconductor chips 30 and 30c is relatively high, the semiconductor chips 30 and 30c can be easily arranged side by side.

[0129] In addition, since the width of the semiconductor chip 20c in the short side direction is short, the bonding wire 81 connecting the semiconductor chips 20 and 20c can be prevented from becoming longer. Since the width of the semiconductor chip 30c in the short side direction is short, the bonding wire 82 connecting the semiconductor chips 30 and 30c can be prevented from becoming longer.

[0130] As in the second modification of the third embodiment, semiconductor chips 20c and 30c may be further provided on the wiring substrate 10. The semiconductor device 1 of the second modification of the third embodiment can obtain the same effects as those of the third embodiment.

[0131] (Third Modification of Third Embodiment) Fig. 22 1 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the third modification of the third embodiment. The third modification of the third embodiment is different from the second modification of the third embodiment in that the semiconductor chips 20 and 30 are stacked. That is, the third modification of the third embodiment is also a combination of the third embodiment and the second modification of the third embodiment.

[0132] exist Fig. 22 In the example shown, the semiconductor chip 20 c is electrically connected to the semiconductor chip 20 of the lowermost layer via the bonding wire 81 . The semiconductor chip 30 c is electrically connected to the semiconductor chip 30 of the lowermost layer via the bonding wire 82 .

[0133] The semiconductor chips 20 and 30 may be stacked as in the third modification of the third embodiment. The semiconductor device 1 of the third modification of the third embodiment can obtain the same effects as those of the second modification of the third embodiment.

[0134] (Fourth Modification of Third Embodiment) Fig.23 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a fourth modification of the third embodiment. The fourth modification of the third embodiment is different from the third modification of the third embodiment in that semiconductor chips 20c and 30c are stacked.

[0135] exist Fig.23In the example shown, two layers of semiconductor chips 20, 20c, 30, 30c are provided. The second layer semiconductor chip 20c is electrically connected to the bottom layer semiconductor chip 20 via bonding wires 81. The second layer semiconductor chip 30c is electrically connected to the bottom layer semiconductor chip 30 via bonding wires 82.

[0136] The semiconductor chips 20c and 30c may be stacked as in the fourth modification of the third embodiment. The semiconductor device 1 of the fourth modification of the third embodiment can obtain the same effects as those of the third modification of the third embodiment.

[0137] (Fifth Modification of the Third Embodiment) Fig.24 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a fifth modification of the third embodiment. The fifth modification of the third embodiment is different from the third embodiment in that the number of semiconductor chips 20 and 30 covering a semiconductor chip 40 is different.

[0138] The semiconductor device 1 includes stacked bodies S1a, S1b, S2a, and S2b. The stacked bodies S1a, S1b, S2a, and S2b are provided at different positions on the plane F10a.

[0139] Each of the laminated bodies S1a and S1b has two layers of laminated semiconductor chips 20. The laminated bodies S1a and S1b are electrically connected to each other via bonding wires 81.

[0140] Each of the stacked bodies S2a and S2b has two stacked semiconductor chips 30. The stacked bodies S2a and S2b are electrically connected to each other via bonding wires 82.

[0141] The semiconductor chip 40 is provided on the surface F10a so that at least a part thereof is covered by the adhesive layers 21 and 31 of the stacked bodies S1a, S1b, S2a, and S2b.

[0142] As in the fifth modification of the third embodiment, the number of semiconductor chips 20 and 30 covering the semiconductor chip 40 may be changed. The semiconductor device 1 of the fifth modification of the third embodiment can obtain the same effects as those of the third embodiment.

[0143] In the above embodiment, semiconductor chips having an aspect ratio of 3 or more and less than 5 can be appropriately arranged. Semiconductor chips having an aspect ratio of 5 or more and less than 10 can be appropriately arranged. Semiconductor chips having an aspect ratio of 10 or more and less than 15 can be appropriately arranged.

[0144] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the scope equivalent to the invention described in the claims. [Explanation of Reference Numerals]

[0145] 1 semiconductor device, 10 wiring substrate, 20 semiconductor chip, 20a semiconductor chip, 20b semiconductor chip, 20c semiconductor chip, 20p pad, 21 adhesive layer, 30 semiconductor chip, 30p pad, 31 adhesive layer, 40 semiconductor chip, 81 bonding wire, 82 bonding wire, 110 spacer, 111 adhesive layer, F10a surface, S1 stacked body, S2 stacked body.

Claims

1. A semiconductor device comprising: a substrate having a first surface; a first stacked body having a plurality of first semiconductor chips; a second stacked body provided at a position different from that of the first stacked body in the in-plane direction of the first surface, and having a plurality of second semiconductor chips; A first adhesive layer is disposed at a lower portion of each of the first semiconductor chips; a second adhesive layer disposed at a lower portion of each of the plurality of second semiconductor chips; a first conductive line electrically connecting the first semiconductor chip and the second semiconductor chip to each other; as well as a second wire electrically connecting the substrate and the second semiconductor chip, The thickness of the first adhesive layer provided under the first semiconductor chip in the lowermost layer is different from the thickness of the other first adhesive layers.

2. The semiconductor device according to claim 1, wherein further comprising a third semiconductor chip disposed on the first surface, The first adhesive layer having a thickness different from that of the other first adhesive layers covers at least a portion of the third semiconductor chip.

3. The semiconductor device according to claim 1, wherein The first adhesive layer having a thickness different from that of the other first adhesive layers covers at least a portion of the second conductive line.

4. The semiconductor device according to claim 1, wherein The first semiconductor chip and the second semiconductor chip are elongated when viewed from a direction substantially perpendicular to the first surface. A plurality of pads disposed on the first semiconductor chip are disposed along one of the two long sides, The plurality of pads provided on the second semiconductor chip are provided along a long side of the two long sides which is close to the first semiconductor chip.

5. A semiconductor device comprising: a substrate having a first surface; a spacer disposed on the first surface; a first semiconductor chip disposed on the spacer; a second semiconductor chip disposed on the spacer so as not to overlap with the first semiconductor chip when viewed from a direction substantially perpendicular to the first surface; A first adhesive layer, which is disposed under the first semiconductor chip; a second adhesive layer disposed under the second semiconductor chip; a third adhesive layer disposed at a lower portion of the spacer; a third semiconductor chip disposed on the first surface in a manner covered by the third adhesive layer; as well as A first wire electrically connects at least one of the first semiconductor chip and the second semiconductor chip to the substrate.

6. The semiconductor device according to claim 5, wherein: The first semiconductor chip has a plurality of first pads connected to the first wire or the second wire, and the second wire electrically connects the first semiconductor chip to the second semiconductor chip. The second semiconductor chip has a plurality of second pads connected to the first wire or the second wire. When viewed from a direction approximately perpendicular to the first surface, the first semiconductor chip is elongated in shape, and the plurality of first solder pads are arranged along one of the two long sides; the second semiconductor chip is elongated in shape, and the plurality of second solder pads are arranged along the long side of the two long sides that is away from the first semiconductor chip.

7. The semiconductor device according to claim 5, wherein: The first semiconductor chip has a plurality of first pads connected to the first wire or the second wire, and the second wire electrically connects the first semiconductor chip to the second semiconductor chip. The second semiconductor chip has a plurality of second pads connected to the first wire or the second wire. When viewed from a direction substantially perpendicular to the first surface, the first semiconductor chip is elongated, and the plurality of first pads are arranged along one of the two long sides. The second semiconductor chip has an elongated shape, and the plurality of second pads are arranged along a long side of two long sides that is close to the first semiconductor chip.

8. The semiconductor device according to claim 5, wherein Also available: a fourth semiconductor chip disposed on the first surface so as not to overlap with the spacer when viewed from a direction substantially perpendicular to the first surface; as well as A third wire electrically connects the first semiconductor chip in contact with the spacer via the first adhesive layer and the fourth semiconductor chip.

9. A semiconductor device comprising: a substrate having a first surface; a plurality of first semiconductor chips arranged on the first surface; a plurality of first adhesive layers disposed at respective lower portions of the plurality of first semiconductor chips; and A second semiconductor chip is provided on the first surface in a manner such that at least a portion of the second semiconductor chip is covered by at least one of the plurality of first adhesive layers.

10. The semiconductor device according to claim 9, wherein A fifth semiconductor chip is further provided on the first surface so as not to overlap with the first semiconductor chip and the second semiconductor chip when viewed in a direction substantially perpendicular to the first surface, and is electrically connected to the first semiconductor chip via a wire.

11. The semiconductor device according to any one of claims 1 to 10, wherein: A ratio of a width of a long side of the first semiconductor chip to a width of a short side is greater than or equal to 3 and less than 5.

12. The semiconductor device according to any one of claims 1 to 10, wherein: A ratio of a width of a long side to a width of a short side of the first semiconductor chip is 5 or more and less than 10.

13. The semiconductor device according to any one of claims 1 to 10, wherein: A ratio of a width of a long side to a width of a short side of the first semiconductor chip is 10 or more and less than 15.

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