Semiconductor structure and manufacturing method thereof

Abstract

The semiconductor structure includes a substrate and a first epitaxial source / drain feature extending into the semiconductor layer. The semiconductor structure includes a first doped region in the semiconductor layer under the first epitaxial source / drain feature. The first doped region includes a first concentration of dopant. The semiconductor structure includes a second epitaxial source / drain feature extending into the semiconductor layer. The semiconductor structure includes a second doped region in the semiconductor layer under the second epitaxial source / drain feature. The second doped region includes a second concentration of the dopant that is less than the first concentration. The embodiment of the invention also relates to a method for manufacturing the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of IC structures (such as three-dimensional transistors) and processing, and similar developments in IC processing and manufacturing are needed to achieve these advances. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor structure, including: a semiconductor layer; a first epitaxial source / drain component extending into the semiconductor layer; a first doped region located in the semiconductor layer below the first epitaxial source / drain component, the first doped region including a first concentration of a dopant; a second epitaxial source / drain component extending into the semiconductor layer; and a second doped region located in the semiconductor layer below the second epitaxial source / drain component, the second doped region including a second concentration of the dopant less than the first concentration.

[0004] Other embodiments of the present application provide a semiconductor structure, comprising: a semiconductor layer; a first source / drain component extending into the semiconductor layer; a first barrier layer located below the first source / drain component, the first barrier layer being disposed at a first distance away from a top surface of the semiconductor layer and comprising a first concentration of a dopant; a second source / drain component extending into the semiconductor layer; and a second barrier layer located below the second source / drain component, the second barrier layer being disposed at a second distance away from the top surface of the semiconductor layer and comprising a second concentration of the dopant, wherein the first distance is less than the second distance.

[0005] Still other embodiments of the present application provide a method for manufacturing a semiconductor structure, comprising: performing a first etching process to form a groove in a semiconductor layer adjacent to a gate structure; forming a doped layer in the groove; performing a second etching process to laterally expand a portion of the groove; and forming a source / drain component in the groove, wherein a bottom surface of the source / drain component contacts the doped layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 A three-dimensional perspective view of an exemplary semiconductor device according to some embodiments of the present disclosure is shown.

[0008] Figure 2A A flow chart of an exemplary method for fabricating an exemplary semiconductor device according to some embodiments of the present disclosure is shown.

[0009] Figure 2B and Figure 2C The present invention is shown together with some embodiments of the present invention. Figure 2A A flow chart of an exemplary method of a portion of an exemplary method.

[0010] Figure 3 and Figure 4 According to some embodiments of the present disclosure, Figure 2A During the various manufacturing stages of the exemplary method Figure 1 A cross-sectional view of an exemplary semiconductor device similar to an exemplary semiconductor device or a portion thereof taken along line BB.

[0011] Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 According to some embodiments of the present disclosure, Figure 2A and / or Figure 2B to Figure 2C During the various manufacturing stages of the exemplary method Figure 1 A cross-sectional view of an exemplary semiconductor device similar to an exemplary semiconductor device or a portion thereof taken along line AA. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] In addition, for ease of description, spatially relative terms such as "under," "below," "lower," "above," "upper," "top," "bottom," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, the terms "about" and "approximately" generally refer to ±10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0014] Figure 1 A perspective view of an exemplary non-planar semiconductor device (hereinafter referred to as a device) 100 according to various embodiments is shown. The device 100 includes a substrate 102 and a fin 104 protruding above the substrate 102. An isolation region 106 is formed on opposite sides of the fin 104, wherein the fin 104 protrudes above the isolation region 106. A gate dielectric layer 108 traverses a channel region of the fin 104 such that it is formed along the sidewalls of the fin 104 and formed above the top surface of the fin 104, and a gate electrode 110 is located above the gate dielectric layer 108, and the gate dielectric layer 108 and the gate electrode 110 together form a gate structure 120. Source / drain regions 112D and 112S (with source / drain features formed thereon, not depicted) are disposed in and above the fin 104 and on opposite sides of the gate dielectric layer 108 and the gate electrode 110. The source / drain regions 112D and 112S extend outward from the gate electrode 110. Provided Figure 1 For reference, multiple cross-sections are shown in the following figures. For example, Figure 3 and Figure 4 The cross section shown in is taken along line BB (ie, along the Y-axis), which extends along the longitudinal axis of the gate structure 120 of the device 100 . Figures 5 to 16 The cross-sections shown in are taken along line AA (i.e., along the X-axis), which is along the longitudinal axis of the fin 104 and extends in a direction, for example, of current flow through a channel region of the fin 104 between the source / drain regions 112S / 112D. For clarity, subsequent figures refer to these reference cross-sections. The source / drain region may be referred to as a source or a drain, either individually or collectively depending on the context, and is configured to provide a source / drain component discussed in detail below.

[0015] Figure 2A 1 is a flow chart of a method 200 for forming a non-planar semiconductor device according to one or more embodiments of the present disclosure. For example, at least some of the operations of method 200 may be used to form a planar device, a three-dimensional fin device (e.g., a FinFET), etc. It should be noted that method 200 is merely an example and is not intended to limit the embodiments of the present disclosure. Therefore, it should be understood that the method 200 may be used in the following embodiments. Figure 2A Additional operations are provided before, during, and after the method 200, and some other operations may only be briefly described herein. In some embodiments, the operations of the method 200 may be similar to those of the exemplary device 300 in the example Figures 3 to 16 , which are discussed in further detail below. Figure 2B and Figure 2C 2 and 3. A flow chart of a method 250 for forming a portion of a device 300 according to one or more embodiments of the present disclosure is shown together. In addition, embodiments of the device 300 are not limited to those depicted herein. For example, the device 300 may include many other devices, such as inductors, fuses, capacitors, coils, etc., which are not shown herein for the purpose of clarity.

[0016] refer to Figure 2A and Figure 3 , method 200 provides a substrate 302 of device 300 in operation 202. Substrate 302 may be a semiconductor substrate (or semiconductor layer), such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a P-type or N-type dopant) or undoped. Substrate 302 may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulating layer is provided on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 302 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0017] In the present embodiment, the substrate 302 includes a first region 302A and a second region 302B configured to provide various devices, such as a planar metal oxide semiconductor field effect transistor (MOSFET), a three-dimensional fin MOSFET (FinFET), other types of MOSFET, or a combination thereof. In the present embodiment, the device 300 provides at least one FinFET. The first region 302A and the second region 302B can be configured to form devices of the same conductivity type or different conductivity types, depending on the type of dopant present therein. For example, in the depicted embodiment, the first region 302A and the second region 302B each include an N-type doped well configured to provide a P-type device (e.g., a PMOS device). In some embodiments, the first region 302A includes an N-type doped well configured to provide a PMOS device, and the second region 302B includes a P-type doped well configured to provide an N-type device (e.g., an NMOS device). The N-type doped well may include an N-type dopant, such as phosphorus (P), arsenic (As), etc., or a combination thereof. The P-type doped well may include a P-type dopant, such as boron (B), gallium (Ga), indium (In), etc., or a combination thereof.

[0018] Figure 3 and Figure 4 The embodiment depicted in Figure 1 BB) represents the structure of the device 300 in the first region 302A or the second region 302B at various manufacturing stages of the method 200 and / or the method 250. The first region 302A and the second region 302B may be disposed adjacent to each other, but such a configuration is not required in the embodiments of the present disclosure. Figures 5 to 16 , the first region 302A and the second region 302B are depicted as being formed along line AA, which is the longitudinal axis of the fin (e.g., semiconductor fin). In other words, the shared fin may extend through the first region 302A and the second region 302B. Alternatively, the first region 302A and the second region 302B may be arranged along line BB, which is the longitudinal axis of the gate structure (e.g., dummy gate structure 310).

[0019] Still reference Figure 2A and Figure 3 In operation 204, method 200 forms a (semiconductor) fin 304 that vertically protrudes or extends from substrate 302. Fin 304 may be more generally referred to as a semiconductor layer that protrudes from substrate 302. Figure 3 and Figure 4In the illustrated embodiment of FIG. 3 , two fins 304 are shown, but it should be understood that device 300 may include any number of fins 304 while remaining within the scope of the disclosed embodiments. In some embodiments, operation 204 is omitted, so that device 300 is configured as a planar MOSFET rather than a FinFET.

[0020] In some embodiments, the fin 304 is formed by patterning the substrate 302 using, for example, photolithography and etching techniques. For example, a mask layer (not depicted) including a pad oxide layer and an upper pad nitride layer is formed over the substrate 302. The pad oxide layer can be a thin film including, for example, silicon oxide formed using a thermal oxidation process. The pad oxide layer can be used as an adhesion layer between the substrate 302 and the upper pad nitride layer. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbonitride, etc., or a combination thereof. For example, the pad oxide layer and the pad nitride layer can each be formed using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0021] The mask layer can be patterned using photolithography techniques. In general, photolithography techniques utilize a photoresist material (not depicted) that is deposited, irradiated (or exposed), and developed to remove portions of the photoresist material. The remaining photoresist material protects the underlying material (such as the mask layer in this example) from subsequent processing steps (such as etching). For example, the photoresist material is used to pattern the pad oxide layer and the pad nitride layer to form a patterned mask, which is then used to pattern the exposed portions of the substrate 302 to form the trenches 308, thereby defining the fins 304 separated by the trenches 308, as shown in FIG. Figure 3 . When a plurality of fins are formed, such a groove 308 may be disposed between any two adjacent fins 304. In some embodiments, the fins 304 are formed by etching a groove 308 in the substrate 302 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be implemented anisotropically. In some embodiments, the grooves 308 may be strips that are parallel to each other and closely spaced relative to each other (as viewed from the top). In some embodiments, the grooves 308 may be continuous and surround each fin 304. In this regard, although not depicted herein, the top surface of the resulting fin 304 is superimposed with a patterned mask until the patterned mask is removed in a subsequent manufacturing step.

[0022] The fin 304 can be patterned by other suitable methods. In one example, the fin 304 can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a spacing that is less than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer (not depicted) is formed over the substrate 302 and patterned using a photolithography process. Spacers (not depicted) are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and then the remaining spacers or mandrels can be used to pattern the fin 304.

[0023] In another example, the top portion of substrate 302 may be replaced by or overlaid with a suitable material, such as an epitaxial material (not depicted) suitable for the intended type (e.g., N-type or P-type) of the semiconductor device to be formed. The epitaxial material may be grown over substrate 302 by any suitable epitaxial process. Thereafter, substrate 302 (with the epitaxial material provided over the top portion) is patterned by the photolithography processes described herein, for example, to form fins 304 including the epitaxial material.

[0024] Still reference Figure 2A and Figure 3, the method 200 forms an isolation region 306 over the substrate 302 to surround the bottom portion of the fin 304 in operation 206. The isolation region 306 (which is formed of a dielectric (or insulating) material) can electrically isolate adjacent fins 304 from each other. The dielectric material may include an oxide (such as silicon oxide (SiO and / or SiO2)), a nitride, a low-k (e.g., having a dielectric constant less than the dielectric constant of silicon oxide, which is about 3.9) dielectric material (e.g., phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.), etc., or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDPCVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system, followed by an annealing or curing process to densify the deposited material into another material, such as an oxide), spin coating, etc., or a combination thereof. Other dielectric materials and / or other formation processes may be used to form the isolation region 306. In the depicted embodiment, the dielectric material of the isolation region 306 includes silicon oxide formed by an FCVD process. Once the dielectric material is deposited, an annealing process may be performed. A planarization process such as a chemical mechanical polishing / planarization (CMP) process may remove any excess dielectric material so that the top surface of the dielectric material and the top surface 304T of the fin 304 (or the top surface of the substrate 302 if the device 300 includes a planar device) are substantially coplanar. The patterned mask above the top surface 304T of the fin 304 may also be removed by the planarization process.

[0025] Subsequently, the dielectric material is recessed to form isolation regions 306 in trenches 308, as shown in FIG. Figure 3 304 . In some embodiments, the isolation region 306 includes a shallow trench isolation (STI) feature. The isolation region 306 is recessed so that the upper portion of the fin 304 protrudes from between adjacent isolation regions 306. The corresponding top surface of the isolation region 306 may have a flat surface (as depicted), a convex surface, a concave surface (such as a depression), or a combination thereof. The top surface of the isolation region 306 may be contoured by any suitable etching process, such as an etching process that is selective to the material of the isolation region 306 relative to the substrate 302 (and the fin 304). For example, a dry etching process or a wet etching process using dilute hydrofluoric (DHF) acid may be implemented to recess the dielectric material to form the isolation region 306.

[0026] As another example of forming the fin 304 and the isolation region 306, a dielectric layer (not depicted) may be formed over the top surface of the substrate 302; a trench may be etched through the dielectric layer; a homoepitaxial structure may be epitaxially grown in the trench; and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form the fin 304. In yet another example, a dielectric layer (not depicted) may be formed over the top surface of the substrate 302; a trench may be etched through the dielectric layer; a heteroepitaxial structure may be epitaxially grown in the trench using a different material than the substrate 302; and the dielectric layer may be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 304. The epitaxially grown material or structure may be doped in situ during growth, which may avoid prior and subsequent implants, but in situ doping and implant doping may be used together.

[0027] refer to Figure 2A , Figure 4 and Figure 5 In operation 208, the method 200 forms a plurality of first dummy gate structures 310A and second dummy gate structures 310B in the first region 302A and the second region 302B, respectively. In some parts of the disclosed embodiments, for the purpose of simplicity, the first dummy gate structures 310A and the second dummy gate structures 310B are collectively referred to as dummy gate structures 310. Figure 4 , each dummy gate structure 310 may cross the channel region 311 of the plurality of fins 304. Figure 5 (and subsequent figures) depict two of each of the first and second dummy gate structures 310A, 310B, but it should be understood that additional dummy gate structures 310 may be formed in each of the first and second regions 302A, 302B, respectively, while remaining within the scope of the presently disclosed embodiments.

[0028] Each dummy gate structure 310 may include a dummy gate dielectric layer (not separately depicted) above the fin 304 and a dummy gate electrode (not separately depicted) above the dummy gate dielectric layer. The dummy gate structure 310 may optionally include an interface layer between the fin 304 and the dummy gate dielectric layer, wherein the interface layer may include an oxide, such as silicon oxide. The dummy gate dielectric layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, multilayers thereof, etc. The dummy gate electrode may include polysilicon.

[0029] The various layers of the dummy gate structure 310 may be deposited as a blanket layer over the fin 304 by any suitable process, such as CVD, atomic layer deposition (ALD) or physical vapor deposition (PVD), thermal growth or chemical growth, and then planarized, for example, by a CMP process. A mask layer (not depicted) including silicon nitride or the like may be deposited over the various blanket layers of the dummy gate structure 310. The mask layer may be patterned using a series of photolithography and etching processes, and then transferred to the blanket layer using any suitable etching process to form the dummy gate structure 310. The dummy gate structure 310 traverses or covers a portion of the fin 304, for example, the channel region 311, wherein the longitudinal direction (e.g., along the longitudinal direction) of the dummy gate structure 310 may be substantially the same as that of the fin 304. Figure 1 The Y-axis of line BB) is substantially perpendicular to the longitudinal direction of fin 304 (eg, along Figure 1 The X-axis of the line AA).

[0030] refer to Figure 5 , after forming the dummy gate structures 310, the method 200 forms gate spacers 320 to surround (e.g., along the sidewalls of each of the dummy gate structures 310 and contact the sidewalls of each of the dummy gate structures 310) each of the dummy gate structures 310. It should be understood that any number of gate spacers may be formed around the dummy gate structures 310 while remaining within the scope of the disclosed embodiments. The gate spacers 320 may include any suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, the low-k materials described above, or the like, or a combination thereof. The gate spacers 320 may be formed by first conformally depositing a dielectric layer over the dummy gate structures 310 using any suitable deposition process (such as thermal oxidation, CVD, etc.); and then removing portions of the dielectric layer using a suitable etching process (e.g., a directional or anisotropic dry etching process), leaving the gate spacers 320 along the opposite sidewalls of the dummy gate structures 310.

[0031] In some embodiments, the method 200 forms a plurality of lightly doped drain (LDD; not depicted) regions in the device 300 after forming the dummy gate structure 310 and before forming the gate spacer 320. The LDD regions may be formed by applying a plasma doping process to portions of each of the fins 304 adjacent to the dummy gate structure 310 (e.g., in their respective source / drain regions). The plasma doping process may include forming a patterned mask (not depicted), such as a patterned photoresist, to cover regions of the device 300 that are to be protected from the plasma doping process. Portions of the LDD regions may extend below the dummy gate structure 310 and into the channel region 311. In some instances, the LDD regions may be formed after forming the gate spacer 320. In some embodiments, the LDD regions are omitted from the device 300.

[0032] refer to Figure 2A The method 200 forms a first source / drain (S / D) component (or S / D structure, epitaxial structure, etc.) 350A (eg, a first source / drain (S / D) component) 350A in a first region 302A over the fin 304 (or substrate 302). Fig. 9 ), and forming a second S / D component 350B in the second region 302B (as shown Fig.13 ) enters operation 210. The first S / D component 350A and the second S / D component 350B are formed by method 250, as shown in Figure 2B and Figure 2C Depicted by the Chinese Communist Party.

[0033] refer to Figure 2B and Figure 5 , method 250 forms a patterned mask 326 over second region 302B to expose first region 302A in operation 252. In some embodiments, as depicted, adhesion layer 322 and protection layer (e.g., hard mask) 324 are conformally deposited over dummy gate structure 310 in that order. Adhesion layer 322 may include any suitable dielectric material, such as an oxide, and is configured to improve bonding between protection layer 324 and / or patterned mask 326. Protection layer 324 may include any suitable dielectric material, such as a nitride, and is configured to reduce or prevent unintentional damage (e.g., from etching or accidental epitaxial growth) to underlying components (e.g., dummy gate structure 310) during subsequent operations, and provide dimensional control (e.g., critical dimension or CD) during subsequent etching processes. In this regard, protection layer 324 has a composition that is at least different from that of adhesion layer 322, creating an etching selectivity therebetween. In some instances, adhesion layer 322 may include silicon oxide, and protection layer 324 may include silicon nitride. Adhesion layer 322 and protection layer 324 may each be conformally deposited by any suitable process, such as ALD, CVD, PVD, etc., or a combination thereof.

[0034] Subsequently, the adhesion layer 322 and the protective layer 324 are patterned to remain only over the second region 302B using a series of photolithography and etching processes (such as those described above with respect to forming the fin 304). For example, patterning the adhesion layer 322 and the protective layer 324 includes: depositing a photoresist material over the substrate 302; exposing the photoresist material; and developing the photoresist material to remove portions thereof to form a patterned mask 326. The patterned mask 326 exposes the first dummy gate structure 310A in the first region 302A without exposing the second dummy gate structure 310B in the second region 302B. The adhesion layer 322 and the protective layer 324 are then etched using the patterned mask 326 as an etching mask to expose the first region 302A to subsequent operations.

[0035] Still reference Figure 2B and Figure 5 , the method 250 forms a first S / D recess 330A in a portion of the fin 304 (or substrate 302 if the fin 304 is omitted from the device 300, such as in a planar FET) in the first region 302A in operation 254. In the present embodiment, the first S / D recess 330A has a depth D1, which is measured from the bottom surface of the first S / D recess 330A to the top surface 304T of the fin 304. As will be discussed in detail below, the depth D1 may vary depending on the composition (e.g., the concentration of germanium) of the subsequently formed first S / D feature 350A.

[0036] The first S / D groove 330A is formed adjacent to the first dummy gate structure 310A (e.g., between two adjacent first dummy gate structures 310A, as depicted) by any suitable etching process. In some embodiments, the first S / D groove 330A is formed by implementing a suitable etching process (such as a dry etching process). For example, the groove can be formed by an anisotropic dry etching process using the first dummy gate structure 310A (and the gate spacer 320) as an etching mask. The depth D1 of the first S / D groove 330A can be controlled by changing one or more parameters of the etching process. For example, the depth D1 can be controlled by adjusting the duration of the etching process, the power of the plasma source applied during the etching process, and / or other suitable parameters until the desired depth D1 is reached. According to some examples, the depth D1 can be in the range from about 10 nm to about 200 nm.

[0037] Then, refer to Figure 2B and Figure 5 , the method 250 performs a first implantation process 402 in operation 256 to form a first doped layer (or first doped region) 340A in the top portion of the fin 304 exposed in the first S / D groove 330A. In this regard, the first doped layer 340A is formed at a depth (or position) corresponding to the depth D1 of the first S / D groove 330A.

[0038] The first doped layer 340A may include a suitable dopant corresponding to the device type formed by the first S / D component 350A. For example, if the first S / D component 350A is configured to form a P-type device (e.g., a planar P-type MOSFET, a P-type FinFET, etc.), the first doped layer 340A includes a P-type dopant, such as boron (or another P-type dopant described above). Similarly, if the first S / D component 350A is configured to form an N-type device (or an NMOS device, such as a planar N-type MOSFET, an N-type FinFET, etc.), the first doped layer 340A includes an N-type dopant, such as phosphorus (and / or another N-type dopant described above). In the present embodiment, the first S / D component 350A is configured to form a P-type device, and the first doped layer 340A includes boron. For the purpose of illustration, boron will be used as an exemplary dopant for describing the remainder of the method 250 and the method 200.

[0039] The first doping layer 340A can be formed by any suitable process, such as an implantation (e.g., ion implantation) process or a diffusion process. In the present embodiment, the first doping layer 340A is formed by implanting boron in the first S / D groove 330A. Various parameters of the implantation process, such as the implantation (or doping) energy, can be adjusted based on the depth D1 at which the first doping layer 340A is formed.

[0040] In some embodiments, the first doped layer 340A includes boron at a concentration C1. In some embodiments, the concentration C1 and the depth D1 have a generally negative correlation. For example, if the concentration C1 increases, the depth D1 will decrease, that is, the first doped layer 340A will be formed closer to the top surface 304T of the fin 304, and the size of the first S / D component 350A will also decrease. In some embodiments, the concentration C1 and the thickness T1 of the first doped layer 340A have a generally positive correlation. For example, if the concentration C1 increases, the thickness T1 will also increase, which can explain the diffusion of boron within the first doped layer 340A.

[0041] In some instances, such as Figure 6, boron may diffuse in the fin 304 (or substrate 302) along the sidewalls of the first S / D groove 330A (e.g., diffuse vertically along the Z-axis) to form a diffusion region 341A connected to the first doped layer 340A. In some embodiments, the depth D2 (which is measured from the bottom surface of the first doped layer 340A to the top surface 304T of the fin 304) explains the depth D1 and the thickness T1, and can be used to indicate the location of the first doped layer 340A. In some embodiments, the first doped layer 340A is formed to have a width W along the X-axis, and the width W is the width of the S / D groove 330A. In some embodiments, due to the diffusion of boron along the X-axis (e.g., lateral diffusion), for example, the first doped layer 340A is formed to have a width F1 greater than the width W. For the purpose of simplicity, the subsequent description of the embodiments of the present disclosure is directed to an embodiment in which the first doped layer 340A has a width W.

[0042] refer to Figure 2B and Figure 6 , the method 250 performs a first wet etching process 404 in operation 258 to laterally expand the first S / D recess 330A along the X-axis. The first wet etching process 404 is performed using a wet etchant that selectively removes portions of the fin 304 (or substrate 302) without removing or substantially removing portions of the gate spacer 320, the first dummy gate structure 310A, and the first doped layer 340A. After performing the first wet etching process 404, the patterned mask 326 is removed from the device 300 by any suitable process, such as plasma ashing or resist stripping.

[0043] The first wet etching process 404 defines a width W1 of the widest portion of the first S / D groove 330A, wherein the width W1 is greater than a width W measured across a top opening of the first S / D groove 330A. In this regard, the profile of the sidewalls of the etched first S / D groove 304A points away from the interior of the first S / D groove 330A. It should be noted that the profile of the sidewalls may have any other shape as long as a portion of the first S / D groove 330A is widened relative to its top opening.

[0044] In some embodiments, the width W1 can be adjusted by controlling the parameters of the first wet etching process 404, such as the concentration of the wet etchant, the duration of the etching process, the size of the first S / D groove 330A (e.g., the depth D1). For example, the width W and W1 are positively correlated, such that a larger width W produces a larger width W1. In some embodiments, the width W and the width W1 are controlled by adjusting the spacing P1 between two adjacent first dummy gate structures 310A, the spacing P1 being the CD of the device 300, which describes the separation distance between two adjacent first dummy gate structures 310A. In this regard, a larger spacing P1 corresponds to a larger width W, which allows a larger amount of wet etchant to interact with the material exposed in the first S / D groove 330A, thereby producing a larger depth D1 and a larger width W1. In some embodiments, the width W1 is also referred to as the tip-to-tip distance of the first S / D feature 350A. According to some examples, the width W1 can be in a range from about 20 nm to about 150 nm.

[0045] Common Reference Figure 2B and FIG. 7A to FIG. 9 , the method 250 forms epitaxial layers 342A, 344A, 346A, and 348A over the first doped layer 340A in the first S / D recess 330A. In the present embodiment, the epitaxial layers 342A and 344A (i.e., collectively referred to as the first epitaxial layer or L1 of the first S / D component 350A), 346A (i.e., the second epitaxial layer or L2 of the first S / D component 350A), and 348A (i.e., the third epitaxial layer or L3 of the first S / D component 350A) have different compositions from each other. For example, in the present embodiment, because the first S / D component 350A is configured to form a P-type device, the epitaxial layers 342A, 344A, and 346A each include silicon germanium (SiGe) doped with a P-type dopant (such as boron), but may differ in the concentration of the germanium included. Alternatively, epitaxial layers 342A, 344A, and 346A may each include silicon (Si) doped with N-type dopants, such as phosphorus and / or arsenic, to form N-type devices.

[0046] refer to Figure 2B and Fig. 7A, the method 250 forms (or grows) an epitaxial layer 342A from the bottom surface and sidewalls of the first S / D groove 330A in operation 260 without completely filling the first S / D groove 330A. In some embodiments, the epitaxial layer 342A is formed by filling the first S / D groove 330A with an epitaxial material and then etching the epitaxial material. In some embodiments, the epitaxial layer 342A is a first sublayer of the first epitaxial layer L1 of the first S / D component 350A and serves as a transition or interface epitaxial layer to promote the subsequent growth of the epitaxial layer 344A. In the present embodiment, the epitaxial layer 342A includes germanium at a concentration G1 (e.g., atomic percentage or at%). The epitaxial layer 342A can be formed by any suitable process, such as metal organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), etc. or a combination thereof. In this embodiment, the bottom surface of the epitaxial layer 342A is in direct contact with the first doped layer 340A. Figure 7B , portions of the sidewalls of epitaxial layer 342A (eg, along the inclined facets) may be in direct contact with diffusion region 341A.

[0047] refer to Figure 2B and Figure 8 The method 250 then forms an epitaxial layer 344A over the epitaxial layer 342A in operation 260. The epitaxial layer 344A is Fig. 9 The epitaxial layer 344A is formed to directly contact each facet (or surface) of the epitaxial layer 342A. The epitaxial layer 344A can be formed using the same process as described above with respect to the epitaxial layer 342A.

[0048] Still reference Figure 2B and Figure 8 In operation 262, method 250 forms an epitaxial layer 346A over epitaxial layer 344A. Epitaxial layer 346A is Fig. 9The epitaxial layer 346A has a protrusion height RH1, and the height RH1 is measured from the top surface 304T of the fin 304 to the top surface of the epitaxial layer 346A. In some embodiments, the top portion of the epitaxial layer 346A is grown to protrude from the top surface 304T of the fin 304, so that the protrusion height RH1 is positive (i.e., greater than zero). In some embodiments, the top portion of the epitaxial layer 346A is located below the top surface 304T of the fin 304, so that the protrusion height RH1 is negative (i.e., less than zero). According to some examples, the protrusion height RH1 can be in a range from about -40nm to about 40nm.

[0049] In the present embodiment, the epitaxial layer 346A includes germanium at a concentration G3, which is higher than the concentrations G1 and G2. In some embodiments, the concentrations G1 and G2 are each about 20 at% to about 30 at%, and the concentration G3 is about 50 at% to about 60 at%. In various embodiments, due to the lattice mismatch between silicon (i.e., in the fin 304 or substrate 302) and silicon germanium (i.e., in the epitaxial layer 346A), the relatively high germanium concentration G3 causes compressive strain in the corresponding channel region 311, which increases the current in the channel region 311 for improved device performance (e.g., higher device speed). However, the increase in the amount of germanium may also increase the germanium concentration gradient between the epitaxial layer 346A and the substrate 302 (and the fin 304), increase the driving force for the diffusion of germanium toward the substrate 302 and potentially cause leakage problems.

[0050] In the present embodiment, the first doped layer 340A is used as a barrier layer for reducing or preventing germanium from diffusing from at least the epitaxial layer 346A into the substrate 302. In this regard, the extent of this barrier to diffusion is determined based on the concentration C1 of boron included in the first doped layer 340A. In the present embodiment, the concentration G3 and the concentration C1 are adjusted to have a generally positive correlation. For example, an increase in the concentration G3 corresponds to an increase in the concentration C1 provided in the first doped layer 340A. In some embodiments, the position of the first doped layer 340A as a diffusion barrier layer for germanium is determined based on the depth D1 of the first S / D groove 330A, as described above.

[0051] refer to Figure 2B and Fig. 9, the method 250 forms an epitaxial layer 348A over the epitaxial layer 346A in operation 264 to complete the formation of the first S / D component 350A, the epitaxial layer 348A being the third epitaxial layer L3 of the first S / D component 350A. In the present embodiment, the epitaxial layer 348A includes a silicon-based capping layer that will be consumed during a subsequent silicidation process. In this regard, the epitaxial layer 348A does not contain or substantially does not contain any germanium. The epitaxial layer 348A has a height CAP1 measured from the top surface 304T of the fin 304 to the top surface of the epitaxial layer 348A. In this regard, the height CAP1 is also related to the protrusion height RH1 of the epitaxial layer 346A.

[0052] In various embodiments, the resulting first S / D component 350A is doped with a suitable dopant, such as boron. The dopant may be introduced by an in-situ doping process while growing the epitaxial layers 342A, 344A, and 346A. Alternatively, the dopant may be introduced by an implantation process after forming the epitaxial layers 342A, 344A, and 346A. An annealing process may be applied after doping the epitaxial layers 342A, 344A, and 346A to activate the dopant.

[0053] After the formation of the first S / D feature 350A in the first region 302A is completed, refer to Figure 2C , the method 250 continues to form a second S / D component 350B in the second region 302B in operations 266-278. Although the method 250 forms the first S / D component 350A before forming the second S / D component 350B, the disclosed embodiments do not limit the order in which the S / D components are formed. For example, the second S / D component 350B (as described below) can be formed before forming the first S / D component 350A.

[0054] refer to Figure 2C and Fig.10 , method 250 forms a patterned mask 328 over first region 302A in operation 266 to pattern the first region 302A in a manner similar to that described above with respect to Figure 5 The second region 302B is exposed during the process described in operation 252. For example, an adhesion layer 322 and a protective layer 324 are conformally deposited over the device 300 (including the first S / D feature 350A) and then patterned using a patterned mask 328 to expose the second region 302B.

[0055] Subsequently, the method 250 forms a second S / D recess 330B in a portion of the fin 304 in the second region 302B in operation 268. The second S / D recess 330B can be formed in a manner similar to that described above with respect to forming the first S / D recess 330A. For example, the second S / D recess 330B can be formed by performing a dry etching process using the adjacent second dummy gate structure 310B as an etching mask.

[0056] In the present embodiment, the second S / D groove 330B has a width W2 across its top opening and a depth D3 measured from the bottom surface of the second S / D groove 330B to the top surface 304T of the fin 304. By adjusting the pitch P2 of at least two adjacent second dummy gate structures 310B, the width W2, the depth D3, or both of them can be adjusted, similar to the above description of the first S / D groove 330A. In the present embodiment, the width W2, the depth D3, or both of them are configured to be different from the width W1 and the depth D1, respectively. Fig.10 , pitch P2 is greater than pitch P1, and width W2 is greater than width W. In addition, by controlling the dry etching process to remove a greater amount of fins 304 relative to the formation of the first S / D recess 330A, the depth D3 of the second S / D recess 330B is configured to be greater than the depth D1.

[0057] Subsequently, the method 250 performs a second implantation process 406 in operation 270 to form a second doping layer 340B in the top portion of the fin 304 (or substrate 302) exposed in the second S / D groove 330B. At this point, the second doping layer 340B is formed to a depth (or position) corresponding to the depth D3 of the second S / D groove 330B, which is greater than the depth D1 of the first S / D groove 330A (or the first S / D feature 350A). In other words, according to the present embodiment, the second doping layer 340B is positioned below the first doping layer 340A.

[0058] The second doped layer 340B is similar to the first doped layer 340A in that they include the same dopant, such as boron in the present embodiment, wherein the second S / D component 350B is configured to provide a P-type device. Optionally, in embodiments where the second S / D component 350B is configured to provide an N-type device, the second doped layer 340B may include phosphorus and / or arsenic. In some embodiments, the second doped layer 340B is formed by performing an implantation process similar to that described above with respect to forming the first doped layer 340A.

[0059] In this regard, the second doped layer 340B is generally configured as a barrier layer to reduce or prevent germanium in the second S / D feature 350B from diffusing out of a subsequently formed epitaxial layer in the second S / D recess 330B into the substrate 302. However, unlike the first doped layer 340A, the second doped layer 340B includes boron at a concentration C2 that is less than the concentration C1. Based on the generally positive correlation between concentration and thickness described above, this difference in concentration causes the thickness T2 of the second doped layer 340B to also be less than the thickness T1. Similar to the first doped layer 340A, as shown in FIG. Fig.11As depicted, boron can diffuse in the fin 304 (or substrate 302) along the sidewalls of the second S / D recess 330B (e.g., vertically along the Z-axis) to form a diffusion region 341B connected to the second doped layer 340B. In some embodiments, due to the diffusion of boron along the X-axis (e.g., lateral diffusion), for example, the second doped layer 340B is formed to have a width F2 greater than the width W2. For simplicity, the subsequent description of embodiments of the present disclosure is directed to embodiments in which the second doped layer 340B has a width W2.

[0060] In this embodiment, the depth D4 (which is measured from the bottom surface of the second doped layer 340B to the top surface 304T of the fin 304) explains the depth D3 and the thickness T2, and can be used to indicate the position of the second doped layer 340B. According to some examples, depending on the difference between the depths D1 and D3 and the difference between the thicknesses T1 and T2 (i.e., the difference between the concentrations C1 and C2), the values of the depths D2 and D4 can be substantially the same or different, and can each be in the range from about 30 nm to about 300 nm. For example, if the difference between the depths D1 and D3 (where D1 < D3) is greater than the difference between the thicknesses T1 and T2 (where T1 > T2), then the depth D4 is greater than the depth D2, and vice versa. In some embodiments, the second doped layer 340B is formed to the width W2 of the S / D recess 330B.

[0061] Reference Figure 2C and Fig.11 and, method 250 implements a second wet etching process (not depicted) in operation 272 to laterally expand the second S / D recess 330B along the X-axis. The second wet etching process is implemented using a wet etchant similar to that used in the first wet etching process 404. The second wet etching process defines the width W3 of the widest part of the second S / D recess 330B, where the width W3 is greater than the width W2. The width W3 can be adjusted in a manner similar to the width W1 described in detail above.

[0062] With common reference to Figure 2C 、 Fig.11 and Fig.12, the method 250 forms a second S / D component 350B including epitaxial layers 342B, 344B, 346B, and 348B over the second doped layer 340B in operations 274-278. In the present embodiment, the functions of the epitaxial layers 342B, 344B, 346B, and 348B of the second S / D component 350B are similar or analogous to those of the epitaxial layers 342A, 344A, 346A, and 348A of the first S / D component 350A, respectively. For example, the epitaxial layers 342B and 344B are collectively considered to be a first epitaxial layer or L1 of the second S / D component 350B; the epitaxial layer 346B is considered to be a second epitaxial layer or L2 of the second S / D component 350B; and the epitaxial layer 348B is considered to be a third epitaxial layer or L3 of the second S / D component 350B. In the present embodiment, after operation 278 of forming the second S / D feature 350B is completed, each of the resulting epitaxial layers 342B, 344B, and 346B comprising silicon germanium is doped with a suitable dopant, such as boron, by a process similar to that described above with respect to doping the first S / D feature 350A.

[0063] Epitaxial layers 342B, 344B, 346B and 348B can be formed in a manner similar to that described above for forming epitaxial layers 342A, 344A, 346A and 348A. In the present embodiment, epitaxial layers 342B, 344B and 346B each include silicon germanium (SiGe) doped with a P-type dopant (such as boron), but differ in the concentration of the germanium included therein. For example, epitaxial layers 342B, 344B and 346B can each include germanium of concentrations G4, G5 and G6, respectively. In the present embodiment, concentration G6 is adjusted to be less than concentration G3 of the first S / D component 350A, but greater than each of concentrations G4 and G5. Concentrations G4 and G5 can be the same or different. In addition, epitaxial layer 348B includes a capping layer based on silicon for forming a silicide layer in a subsequent silicidation process.

[0064] refer to Fig.10 and Fig.12 , since the depth D3 is greater than the depth D1, the top surface of the epitaxial layer 346B is located below the top surface 304T of the fin 304, so that the protrusion height RH2 of the epitaxial layer 346B (corresponding to the protrusion height RH1 of the epitaxial layer 346A) is negative (i.e., less than zero). According to some examples, the protrusion height RH2 can be in the range from about -40nm to about 40nm. Therefore, the height CAP2 of the epitaxial layer 348B (which is measured from the top surface 304T of the fin 304 to the top surface of the epitaxial layer 348B and is related to the protrusion height RH2 of the epitaxial layer 346B) is less than the height CAP1.

[0065] refer to Fig.13By adjusting the relative position and concentration of the first doping layer 340A and the second doping layer 340B, the first S / D component 350A and the second S / D component 350B can be adjusted to have different profiles. For example, by forming the first doping layer 340A closer to the top surface 304T of the fin 304 than the second doping layer 340B, that is, the depth D3 is greater than the depth D1, the size of the second S / D component 350B embedded in the fin 304 is larger than the size of the first S / D component 350A, which enables a higher switching speed in the device formed by the second S / D component 350B. In various embodiments, the depth of each of the S / D components 350A and 350B is also related to other profile parameters, such as the protrusion height RH (negative correlation) and the width of the widest part of the S / D component (positive correlation). For example, referring to Fig.13 , the second S / D feature 305B has a width W3 greater than the width W1 and a protrusion height RH2 less than the protrusion height RH1.

[0066] In various embodiments, the concentrations C1 and C2 of boron in the first doped layer 340A and the second doped layer 340B are adjusted according to the concentration of germanium in their corresponding epitaxial layers, respectively, for improved blocking properties against germanium diffusion into the channel region of the device 300. For example, referring to Fig.13 , the concentration C1 is adjusted to be greater than the concentration C2 because the diffusion degree of germanium in the first S / D component 350A (which has a higher germanium concentration G3) is greater than the diffusion degree of germanium in the second S / D component 350B (which has a lower germanium concentration G6). In addition, in some embodiments, too high concentrations C1 or C2 may also cause boron to diffuse into the channel region 311 of the device 300, which may adversely affect device performance. In this regard, the first S / D component 350A having a higher germanium concentration G3 and the corresponding first doping layer 340A having a higher boron concentration C1 are formed at a shallower depth D1 than the second S / D component 350B (which has a lower germanium concentration G6) and the corresponding second doping layer 340B having a lower boron concentration C2.

[0067] Therefore, the disclosed embodiments provide methods for independently adjusting various parameters of epitaxial formation to realize S / D components with different profiles on a single substrate, and thus realize devices with different performances. In addition, the doped layer implanted under the source / drain component provides a barrier to the diffusion of germanium from the S / D component to the nearby channel region, thereby reducing or preventing leakage in the device.

[0068] refer to Fig.13, after forming the second S / D feature 350B, the adhesion layer 322 and the protective layer 324 remaining above the first region 302A are subsequently removed from the device 300. The adhesion layer 322 and the protective layer 324 can be removed by any suitable etching process, such as a dry etching process or a wet etching process. In some embodiments, the etching process is selective to the adhesion layer 322 and the protective layer 324, without removing or substantially removing adjacent components of the device 300.

[0069] refer to Figure 2A and Fig.14 , the method 200 forms an interlayer dielectric (ILD) layer 354 over the device 300 in operation 212. In some embodiments, before forming the ILD layer 354, a contact etch stop layer (CESL; not depicted) is formed over the device 300. The ILD layer 354 and the CESL include different materials to provide etching selectivity between them in subsequent manufacturing processes. The CESL may include any suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon oxide, etc., or a combination thereof, and may be formed by a suitable formation method, such as CVD, ALD, PVD, etc., or a combination thereof. In some embodiments, the ILD layer 354 includes any suitable dielectric material, such as silicon oxide, a low-k dielectric material as described above, etc., or a combination thereof, and may be deposited by any suitable method, such as CVD, PECVD, FCVD, etc. After forming the ILD layer 354, a planarization process, such as a CMP process, may be performed to achieve a flush top surface for the dielectric layer 347. The CMP process may also remove portions of the mask and CESL disposed over the dummy gate structure 310. After the planarization process, the top surface of dielectric layer 347 is substantially coplanar with the top surface of dummy gate structure 310, as depicted herein. In some embodiments, dielectric layer 347 is omitted, thereby making ILD layer 354 (after planarization) substantially coplanar with the top surface of dummy gate structure 310.

[0070] refer to Figure 2A and Fig.15 In operation 214, the method 200 replaces the first dummy gate structure 310A with the first metal gate structure 360A, and replaces the second dummy gate structure 310B with the second metal gate structure 360B. In some parts of the disclosed embodiments, for simplicity, the first metal gate structure 360A and the second metal gate structure 360B are collectively referred to as metal gate structures 360.

[0071] Replacing the dummy gate structure 310 includes first removing the dummy gate structure 310 to form a gate trench (not depicted) between the gate spacers 320. In some embodiments, the dummy gate structure 310 is removed by one or more etching steps between the corresponding gate spacers 320 to expose the channel region 311 of the fin 304. In some embodiments, when etching the dummy gate electrode, the dummy gate dielectric layer (not depicted) can be used as an etch stop layer. The dummy gate dielectric layer can then be removed after removing the dummy gate electrode. In some examples, the top portion of the gate spacer 320 can be removed (or shortened) by a suitable etching process to expose the top portion of the ILD layer 354.

[0072] refer to Figure 2A and Fig.15 , method 200 forms a metal gate structure 360 ​​in the gate trench. The first metal gate structure 360A is formed adjacent to the first S / D feature 350A in the first region 302A, and the second metal gate structure 360B is formed adjacent to the second S / D feature 350B in the second region 302B. In some embodiments, forming the metal gate structure 360 ​​includes conformally depositing a gate dielectric layer (not separately depicted) in the gate trench. The gate dielectric layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, a high-k dielectric material (i.e., having a dielectric constant greater than the dielectric constant of silicon oxide, the dielectric constant of silicon oxide being about 3.9), etc., or a combination thereof. The high-k dielectric material may include an oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, etc., or a combination thereof. The gate dielectric layer may be formed by any suitable method, such as ALD, CVD, PECVD, molecular beam deposition (MBD), etc., or a combination thereof. In some embodiments, an interfacial layer (not depicted) may be formed in the gate trench before forming the gate dielectric layer. The interfacial layer may include an oxide, such as silicon oxide, and may be formed by any suitable method, such as ALD, CVD, thermal oxidation, chemical oxidation, etc., or a combination thereof.

[0073] Subsequently, a gate electrode (not separately depicted) is formed over the gate dielectric layer, thereby producing a metal gate structure 360 ​​in the gate trench. The gate electrode may include any suitable metal, such as tungsten (W), copper (Cu), ruthenium (Ru), aluminum (Al), gold (Au), cobalt (Co). The gate electrode may be formed as a blanket layer over the gate dielectric layer by any suitable method (such as PVD, CVD, electroplating, chemical plating, etc., or a combination thereof), and then planarized by, for example, a CMP process to expose the top surface of the gate spacer 320. Although not depicted, the gate electrode may also include a barrier layer, a seed layer, etc., or a combination thereof. In one example, the barrier layer may include Ti, Ta, TiN, TaN, etc., or a combination thereof, and may be deposited by any suitable method, such as CVD or ALD.

[0074] In some embodiments, although not depicted, one or more work function layers may be conformally formed over the gate dielectric layer before forming the gate electrode. The work function layer may include a P-type work function layer, an N-type work function layer, a multilayer thereof, or a combination thereof. In the discussion herein, the work function layer may also be referred to as a work function metal. Examples of work function layers may include TiN, TaN, Ru, Mo, Al, ZrSi2, MoSi2, TaSi2, NiSi2, WN, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, etc., or a combination thereof. The work function layer may be deposited by CVD, PVD, ALD, etc., or a combination thereof. Additional layers (not depicted) including a capping layer, a glue layer (or an adhesive layer), etc., or a combination thereof may also be formed between the gate dielectric layer and the gate electrode by any suitable method (such as CVD, PVD, ALD, MBD, etc., or a combination thereof). In some embodiments, the capping layer may include silicon, silicon oxide, silicon nitride, etc., or a combination thereof. The glue layer may each include Ti, Ta, TiN, TaN, etc. or a combination thereof. In some embodiments, the work function layer, capping layer, glue layer, etc. may each be formed to have a U-shaped configuration over the gate dielectric layer, which is also formed to have a U-shaped configuration.

[0075] Still reference Figure 2A and Fig.15, the method 200 forms a first silicide layer 366A over the first S / D component 350A and forms a second silicide layer 366B over the second S / D component 350B in operation 216. In the present embodiment, forming the first silicide layer 366A and the second silicide layer 366B includes: first forming an ILD layer 364 over the ILD layer 354; and then patterning the ILD layers 364 and 354 to form S / D contact openings (not depicted) over each of the first S / D component 350A and the second S / D component 350B. The S / D contact openings can be formed by a series of photolithography and etching techniques similar to those described above with respect to forming the fin 304. In some embodiments, a gate contact opening (not depicted) over the metal gate structure 360 ​​is also formed in a similar manner.

[0076] Subsequently, a metal layer (not depicted) including, for example, nickel (Ni), titanium (Ti), tungsten (W), cobalt (Co), molybdenum (Mo), etc., or a combination thereof, is deposited over the exposed epitaxial layers 348A and 348B in their respective S / D contact openings. The metal layer may be deposited by any suitable process at high temperature, such as CVD, PVD, ALD, etc., or a combination thereof, to allow the bottom portion of the metal layer to react with the exposed epitaxial layers 348A and 348B. The reaction produces a first silicide layer 366A over the epitaxial layer 346A and a second silicide layer 366B over the epitaxial layer 346B. Any unreacted metal layer disposed over the first silicide layer 266A and the second silicide layer 266B may be removed by a suitable etching process.

[0077] Still reference Figure 2A and Fig.15, the method 200 forms a first S / D contact 372A and a second S / D contact 372B in the S / D contact opening in operation 218. Subsequently, a conductive material (e.g., metal) is deposited and planarized over the device 300, thereby filling the S / D contact opening to form a first S / D contact 372A electrically coupled to the first silicide layer 366A and a second S / D contact 372B electrically coupled to the second silicide layer 366B, and filling the gate contact opening to form a first gate contact 370A electrically coupled to the first metal gate structure 360A and a second gate contact 370B electrically coupled to the second metal gate structure 360B. In some embodiments, since the first S / D component 350A has a positive protrusion height RH1 and a relatively large height CAP1 and the second S / D component 350B has a negative protrusion height RH2 and a relatively small height CAP2, forming the S / D contact opening over the first S / D component 350A may over-etch a portion of the epitaxial layer 348A. Thus, the bottom surface of the first S / D contact 372A extends below the top surface of the first silicide layer 366A (formerly the epitaxial layer 348A), while the bottom surface of the second S / D contact 372B remains above the top surface of the second silicide layer 366B.

[0078] Afterwards, return to reference Figure 2A , method 200 may perform additional operations on device 300 at operation 220. For example, interconnect features (e.g., vias and conductive lines) may be formed to electrically couple components of device 300 (such as S / D contacts 372A and 372B and gate contacts 370A and 370B) with additional features.

[0079] In some embodiments, reference Fig.16 , Fig.16 and Fig.15 In contrast, the first doped layer 340A and the second doped layer 340B are tuned to have the same boron concentration so that they have the same thickness T3 despite being positioned at different depths relative to the top surface 304T of the fin 304 .

[0080] According to one aspect of an embodiment of the present disclosure, a semiconductor structure includes a semiconductor layer. The semiconductor structure includes a first epitaxial source / drain component extending into the semiconductor layer. The semiconductor structure includes a first doped region in the semiconductor layer below the first epitaxial source / drain component. The first doped region includes a first concentration of dopant. The semiconductor structure includes a second epitaxial source / drain component extending into the semiconductor layer. The semiconductor structure includes a second doped region in the semiconductor layer below the second epitaxial source / drain component. The second doped region includes a second concentration of dopant less than the first concentration.

[0081] According to another aspect of an embodiment of the present disclosure, a semiconductor structure includes a semiconductor layer. The semiconductor structure includes a first source / drain component extending into the semiconductor layer. The semiconductor structure includes a first barrier layer located below the first source / drain component, wherein the first barrier layer is disposed at a first distance away from a top surface of the semiconductor layer. The first barrier layer includes a first concentration of dopant. The semiconductor structure includes a second source / drain component extending into the semiconductor layer. The semiconductor structure includes a second barrier layer located below the second source / drain component, wherein the second barrier layer is disposed at a second distance away from a top surface of the semiconductor layer. The first distance is less than the second distance. The second barrier layer includes a second concentration of dopant.

[0082] According to another aspect of an embodiment of the present disclosure, a method includes performing a first etching process to form a recess in a semiconductor layer adjacent to a gate structure. The method includes forming a doped layer in the recess. The method includes performing a second etching process to laterally expand a portion of the recess. The method includes forming a source / drain component in the recess, wherein a bottom surface of the source / drain component contacts the doped layer.

[0083] Some embodiments of the present application provide a semiconductor structure, comprising: a semiconductor layer; a first epitaxial source / drain component extending into the semiconductor layer; a first doped region located in the semiconductor layer below the first epitaxial source / drain component, the first doped region comprising a first concentration of a dopant; a second epitaxial source / drain component extending into the semiconductor layer; and a second doped region located in the semiconductor layer below the second epitaxial source / drain component, the second doped region comprising a second concentration of the dopant less than the first concentration. In some embodiments, a first distance between a bottom surface of the first epitaxial source / drain component and a top surface of the semiconductor layer is less than a second distance between a bottom surface of the second epitaxial source / drain component and the top surface of the semiconductor layer. In some embodiments, the first distance between the first doped region and the top surface of the semiconductor layer is less than a second distance between the second doped region and the top surface of the semiconductor layer. In some embodiments, the first doped region has a first thickness, and the second doped region has a second thickness less than the first thickness. In some embodiments, the first epitaxial source / drain component and the second epitaxial source / drain component comprise silicon germanium, and wherein the dopant comprises boron. In some embodiments, the first epitaxial source / drain feature includes a third concentration of germanium, and the second epitaxial source / drain feature includes a fourth concentration of germanium that is less than the third concentration. In some embodiments, a first width of the first epitaxial source / drain feature and a second width of the second epitaxial source / drain feature each increase and then decrease in a direction from a top surface of the semiconductor layer toward the first doped region and the second doped region, respectively. In some embodiments, the first width has a first maximum value, and the second width has a second maximum value that is greater than the first maximum value.

[0084] Some other embodiments of the present application provide a semiconductor structure, comprising: a semiconductor layer; a first source / drain component extending into the semiconductor layer; a first barrier layer located below the first source / drain component, the first barrier layer being disposed at a first distance away from a top surface of the semiconductor layer and comprising a first concentration of a dopant; a second source / drain component extending into the semiconductor layer; and a second barrier layer located below the second source / drain component, the second barrier layer being disposed at a second distance away from the top surface of the semiconductor layer and comprising a second concentration of the dopant, wherein the first distance is less than the second distance. In some embodiments, the first concentration is the same as the second concentration. In some embodiments, the first concentration is greater than the second concentration. In some embodiments, the widest portion of the first source / drain component has a first width, and the widest portion of the second source / drain component has a second width greater than the first width. In some embodiments, the top surface of the first source / drain component is separated from the top surface of the semiconductor layer by a third distance, and the top surface of the second source / drain component is separated from the top surface of the semiconductor layer by a fourth distance, and wherein the third distance is greater than the fourth distance. In some embodiments, the first source / drain feature includes a third concentration of germanium, and the second source / drain feature includes a fourth concentration of germanium that is less than the third concentration.

[0085] Still other embodiments of the present application provide a method for manufacturing a semiconductor structure, comprising: performing a first etching process to form a recess in a semiconductor layer adjacent to a gate structure; forming a doped layer in the recess; performing a second etching process to laterally expand a portion of the recess; and forming a source / drain component in the recess, wherein the bottom surface of the source / drain component contacts the doped layer. In some embodiments, forming the source / drain component comprises forming a plurality of epitaxial layers. In some embodiments, forming the source / drain component makes the top portion of the source / drain component protrude from the top surface of the semiconductor layer. In some embodiments, the method further comprises forming a silicide layer in the top portion of the source / drain component. In some embodiments, the method further comprises: forming a dielectric layer above the silicide layer; performing a third etching process to form a contact opening in the dielectric layer; and forming a contact component in the contact opening. In some embodiments, the groove is a first groove, the gate structure is a first gate structure, the doping layer is a first doping layer including a first concentration of a dopant, and the source / drain component is a first source / drain component, and after forming the first source / drain component, the method further includes: performing a third etching process to form a second groove adjacent to the second gate structure; forming a second doping layer in the second groove, the second doping layer including the dopant at a second concentration less than the first concentration; performing a fourth etching process to laterally expand the second groove; and forming a second source / drain component in the second groove, the second source / drain component contacting the second doping layer.

[0086] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent configurations do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, include: Semiconductor layer; a first epitaxial source / drain feature extending into the semiconductor layer; a first doped region located in the semiconductor layer below the first epitaxial source / drain component, the first doped region comprising a first concentration of a dopant; a second epitaxial source / drain feature extending into the semiconductor layer; as well as A second doped region is located in the semiconductor layer below the second epitaxial source / drain feature, the second doped region including a second concentration of the dopant that is less than the first concentration.

2. The semiconductor structure according to claim 1, in, A first distance between a bottom surface of the first epitaxial source / drain feature and a top surface of the semiconductor layer is smaller than a second distance between a bottom surface of the second epitaxial source / drain feature and the top surface of the semiconductor layer.

3. The semiconductor structure according to claim 1, in, A first distance between the first doping region and a top surface of the semiconductor layer is smaller than a second distance between the second doping region and the top surface of the semiconductor layer.

4. The semiconductor structure according to claim 1, in, The first doped region has a first thickness, and the second doped region has a second thickness that is less than the first thickness.

5. The semiconductor structure according to claim 1, in, The first epitaxial source / drain feature and the second epitaxial source / drain feature include silicon germanium, and wherein the dopant includes boron.

6. The semiconductor structure according to claim 5, in, The first epitaxial source / drain feature includes a third concentration of germanium, and the second epitaxial source / drain feature includes a fourth concentration of germanium that is less than the third concentration.

7. The semiconductor structure according to claim 1, in, A first width of the first epitaxial source / drain feature and a second width of the second epitaxial source / drain feature each increase and then decrease in a direction from a top surface of the semiconductor layer toward the first doped region and the second doped region, respectively.

8. The semiconductor structure according to claim 7, in, The first width has a first maximum value, and the second width has a second maximum value greater than the first maximum value.

9. A semiconductor structure, include: Semiconductor layer; a first source / drain feature extending into the semiconductor layer; a first barrier layer beneath the first source / drain feature, the first barrier layer being disposed a first distance away from a top surface of the semiconductor layer and comprising a first concentration of a dopant; a second source / drain feature extending into the semiconductor layer; as well as A second barrier layer is located below the second source / drain feature, the second barrier layer is disposed at a second distance away from the top surface of the semiconductor layer and includes a second concentration of the dopant, wherein the first distance is less than the second distance.

10. A method of manufacturing a semiconductor structure, include: performing a first etching process to form a recess in the semiconductor layer adjacent to the gate structure; forming a doping layer in the groove; performing a second etching process to laterally expand a portion of the recess; as well as A source / drain feature is formed in the recess, wherein a bottom surface of the source / drain feature contacts the doped layer.

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