Die edge guard ring based on back contact

Abstract

The invention relates to a die edge guard ring based on backside contact. A guard ring is described. In an example, a semiconductor die includes an active device layer including a plurality of nanobelt devices. A dielectric structure is over the active device layer. A first die edge metal guard ring is in the dielectric structure and surrounds an outer periphery of the plurality of nanobelt devices. A plurality of metallization layers are in the dielectric structure and within the first die edge metal guard ring. A plurality of direct backside contacts extend to the active device layer. A plurality of backside metallization structures is underlying the plurality of direct backside contacts. A plurality of direct backside contacts are connected to the plurality of backside metallization structures. A second die edge metal guard ring laterally surrounds the plurality of backside metallization structures.

Description

Technical Field

[0001] Embodiments of the present disclosure pertain to the field of advanced integrated circuit structure fabrication, and in particular, to the field of backside contact based die edge protection rings. Background Art

[0002] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased functional unit density within the limited area of ​​a semiconductor chip. For example, shrinking transistor size allows an increased number of memory or logic devices to be combined on a chip, facilitating the manufacture of products with increased capacity. However, the quest for greater capacity is not without its problems. The necessity to optimize the performance of each device becomes increasingly important.

[0003] The variability of conventional and currently known manufacturing processes may limit the possibility of further scaling them to smaller and smaller nodes. Therefore, the manufacturing of functional components required for future technology nodes may require the introduction of new methods or the integration of new technologies in or instead of current manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 A cross-sectional view of a guard ring 100 for a fin-based process flow is illustrated.

[0005] Figure 2 A cross-sectional view of an integrated circuit structure 120 including a guard ring and a device region for a nanoribbon process flow having only front contacts and no back contacts is illustrated.

[0006] Figure 3 A cross-sectional view of an integrated circuit structure 150 for a nanoribbon process flow with direct backside contact according to an embodiment of the present disclosure is illustrated, the integrated circuit structure 150 including guard ring option 1, guard ring option 2, and a device region.

[0007] Figure 4A A cross-sectional view of a semiconductor die having only a front-side moisture barrier seal ring and only front-side wiring is illustrated.

[0008] Figure 4B A cross-sectional view of a semiconductor die with only a front-side moisture barrier seal ring and front-side wiring and back-side direct contacts is illustrated.

[0009] Figure 4C A cross-sectional view of a semiconductor die having only a front-side moisture barrier seal ring and both front-side and back-side wiring is illustrated.

[0010] Figure 4DA cross-sectional view of a semiconductor die with direct back side contact and back side wiring and a back side moisture barrier seal ring according to an embodiment of the present disclosure is illustrated.

[0011] Figure 4E A cross-sectional view of another semiconductor die having direct back side contact and back side wiring and a back side moisture barrier seal ring according to an embodiment of the present disclosure is illustrated.

[0012] Figure 5 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present invention is illustrated.

[0013] Fig. 6A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is illustrated.

[0014] Figure 6B The diagram shows a cross-sectional view taken along the a-a' axis according to an embodiment of the present disclosure. Fig. 6A A cross-sectional view of a source or drain electrode of a nanowire-based integrated circuit structure.

[0015] Figure 6C FIG. 1 shows a diagram of a 3D image taken along the bb' axis according to an embodiment of the present disclosure. Fig. 6A Cross-sectional view of the channel of a nanowire-based integrated circuit structure.

[0016] Figure 7 A cross-sectional view of an integrated circuit structure having four metallization layers with metal line compositions and pitches over two metallization layers with different metal line compositions and smaller pitches is illustrated in accordance with an embodiment of the present disclosure.

[0017] Figure 8 A computing device according to one implementation of the present disclosure is illustrated.

[0018] Fig. 9 An interposer including one or more embodiments of the present disclosure is illustrated.

[0019] Fig.10 is an isometric view of a mobile computing platform according to one embodiment of the present disclosure, the mobile computing platform employing an IC manufactured according to one or more processes described herein, or including one or more features described herein.

[0020] Fig.11 Illustrated is a cross-sectional view of a flip-chip mounted die according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] A back contact based die edge protection ring is described. In the following description, many specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other cases, well-known features such as integrated circuit design layouts are not described in detail in order to avoid unnecessarily obscuring the embodiments of the present disclosure. In addition, it is to be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0022] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of these embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration". Any implementation described as an example in the text is not necessarily to be construed as being preferred or superior to other implementations. In addition, it is not intended to be bound by any express or implied theory presented in the preceding technical field, background technology, summary of the invention, or the following detailed description.

[0023] This specification includes references to "one embodiment" or "an embodiment." The appearance of the phrase "in one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0024] Terminology. The following paragraphs provide definitions or context for terms found in this disclosure, including the appended claims:

[0025] “Comprising”. This term is open ended. As used in the appended claims, this term does not exclude additional structures or operations.

[0026] "Configured to." Various units or components may be described or claimed as being "configured to" perform one or more tasks. In such contexts, "configured to" is used to imply structure by indicating that the unit or component includes structure to perform those tasks during operation. Thus, the unit or component may be considered to be configured to perform tasks even when the specified unit or component is not currently operational (e.g., not turned on or inactive). Reciting that a unit or circuit or component is "configured to" perform one or more tasks expressly does not intend to invoke 35 U.S.C. §112, sixth paragraph, with respect to that unit or component.

[0027] "First," "second," etc. As used herein, these terms are used as labels for the nouns that precede them, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0028] "Coupled" - The following description refers to elements or nodes or features that are "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element or node or feature is directly or indirectly joined to (or communicates directly or indirectly with) another element or node or feature, and not necessarily mechanically.

[0029] In addition, in the following description, certain terms may also be used for reference purposes only, and thus are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "rear," "posterior," "side," "outer," and "inner" describe the orientation or position, or both, of parts of a component within a consistent but arbitrary frame of reference, which becomes clear by reference to the text and related drawings describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0030] “Inhibit” - As used herein, inhibit is used to describe reducing or minimizing an effect. When a component or feature is described as inhibiting an action, motion, or condition, it may completely prevent the result or outcome or future state. Additionally, “inhibit” may also refer to reducing or mitigating an outcome, performance, or effect that might otherwise occur. Thus, when a component, element, or feature is said to inhibit a result or state, it need not completely prevent or eliminate that result or state.

[0031] Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses everything up to (but not including) the deposition of metal interconnect layers. After the final FEOL operations, the result is typically a wafer with isolated transistors (e.g., without any lines).

[0032] Embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal layers, and joints for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnects, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0033] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although exemplary processing schemes may be described using FEOL processing scenarios, such methods may also be applicable to BEOL processing. Similarly, although exemplary processing schemes may be described using BEOL processing scenarios, such methods may also be applicable to FEOL processing.

[0034] According to one or more embodiments of the present disclosure, a backside contact based die edge protection ring solution is described. One or more embodiments are directed to a sealed die edge ring for a structure with a direct backside contact for a nanoribbon based device (where the term nanoribbon may also refer to nanowires or nanosheets).

[0035] To provide context, direct back contact to nanoribbon transistors is one of the key features that enables technology scaling. A reliable solution compatible with the direct back contact scheme is needed to prevent moisture penetration and achieve crack arrest at the die edge.

[0036] According to one or more embodiments of the present disclosure, a method is provided to have the front contacts directly on the back contacts in the die edge guard ring area without any nanoribbons in between, thereby resulting in a full metal wall. Advantages of implementing the embodiments described herein may include achieving a completely hermetic seal around the die, which will protect the internal circuits (metal and dielectric) from moisture damage during the life of the product and also help with crack arrest.

[0037] The implementation of the embodiments described herein can be revealed by the full metal walls present in the die edge guard ring area. Reverse engineering techniques such as TEM in the guard ring area will highlight these features.

[0038] To provide further context, nanoribbon (or Gate All Around, GAA) transistors and backside power delivery (PowerVia) are some of the key drivers that enable technology scaling beyond FINFET process flows. A typical nanoribbon flow uses deep boundary vias (DVBs) that connect the frontside transistor contacts to the backside metal layer. To enable further logic scaling, one of the main options is to have the backside contacts directly on the nanoribbon.

[0039] For all the above architectures, it is imperative to develop a die etch guard ring solution that prevents moisture intrusion into the active circuit during product use and helps combat chip cracking. For FINFET processes, the guard ring solutions that have been implemented in the industry are Figure 1 as shown in .

[0040] Figure 1 A cross-sectional view of a guard ring 100 for a fin-based process flow is illustrated. The guard ring 100 includes a silicon fin 102, a trench contact 104, a trench via 106, a lowest metallization layer 108, and a back end (BE) / far back end (FBE) layer 110.

[0041] For the nanoribbon process with only front-side contacts, deep boundary vias or deep via bars (DVBs) are connected to the back metal layer BM0 and form a full metal wall that acts as a guard ring, such as Figure 2 as shown in .

[0042] Figure 2 A cross-sectional view of an integrated circuit structure 120 for a nanoribbon process flow with only front contacts and no back contacts is shown, the integrated circuit structure 120 including a guard ring and a device region. The guard ring includes a back end (BE) / far back end (FBE) layer 122, a first back metal layer 124, a deep via bar 126, a trench contact 128, a trench via 130, a lowest metallization layer 132, and a back end (BE) / far back end (FBE) layer 134. The device region includes a deep via bar 136, a diffusion region or structure 138, and a trench contact 140.

[0043] According to one or more embodiments of the present disclosure, a guard ring scheme is described that provides a solution for nanoribbon processes with direct backside contact.

[0044] Figure 3 A cross-sectional view of an integrated circuit structure 150 for a nanoribbon process flow with direct backside contact according to an embodiment of the present disclosure is illustrated, the integrated circuit structure 150 including guard ring option 1, guard ring option 2, and a device region. It is to be understood that a FinFET structure may be used in place of a nanoribbon structure.

[0045] refer to Figure 3 , guard ring option 1 includes back end (BE) / far back end (FBE) layer 152, first back metal layer 154, direct back contact 156, trench contact 158, trench via 160, lowest metallization layer 162, and back end (BE) / far back end (FBE) layer. Guard ring option 2 includes back end (BE) / far back end (FBE) layer 170, first back metal layer 172, direct back contact 174, trench contact 176, trench via 178, lowest metallization layer 180, and back end (BE) / far back end (FBE) layer. The device area includes direct back contact 190, diffusion area or structure 192, and trench contact 194.

[0046] Reference again Figure 3, structure 150 includes a nanoribbon in the device area, where a front contact (TCN) 194 and a direct back contact 190 are located on the nanoribbon 192. Since the gate oxide around the nanoribbon is not sealed, if this configuration is used in a guard ring, it may not work as an effective option. In an embodiment, two guard ring options are provided to achieve an effective metal guard ring. For option 1, the direct contact 156 is etched and filled with a deeper metal than in the device area. Similarly, for option 2, the TCN layer 176 is etched and filled with a deeper metal than the TCN in the device area.

[0047] As a comparison structure, Figure 4A A cross-sectional view of a semiconductor die having only a front-side moisture barrier seal ring and only front-side wiring is illustrated.

[0048] refer to Figure 4A , semiconductor die 400 includes a substrate or back layer 402. An active die area 404 may represent an area where an active device layer 406, such as a transistor layer, is located on the substrate or back layer 402. A dielectric structure 408, which may include multiple layers of dielectric and / or insulating materials, is located on the active device layer 406. A die edge metal protection ring 410 surrounds the periphery of the substrate 408, and as will be appreciated, may form a ring or frame around the active device layer 406 (the use of the term ring may encompass a square or rectangular or other frame). As depicted, the die edge metal protection ring 410 may include multiple layers of alternating metal lines 410B and vias 410A. A sealing passivation layer 412, such as a silicon nitride or polyimide layer, is located over the dielectric structure 408 and the die edge metal protection ring 410.

[0049] As another comparison structure, Figure 4B A cross-sectional view of a semiconductor die with only a front-side moisture barrier seal ring and front-side wiring and back-side direct contacts is illustrated.

[0050] refer to Figure 4B, the semiconductor die 420 includes a bottom dielectric layer 402B, such as a dielectric layer formed after removing the remaining substrate and / or sub-fins and replacing them with dielectric materials. An active device layer 406, such as a transistor layer, is located above the bottom dielectric layer 402B. A dielectric structure 408B, which may include multiple layers of dielectric and / or insulating materials, is located above the active device layer 406. A die edge metal protection ring 410 surrounds the periphery of the active device layer 406, and as will be understood, a ring or frame can be formed around the active device layer 406 (the use of the term ring can cover square or rectangular or other frames). As depicted, the die edge metal protection ring 410 can include multiple layers of alternating metal lines and vias. A sealing passivation layer 412, such as silicon nitride or other sealing layer, is located above the dielectric structure 408B and the die edge metal protection ring 410. A direct back contact 424 is coupled to a back-end of line (BEOL) metallization layer 425 within the perimeter of the die edge metal protection ring 410. Direct back contact 424 may represent Figure 3 A combination of features 174 / 176 or Figure 3 A BEOL metallization layer 425 is coupled to the bump 422 , for example for connection to the top die. A direct backside contact 424 is coupled to a first backside metallization layer 426 .

[0051] As another comparison structure, Figure 4C A cross-sectional view of a semiconductor die having only a front-side moisture barrier seal ring and both front-side and back-side wiring is illustrated.

[0052] refer to Figure 4C , the semiconductor die 430 includes a bottom dielectric layer 402C, such as a dielectric layer formed after removing the remaining substrate and / or sub-fins and replacing them with dielectric materials. An active device layer 406, such as a transistor layer, is located above the bottom dielectric layer 402C. A dielectric structure 408C, which may include multiple layers of dielectric and / or insulating materials, is located above the active device layer 406. A die edge metal protection ring 410 surrounds the periphery of the active device layer 406, and as will be understood, a ring or frame can be formed around the active device layer 406 (the use of the term ring can cover square or rectangular or other frames). As depicted, the die edge metal protection ring 410 can include multiple layers of alternating metal lines and vias. A sealing passivation layer 412, such as silicon nitride or other sealing layer, is located above the dielectric structure 408C and the die edge metal protection ring 410. A direct back contact 424 is coupled to a back end of line (BEOL) metallization layer 425 within the perimeter of the die edge metal protection ring 410. Direct back contact 424 may represent Figure 3 A combination of features 174 / 176 or Figure 3The BEOL metallization layer 425 is coupled to the bump 422, for example, for connection to the top die. The direct back contact 424 is also coupled to a back side metallization structure 434 (also called package side wiring), which can be included in the dielectric layer or layer stack 432. The back side metallization structure 434 is coupled to the package side bump 436, for example, for coupling to the package substrate or board.

[0053] Embodiments may be implemented to provide a sealing ring around the back side of the direct back side contact structure.

[0054] As an exemplary structure, Figure 4D A cross-sectional view of a semiconductor die with direct back side contact and back side wiring and a back side moisture barrier seal ring according to an embodiment of the present disclosure is illustrated.

[0055] refer to Figure 4D , the semiconductor die 440 includes a bottom dielectric layer 402D, such as a dielectric layer formed after removing the remaining substrate and / or sub-fins and replacing them with dielectric materials. An active device layer 406, such as a transistor layer, is located above the bottom dielectric layer 402D. A dielectric structure 408D, which may include multiple layers of dielectric and / or insulating materials, is located above the active device layer 406. A die edge metal protection ring 410 surrounds the periphery of the active device layer 406, and as will be understood, a ring or frame can be formed around the active device layer 406 (the use of the term ring can cover square or rectangular or other frames). As depicted, the die edge metal protection ring 410 can include multiple layers of alternating metal lines and vias. A sealing passivation layer 412, such as silicon nitride or other sealing layer, is located above the dielectric structure 408D and the die edge metal protection ring 410. A direct back contact 424 is coupled to a back end of line (BEOL) metallization layer 425 within the perimeter of the die edge metal protection ring 410. Direct back contact 424 may represent Figure 3 A combination of features 174 / 176 or Figure 3The BEOL metallization layer 425 is coupled to the bump 422, for example, for connection to the top die. The direct back contact 424 is also coupled to a back metallization structure 434 (also referred to as package side wiring), which can be included in the dielectric layer or layer stack 442. The back metallization structure 434 is coupled to the package side bump 448, for example, for coupling to a package substrate or board. The second die edge metal protection ring 444 surrounds the periphery of the back side of the substrate 402D, and as will be understood, a ring or frame can be formed around the back metallization structure 434 (the use of the term ring can include square or rectangular or other frames). As depicted, the second die edge metal protection ring 444 can include multiple layers of alternating metal lines and vias. A second sealing passivation layer 446 such as a silicon nitride or polyimide layer is located below the dielectric structure 442 and the second die edge metal protection ring 444.

[0056] As an exemplary structure, Figure 4E A cross-sectional view of another semiconductor die having direct back side contact and back side wiring and a back side moisture barrier seal ring according to an embodiment of the present disclosure is illustrated.

[0057] refer to Figure 4E , the semiconductor die 450 includes a bottom dielectric layer 402E, such as a dielectric layer formed after removing the remaining substrate and / or sub-fins and replacing them with dielectric materials. An active device layer 406, such as a transistor layer, is located above the bottom dielectric layer 402E. A dielectric structure 408E, which may include multiple layers of dielectric and / or insulating materials, is located above the active device layer 406. A die edge metal protection ring 410 surrounds the periphery of the substrate or back layer 402E, and as will be understood, a ring or frame can be formed around the active device layer 406 (the use of the term ring can cover square or rectangular or other frames). As depicted, the die edge metal protection ring 410 can include multiple layers of alternating metal lines and vias. A sealing passivation layer 412, such as a silicon nitride or polyimide layer, is located above the dielectric structure 408E and the die edge metal protection ring 410. A direct back contact 424 is coupled to a back end of line (BEOL) metallization layer 425 within the perimeter of the die edge metal protection ring 410. Direct back contact 424 may represent Figure 3 A combination of features 174 / 176 or Figure 3The BEOL metallization layer 425 is coupled to the bump 422, for example, for connection to the top die. The direct back contact is also coupled to the back metallization structure 434 (also referred to as the package side wiring), which can be included in the dielectric layer or layer stack 442. The back metallization structure 434 is coupled to the package side bump 448, for example, for coupling to the package substrate or board. The second die edge metal protection ring 444 surrounds the back side of the substrate or the periphery of the back layer 402E, and as will be understood, a ring or frame can be formed around the back metallization structure 434 (the use of the term ring can cover square or rectangular or other frames). As depicted, the second die edge metal protection ring 444 can include multiple layers of alternating metal lines and vias. A second sealing passivation layer 446 such as a silicon nitride or polyimide layer is located below the dielectric structure 442 and the second die edge metal protection ring 444. The direct back contact wall 452 couples the die edge metal guard ring 410 to the second die edge metal guard ring 444. The direct back contact wall can be a single unified conductive structure. As will be appreciated, the direct back contact wall 452 can form a ring or frame (the use of the term ring can encompass square or rectangular or other frames).

[0058] It is to be understood that the structure resulting from the exemplary processing scheme described above can be used in the same or similar form with processing operations for device manufacturing (such as PMOS and / or NMOS device manufacturing). As an example of a complete device that can be included with a backside contact-based die edge protection ring, Figure 5 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is illustrated.

[0059] refer to Figure 5 , the semiconductor structure or device 500 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 504 and a sub-fin region 505) within a trench isolation region 506. In an embodiment, instead of a solid fin, the non-planar active region is divided into nanowires (such as nanowires 504A and 504B) above the sub-fin region 505, as represented by the dashed lines. In either case, for ease of describing the non-planar integrated circuit structure 500, the non-planar active region 504 is referred to below as a protruding fin portion. In an embodiment, as depicted, the sub-fin region 505 also includes a relaxed buffer layer 542 and a defect modification layer 540.

[0060] Gate line 508 is disposed over the protruding portion 504 of the non-planar active area (including around nanowires 504A and 504B, if applicable) and over a portion of trench isolation region 506. As shown, gate line 508 includes a gate electrode 550 and a gate dielectric layer 552. In one embodiment, gate line 508 may also include a dielectric cap layer 554. Also visible from this angle are gate contact 514 and overlying gate contact via 516, as well as overlying metal interconnect 560, all of which are disposed in an interlayer dielectric stack or layer 570. From Figure 5 It can also be seen from the perspective of that in one embodiment, the gate contact 514 is disposed above the trench isolation region 506, but not on the non-planar active region. In another embodiment, the gate contact 514 is above the non-planar active region.

[0061] In an embodiment, the semiconductor structure or device 500 is a non-planar device, such as, but not limited to, a fin FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is formed by or in a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 508 surrounds at least the top surface and a pair of sidewalls of the three-dimensional body.

[0062] Likewise, Figure 5 As depicted in , in an embodiment, an interface 580 exists between the protruding fin portion 504 and the sub-fin region 505. The interface 580 can be a transition region between the doped sub-fin region 505 and the lightly doped or undoped upper fin portion 504. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is optionally provided from an adjacent solid-state doping layer at the sub-fin location. In a particular such embodiment, the width of each fin is less than 10 nanometers.

[0063] Despite Figure 5 508 , but it is understood that the source or drain region of the protruding fin portion 504 or the source or drain region adjacent thereto is located on either side of the gate line 508, i.e., entering and leaving the page. In one embodiment, the material of the protruding fin portion 504 in the source or drain location is removed and replaced with another semiconductor material, for example, by forming an epitaxial source or drain structure through epitaxial deposition. The source or drain region can extend below the height of the dielectric layer of the trench isolation region 506, i.e., into the sub-fin region 505. According to an embodiment of the present disclosure, the more heavily doped sub-fin region, i.e., the doped portion of the fin below the interface 580, suppresses source-to-drain leakage through that portion of the bulk semiconductor fin. In an embodiment, the source and drain regions have associated asymmetric source and drain contact structures.

[0064] Reference again Figure 5In an embodiment, fins 504 / 505 (and possibly nanowires 504A and 504B) are comprised of a crystalline silicon germanium layer, which may be doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof.

[0065] In an embodiment, the trench isolation region 506 and the trench isolation regions (trench isolation structures or trench isolation layers) described throughout the present disclosure may be composed of a material suitable for ultimately electrically isolating or facilitating the isolation of a portion of a permanent gate structure from an underlying bulk substrate, or suitable for isolating an active region formed within an underlying bulk substrate, such as isolating a fin active region. For example, in one embodiment, the trench isolation region 506 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0066] The gate line 508 may be composed of a gate electrode stack including a gate dielectric layer 552 and a gate electrode layer 550. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer 552 is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, tantalum scandium lead oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer 552 may include a native oxide layer formed by the top layers of the substrate fin 504. In an embodiment, the gate dielectric layer 552 is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 552 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a “U” shaped structure including a bottom portion substantially parallel to a substrate surface and two sidewall portions substantially perpendicular to a top surface of the substrate.

[0067] In one embodiment, the gate electrode layer 550 is composed of a metal layer, such as but not limited to metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxide. In a specific embodiment, the gate electrode layer 550 is composed of a non-work function setting filling material formed on a metal work function setting layer. Depending on whether the transistor is a PMOS or NMOS transistor, the gate electrode layer 550 may be composed of a P-type work function metal or an N-type work function metal. In some implementations, the gate electrode layer 550 may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include but are not limited to ruthenium, palladium, platinum, cobalt, nickel, tungsten and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9eV and about 5.2eV. For NMOS transistors, metals that can be used for gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode may be composed of a "U"-shaped structure, the "U"-shaped structure including a bottom portion substantially parallel to the substrate surface and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one metal layer forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate, and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In a further implementation of the present disclosure, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0068] The spacers associated with the gate electrode stack may be composed of a material suitable for ultimately electrically isolating or facilitating isolation of the permanent gate structure from adjacent conductive contacts (such as self-aligned contacts). For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0069] The gate contact 514 and the overlying gate contact via 516 may be made of a conductive material. In an embodiment, one or more contacts or vias are made of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

[0070] In an embodiment (although not shown), a contact pattern is formed that is essentially fully aligned with the existing gate pattern 508, while eliminating the use of a lithography step with a very strict alignment budget. In an embodiment, the contact pattern is a vertically symmetrical contact pattern or an asymmetric contact pattern. In other embodiments, all contacts are connected to the front side and are not asymmetric. In one such embodiment, the self-alignment method enables the use of inherently highly selective wet etching (e.g., relative to conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the method enables the elimination of the need for the originally critical lithography operation used in the conventional method to generate the contact pattern. In an embodiment, the trench contact grid is not patterned separately, but is formed between the polycrystalline (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grating is patterned but before the gate grating is cut.

[0071] In an embodiment, providing structure 500 involves manufacturing gate stack structure 508 by replacing gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material can be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, rather than proceeding from an earlier process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process including the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etching process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etching process including aqueous phosphoric acid.

[0072] Reference again Figure 5 , the arrangement of the semiconductor structure or device 500 places the gate contact above the isolation region. This arrangement can be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of a gate electrode that is formed above the active region, for example, formed above the sub-fin 505, and in the same layer as the trench contact via.

[0073] In an embodiment, a pixel structure cutting method such as described above may be used to form Figure 5 structure.

[0074] It is to be understood that not all aspects of the above-described processes need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. In addition, the processes described herein can be used to manufacture one or more semiconductor devices. The semiconductor device can be a transistor or a similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. In addition, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanobelt device, a tri-gate device, an independently accessed dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for manufacturing semiconductor devices at sub-10 nanometer (10nm) technology nodes.

[0075] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, fluorinated silicon oxides, carbon-doped silicon oxides, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0076] In an embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. Common examples are copper lines and structures used between copper and the surrounding ILD materials that may or may not include a barrier layer. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Therefore, the interconnect may be a single material layer, or may be formed by several layers, including a conductive liner layer and a filling layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form an interconnect. In an embodiment, the interconnect is composed of a conductive material, such as but not limited to copper, aluminum, titanium, zirconium, hafnium, vanadium, ruthenium, cobalt, nickel, palladium, platinum, tungsten, silver, gold, or an alloy thereof. In the art, interconnects are sometimes also referred to as traces, wires, lines, metals, or simply interconnects.

[0077] In an embodiment, as also used throughout this specification, the hard mask material, cover layer or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, cover material or plug materials can be used in different zones to provide different growth or etching selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, cover layer or plug layer includes a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard masks, cover layers or plug layers known in the art may be used. The hard mask layer, cover layer or plug layer may be formed by CVD, PVD or other deposition methods.

[0078] In an embodiment, as also used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), EUV and / or EBDW lithography, etc. Positive resists or negative resists can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography mask portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific such embodiment, the topography mask portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0079] To highlight an exemplary integrated circuit structure having three vertically arranged nanowires, according to an embodiment of the present disclosure, Fig. 6A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure is shown. Figure 6B The diagram shows the intersection of the Fig. 6A A cross-sectional view of a source or drain electrode of a nanowire-based integrated circuit structure. Figure 6C The diagram shows the intersection of the Fig. 6A Cross-sectional view of the channel of a nanowire-based integrated circuit structure.

[0080] refer to Fig. 6A, the integrated circuit structure 600 includes one or more vertically stacked nanowires (604 groups) above a substrate 602. In an embodiment, as depicted, a relaxed buffer layer 602C, a defect modification layer 602B, and a lower substrate portion 602A are included in the substrate 602, as depicted. For illustrative purposes, in order to emphasize the nanowire portion, the optional fins formed below the bottommost nanowire and from the substrate 602 are not depicted. The embodiments herein are directed to both single-wire devices and multi-wire devices. As an example, for illustrative purposes, three nanowire-based devices having nanowires 604A, 604B, and 604C are shown. For ease of description, nanowire 604A is used as an example, where the description focuses on one of the nanowires. It is to be understood that when describing the properties of one nanowire, embodiments based on multiple nanowires may have the same or essentially the same properties for each nanowire.

[0081] Each nanowire 604 includes a channel region 606 in the nanowire. The channel region 606 has a length (L). Figure 6C , the channel region also has a perimeter (Pc) orthogonal to the length (L). Fig. 6A and 6C In both, the gate electrode stack 608 surrounds the entire perimeter (Pc) of each channel region 606. The gate electrode stack 608 includes a gate electrode and a gate dielectric layer (not shown) between the channel region 606 and the gate electrode. In an embodiment, the channel region is discrete because it is completely surrounded by the gate electrode stack 608 without any intermediate materials, such as underlying substrate materials or overlying channel fabrication materials. Accordingly, in an embodiment having multiple nanowires 604, the channel regions 606 of the nanowires are also discrete relative to each other.

[0082] refer to Fig. 6A and 6B In both, the integrated circuit structure 600 includes a pair of non-discrete source or drain regions 610 / 612. The pair of non-discrete source or drain regions 610 / 612 are located on either side of a channel region 606 of a plurality of vertically stacked nanowires 604. In addition, the pair of non-discrete source or drain regions 610 / 612 are adjacent to the channel regions 606 of the plurality of vertically stacked nanowires 604. In one such embodiment (not depicted), the pair of non-discrete source or drain regions 610 / 612 are directly vertically adjacent to the channel regions 606 because epitaxial growth is over and between portions of the nanowires extending beyond the channel regions 606, where the nanowire ends are shown within the source or drain structure. In another embodiment, as Fig. 6A As depicted in , the pair of non-discrete source or drain regions 610 / 612 are indirectly vertically adjacent to the channel region 606 because they are formed at the ends of the nanowires rather than between the nanowires.

[0083] In an embodiment, as depicted, the source or drain regions 610 / 612 are non-discrete in that there is not a separate and discrete source or drain region for each channel region 606 of the nanowire 604. Accordingly, in an embodiment having multiple nanowires 604, the source or drain regions 610 / 612 of the nanowires are global or unified source or drain regions, rather than being discrete for each nanowire. That is, the non-discrete source or drain regions 610 / 612 are global in the sense that a single unified feature is used as the source or drain region for multiple (in this case, 3) nanowires 604, and more particularly, for more than one discrete channel region 606. In one embodiment, from a cross-sectional perspective perpendicular to the length of the discrete channel region 606, each of the pair of non-discrete source or drain regions 610 / 612 is approximately rectangular in shape, having a bottom tapered portion and a top apex portion, as shown in FIG. Figure 6B However, in other embodiments, the source or drain regions 610 / 612 of the nanowires are relatively large, but are discrete, non-vertically merged epitaxial structures, such as small blocks.

[0084] According to the embodiments of the present disclosure, and Fig. 6A and 6B As depicted in , the integrated circuit structure 600 also includes a pair of contacts 614, each contact 614 being located on one of the pair of non-discrete source or drain regions 610 / 612. In one such embodiment, each contact 614 completely surrounds the corresponding non-discrete source or drain region 610 / 612 in a vertical sense. On the other hand, the entire perimeter of the non-discrete source or drain region 610 / 612 may not be in contact with the contact 614, and thus the contact 614 only partially surrounds the non-discrete source or drain region 610 / 612, as shown in FIG. Figure 6B In a comparative embodiment not depicted, the entire perimeter of the non-discrete source or drain region 610 / 612 taken along the aa′ axis is surrounded by the contact 614 .

[0085] Reference again Fig. 6A In an embodiment, the integrated circuit structure 600 further includes a pair of spacers 616. As depicted, outer portions of the pair of spacers 616 may overlap portions of the non-discrete source or drain regions 610 / 612, providing “embedded” portions of the non-discrete source or drain regions 610 / 612 beneath the pair of spacers 616. Also as depicted, the embedded portions of the non-discrete source or drain regions 610 / 612 may not extend beneath the entirety of the pair of spacers 616.

[0086] Substrate 602 may be made of a material suitable for integrated circuit structure fabrication. In one embodiment, substrate 602 includes a lower bulk substrate made of a single crystal material, which may include, but is not limited to, silicon, germanium, silicon germanium, germanium tin, silicon germanium tin, or a III-V compound semiconductor material. An upper insulator layer made of a material including, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride is located on the lower bulk substrate. Thus, structure 600 may be manufactured from a starting semiconductor-on-insulator substrate. Alternatively, structure 600 is formed directly from a bulk substrate, and local oxidation is used to form an electrically insulating portion to replace the upper insulator layer described above. In another alternative embodiment, structure 600 is formed directly from a bulk substrate, and doping is used to form an electrically isolated active region thereon, such as a nanowire. In one such embodiment, the first nanowire (i.e., close to the substrate) is in the form of an ω-FET type structure.

[0087] In an embodiment, the nanowire 604 may be sized as a wire or a ribbon, as described below, and may have square or rounded corners. In an embodiment, the nanowire 604 is made of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowire is single crystalline. For example, for silicon nanowire 604, the single crystalline nanowire may be based on a (100) global orientation, such as having a 100-square root in the z direction. <100> Plane. Other orientations are also contemplated as described below. In an embodiment, the dimensions of nanowire 604 are nanometer-scale from a cross-sectional perspective. For example, in a specific embodiment, the smallest dimension of nanowire 604 is less than about 20 nanometers. In an embodiment, nanowire 604 is composed of strained material, particularly in channel region 606.

[0088] refer to Figure 6C , in an embodiment, each channel region 606 has a width (Wc) and a height (Hc), the width (Wc) being approximately the same as the height (Hc). That is, in both cases, the channel region 606 is square in cross-sectional profile, or circular if rounded. In another aspect, the width and height of the channel region need not be the same, such as in the case of the nanoribbons described throughout.

[0089] In one embodiment, as described throughout, an integrated circuit structure includes a non-planar device such as, but not limited to, a finFET or tri-gate device having corresponding one or more overlying nanowire structures. In such an embodiment, the corresponding semiconductor channel region is comprised of or formed in a three-dimensional body with one or more discrete nanowire channel portions overlying the three-dimensional body. In one such embodiment, the gate structure surrounds at least a top surface and a pair of sidewalls of the three-dimensional body and further surrounds each of the one or more discrete nanowire channel portions.

[0090] In an embodiment, a pixel structure cutting method such as described above may be used to form Figures 6A-6C structure.

[0091] In an embodiment, as described throughout, the lower substrate may be composed of a semiconductor material that can withstand the manufacturing process and in which charge can migrate. In an embodiment, the substrate is a bulk substrate composed of a crystalline silicon, silicon / germanium or germanium layer doped with charge carriers (such as but not limited to phosphorus, arsenic, boron, gallium or a combination thereof) to form an active region. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on top of a different crystalline substrate (e.g., a silicon epitaxial layer grown on a boron-doped bulk silicon single crystal substrate). The bulk substrate may alternatively be composed of a III-V group material. In an embodiment, the bulk substrate is composed of a III-V group material, such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide or a combination thereof. In one embodiment, the bulk substrate is composed of a III-V group material, and the charge carrier dopant impurity atoms are atoms such as but not limited to carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

[0092] On the other hand, the back-end of the line (BEOL) layers of an integrated circuit generally include conductive microelectronic structures, which are referred to in the art as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. According to one or more embodiments of the present disclosure, the BEOL structures of the integrated circuit include a die edge protection ring based on a back side contact as described above.

[0093] As an exemplary but non-limiting BEOL structure, Figure 7 The cross-sectional view of an integrated circuit structure according to an embodiment of the present disclosure is illustrated, the integrated circuit structure having four metallization layers with metal line composition and pitch, located above two metallization layers with different metal line composition and smaller pitch. It is to be understood that the die edge protection ring based on the back contact as described above can be combined with the following Figure 7 One or more layers of the described integrated circuit structure are integrated.

[0094] refer to Figure 7 , the integrated circuit structure 700 includes a first plurality of conductive interconnects 704 in and separated by a first inter-layer dielectric (ILD) layer 702 over a substrate 701. Individual conductive interconnects of the first plurality of conductive interconnects 704 include a first conductive barrier material 706 along sidewalls and a bottom of a first conductive fill material 708. Individual conductive interconnects of the first plurality of conductive interconnects 704 are arranged along a first direction 798 (e.g., into and out of the page).

[0095] The second plurality of conductive interconnects 714 are located in and separated by the second ILD layer 712 above the first ILD layer 702. Each of the second plurality of conductive interconnects 714 includes the first conductive barrier material 706 along the sidewalls and bottom of the first conductive fill material 708. Each of the second plurality of conductive interconnects 714 is along a second direction 799 orthogonal to the first direction 798.

[0096] The third plurality of conductive interconnects 724 are located in and separated by the third ILD layer 722 above the second ILD layer 712. Each of the third plurality of conductive interconnects 724 includes a second conductive barrier material 726 along the sidewalls and bottom of a second conductive fill material 728. The second conductive fill material 728 is different in composition from the first conductive fill material 708. Each of the third plurality of conductive interconnects 724 is along a first direction 798.

[0097] The fourth plurality of conductive interconnects 734 are located in and separated by the fourth ILD layer 732 above the third ILD layer 722. Each of the fourth plurality of conductive interconnects 734 includes the second conductive barrier material 726 along the sidewalls and bottom of the second conductive fill material 728. Each of the fourth plurality of conductive interconnects 734 is along the second direction 799.

[0098] The fifth plurality of conductive interconnects 744 are located in and separated by the fifth ILD layer 742 above the fourth ILD layer 732. Each of the fifth plurality of conductive interconnects 744 includes the second conductive barrier material 726 along the sidewalls and bottom of the second conductive fill material 728. Each of the fifth plurality of conductive interconnects 744 is along the first direction 798.

[0099] The sixth plurality of conductive interconnects 754 are located in and separated by the sixth ILD layer 752 above the fifth ILD layer 742. Each of the sixth plurality of conductive interconnects 754 includes the second conductive barrier material 726 along the sidewalls and bottom of the second conductive fill material 728. Each of the sixth plurality of conductive interconnects 754 is along the second direction 799.

[0100] In an embodiment, the second conductive fill material 728 consists essentially of copper, and the first conductive fill material 708 consists essentially of cobalt. In an embodiment, the first conductive fill material 708 includes copper having a first dopant impurity atomic concentration, and the second conductive fill material 728 includes copper having a second dopant impurity atomic concentration, the second dopant impurity atomic concentration being less than the first dopant impurity atomic concentration.

[0101] In an embodiment, the first conductive barrier material 706 is different in composition from the second conductive barrier material 726. In another embodiment, the first conductive barrier material 706 and the second conductive barrier material 726 have the same composition.

[0102] In an embodiment, the first conductive via 719 is located on and electrically coupled to a single conductive interconnect line 704A in the first plurality of conductive interconnect lines 704. The single conductive interconnect line 714A in the second plurality of conductive interconnect lines 714 is located on and electrically coupled to the first conductive via 719.

[0103] The second conductive via 729 is located on and electrically coupled to a single conductive interconnect line 714B of the second plurality of conductive interconnect lines 714. The single conductive interconnect line 724A of the third plurality of conductive interconnect lines 724 is located on and electrically coupled to the second conductive via 729.

[0104] The third conductive via 739 is located on and electrically coupled to a single conductive interconnect 724B in the third plurality of conductive interconnects 724. A single conductive interconnect 734A in the fourth plurality of conductive interconnects 734 is located on and electrically coupled to the third conductive via 739.

[0105] The fourth conductive via 749 is located on and electrically coupled to a single conductive interconnect line 734B in the fourth plurality of conductive interconnect lines 734. The single conductive interconnect line 744A in the fifth plurality of conductive interconnect lines 744 is located on and electrically coupled to the fourth conductive via 749.

[0106] The fifth conductive via 759 is located on and electrically coupled to a single conductive interconnect line 744B in the fifth plurality of conductive interconnect lines 744. The single conductive interconnect line 754A in the sixth plurality of conductive interconnect lines 754 is located on and electrically coupled to the fifth conductive via 759.

[0107] In one embodiment, the first conductive via 719 includes the first conductive barrier material 706 along the sidewalls and bottom of the first conductive filling material 708. The second conductive via 729, the third conductive via 739, the fourth conductive via 749, and the fifth conductive via 759 include the second conductive barrier material 726 along the sidewalls and bottom of the second conductive filling material 728.

[0108] In an embodiment, the first ILD layer 702, the second ILD layer 712, the third ILD layer 722, the fourth ILD layer 732, the fifth ILD layer 742, and the sixth ILD layer 752 are separated from each other by corresponding etch stop layers 790 between adjacent ILD layers. In an embodiment, the first ILD layer 702, the second ILD layer 712, the third ILD layer 722, the fourth ILD layer 732, the fifth ILD layer 742, and the sixth ILD layer 752 include silicon, carbon, and oxygen.

[0109] In an embodiment, each of the first plurality of conductive interconnects 704 and the second plurality of conductive interconnects 714 has a first width (W1). Each of the third plurality of conductive interconnects 724, the fourth plurality of conductive interconnects 734, the fifth plurality of conductive interconnects 744, and the sixth plurality of conductive interconnects 754 has a second width (W2) greater than the first width (W1).

[0110] It is to be understood that the above-mentioned layers and materials associated with back-end-of-line (BEOL) structures and processes may be formed on or above an underlying semiconductor substrate or structure, such as one or more underlying device layers of an integrated circuit. In an embodiment, the underlying semiconductor substrate represents a general workpiece object for manufacturing integrated circuits. The semiconductor substrate typically includes a wafer or other silicon wafer or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon, and silicon on insulator (SOI), as well as similar substrates formed from other semiconductor materials, such as substrates including germanium, carbon, or III-V materials. Depending on the stage of manufacturing, semiconductor substrates typically include transistors, integrated circuits, etc. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. In addition, the depicted structure can be manufactured on an underlying lower level interconnect layer.

[0111] Although the foregoing methods of fabricating a metallization layer or a portion of a metallization layer of a BEOL metallization layer are described in detail with respect to selected operations, it is understood that additional or intermediate operations for fabrication may include standard microelectronics fabrication processes such as lithography, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, or any other actions associated with microelectronic component fabrication. Furthermore, it is understood that the process operations described with respect to the foregoing process flows may be practiced in an alternative order, not every operation needs to be performed, or additional process operations may be performed, or both may be performed.

[0112] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, fluorinated silicon oxides, carbon-doped silicon oxides, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0113] In an embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. Common examples are copper lines and structures used between copper and the surrounding ILD materials that may or may not include a barrier layer. As used herein, the term "metal" includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack or alloy of different metals, and the like. Therefore, the interconnect may be a single material layer, or may be formed by several layers, including a conductive liner layer and a filling layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form an interconnect. In an embodiment, the interconnect is composed of a conductive material, such as, but not limited to, copper, aluminum, titanium, zirconium, hafnium, vanadium, ruthenium, cobalt, nickel, palladium, platinum, tungsten, silver, gold, or its alloy. In the art, interconnects are sometimes also referred to as traces, wires, lines, metals, or simply interconnects.

[0114] In an embodiment, as also used throughout this specification, the hard mask material is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask materials may be used in different zones to provide different growth or etching selectivities to each other and to underlying dielectric and metal layers. In some embodiments, the hard mask layer comprises a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material comprises a metal species. For example, the hard mask or other overlying material may include a layer of titanium or another metal nitride (e.g., titanium nitride). Potentially smaller amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other hard mask layers known in the art may be used, depending on the particular implementation. The hard mask layer may be formed by CVD, PVD, or by other deposition methods.

[0115] In an embodiment, as also used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, or electron beam direct write (EBDW) lithography, etc. Positive resists or negative resists can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography mask portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific such embodiment, the topography mask portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0116] The embodiments disclosed herein can be used to manufacture a variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a variety of electronic devices known in the art. For example, they are used in computer systems (e.g., desktop computers, laptop computers, servers), cellular phones, personal electronic devices, etc. The integrated circuit can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. via one or more buses. Each of the processor, memory, and chipset can be manufactured using the methods disclosed herein.

[0117] Figure 8 A computing device 800 according to one implementation of the present disclosure is illustrated. The computing device 800 houses a board 802. The board 802 may include a plurality of components, including, but not limited to, a processor 804 and at least one communication chip 806. The processor 804 is physically and electrically coupled to the board 802. In some implementations, at least one communication chip 806 is also physically and electrically coupled to the board 802. In further implementations, the communication chip 806 is part of the processor 804.

[0118] Depending on its application, the computing device 800 may include other components that may or may not be physically and electrically coupled to the board 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.).

[0119] The communication chip 806 enables wireless communication to transmit data to and from the computing device 800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which can transmit data through non-solid media by using modulated electromagnetic radiation. The term does not mean that the associated device does not contain any wires, although in some embodiments they may not contain any wires. The communication chip 806 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and later. The computing device 800 may include multiple communication chips 806. For example, the first communication chip 806 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 806 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0120] The processor 804 of the computing device 800 includes an integrated circuit die packaged within the processor 804. In some implementations of the embodiments of the present disclosure, the processor includes a back contact based die edge protection ring constructed according to implementations of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from a register or memory to transform the electronic data or both into other electronic data that can be stored in a register or memory or both.

[0121] The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. According to another implementation of the present disclosure, the communication chip includes a backside contact based die edge protection ring constructed according to implementations of the present disclosure.

[0122] In a further implementation, another component housed within computing device 800 may include a backside contact based die edge protection ring constructed in accordance with implementations of embodiments of the present disclosure.

[0123] In various embodiments, computing device 800 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 800 may be any other electronic device that processes data.

[0124] Fig. 9 An interposer 900 including one or more embodiments of the present disclosure is illustrated. Interposer 900 is an intervening substrate used to bridge a first substrate 902 to a second substrate 904. The first substrate 902 can be, for example, an integrated circuit die. The second substrate 904 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. In general, the purpose of interposer 900 is to extend the connection to a wider spacing, or to reroute the connection to a different connection. For example, interposer 900 can couple an integrated circuit die to a ball grid array (BGA) 906, which can then be coupled to a second substrate 904. In some embodiments, the first and second substrates 902 / 904 are attached to opposite sides of interposer 900. In other embodiments, the first and second substrates 902 / 904 are attached to the same side of interposer 900. And, in further embodiments, three or more substrates are interconnected through interposer 900.

[0125] Interposer 900 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In further implementations, interposer 900 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use with semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0126] The interposer 900 may include metal interconnects 908 and vias 910, including but not limited to through silicon vias (TSVs) 912. The interposer 900 may also include embedded devices 914, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 900. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used to manufacture the interposer 900 or to manufacture components included in the interposer 900.

[0127] Fig.101 is an isometric view of a mobile computing platform 1000 according to an embodiment of the present disclosure, which uses an integrated circuit (IC) manufactured according to one or more processes described herein, or includes one or more features described herein.

[0128] The mobile computing platform 1000 may be any portable device configured for each of electronic data display, electronic data processing, and wireless electronic data transmission. For example, the mobile computing platform 1000 may be any of a tablet computer, a smart phone, a laptop computer, etc., and includes a display screen 1005 (in an exemplary embodiment, the display screen 1005 is a touch screen (capacitive, inductive, resistive, etc.)), a chip-level (SoC) or package-level integrated system 1010, and a battery 1013. As illustrated, the higher the level of integration in the system 1010 enabled by a higher transistor packing density, the larger the portion of the mobile computing platform 1000 that can be occupied by a battery 1013 or a non-volatile memory (such as a solid-state drive), or the larger the number of transistor gates used to improve the functionality of the platform. Similarly, the greater the carrier mobility of each transistor in the system 1010, the stronger the functionality. In this way, the techniques described herein may enable performance and form factor improvements in the mobile computing platform 1000.

[0129] The integrated system 1010 is further illustrated in an expanded view 1020. In an exemplary embodiment, the packaged device 1077 includes at least one memory chip (e.g., RAM), or at least one processor chip (e.g., a multi-core microprocessor and / or a graphics processor) that is manufactured according to one or more processes described herein or includes one or more features described herein. The packaged device 1077 is also coupled to the board 1060 along with one or more power management integrated circuits (PMICs) 1015, an RF (wireless) integrated circuit (RFIC) 1025 including a broadband RF (wireless) transmitter and / or receiver (e.g., including digital baseband and analog front-end modules, and also including a power amplifier on the transmit path and a low noise amplifier on the receive path), and its controller 1011. Functionally, the PMIC 1015 performs battery power regulation, DC to DC conversion, etc., and therefore has an input coupled to the battery 1013, and has an output that provides current supply to all other functional modules. As further illustrated, in an exemplary embodiment, RFIC 1025 has an output coupled to an antenna to provide implementation of any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocol designated as 3G, 4G, 5G and later. In alternative implementations, each of these board-level modules can be integrated into a separate IC coupled to the packaging substrate of the packaged device 1077, or integrated within a single IC (SoC) coupled to the packaging substrate of the packaged device 1077.

[0130] On the other hand, semiconductor packaging is used to protect an integrated circuit (IC) chip or die and also provide an electrical interface for the die to external circuits. As the demand for smaller electronic devices increases, semiconductor packages are designed to be even more compact and must support greater circuit density. In addition, the demand for higher performance devices has led to the need for an improved semiconductor package that enables a thin package profile and low overall warpage that is compatible with subsequent assembly processes.

[0131] In an embodiment, wire bonding to a ceramic or organic packaging substrate is used. In another embodiment, the die is mounted to a ceramic or organic packaging substrate using a C4 process. In particular, a C4 solder ball connection can be implemented to provide a flip chip interconnect between the semiconductor device and the substrate. Flip chip or controlled collapse chip connection (C4) is a type of mounting for semiconductor devices (such as integrated circuit (IC) chips, MEMS or components) that utilizes solder bumps instead of wire bonding. Solder bumps are deposited on C4 pads located on the top side of the substrate package. In order to mount the semiconductor device to the substrate, it is turned over so that the active side is facing down on the mounting area. Solder bumps are used to connect the semiconductor device directly to the substrate.

[0132] Fig.11 Illustrated is a cross-sectional view of a flip-chip mounted die according to an embodiment of the present disclosure.

[0133] refer to Fig.11 According to an embodiment of the present disclosure, device 1100 includes a die 1102, such as an integrated circuit (IC) manufactured according to one or more processes described herein, or including one or more features described herein. Die 1102 includes metallized pads 1104 thereon. A package substrate 1106 (such as a ceramic or organic substrate) includes connections 1108 thereon. Die 1102 and package substrate 1106 are electrically connected via solder balls 1110 coupled to metallized pads 1104 and connections 1108. An underfill material 1112 surrounds solder balls 1110.

[0134] Processing a flip chip can be similar to regular IC manufacturing, with some additional operations. Near the end of the manufacturing process, the attachment pads are metallized to make them more receptive to solder. This typically includes several treatments. Small dots of solder are then deposited on each metallized pad. The chip is then cut from the wafer as usual. To connect the flip chip into a circuit, the chip is inverted to bring the solder joints down to the underlying electronics or connectors on the circuit board. The solder is then re-melted to create an electrical connection, typically using ultrasound or, alternatively, a reflow soldering process. This also leaves a small space between the chip circuitry and the underlying mounting. In most cases, it is then "underfilled" with an electrically insulating adhesive to provide a stronger mechanical connection, provide a thermal bridge, and ensure that the solder joints are not stressed due to differential heating of the chip and the rest of the system.

[0135] In other embodiments, newer packaging and die-to-die interconnect methods (such as through silicon vias (TSVs) and silicon interposers) are implemented to manufacture high-performance multi-chip modules (MCMs) and system-in-package (SiPs) that incorporate integrated circuits (ICs) manufactured according to one or more processes described herein according to embodiments of the present disclosure or include one or more features described herein.

[0136] Thus, embodiments of the present disclosure include a backside contact based die edge protection ring.

[0137] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even in the case where only a single embodiment is described with respect to a particular feature. Unless otherwise stated, the examples of features provided in the present disclosure are intended to be illustrative rather than limiting. The above description is intended to encompass substitutions, modifications, and equivalents that will be apparent to those skilled in the art having the benefit of this disclosure.

[0138] The scope of the present disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be made during the prosecution of the present application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with features of the independent claims, and features from individual independent claims may be combined in any appropriate manner, and not merely in the specific combinations listed in the appended claims.

[0139] The following examples relate to further embodiments. The various features of the different embodiments may be combined in various ways with some features included and others excluded to suit a variety of different applications.

[0140] Example embodiment 1: A semiconductor die includes an active device layer, the active device layer including a plurality of nanoribbon devices. A dielectric structure is located above the active device layer. A first die edge metal guard ring is located in the dielectric structure and surrounds the periphery of the plurality of nanoribbon devices. A plurality of metallization layers are located in the dielectric structure and within the first die edge metal guard ring. A plurality of direct back contacts extend to the active device layer. A plurality of back metallization structures are located below the plurality of direct back contacts. A plurality of direct back contacts are connected to the plurality of back metallization structures. A second die edge metal guard ring laterally surrounds the plurality of back metallization structures.

[0141] Example Embodiment 2: The semiconductor die of Example Embodiment 1, wherein the first die edge metal guard ring is a first square or rectangular frame, and the second die edge metal guard ring is a second square or rectangular frame.

[0142] Example Embodiment 3: The semiconductor die of Example Embodiment 1 or 2, wherein the first die edge metal guard ring and the second die edge metal guard ring each include multiple layers of alternating metal lines and vias.

[0143] Example Embodiment 4: The semiconductor die of Example Embodiment 1, 2, or 3, wherein the first die edge metal guard ring comprises a trench contact.

[0144] Example Embodiment 5: The semiconductor die of Example Embodiment 1, 2, 3, or 4, further comprising a second plurality of direct backside contacts coupling the first die edge metal guard ring to the second die edge metal guard ring.

[0145] Example embodiment 6: A semiconductor die includes an active device layer, the active device layer including multiple fins or multiple fin-based devices. A dielectric structure is located above the active device layer. A first die edge metal protection ring is located in the dielectric structure and surrounds the periphery of the fins or the multiple fin-based devices. Multiple metallization layers are located in the dielectric structure and within the first die edge metal protection ring. Multiple direct back contacts extend to the active device layer. Multiple back metallization structures are located below the multiple direct back contacts. Multiple direct back contacts are connected to the multiple back metallization structures. A second die edge metal protection ring laterally surrounds the multiple back metallization structures.

[0146] Example Embodiment 7: The semiconductor die of Example Embodiment 6, wherein the first die edge metal guard ring is a first square or rectangular frame, and the second die edge metal guard ring is a second square or rectangular frame.

[0147] Example Embodiment 8: The semiconductor die of Example Embodiment 6 or 7, wherein the first die edge metal guard ring and the second die edge metal guard ring each include multiple layers of alternating metal lines and vias.

[0148] Example Embodiment 9: The semiconductor die of Example Embodiment 6, 7, or 8, wherein the first die edge metal guard ring comprises a trench contact.

[0149] Example Embodiment 10: The semiconductor die of Example Embodiment 6, 7, 8, or 9, further comprising a second plurality of direct backside contacts coupling the first die edge metal guard ring to the second die edge metal guard ring.

[0150] Example embodiment 11: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure, the integrated circuit structure including an active device layer, the active device layer including multiple nanoribbon devices or fin-based devices. A dielectric structure is located above the active device layer. A first tube core edge metal protection ring is located in the dielectric structure and surrounds the periphery of the multiple nanoribbon devices or fin-based devices. Multiple metallization layers are located in the dielectric structure and within the first tube core edge metal protection ring. Multiple direct back contacts extend to the active device layer. Multiple back metallization structures are located below the multiple direct back contacts. The multiple direct back contacts are connected to the multiple back metallization structures. A second tube core edge metal protection ring laterally surrounds the multiple back metallization structures.

[0151] Example embodiment 12: The computing device of example embodiment 11, comprising a plurality of nanoribbon devices.

[0152] Example Embodiment 13: The computing device of Example Embodiment 11 or 12, comprising a plurality of fin-based devices.

[0153] Example Embodiment 14: The computing device of Example Embodiment 11, 12, or 13, further comprising a memory coupled to the board.

[0154] Example Embodiment 15: The computing device of Example Embodiment 11, 12, 13 or 14, further comprising a communication chip coupled to the board.

[0155] Example Embodiment 16: The computing device of Example Embodiment 11, 12, 13, 14, or 15, further comprising a battery coupled to the board.

[0156] Example Embodiment 17: The computing device of Example Embodiment 11, 12, 13, 14, 15, or 16, further comprising a camera coupled to the board.

[0157] Example Embodiment 18: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, or 17, further comprising a display coupled to the board.

[0158] Example Embodiment 19: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0159] Exemplary Embodiment 20: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

Claims

1. A semiconductor die, comprising: an active device layer having a plurality of nanoribbon devices; a dielectric structure located above the active device layer; a first die edge metal guard ring disposed in the dielectric structure and surrounding a periphery of the plurality of nanoribbon devices; a plurality of metallization layers located in the dielectric structure and within the first die edge metal guard ring; a plurality of direct backside contacts extending to the active device layer; a plurality of back side metallization structures underlying the plurality of direct back side contacts, wherein the plurality of direct back side contacts are connected to the plurality of back side metallization structures; as well as A second die edge metal guard ring laterally surrounds the plurality of back side metallization structures. 2 . The semiconductor die of claim 1 , wherein the first die edge metal guard ring is a first square or rectangular frame, and the second die edge metal guard ring is a second square or rectangular frame. 3 . The semiconductor die of claim 1 , wherein the first die edge metal guard ring and the second die edge metal guard ring each comprise multiple layers of alternating metal lines and vias. 4 . The semiconductor die of claim 1 , wherein the first die edge metal guard ring comprises a trench contact.

5. The semiconductor die according to claim 1 or 2, further comprising: A second plurality of direct backside contacts couples the first die edge metal guard ring to the second die edge metal guard ring.

6. A semiconductor die, comprising: an active device layer including a plurality of fin-based devices; a dielectric structure located above the active device layer; a first die edge metal guard ring located in the dielectric structure and surrounding a periphery of the plurality of fin-based devices; a plurality of metallization layers located in the dielectric structure and within the first die edge metal guard ring; a plurality of direct backside contacts extending to the active device layer; a plurality of back side metallization structures underlying the plurality of direct back side contacts, wherein the plurality of direct back side contacts are connected to the plurality of back side metallization structures; as well as A second die edge metal guard ring laterally surrounds the plurality of back side metallization structures. 7 . The semiconductor die of claim 6 , wherein the first die edge metal guard ring is a first square or rectangular frame and the second die edge metal guard ring is a second square or rectangular frame.

8. The semiconductor die of claim 6 or 7, wherein the first die edge metal guard ring and the second die edge metal guard ring each comprise multiple layers of alternating metal lines and vias.

9. The semiconductor die of claim 6 or 7, wherein the first die edge metal guard ring comprises a trench contact.

10. The semiconductor die of claim 6 or 7, further comprising: A second plurality of direct backside contacts couples the first die edge metal guard ring to the second die edge metal guard ring.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: an active device layer including a plurality of nanoribbon devices or fin-based devices; a dielectric structure located above the active device layer; a first die edge metal guard ring located in the dielectric structure and surrounding a periphery of the plurality of nanoribbon devices or fin-based devices; a plurality of metallization layers located in the dielectric structure and within the first die edge metal guard ring; a plurality of direct backside contacts extending to the active device layer; a plurality of back side metallization structures underlying the plurality of direct back side contacts, wherein the plurality of direct back side contacts are connected to the plurality of back side metallization structures; and A second die edge metal guard ring laterally surrounds the plurality of back side metallization structures.

12. The computing device of claim 11, comprising a plurality of nanoribbon devices.

13. The computing device of claim 11 or 12, comprising a plurality of fin-based devices.

14. The computing device according to claim 11 or 12, further comprising: A memory is coupled to the board.

15. The computing device according to claim 11 or 12, further comprising: A communication chip is coupled to the board.

16. The computing device according to claim 11 or 12, further comprising: A battery coupled to the board.

17. The computing device according to claim 11 or 12, further comprising: A camera is coupled to the board.

18. The computing device according to claim 11 or 12, further comprising: A display is coupled to the panel.

19. The computing device of claim 11 or 12, wherein the component is a packaged integrated circuit die.

20. The computing device of claim 11 or 12, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

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