Radiation-proof power field effect transistor and manufacturing method thereof

Abstract

The invention discloses an anti-radiation power field effect transistor and a manufacturing method thereof.The field effect transistor comprises a gate structure layer, an epitaxial layer and a substrate layer which are arranged in a stacked mode in the first direction, and a plurality of first conductive structure regions, a plurality of JFET regions and a plurality of second conductive structure regions are arranged on the side, close to the gate structure layer, in the epitaxial layer; in the first direction and the second direction, the thickness and the width of the second conductive structure regions are smaller than those of the first conductive structure regions, each JFET region is arranged between the adjacent first conductive structure regions, and each second conductive structure region is correspondingly arranged in each JFET region; wherein the epitaxial layer and the JFET region have a first conductive type, and the first conductive structure region and the second conductive structure region both have a first conductive type region and a second conductive type region. According to the anti-radiation power field effect transistor and the manufacturing method thereof, the manufacturing process of the field effect transistor is relatively simple, the field effect transistor has relatively strong anti-radiation capability, and the performance of the field effect transistor can be ensured.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a radiation-resistant power field effect transistor and a manufacturing method thereof. Background Art

[0002] Power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is widely used in the field of electronic power. With the development of the aerospace field, power MOSFET is also used in space environments with a large number of charged particles and cosmic rays. In such a space environment, ordinary power MOSFET will fail due to single event gate rupture (SEGR), causing irreversible physical damage to the gate oxide layer of the power MOSFET and unable to work normally.

[0003] At present, in order to prevent the single particle gate punch-through phenomenon in power MOSFET, the thickness of the gate oxide layer is usually increased through the locos process, or a P-type injection structure is introduced in the JFET area. However, the locos process is relatively complex and has a weak single particle resistance capability, and it will affect the total dose performance of the power MOSFET and may also cause leakage risks. The use of P-type injection in the JFET area will cause the JFET area to become narrower and the on-resistance to be larger, affecting the performance of the power MOSFET. Summary of the invention

[0004] The present application provides a radiation-resistant power field effect transistor and a manufacturing method thereof. The manufacturing process of the field effect transistor is relatively simple, has strong radiation resistance, and can ensure the performance of the field effect transistor.

[0005] The present application provides a radiation-resistant power field effect transistor, which includes a gate structure layer, an epitaxial layer and a substrate layer stacked along a first direction. On a side close to the gate structure layer, a plurality of first conductive structure regions, a plurality of JFET regions and a plurality of second conductive structure regions are arranged in the epitaxial layer. Along the first direction and the second direction, the thickness and width of the second conductive structure region are both smaller than the first conductive structure region. Each JFET region is arranged between adjacent first conductive structure regions, and each second conductive structure region is correspondingly arranged in each JFET region; wherein the epitaxial layer and the JFET region have a first conductive type, and the ion concentration of the JFET region is higher than the ion concentration of the epitaxial layer, and the first conductive structure region and the second conductive structure region both have a first conductive type region and a second conductive type region.

[0006] As the radiation-resistant power field effect transistor above, wherein along the first direction, the thickness of the second conductive structure region is 50% or less of the thickness of the first conductive structure region; along the second direction, the width of the second conductive structure region is 50% or less of the width of the first conductive structure region.

[0007] As above, the radiation-resistant power field effect transistor, wherein the first conductive structure region includes a first well region, a first heavily doped region and a second heavily doped region, the first well region extends from the first surface of the epitaxial layer in the first direction to the inside, the first heavily doped region and the second heavily doped region are both arranged in the first well region and both extend inward along the first surface of the epitaxial layer, and the second heavily doped region is arranged on both sides of the first heavily doped region in the second direction; wherein the first well region and the first heavily doped region have the second conductivity type, and the second heavily doped region has the first conductivity type.

[0008] As above, the radiation-resistant power field effect transistor, wherein the second conductive structure region includes a second well region, a third heavily doped region and a fourth heavily doped region, the second well region extends from the first surface of the epitaxial layer in the first direction to the inside, the third heavily doped region and the fourth heavily doped region are both arranged in the second well region and both extend inward along the first surface of the epitaxial layer, and the fourth heavily doped region is arranged on both sides of the third heavily doped region in the second direction; wherein the second well region and the third heavily doped region have the second conductivity type, and the fourth heavily doped region has the first conductivity type.

[0009] In the above radiation-resistant power field effect transistor, along the second direction, the width of the third heavily doped region is smaller than the width of the first heavily doped region, and the width of the fourth heavily doped region is smaller than the width of the second heavily doped region.

[0010] The radiation-resistant power field effect transistor as above, further includes a first electrode layer and an isolation layer, the isolation layer is arranged between the first electrode layer and the gate structure layer, and is used to isolate the first electrode layer from the conductive connection with the gate structure layer, the isolation layer has a plurality of connecting parts arranged at intervals along the second direction, each connecting part is arranged relative to the first conductive structure area or the second conductive structure area, and the first electrode layer is conductively connected to the first conductive structure area or the second conductive structure area through the connecting part.

[0011] As above, the radiation-resistant power field effect transistor, wherein the first electrode layer includes a first electrode body portion and a plurality of first electrode connecting portions, the first electrode body portion is a plate-like structure perpendicular to the first direction, the first electrode connecting portion extends along the first direction and protrudes from the first electrode body portion in the direction toward the epitaxial layer, and the plurality of first electrode connecting portions are arranged one by one in the plurality of connecting portions; a portion of the first electrode connecting portions forms ohmic contacts with both the first heavily doped region and the second heavily doped region, and another portion of the first electrode connecting portions forms ohmic contacts with both the third heavily doped region and the fourth heavily doped region.

[0012] As above, the radiation-resistant power field effect transistor, wherein the isolation layer also includes multiple accommodating portions for accommodating the gate structure layer, each accommodating portion is arranged between two adjacent connecting portions, and each connecting portion is conductively connected to the JFET region and the first conductive structure region and the second conductive structure region adjacent to the JFET region.

[0013] On the other hand, the present application also provides a method for manufacturing a radiation-resistant power field effect transistor, which comprises:

[0014] Performing epitaxial growth on one side of the substrate layer in a first direction to form an epitaxial layer having a first conductivity type;

[0015] Implanting first conductive type ions on a first surface of the epitaxial layer and performing annealing to form a JFET region;

[0016] Implanting second conductive type ions into both sides and the interior of the JFET region from the first surface of the epitaxial layer, and annealing to form a first well region and a second well region;

[0017] Implanting heavily doped second conductive type ions into the first well region and the second well region on the first surface of the epitaxial layer, and activating them to form a first heavily doped region and a third heavily doped region respectively;

[0018] Implanting heavily doped first conductivity type ions into both sides of the first heavily doped region and both sides of the third heavily doped region on the first surface of the epitaxial layer, and activating them to form a second heavily doped region and a fourth heavily doped region;

[0019] Disposing a gate structure layer conductively connected to the JFET region on the first surface of the epitaxial layer;

[0020] An isolation layer, a first electrode layer and a passivation layer are sequentially arranged on one side of the first surface of the epitaxial layer, and a second electrode layer is arranged on the second surface of the substrate layer.

[0021] The manufacturing method of the radiation-resistant power field effect transistor as mentioned above, wherein the step of setting an isolation layer and a first electrode layer on one side of the first surface of the epitaxial layer specifically includes: depositing an isolation dielectric on the first surface of the epitaxial layer and the surface of the gate structure layer to form an isolation layer, and forming an accommodation portion for accommodating the gate structure layer on the side of the isolation layer close to the epitaxial layer; performing hole etching on the isolation layer along a first direction to form a plurality of connecting portions; depositing metal on the surface of the isolation layer and in the connecting portions to form a first electrode layer, the first electrode layer including a first electrode body portion arranged on the surface of the isolation layer and a first electrode connecting portion arranged in the connecting portion.

[0022] The field effect transistor of the present application includes a gate structure layer, an epitaxial layer and a substrate layer stacked along a first direction. On a side close to the gate structure layer, a plurality of first conductive structure regions, a plurality of JFET regions and a plurality of second conductive structure regions are arranged in the epitaxial layer. The second conductive structure region is arranged in the JFET region between two adjacent first conductive structure regions, and the second conductive structure region has a first conductive type region and a second conductive type region, so that it can work together with the JFET region to resist the high field strength of the coupling part of the JFET region and the gate structure layer, so that the field strength at the gate structure layer is reduced, thereby making the field effect transistor have a strong radiation resistance capability, and a channel can be formed inside the second conductive structure region having the first conductive type region and the second conductive type region, thereby increasing the overall channel number of the field effect transistor and reducing the on-resistance; the width and thickness of the second conductive structure region are both smaller than the first conductive structure region, and the area occupied by the second conductive structure region in the JFET region is smaller, so that the JFET region between the two first conductive structure regions has a sufficient area, and the on-resistance at the JFET region is small, thereby ensuring the performance of the field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 This is a schematic diagram of the overall structure of the radiation-resistant power field effect transistor according to an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a first well region and a second well region of a radiation-resistant power field effect transistor according to an embodiment of the present application;

[0026] Figure 3 A schematic diagram of a second heavily doped region and a fourth heavily doped region of a radiation-resistant power field effect transistor according to an embodiment of the present application;

[0027] Figure 4 A schematic diagram of a first heavily doped region and a third heavily doped region of a radiation-resistant power field effect transistor according to an embodiment of the present application;

[0028] Figure 5 A schematic diagram of a gate structure layer of a radiation-resistant power field effect transistor according to an embodiment of the present application;

[0029] Figure 6 A schematic diagram of an isolation layer of a radiation-resistant power field effect transistor according to an embodiment of the present application;

[0030] Figure 7A schematic diagram of a first electrode layer of a radiation-resistant power field effect transistor according to an embodiment of the present application;

[0031] Figure 8 Flow chart of a method for manufacturing a radiation-resistant power field effect transistor according to an embodiment of the present application.

[0032] Description of Figure Numbers:

[0033] 10. first electrode layer; 11. first electrode body; 12. first electrode connection portion; 20. gate structure layer; 21. gate dielectric layer; 22. polysilicon gate; 30. epitaxial layer; 40. substrate layer; 50. second electrode layer; 60. first conductive structure region; 61. first well region; 62. first heavily doped region; 63. second heavily doped region; 70. JFET region; 80. second conductive structure region; 81. second well region; 82. third heavily doped region; 83. fourth heavily doped region; 90. isolation layer; 91. connecting portion; 92. accommodating portion; 100. passivation layer;

[0034] X, first direction; Y, second direction. DETAILED DESCRIPTION

[0035] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0036] like Figures 1 to 7 As shown, an embodiment of the present application provides a radiation-resistant power field effect transistor, which includes a gate structure layer 20, an epitaxial layer 30 and a substrate layer 40 stacked along a first direction X. On the side close to the gate structure layer 20, a plurality of first conductive structure regions 60, a plurality of JFET regions 70 and a plurality of second conductive structure regions 80 are arranged in the epitaxial layer 30. Along the first direction X and the second direction Y, the thickness and width of the second conductive structure region 80 are both smaller than the first conductive structure region 60. Each JFET region 70 is arranged between adjacent first conductive structure regions 60, and each second conductive structure region 80 is correspondingly arranged in each JFET region 70; wherein, the epitaxial layer 30 and the JFET region 70 have a first conductive type, and the ion concentration of the JFET region 70 is higher than the ion concentration of the epitaxial layer 30, and the first conductive structure region 60 and the second conductive structure region 80 both have a first conductive type region and a second conductive type region.

[0037] Specifically, the first conductivity type is N-type, that is, the epitaxial layer 30 and the JFET region 70 are both N-type regions, and the second conductivity type is P-type, that is, there are N-type regions and P-type regions in the first conductive structure region 60 and the second conductive structure region 80. It should be noted that the first conductivity type can also be set to P-type and the second conductivity type can be set to N-type.

[0038] In specific implementation, the field effect transistor of the embodiment of the present application includes a gate structure layer 20, an epitaxial layer 30 and a substrate layer 40 stacked along a first direction X. On the side close to the gate structure layer 20, a plurality of first conductive structure regions 60, a plurality of JFET regions 70 and a plurality of second conductive structure regions 80 are arranged in the epitaxial layer 30. When the field effect transistor is manufactured as a whole, the gate structure layer 20 is an ordinary gate structure, and there is no need to use a locos (Local Oxidation of Silicon) process to increase the thickness of the gate oxide layer, that is, there is no need to separately make a locos plate and a separate thermal process to form a locos structure. Therefore, the overall process is relatively simple and the manufacturing cost is low.

[0039] The second conductive structure region 80 is arranged in the JFET region 70 between two adjacent first conductive structure regions 60, and the second conductive structure region 80 has a first conductive type region and a second conductive type region, so that it can work together with the JFET region 70 to resist the high field strength of the coupling portion of the JFET region 70 and the gate structure layer 20, so that the field strength at the gate structure layer 20 is reduced, thereby making the field effect transistor have a strong radiation resistance capability, and a channel can be formed inside the second conductive structure region 80 having the first conductive type region and the second conductive type region, thereby increasing the overall channel number of the field effect transistor and reducing the on-resistance; the width and thickness of the second conductive structure region 80 are both smaller than the first conductive structure region 60, and the area occupied by the second conductive structure region 80 in the JFET region 70 is smaller, so that the JFET region 70 between the two first conductive structure regions 60 has a sufficient area, and the on-resistance at the JFET region 70 is small, thereby ensuring the performance of the field effect transistor.

[0040] like Figure 1 As shown, the radiation-resistant power field effect transistor of an embodiment of the present application, wherein, along the first direction X, the thickness of the second conductive structure region 80 is 50% or less of the thickness of the first conductive structure region 60; along the second direction Y, the width of the second conductive structure region 80 is 50% or less of the width of the first conductive structure region 60.

[0041] In a specific implementation, since the second conductive structure region 80 is disposed in the JFET region 70 between two adjacent first conductive structure regions 60, the smaller the area it occupies, the larger the area of ​​the JFET region 70. Setting the thickness and width of the second conductive structure region 80 to 50% or less of the thickness and width of the first conductive structure region 60 can ensure that the JFET region 70 has a sufficiently large area to avoid excessive on-resistance.

[0042] like Figure 6 As shown, the radiation-resistant power field effect transistor of an embodiment of the present application further includes a first electrode layer 10 and an isolation layer 90. The isolation layer 90 is arranged between the first electrode layer 10 and the gate structure layer 20, and is used to isolate the first electrode layer 10 from the conductive connection with the gate structure layer 20. The isolation layer 90 has a plurality of connecting portions 91 arranged at intervals along the second direction. Each connecting portion 91 is arranged relative to the first conductive structure area 60 or the second conductive structure area 80. The first electrode layer 10 is conductively connected to the first conductive structure area 60 or the second conductive structure area 80 through the connecting portion 91.

[0043] In the embodiment of the present application, the first electrode layer 10 is the source of the field effect transistor. The field effect transistor also includes a second electrode layer 50 disposed under the substrate layer 40. The second electrode layer 50 is the drain of the field effect transistor. The two are spaced apart on both sides of the semiconductor structure composed of the epitaxial layer 30 and the substrate layer 40 in the first direction X. When a forward voltage is applied to the gate structure layer 20, a channel is formed between the gate structure layer 20 and the first conductive structure area 60 and the second conductive structure area 80 in the epitaxial layer 30. At this time, the voltage difference between the first electrode layer 10 and the second electrode layer 50 drives the current from the second electrode layer 50 through the substrate layer 40, the epitaxial layer 30, the JFET area 70, the first conductive structure area 60 and the second conductive structure area 80 to the first electrode layer 10 in sequence.

[0044] The isolation layer 90 is disposed between the first electrode layer 10 and the gate structure layer 20 to prevent the gate structure layer 20 from being electrically connected to the first electrode layer 10, thereby preventing the first electrode layer 10 from being affected when a voltage is applied to the gate structure layer 20, so that the field effect transistor can work normally.

[0045] The provision of multiple connecting portions 91 enables the first electrode layer 10 to directly pass through the connecting portions 91 and contact the first conductive structure region 60 or the second conductive structure region 80 when the first electrode layer 10 is conductively connected to the first conductive structure region 60 or the second conductive structure region 80, thereby avoiding contact with the gate structure layer 20 disposed on the first surface of the epitaxial layer 30, thereby achieving a better isolation effect.

[0046] like Figure 4As shown, the radiation-resistant power field effect transistor of an embodiment of the present application, wherein the first conductive structure region 60 includes a first well region 61, a first heavily doped region 62 and a second heavily doped region 63, the first well region 61 extends from the first surface of the epitaxial layer 30 in the first direction X to the inside, the first heavily doped region 62 and the second heavily doped region 63 are both arranged in the first well region 61 and both extend inward along the first surface of the epitaxial layer 30, and the second heavily doped region 63 is arranged on both sides of the first heavily doped region 62 in the second direction Y; wherein the first well region 61 and the first heavily doped region 62 have the second conductivity type, and the second heavily doped region 63 has the first conductivity type.

[0047] In a specific implementation, the first well region 61 of the first conductive structure region 60 is a P-type region, which is entirely arranged in the N-type epitaxial layer 30. The first heavily doped region 62 in the first well region 61 is also a P-type region. The ion concentration of the first heavily doped region 62 is higher than the ion concentration of the first well region 61. The second heavily doped region 63 is an N-type region, which is also arranged in the first well region 61 and on both sides of the first heavily doped region 62. Therefore, a channel can be formed in the first conductive structure region 60 between the JFET region 70 and the first electrode layer 10, thereby forming a complete path from the second electrode layer 50 to the first electrode layer 10, so that the field effect transistor can achieve its conduction effect.

[0048] like Figure 4 As shown, the radiation-resistant power field effect transistor of an embodiment of the present application, wherein the second conductive structure region 80 includes a second well region 81, a third heavily doped region 82 and a fourth heavily doped region 83, the second well region 81 extends from the first surface of the epitaxial layer 30 in the first direction X to the inside, the third heavily doped region 82 and the fourth heavily doped region 83 are both arranged in the second well region 81 and both extend inward along the first surface of the epitaxial layer 30, and the fourth heavily doped region 83 is arranged on both sides of the third heavily doped region 82 in the second direction Y; wherein the second well region 81 and the third heavily doped region 82 have the second conductivity type, and the fourth heavily doped region 83 has the first conductivity type.

[0049] In a specific implementation, the second well region 81 of the second conductive structure region 80 is a P-type region, which is entirely arranged in the N-type JFET region 70. The third heavily doped region 82 in the second well region 81 is also a P-type region, and the ion concentration of the third heavily doped region 82 is higher than the ion concentration of the second well region 81. The fourth heavily doped region 83 is an N-type region, which is also arranged in the second well region 81 and on both sides of the third heavily doped region 82. Therefore, the second conductive structure region 80 composed of the second well region 81, the third heavily doped region 82 and the fourth heavily doped region 83 is a small MOSFET structure. Two channels can be formed through the second conductive structure region 80 from the JFET region 70 on both sides of the second conductive structure region 80 to the first electrode layer 10, thereby increasing the number of channels of the overall field effect transistor and further reducing the overall on-resistance.

[0050] Moreover, the threshold voltage of the second conductive structure area 80 is greater than or equal to the threshold voltage of the first conductive structure area 60. When the voltage applied by the gate structure layer 20 reaches the threshold voltage of the first conductive structure area 60 but does not reach the threshold voltage of the second conductive structure area 80, the first conductive structure area 60 is in an on state, and the second conductive structure area 80 is not turned on. At this time, the entire device of the field effect transistor can also be in a conducting state. Therefore, the second conductive structure area 80 is only used as an auxiliary structure to reduce the on-resistance, and is not a structure for controlling the field effect transistor to be turned on or off. It should be noted that the above is only an explanation of the second conductive structure area 80 not being a structure for controlling the field effect transistor to be turned on or off. In the actual operation process of the field effect transistor, the voltage value applied by the gate structure layer 20 is simultaneously greater than the threshold voltage of the second conductive structure area 80 and the threshold voltage of the first conductive structure area 60, so that the first conductive structure area 60 and the second conductive structure area 80 can both be in an on state when the field effect transistor is working.

[0051] like Figure 4 As shown, in the radiation-resistant power field effect transistor of the embodiment of the present application, along the second direction Y, the width of the third heavily doped region 82 is smaller than the width of the first heavily doped region 62, and the width of the fourth heavily doped region 83 is smaller than the width of the second heavily doped region 63. In the first direction X, the thicknesses of the first heavily doped region 62, the second heavily doped region 63, the third heavily doped region 82 and the fourth heavily doped region 83 are the same.

[0052] In specific implementation, not only is the overall size of the second well region 81 smaller than the overall size of the first well region 61, but the widths of the third heavily doped region 82 and the fourth heavily doped region 83 provided in the second well region 81 are also smaller than the widths of the first heavily doped region 62 and the second heavily doped region 63 provided in the first well region 61, respectively, thereby further ensuring that the overall size of the second conductive structure region 80 is smaller than the overall size of the first conductive structure region 60, and also ensuring that the third heavily doped region 82 and the fourth heavily doped region 83 can be completely provided inside the second well region 81, thereby forming a small MOSFET structure in the JFET region 70.

[0053] Optionally, along the first direction X, the thickness of the third heavily doped region 82 is smaller than the thickness of the first heavily doped region 62 , and the thickness of the fourth heavily doped region 83 is smaller than the thickness of the second heavily doped region 63 .

[0054] like Figure 7As shown, the radiation-resistant power field effect transistor of the embodiment of the present application, wherein the first electrode layer 10 includes a first electrode body portion 11 and a plurality of first electrode connecting portions 12, the first electrode body portion 11 is a plate-like structure perpendicular to the first direction X, the first electrode connecting portion 12 extends along the first direction X and protrudes from the first electrode body portion 11 in a direction toward the epitaxial layer 30, and the plurality of first electrode connecting portions 12 are arranged one by one in the plurality of connecting portions 91; a portion of the first electrode connecting portion 12 forms ohmic contacts with both the first heavily doped region 62 and the second heavily doped region 63, and another portion of the first electrode connecting portion 12 forms ohmic contacts with both the third heavily doped region 82 and the fourth heavily doped region 83.

[0055] In a specific implementation, a plurality of first electrode connection portions 12 are arranged along the first direction X to protrude from the first electrode body portion 11 of the plate-like structure, and can be arranged one-to-one in the plurality of connecting portions 91, and are conductively connected to the first conductive structure area 60 and the second conductive structure area 80 through the plurality of connecting portions 91, thereby forming a complete current path when the gate is in the on state.

[0056] In addition, a portion of the first electrode connection portion 12 forms ohmic contact with the first heavily doped region 62 and the second heavily doped region 63, and another portion of the first electrode connection portion 12 forms ohmic contact with the third heavily doped region 82 and the fourth heavily doped region 83 to prevent secondary breakdown of the field effect transistor.

[0057] like Figure 6 As shown, the radiation-resistant power field effect transistor of an embodiment of the present application, wherein the isolation layer 90 also includes a plurality of accommodating portions 92 for accommodating the gate structure layer 20, each accommodating portion 92 is arranged between two adjacent connecting portions 91, and each connecting portion 91 is conductively connected to the JFET region 70 and the first conductive structure region 60 and the second conductive structure region 80 adjacent to the JFET region 70.

[0058] In a specific implementation, the gate structure layer 20 is accommodated in the accommodating portion 92 of the isolation layer 90, and the accommodating portion 92 is arranged between two adjacent connecting portions 91, so that the gate structure layer 20 can be separated from the first electrode connecting portion 12 in the connecting portion 91, thereby avoiding direct contact between the gate structure layer 20 and the first electrode connecting portion 12 and causing conductive connection.

[0059] Specifically, the gate structure layer 20 includes a gate dielectric layer 21 and a polysilicon gate 22 stacked along a first direction X. The gate dielectric layer 21 is disposed on the first surface of the epitaxial layer 30 and is conductively connected to the JFET region 70 and the first conductive structure region 60 and the second conductive structure region 80 adjacent to the JFET region 70.

[0060] A passivation layer 100 is further provided on the first electrode layer 10 for protecting the overall structure of the field effect transistor. The passivation layer 100 is made of metal oxide and can improve the stability, reliability and corrosion resistance of the field effect transistor.

[0061] like Figure 8 As shown, the embodiment of the present application also provides a method for manufacturing a radiation-resistant power field effect transistor, which includes:

[0062] S110, such as Figure 2 As shown, epitaxial growth is performed on one side of the substrate layer 40 in the first direction X to form an epitaxial layer 30 having a first conductivity type; wherein the substrate layer 40 is made of a semiconductor material such as silicon or silicon carbide, and the substrate layer 40 can serve as a base structure for epitaxial growth of the epitaxial layer 30. After the epitaxial layer 30 is formed, the second surface of the epitaxial layer 30 in the first direction X is in contact with the substrate layer 40;

[0063] S120, such as Figure 2 As shown, the first conductive type ions are implanted on the first surface of the epitaxial layer 30, and annealing is performed to form a JFET region 70; wherein the first surface of the epitaxial layer 30 is arranged on the side of the epitaxial layer 30 facing away from the substrate layer 40, and the ion concentration of the JFET region 70 is higher than the ion concentration of the epitaxial layer 30;

[0064] S130, such as Figure 2 As shown, second conductive type ions are implanted into both sides and the inside of the JFET region 70 from the first surface of the epitaxial layer 30, and annealing is performed to form a first well region 61 and a second well region 81; wherein the ion concentration of the first well region 61 and the ion concentration of the second well region 81 are also greater than the ion concentration of the epitaxial layer 30;

[0065] S140, such as Figure 3 As shown, heavily doped second conductive type ions are implanted into the first well region 61 and the second well region 81 on the first surface of the epitaxial layer 30, and activated to form the first heavily doped region 62 and the third heavily doped region 82, respectively; wherein the ion concentrations of the first heavily doped region 62 and the third heavily doped region 82 are higher than the ion concentrations of the first well region 61 and the second well region 81;

[0066] S150, such as Figure 4As shown, heavily doped first conductive type ions are implanted on both sides of the first heavily doped region 62 and both sides of the third heavily doped region 82 on the first surface of the epitaxial layer 30, and are activated to form the second heavily doped region 63 and the fourth heavily doped region 83, respectively; wherein the ion concentrations of the second heavily doped region 63 and the fourth heavily doped region 83 are also higher than the ion concentrations of the first well region 61 and the second well region 81, and after the second heavily doped region 63 and the fourth heavily doped region 83 are formed, the first well region 61, the first heavily doped region 62 and the second heavily doped region 63 can jointly form the first conductive structure region 60, and the second well region 81, the third heavily doped region 82 and the fourth heavily doped region 83 can jointly form the second conductive structure region 80, thereby forming a complete semiconductor structure;

[0067] S160, such as Figure 5 As shown, a gate structure layer 20 conductively connected to the JFET region 70 is disposed on the first surface of the epitaxial layer 30; wherein the gate structure layer 20 is also conductively connected to the first conductive structure region 60 and the second conductive structure region 80 to form a conductive channel for current to pass through;

[0068] S170, such as Figure 1 and Figure 7 As shown, an isolation layer 90, a first electrode layer 10 and a passivation layer 100 are sequentially arranged on one side of the first surface of the epitaxial layer 30, and a second electrode layer 50 is arranged on the second surface of the substrate layer 40; wherein the first electrode layer 10 is the source of the field effect transistor, the second electrode layer 50 is the drain of the field effect transistor, and the passivation layer 100 is arranged on the surface of the source to protect the internal structure of the field effect transistor.

[0069] In specific implementation, the method for manufacturing a radiation-resistant power field effect transistor according to the embodiment of the present application can be used to manufacture a power field effect transistor with radiation-resistant performance. The field effect transistor includes a gate structure layer 20, an epitaxial layer 30 and a substrate layer 40 stacked along a first direction X. On one side close to the gate structure layer 20, the epitaxial layer 30 is provided with a plurality of first conductive structure regions 60, a plurality of JFET regions 70 and a plurality of second conductive structure regions 80. The second conductive structure region 80 is provided in the JFET region 70 between two adjacent first conductive structure regions 60, and the second conductive structure region 80 has a first conductive type region and the second conductive type region, so that they can work together with the JFET region 70 to resist the high field strength of the coupling part of the JFET region 70 and the gate structure layer 20, reduce the field strength at the gate structure layer 20, and thus make the field effect transistor have a strong radiation resistance capability; the width and thickness of the second conductive structure region 80 are smaller than the first conductive structure region 60, and the area occupied by the second conductive structure region 80 in the JFET region 70 is smaller, so that the JFET region 70 between the two first conductive structure regions 60 has sufficient area, and the on-resistance at the JFET region 70 is small, thereby ensuring the performance of the field effect transistor.

[0070] In step S160, if Figure 5 As shown, it also specifically includes:

[0071] S161, performing a thermal oxidation operation on the first surface of the epitaxial layer 30 to form a gate dielectric layer 21, wherein the middle portion of the gate dielectric layer 21 covers the JFET region 70, and both ends of the gate dielectric layer 21 cover the first conductive structure region 60 and the second conductive structure region 80 respectively, and are connected to the first well region 61 and the second well region 81 close to the JFET region 70, and are also connected to a portion of the second heavily doped region 63 and a portion of the fourth heavily doped region 83 close to the JFET region 70;

[0072] S162 , growing polysilicon on the surface of the gate dielectric layer 21 away from the epitaxial layer 30 , and forming a polysilicon gate 22 by etching.

[0073] like Figure 6 As shown, the manufacturing method of the radiation-resistant power field effect transistor of the embodiment of the present application, wherein the step of setting the isolation layer 90 and the first electrode layer 10 on one side of the first surface of the epitaxial layer 30 specifically includes: depositing an isolation dielectric on the first surface of the epitaxial layer 30 and the surface of the gate structure layer 20 to form the isolation layer 90, and forming a receiving portion 92 for accommodating the gate structure layer 20 on the side of the isolation layer 90 close to the epitaxial layer 30; performing hole etching on the isolation layer 90 along the first direction X to form a plurality of connecting portions 91; depositing metal on the surface of the isolation layer 90 and in the connecting portions 91 to form the first electrode layer 10, and the first electrode layer 10 includes a first electrode body portion 11 provided on the surface of the isolation layer 90 and a first electrode connecting portion 12 provided in the connecting portion 91.

[0074] In a specific implementation, when the isolation layer 90 is formed, since there are multiple gate structure layers 20 on the first surface of the epitaxial layer 30, the isolation layer 90 has a recessed structure accommodating portion 92 after formation. The gate structure layer 20 is arranged in the accommodating portion 92 and will not come into direct contact with the first electrode layer 10, thereby enabling isolation. After the overall structure of the isolation layer 90 is formed, the isolation layer 90 is hole-etched along the first direction X to form multiple connecting portions 91. The arrangement of the connecting portion 91 enables the first electrode layer 10 to form a first electrode connecting portion 12 in the connecting portion 91 when it is formed. The first electrode connecting portion 12 passes through the connecting portion 91 to be conductively connected to the first conductive structure area 60 or the second conductive structure area 80, thereby enabling the field effect transistor to achieve its full function.

[0075] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0076] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A radiation-resistant power field effect transistor, characterized in that: The invention comprises a gate structure layer (20), an epitaxial layer (30) and a substrate layer (40) stacked along a first direction (X); on a side close to the gate structure layer (20), the epitaxial layer (30) is provided with a plurality of first conductive structure regions (60), a plurality of JFET regions (70) and a plurality of second conductive structure regions (80); along the first direction (X) and the second direction (Y), the thickness and width of the second conductive structure region (80) are both smaller than those of the first conductive structure region (60); each of the JFET regions (70) is arranged between adjacent first conductive structure regions (60); and each of the second conductive structure regions (80) is respectively arranged in each of the JFET regions (70); The epitaxial layer (30) and the JFET region (70) have a first conductivity type, and the ion concentration of the JFET region (70) is higher than the ion concentration of the epitaxial layer (30), and the first conductive structure region (60) and the second conductive structure region (80) both have a first conductive type region and a second conductive type region.

2. The radiation-resistant power field effect transistor according to claim 1, characterized in that: Along the first direction (X), the thickness of the second conductive structure region (80) is 50% or less of the thickness of the first conductive structure region (60); along the second direction (Y), the width of the second conductive structure region (80) is 50% or less of the width of the first conductive structure region (60).

3. The radiation-resistant power field effect transistor according to claim 1, characterized in that: The first conductive structure region (60) comprises a first well region (61), a first heavily doped region (62) and a second heavily doped region (63); the first well region (61) extends from the first surface of the epitaxial layer (30) in the first direction (X) to the inside; the first heavily doped region (62) and the second heavily doped region (63) are both arranged in the first well region (61) and extend inwardly along the first surface of the epitaxial layer (30); and the second heavily doped region (63) is arranged on both sides of the first heavily doped region (62) in the second direction (Y); The first well region (61) and the first heavily doped region (62) have the second conductivity type, and the second heavily doped region (63) has the first conductivity type.

4. The radiation-resistant power field effect transistor according to claim 3, characterized in that: The second conductive structure region (80) comprises a second well region (81), a third heavily doped region (82) and a fourth heavily doped region (83); the second well region (81) extends from the first surface of the epitaxial layer (30) in the first direction (X) to the inside; the third heavily doped region (82) and the fourth heavily doped region (83) are both arranged in the second well region (81) and extend inwardly along the first surface of the epitaxial layer (30); the fourth heavily doped region (83) is arranged on both sides of the third heavily doped region (82) in the second direction (Y); The second well region (81) and the third heavily doped region (82) have the second conductivity type, and the fourth heavily doped region (83) has the first conductivity type.

5. The radiation-resistant power field effect transistor according to claim 4, characterized in that: Along the second direction (Y), the width of the third heavily doped region (82) is smaller than the width of the first heavily doped region (62), and the width of the fourth heavily doped region (83) is smaller than the width of the second heavily doped region (63).

6. The radiation-resistant power field effect transistor according to claim 4, characterized in that: The invention also comprises a first electrode layer (10) and an isolation layer (90), wherein the isolation layer (90) is arranged between the first electrode layer (10) and the gate structure layer (20) and is used to isolate the first electrode layer (10) from being conductively connected to the gate structure layer (20), and the isolation layer (90) has a plurality of connecting portions (91) arranged at intervals along the second direction, each of the connecting portions (91) being arranged relative to the first conductive structure region (60) or the second conductive structure region (80), and the first electrode layer (10) is conductively connected to the first conductive structure region (60) or the second conductive structure region (80) through the connecting portions (91).

7. The radiation-resistant power field effect transistor according to claim 6, characterized in that: The first electrode layer (10) comprises a first electrode body portion (11) and a plurality of first electrode connecting portions (12); the first electrode body portion (11) is a plate-shaped structure perpendicular to the first direction (X); the first electrode connecting portion (12) extends along the first direction (X) and protrudes from the first electrode body portion (11) in a direction toward the epitaxial layer (30); and the plurality of first electrode connecting portions (12) are arranged in a one-to-one correspondence within the plurality of connecting portions (91); A portion of the first electrode connecting portion (12) forms ohmic contact with both the first heavily doped region (62) and the second heavily doped region (63), and another portion of the first electrode connecting portion (12) forms ohmic contact with both the third heavily doped region (82) and the fourth heavily doped region (83).

8. The radiation-resistant power field effect transistor according to claim 6, characterized in that: The isolation layer (90) further comprises a plurality of accommodating portions (92) for accommodating the gate structure layer (20), each of the accommodating portions (92) being arranged between two adjacent connecting portions (91), and each of the connecting portions (91) being conductively connected to the JFET region (70) and the first conductive structure region (60) and the second conductive structure region (80) adjacent to the JFET region (70).

9. A method for manufacturing a radiation-resistant power field effect transistor, characterized in that: include: Performing epitaxial growth on one side of the substrate layer (40) in a first direction (X) to form an epitaxial layer (30) having a first conductivity type; Implanting first conductive type ions on a first surface of the epitaxial layer (30), and performing annealing to form a JFET region (70); Implanting second conductive type ions from the first surface of the epitaxial layer (30) into both sides and the interior of the JFET region (70), and annealing to form a first well region (61) and a second well region (81); Implanting heavily doped second conductive type ions into the first well region (61) and the second well region (81) on the first surface of the epitaxial layer (30), and activating them to form a first heavily doped region (62) and a third heavily doped region (82); On the first surface of the epitaxial layer (30), heavily doped ions of the first conductive type are respectively implanted into both sides of the first heavily doped region (62) and both sides of the third heavily doped region (82), and activated to form a second heavily doped region (63) and a fourth heavily doped region (83); A gate structure layer (20) conductively connected to the JFET region (70) is provided on a first surface of the epitaxial layer (30); An isolation layer (90), a first electrode layer (10) and a passivation layer (100) are sequentially arranged on one side of the first surface of the epitaxial layer (30), and a second electrode layer (50) is arranged on the second surface of the substrate layer (40).

10. The method for manufacturing a radiation-resistant power field effect transistor according to claim 9, characterized in that: The step of providing an isolation layer (90) and a first electrode layer (10) on one side of the first surface of the epitaxial layer (30) specifically comprises: An isolation dielectric is deposited on the first surface of the epitaxial layer (30) and the surface of the gate structure layer (20) to form the isolation layer (90), and a receiving portion (92) for receiving the gate structure layer (20) is formed on a side of the isolation layer (90) close to the epitaxial layer (30); Performing hole etching on the isolation layer (90) along the first direction (X) to form a plurality of connecting portions (91); Metal is deposited on the surface of the isolation layer (90) and in the connecting portion (91) to form the first electrode layer (10), wherein the first electrode layer (10) comprises a first electrode body portion (11) disposed on the surface of the isolation layer (90) and a first electrode connecting portion (12) disposed in the connecting portion (91).

Images