Gate driving structure and display device

Abstract

The invention discloses a gate driving structure and a display device. The gate driving structure comprises an output module, and the output module is connected with an output line. The gate driving structure further comprises a plurality of function modules, the function modules are connected with the output line, and the function modules cooperate with the output module to form scanning signals; the at least one functional module comprises a first thin film transistor; the first thin film transistor comprises a first semiconductor layer, a first source drain electrode layer and a first buffer layer; the first source and drain electrode layer comprises a first source electrode layer and a first drain electrode layer, and the first source electrode layer and the first drain electrode layer are arranged above the first semiconductor layer; the first buffer layer is arranged between the first source electrode layer and the first semiconductor layer and between the first drain electrode layer and the first semiconductor layer, the first buffer layer is a composite metal layer, and leakage current of the first thin film transistor is reduced based on the composite metal layer. According to the technical scheme, the influence of leakage current can be reduced, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to a gate driving structure and a display device. Background Art

[0002] The gate driver on array (GOA) technology is used in the array substrate to realize the line-by-line scanning drive of the display panel. The stability of the GOA circuit is directly related to the display stability of the display panel. However, the GOA circuit has a complex structure. A large number of signal lines and thin film transistors (TFT) are densely arranged in the GOA circuit. The GOA circuit is easily affected by leakage current, resulting in the instability of the logic function of the GOA circuit. It is easy to make mistakes when the display panel is driven for line-by-line scanning, resulting in a poor display effect of the display panel. Summary of the invention

[0003] The purpose of the present application is to provide a gate driving structure that can effectively reduce the influence of leakage current and improve the display effect of a display panel.

[0004] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0005] According to one aspect of the embodiments of the present application, the present application provides a gate driving structure, the gate driving structure comprising an output module, the output module being connected to an output line;

[0006] The gate driving structure further comprises a plurality of functional modules, at least some of which are connected to the output line, and the functional modules cooperate with the output module to form a scanning signal;

[0007] At least one of the functional modules includes a first thin film transistor, and the first thin film transistor includes:

[0008] a first semiconductor layer;

[0009] a first source-drain electrode layer, wherein the first source-drain electrode layer comprises a first source electrode layer and a first drain electrode layer, and the first source electrode layer and the first drain electrode layer are arranged above the first semiconductor layer;

[0010] A first buffer layer is provided between the first source layer and the first semiconductor layer, and between the first drain layer and the first semiconductor layer. The first buffer layer is a composite metal layer. The composite metal layer is used to reduce leakage current of the first thin film transistor.

[0011] In one aspect, the gate driving structure further includes an organic layer, and the organic layer is disposed above the first source and drain electrode layer.

[0012] In one aspect, a channel region is formed between the first source electrode layer and the first drain electrode layer, and the organic layer at least covers the channel region.

[0013] In one aspect, the organic layer is at least one of a red color resist layer, a green color resist layer, and a blue color resist layer.

[0014] In one aspect, the first buffer layer includes at least two metals selected from the group consisting of molybdenum, titanium, aluminum, tantalum, nickel, and neodymium.

[0015] In one aspect, the output module includes a second thin film transistor, the second thin film transistor is disposed in the same layer as the first thin film transistor, and the second thin film transistor includes:

[0016] a second semiconductor layer;

[0017] a second source-drain electrode layer, the second source-drain electrode layer comprising a second source electrode layer and a second drain electrode layer, the second source electrode layer and the second drain electrode layer being arranged above the second semiconductor layer;

[0018] A second buffer layer, wherein the second buffer layer is disposed between the second source layer and the second semiconductor layer, and between the second drain layer and the second semiconductor layer, and the second buffer layer is a single metal layer, and the on-state current of the second thin film transistor is increased based on the single metal layer.

[0019] In one aspect, the second buffer layer is a metal selected from the group consisting of molybdenum, titanium, aluminum, tantalum, nickel and neodymium.

[0020] In one aspect, the gate drive structure further includes a first insulating layer and a second insulating layer;

[0021] The first thin film transistor includes a first gate layer, the first insulating layer is arranged between the first gate layer and the first semiconductor layer, and the second insulating layer covers the surface of the first source and drain layer;

[0022] The second thin film transistor further includes a second gate layer, the first insulating layer extends between the second semiconductor layer and the second gate layer, and the second insulating layer extends to the second source and drain electrode layer and covers the second source and drain electrode layer;

[0023] The gate driving structure further includes a planar layer, which is disposed above the first thin film transistor and extends to the second thin film transistor and covers the second insulating layer.

[0024] In one aspect, the functional modules are respectively a charging module, a pull-up module, a pull-down module, a first reset module, a second reset module and a capacitor, the capacitor comprises a first electrode plate and a second electrode plate arranged opposite to each other, and the capacitor is arranged on the output line;

[0025] The charging module is connected to the first electrode plate, the first reset module is connected to the first electrode plate, the second reset module is connected to the second electrode plate, the pull-up module is connected to the pull-down module, and the pull-down module is connected to the first reset module and the second reset module;

[0026] The first thin film transistor is respectively provided in the charging module, the pull-up module, the pull-down module, the first reset module and the second reset module, or the first thin film transistor is respectively provided in the charging module, the pull-down module, the first reset module and the second reset module, and the second thin film transistor is provided in the pull-up module.

[0027] In addition, in order to solve the above problems, the present application also provides a display device, which has a display area and a non-display area, and the non-display area is arranged around the display area. The display device includes the gate driving structure as described above, and the gate driving structure is arranged in the non-display area.

[0028] In the present application, a scanning signal is formed by cooperating with an output module through multiple functional modules, and the scanning signal can drive the display panel to scan line by line. In the first thin film transistor, a first buffer layer is arranged between the first source layer and the first semiconductor layer, and similarly, a first buffer layer is also arranged between the first drain layer and the first semiconductor layer. Since the first buffer layer is a composite metal layer, the contact resistance between the first buffer layer and the first semiconductor layer can be increased, thereby reducing the leakage current of the first thin film transistor, thereby reducing the influence of the leakage current, making the scanning signal more stable, and improving the display effect of the display panel.

[0029] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1The schematic diagram shows the structure of the first thin film transistor in the gate driving structure of the present application.

[0032] Figure 2 The schematic diagram of the structure of the second thin film transistor in the gate driving structure of the present application is shown schematically.

[0033] Figure 3 The circuit connection diagram of the gate drive structure in the present application is schematically shown.

[0034] Figure 4 The timing control diagram of the gate drive structure in the present application is schematically shown.

[0035] Figure 5 The structural diagram of the display device in the present application is schematically shown.

[0036] The following are the descriptions of the reference numerals:

[0037] 100, output module; 110, output line; 200, functional module; 210, charging module; 220, first reset module; 230, second reset module; 240, pull-up module; 250, pull-down module; C, capacitor; 310, first thin film transistor; 320, second thin film transistor; 400, organic layer; 500, substrate; 600, metal barrier layer; 700, flat layer; 800, conductive layer; 910, display area; 920, non-display area; U, first connection point; P, second connection point; D, third connection point; VSS1, first low level line; VSS2, second low level line; CLK, first clock signal; CLKB, second clock signal; INPUT, input signal; OUTPUT, scan signal; RESET, reset signal;

[0038] M1, first response switch; M2, second response switch; M3, third response switch; M4, fourth response switch; M5, fifth response switch; M6, sixth response switch; M7, seventh response switch; M8, eighth response switch; 311, first semiconductor layer; 312, first source and drain layer; 313, first buffer layer; 314, first gate layer; 315, first insulating layer; 316, second insulating layer;

[0039] 321, a second semiconductor layer; 322, a second source and drain layer; 323, a second buffer layer; 324, a second gate layer;

[0040] 3121, first source layer; 3122, first drain layer; 3123, channel region; 3221, second source layer; 3222, second drain layer. DETAILED DESCRIPTION

[0041] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0042] See also Figure 1 and Figure 3 As shown, the present application provides a gate driving structure, which includes an output module 100 , the output module 100 is connected to an output line 110 , and is used to provide a first clock signal CLK to the output line 110 .

[0043] The gate drive structure also includes a number of functional modules 200, at least some of which are connected to the output line 110, and the functional modules 200 cooperate with the output module 100 to form a scan signal OUTPUT. The functional module 200 can provide different waveform signals to the output line 110, thereby forming a scan signal OUTPUT by superimposing the first clock signal CLK provided by the output module 100. The scan signal OUTPUT can also be understood as an output signal. The display panel can be scanned line by line by the scan signal OUTPUT, and the corresponding pixel unit of the display panel can be driven to turn on. For example, the display panel includes pixel units distributed in a matrix, and each pixel unit is provided with a drive switch. The scan signal OUTPUT acts on the gate of the drive switch, and the source and drain of the drive switch are connected. The data signal provided by the data line can be loaded to the pixel unit through the drive switch, so that the pixel unit emits light.

[0044] In this embodiment, at least one functional module 200 includes a first thin film transistor 310, and the first thin film transistor 310 includes: a first semiconductor layer 311, a first source and drain layer 312 and a first buffer layer 313, the first source and drain layer 312 includes a first source layer 3121 and a first drain layer 3122, and the first source layer 3121 and the first drain layer 3122 are arranged above the first semiconductor layer 311; the first source layer 3121 and the first drain layer 3122 are arranged on the same layer.

[0045] The first buffer layer 313 is disposed between the first source layer 3121 and the first semiconductor layer 311, and between the first drain layer 3122 and the first semiconductor layer 311. The first buffer layer 313 is a composite metal layer, and the first source layer 3121 and the first semiconductor layer 311 are separated by the first buffer layer 313, and the first drain layer 3122 and the first semiconductor layer 311 are also separated. Since the first buffer layer 313 is a composite metal layer, the composite metal layer is used to reduce the leakage current of the first thin film transistor 310. The first source and drain layer 312 is generally a metal layer, such as copper metal.

[0046] In this embodiment, a scan signal OUTPUT is formed by cooperating with the output module 100 through multiple functional modules 200, and the scan signal OUTPUT can drive the display panel to scan line by line. In the first thin film transistor 310, a first buffer layer 313 is arranged between the first source layer 3121 and the first semiconductor layer 311, and similarly, a first buffer layer 313 is also arranged between the first drain layer 3122 and the first semiconductor layer 311. Since the first buffer layer 313 is a composite metal layer, the contact resistance between the first buffer layer 313 and the first semiconductor layer 311 can be increased, thereby reducing the leakage current of the first thin film transistor 310, thereby reducing the influence of the leakage current, making the scan signal OUTPUT more stable, and improving the display effect of the display panel.

[0047] It can be further understood that by providing the first thin film transistor 310 in the functional module 200, the performance of the functional module 200 is more stable, the leakage current thereof is reduced, and the scanning signal OUTPUT formed in cooperation with the output module 100 is also more stable.

[0048] In this application, the transistor is affected by the external environment such as light, which can easily make the leakage current of the transistor unstable, and the leakage current will increase. For this reason, in one embodiment of the present application, the gate drive structure also includes an organic layer 400, and the organic layer 400 is arranged above the first source and drain electrode layer 312. The organic layer 400 can block external light and reduce the situation where light is irradiated on the first thin film transistor 310. Thereby reducing the influence of external light on the first thin film transistor 310. The generation of leakage current in the first thin film transistor 310 is further reduced, making the performance of the first thin film transistor 310 more stable, that is, the operation of the functional module 200 is more stable.

[0049] In one embodiment of the present application, a channel region 3123 is formed between the first source electrode layer 3121 and the first drain electrode layer 3122, and the organic layer 400 at least covers the channel region 3123. It can be understood that the channel region 3123 mainly includes the first semiconductor layer 311 located between the first source electrode layer 3121 and the first drain electrode layer 3122, and the organic layer 400 can cover the first semiconductor layer 311 located between the first source electrode layer 3121 and the first drain electrode layer 3122, thereby reducing the influence of light on the first semiconductor layer 311 in the channel region 3123, thereby reducing leakage current.

[0050] In one embodiment of the present application, the organic layer 400 is at least one of a red color resist layer, a green color resist layer, and a blue color resist layer. A general display panel includes a display area 910 and a non-display area 920 arranged around the display area 910. The color resist layer is arranged in the display area 910, and the light emitted by the pixel unit of the display area 910 can pass through the color resist layer, thereby presenting a corresponding color. For example, the light of the pixel unit presents red light when passing through the red color resist layer, green light when passing through the green color resist layer, and blue light when passing through the blue color resist layer. Different colors can be formed by three different color ratios.

[0051] Regarding the principle of the color-resist layer attenuating light, for example, when light passes through the red color-resist layer, only red light can pass through, and light of other colors is filtered out, thereby reducing the overall amount of light. For the green color-resist layer and the blue color-resist layer, green light and blue light can pass through respectively. In general, the color-resist layer can reduce the amount of light and reduce the impact on the channel region 3123.

[0052] As can be seen from the above, when setting the color resist layer, the color resist material can be simultaneously coated on the top of the first thin film transistor 310. When etching, the etching of the organic layer 400 on the first thin film transistor 310 is completed simultaneously, reducing the subsequent steps of setting the organic layer 400 and etching the organic layer 400. When the color resist layer of the display area 910 is completed, the setting of the organic layer 400 of the non-display area 920 is also completed simultaneously, thereby improving the manufacturing processing efficiency.

[0053] In addition, the organic layer 400 can also be formed by a combination of two of the red color resist material, the green color resist material and the blue color resist material, or a combination of the three materials. For example, the organic layer 400 can be a mixture of red color resist material, green color resist material and blue color resist material in a certain proportion. Alternatively, the red color resist layer, the green color resist layer and the blue color resist layer are stacked in sequence, and the thickness of the organic layer 400 that reduces light can be increased by stacking the layers, further reducing the light passing through the organic layer 400.

[0054] In the present application, the gate drive structure can be applied to large-size and high-resolution display screens. In large-size and high-resolution display screens, the resistance load of the gate signal line increases greatly, and the output unit transistor in the GOA circuit needs to have a stronger output capability. To this end, the related art usually adopts the method of increasing the width of the output unit transistor, but this will make the design and arrangement of the output unit transistor occupy a larger space, resulting in the border of the display screen being too wide, making it difficult to achieve a narrow border.

[0055] See also Figure 2As shown, in order to solve the above problem, in one embodiment of the present application, the output module 100 includes a second thin film transistor 320, and the second thin film transistor 320 is arranged in the same layer as the first thin film transistor 310. By arranging the first thin film transistor 310 and the second thin film transistor 320, the second thin film transistor 320 can be manufactured while the first thin film transistor 310 is arranged, thereby improving the manufacturing efficiency.

[0056] The second thin film transistor 320 includes: a second semiconductor layer 321, a second source-drain electrode layer 322, and a second buffer layer 323; the second source-drain electrode layer 322 includes a second source electrode layer 3221 and a second drain electrode layer 3222, and the second source electrode layer 3221 and the second drain electrode layer 3222 are arranged above the second semiconductor layer 321; the second source-drain electrode layer 322 is arranged in the same layer as the first source-drain electrode layer 312, the first semiconductor layer 311 and the second semiconductor layer 321 are arranged in the same layer, the first buffer layer 313 and the second buffer layer 323 are arranged in the same layer, the second source-drain electrode layer 322 and the first source-drain electrode layer 312 can be made of the same material, and the first semiconductor layer 311 and the second semiconductor layer 321 can also be made of the same material. In order to ensure that the second thin film transistor 320 plays a different role from the first thin film transistor 310, the first buffer layer 313 and the second buffer layer 323 can be made of different materials.

[0057] Specifically, the second buffer layer 323 is disposed between the second source layer 3221 and the second semiconductor layer 321 , and between the second drain layer 3222 and the second semiconductor layer 321 . The second buffer layer 323 is a single metal layer, and the on-state current of the second thin film transistor 320 is increased based on the single metal layer.

[0058] By setting the second buffer layer 323 as a single metal, the single metal has better conductivity, which can reduce the contact resistance between the second buffer layer 323 and the second semiconductor layer 321. Under the same driving voltage, the output module 100 can have a larger current flowing through, thereby increasing the on-state current of the second thin film transistor 320. That is, in this embodiment, the second thin film transistor 320 does not need a larger width. By setting the second buffer layer 323, it is ensured that the second thin film transistor 320 can have a larger output capacity, and even a limited space position can provide a larger current, which is conducive to achieving a narrow frame.

[0059] Further, based on the above embodiment, the first buffer layer 313 includes at least two metals selected from molybdenum, titanium, aluminum, tantalum, nickel and neodymium. The first buffer layer 313 may also be a mixture of two or more of the above metals. The mixed composite metal can increase the contact resistance. The second buffer layer 323 is a metal selected from molybdenum, titanium, aluminum, tantalum, nickel and neodymium. The single metal can reduce the contact resistance.

[0060] In one embodiment of the present application, the gate driving structure further includes a first insulating layer 315 and a second insulating layer 316. The first insulating layer 315 and the second insulating layer 316 can protect the first thin film transistor 310 and the second thin film transistor 320 from short circuits by providing the first insulating layer 315 and the second insulating layer 316. Moreover, the influence of external water vapor on the first thin film transistor 310 and the second thin film transistor 320 can also be reduced.

[0061] The first thin film transistor 310 includes a first gate layer 314, a first insulating layer 315 disposed between the first gate layer 314 and the first semiconductor layer 311, and the first insulating layer 315 covers the surface of the first gate layer 314 to protect the first gate layer 314 and prevent the first gate layer 314 from being short-circuited or interfered by external signals. The second insulating layer 316 is disposed between the first source-drain electrode layer 312 and the organic layer 400; the second insulating layer 316 covers the surface of the first source-drain electrode layer 312 to prevent the first source-drain electrode layer 312 from being affected by a short circuit.

[0062] The second thin film transistor 320 further includes a second gate layer 324, the first insulating layer 315 extends between the second semiconductor layer 321 and the second gate layer 324, and the second insulating layer 316 extends to the upper surface of the second source-drain electrode layer 322. The first insulating layer 315 can also provide insulation protection for the second gate layer 324 to reduce interference from short circuits or other circuits. Similarly, the second insulating layer 316 can provide insulation protection for the second source-drain electrode layer 322.

[0063] The gate driving structure further includes a planar layer 700, which is disposed above the first thin film transistor, specifically, the planar layer 700 is disposed on the upper surface of the organic layer 400, and the planar layer 700 extends to the second thin film transistor 320 and covers the upper part of the second insulating layer 316. The planar layer 700 is used to further protect the first thin film transistor 310 and the second thin film transistor 320, and can also ensure that the upper part of the first thin film transistor 310 and the second thin film transistor 320 is flat.

[0064] The gate drive structure of the present application may also be provided with a conductive layer 800 as required, and the conductive layer 800 is provided above the planar layer 700. The conductive layer 800 may be provided above the first thin film transistor 310 and above the second thin film transistor 320, respectively, and a hole may be opened at a position between the conductive layer 800 and the thin film transistor to connect the conductive layer 800 to the drain layer. In this way, the first thin film transistor 310 and the second thin film transistor 320 may be used as control switches to control the on and off of transmitting various electrical signals.

[0065] The manufacturing steps of the gate drive structure of the present application are described as follows:

[0066] A metal barrier material is disposed on the substrate 500, and is etched to form a metal barrier layer 600. A first metal material is disposed on the metal barrier layer 600, and the first metal material is processed by a light irradiation process and an etching process to form a first metal layer. The metal barrier layer 600 and the first metal layer may be disposed by physical vapor deposition. Two first metal layers are disposed, one of which is the first gate layer 314 of the first thin film transistor 310, and the other first metal layer is the second gate of the second thin film transistor 320. The metal barrier layer 600 can increase the bonding effect between the first metal layer and the substrate 500, and can also prevent particles in the first metal layer from diffusing to the substrate 500.

[0067] A first insulating layer 315 is formed on the first metal layer by plasma enhanced chemical vapor deposition, a semiconductor layer is deposited on the first insulating layer 315 , and the semiconductor layer is etched to form a first semiconductor body layer and a second semiconductor layer 321 .

[0068] A composite metal layer is disposed above the first semiconductor layer 311, and a single metal layer is disposed above the second semiconductor layer 321, that is, a first buffer layer 313 is disposed above the first semiconductor layer 311, and a second buffer layer 323 is disposed above the second semiconductor layer 321. For example, the first buffer layer 313 and the second buffer layer 323 can be formed by masking.

[0069] A second metal layer is disposed above the first buffer layer 313 , and the second metal layer is processed by etching to form a first source layer 3121 and a first drain layer 3122 , and a second source layer 3221 and a second drain layer 3222 are simultaneously formed.

[0070] The organic layer 400 is disposed above the position corresponding to the first source-drain electrode layer 312 , so that the organic layer 400 can at least cover the channel region 3123 of the first thin film transistor 310 .

[0071] A planar layer 700 is disposed above the organic layer 400, and the planar layer 700 covers and extends above the second thin film transistor 320. When a conductive layer 800 is required, holes can be opened in the first drain electrode layer 3122 and the second drain electrode layer 3222, respectively, and a conductive layer 800 is disposed at the corresponding opening positions. The conductive layer 800 can be ITO (Indium Tin Oxides).

[0072] See also Figure 3As shown, in one embodiment of the present application, the functional modules 200 are respectively a charging module 210, a pull-up module 240, a pull-down module 250, a first reset module 220, a second reset module 230 and a capacitor C, the capacitor C includes a first electrode plate and a second electrode plate arranged opposite to each other, and the capacitor C is arranged on the output line 110; the first electrode plate and the second electrode plate are arranged opposite to each other, and the first electrode plate and the second electrode plate are respectively connected to the output line 110.

[0073] The charging module 210 is connected to the first electrode plate, the first reset module 220 is connected to the first electrode plate, the second reset module 230 is connected to the second electrode plate, the pull-up module 240 is connected to the pull-down module 250, and the pull-down module 250 is connected to the first reset module 220 and the second reset module 230; the first reset module 220 is also connected to the first low level line VSS1, and the second reset module 230 is connected to the second low level line VSS2. When the first reset module 220 is working, the voltage of the first low level line VSS1 can be loaded onto the first electrode plate, and when the second reset module 230 is working, the voltage of the second low level line VSS2 can be loaded onto the second electrode plate. The connection point between the first electrode plate and the output line 110 is the first connection point U, and the connection point between the second electrode plate and the output line 110 is the second connection point P.

[0074] The specific structures of the functional modules 200 and the output module 100 in this embodiment are described below by way of example:

[0075] The charging module 210 includes a first response switch M1, a first end of the first response switch M1 receives an input signal INPUT, a second end of the first response switch M1 is connected to a second connection point P, and a control end of the first response switch M1 is connected to the first end of the first response switch M1 to receive the input signal INPUT.

[0076] The output module 100 includes a second response switch M2 , a first end of the second response switch M2 receives a first clock signal CLK, a second end of the second response switch M2 is connected to a first connection point U, and a control end of the second response switch M2 is connected to a second connection point P.

[0077] The first reset module 220 includes a third response switch M3, a first end of the third response switch M3 is connected to the first low level line VSS1, the first low level line VSS1 is used to provide a first voltage, a second end of the third response switch M3 is connected to the first connection point U, and a control end of the third response switch M3 receives a first reset signal to load the first voltage to the first connection point U.

[0078] The pull-up module 240 includes a fourth response switch M4, and the pull-down module 250 includes a fifth response switch M5, a sixth response switch M6, and a seventh response switch M7. The second end of the fourth response switch M4 receives the second clock signal CLKB, the first end of the fourth response switch M4 is connected to the second end of the fifth response switch M5, and the control end of the fourth response switch M4 receives the second clock signal CLKB. The connection point between the first end of the fourth response switch M4 and the second end of the fifth response switch M5 is the third connection point D. The first end of the fifth response switch M5 is connected to the second low level line VSS2, the second low level line VSS2 provides the second voltage, and the control end of the fifth response switch M5 is connected to the second connection point P. The first end of the sixth response switch M6 is connected to the second end of the third response switch M3, the second end of the sixth response switch M6 is connected to the first end of the third response switch M3, and the control end of the sixth response switch M6 is connected to the third connection point D. The first end of the seventh response switch M7 is connected to the second low level line VSS2, the second end of the seventh response switch M7 is connected to the second connection point P, and the control end of the seventh response switch M7 is connected to the third connection point D.

[0079] The second reset module 230 includes an eighth response switch M8, a first end of the eighth response switch M8 is connected to the second connection point P, a second end of the eighth response switch M8 is connected to the second low level line VSS2, and a control end of the eighth response switch M8 receives a second reset signal to load the second voltage to the second connection point P. The first reset signal and the second reset signal can be the same reset signal RESET, that is, the control end of the third response switch M3 and the control end of the eighth response switch M8 are connected to the same point. They can also be different reset signals RESET, that is, the control end of the third response switch M3 and the control end of the eighth response switch M8 are connected to different points.

[0080] See also Figure 4 As shown, for the working process of the gate driving structure of the present application, combined with the timing diagram, it can be seen that the timing control process is divided into five steps:

[0081] Step I: The input signal INPUT of the previous level unit is at a low level, the first clock signal CLK is at a high level, the first response switch M1 is disconnected, the second connection point P is at a low level, the control end of the second response switch M2 receives a low level voltage, the second response switch M2 is disconnected, and the scan signal OUTPUT is at a low level.

[0082] Step II: the input signal INPUT is at a high level, the first response switch M1 writes the high level of the input signal INPUT into the second connection point P, the second response switch M2 is turned on, the first clock signal CLK is at a low level, and the scan signal OUTPUT is still output at a low level.

[0083] Step III: The first clock signal CLK is at a high level. Under the coupling effect of the capacitor C, the level of the second connection point P is further pulled up. At this time, the output capacity of the second response switch M2 increases, and the scanning signal OUTPUT outputs a high level.

[0084] Step IV: The first reset signal and the second reset signal are both high level, the third response switch M3 and the eighth response switch M8 are both turned on, the first low potential line loads the first voltage to the first connection point U, the second low potential line loads the second voltage to the second connection point P, and the scan signal OUTPUT outputs a low level.

[0085] Step V: The input signal INPUT is at a low level, the second connection point P is always at a low level, the third connection point D is at a high level, the sixth response switch M6 and the seventh response switch M7 are turned on, the second voltage continuously acts on the second connection point P, the first voltage continuously acts on the first connection point U, and the scan signal OUTPUT is maintained at a low level.

[0086] In the present application, there are at least two situations for disposing the first thin film transistor 310 and the second thin film transistor 320 .

[0087] In the first case, the charging module 210, the pull-up module 240, the pull-down module 250, the first reset module 220 and the second reset module 230 are respectively provided with the first thin film transistor 310. That is to say, at this time, the first response switch M1, the third response switch M3, the fourth response switch M4, the fifth response switch M5, the sixth response switch M6, the seventh response switch M7 and the eighth response switch M8 are all the first thin film transistor 310, and the second response switch M2 is the second thin film transistor 320.

[0088] For the first case, it can be seen that the charging module 210, the pull-up module 240, the pull-down module 250, the first reset module 220 and the second reset module 230 have lower leakage current, which can make the pull-down module 250 in a relatively stable working state, and the gate drive structure can work stably even in a high temperature environment, thereby improving the reliability of the work. At the same time, the output module 100 can obtain a larger on-state current through the setting of the second thin film transistor 320, reduce the width of the second thin film transistor 320 itself, and facilitate the realization of a narrow frame.

[0089] In the second case, the charging module 210, the pull-down module 250, the first reset module 220 and the second reset module 230 are respectively provided with the first thin film transistor 310, and the pull-up module 240 is provided with the second thin film transistor 320. That is to say, at this time, the first response switch M1, the third response switch M3, the fourth response switch M4, the fifth response switch M5, the sixth response switch M6, the seventh response switch M7 and the eighth response switch M8 are all first thin film transistors 310. The second response switch M2 and the fourth response switch M4 are second thin film transistors 320.

[0090] For the second case, by setting the first thin film transistor 310 in the charging module 210, the pull-down module 250, the first reset module 220 and the second reset module 230, it is possible to have a lower leakage current, and the pull-down module 250 can be in a relatively stable working state, thereby improving the reliability of the gate drive structure working in a high temperature environment. At the same time, in addition, by setting the second thin film transistor 320 in the pull-up module 240 and the output module 100, a larger on-state current can be obtained, further reducing the width of the position occupied by the gate drive structure, which is conducive to the structural design of a narrow frame.

[0091] Embodiment 2

[0092] See also Figure 5 As shown, the present application also provides a display device, the display device has a display area 910 and a non-display area 920, the non-display area 920 is arranged around the display area 910, and the display device includes the gate driving structure as described above, and the gate driving structure is arranged in the non-display area 920. Setting the gate driving structure in the non-display area 920 can avoid affecting the picture of the display area 910.

[0093] For other specific implementations and beneficial effects of the display device, please refer to the above-mentioned gate driving structure solution, which will not be described in detail here.

[0094] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary technical means in the art that are not disclosed in the present application.

[0095] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A gate driving structure, characterized in that: The gate driving structure includes an output module, and the output module is connected to the output line; The gate driving structure further comprises a plurality of functional modules, at least some of which are connected to the output line, and the functional modules cooperate with the output module to form a scanning signal; At least one of the functional modules includes a first thin film transistor, and the first thin film transistor includes: a first semiconductor layer; a first source-drain electrode layer, wherein the first source-drain electrode layer comprises a first source electrode layer and a first drain electrode layer, and the first source electrode layer and the first drain electrode layer are arranged above the first semiconductor layer; A first buffer layer is provided between the first source layer and the first semiconductor layer, and between the first drain layer and the first semiconductor layer. The first buffer layer is a composite metal layer. The composite metal layer is used to reduce leakage current of the first thin film transistor.

2. The gate driving structure according to claim 1, characterized in that: The gate driving structure further includes an organic layer, and the organic layer is arranged above the first source and drain electrode layer.

3. The gate driving structure according to claim 2, characterized in that: A channel region is formed between the first source electrode layer and the first drain electrode layer, and the organic layer at least covers the channel region.

4. The gate driving structure according to claim 2, characterized in that: The organic layer is at least one of a red color resist layer, a green color resist layer, and a blue color resist layer.

5. The gate driving structure according to claim 1, characterized in that: The first buffer layer includes at least two metals selected from the group consisting of molybdenum, titanium, aluminum, tantalum, nickel and neodymium.

6. The gate driving structure according to any one of claims 1 to 5, characterized in that: The output module includes a second thin film transistor, which is disposed in the same layer as the first thin film transistor, and the second thin film transistor includes: a second semiconductor layer; a second source-drain electrode layer, the second source-drain electrode layer comprising a second source electrode layer and a second drain electrode layer, the second source electrode layer and the second drain electrode layer being arranged above the second semiconductor layer; A second buffer layer, wherein the second buffer layer is disposed between the second source layer and the second semiconductor layer, and between the second drain layer and the second semiconductor layer, and the second buffer layer is a single metal layer, and the on-state current of the second thin film transistor is increased based on the single metal layer.

7. The gate driving structure according to claim 6, characterized in that: The second buffer layer is a metal selected from the group consisting of molybdenum, titanium, aluminum, tantalum, nickel and neodymium.

8. The gate driving structure according to claim 6, characterized in that: The gate driving structure further includes a first insulating layer and a second insulating layer; The first thin film transistor includes a first gate layer, the first insulating layer is arranged between the first gate layer and the first semiconductor layer, and the second insulating layer covers the surface of the first source and drain layer; The second thin film transistor further includes a second gate layer, the first insulating layer extends between the second semiconductor layer and the second gate layer, and the second insulating layer extends to the second source and drain electrode layer and covers the second source and drain electrode layer; The gate driving structure further includes a planar layer, which is disposed above the first thin film transistor and extends to the second thin film transistor and covers the second insulating layer.

9. The gate driving structure according to claim 6, characterized in that: The functional modules are respectively a charging module, a pull-up module, a pull-down module, a first reset module, a second reset module and a capacitor, the capacitor comprises a first electrode plate and a second electrode plate arranged opposite to each other, and the capacitor is arranged on the output line; The charging module is connected to the first electrode plate, the first reset module is connected to the first electrode plate, the second reset module is connected to the second electrode plate, the pull-up module is connected to the pull-down module, and the pull-down module is connected to the first reset module and the second reset module; The first thin film transistor is respectively provided in the charging module, the pull-up module, the pull-down module, the first reset module and the second reset module, or the first thin film transistor is respectively provided in the charging module, the pull-down module, the first reset module and the second reset module, and the second thin film transistor is provided in the pull-up module.

10. A display device, characterized in that: The display device has a display area and a non-display area, wherein the non-display area is arranged around the display area. The display device comprises the gate driving structure according to any one of claims 1 to 9, wherein the gate driving structure is arranged in the non-display area.

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