Efficient current sharing method and device for power supply system and storage medium

Abstract

The invention discloses an efficient current sharing method and device for a power supply system and a storage medium, and the method comprises the steps: setting an RAM unit in each power supply device, and loading a corresponding relation table and a plurality of pieces of actual operation data into the RAM units when the power supply devices are started; therefore, the FPGA optical fiber communication module can have the capability of obtaining actual operation data from the operation ADC data acquired by the data sampling module, so that the time spent on data preprocessing of the control module can be reduced, the overall data processing data of the control module is improved, the matching with the high-speed communication rate of an optical fiber communication link is realized, and the communication efficiency of the optical fiber communication link is improved. And the response rate is improved on the whole, and the dynamic characteristics of a large number of power supply devices during parallel operation are better ensured.

Description

Technical Field

[0001] The present application relates to the field of power supplies, and in particular to a method, device and storage medium for efficient current balancing in a power supply system. Background Art

[0002] Power supplies are usually connected in parallel to provide a greater output, and current sharing is an important step in the parallel process. In order to achieve current sharing, the current general practice is: the user specifies a power supply as the master, and the other power supplies are controlled by the master as slaves. The master needs to collect the current of each slave, and then sum and average it as the slave setting and send it to each slave. The whole process has the problem of slow response. Summary of the invention

[0003] The present application aims to propose a method, device and storage medium for efficient current balancing of a power supply system, thereby improving the response efficiency during power parallel connection.

[0004] According to the efficient current equalization method for a power supply system of the first aspect of the present application, the power supply system includes a plurality of power supply devices that need to be paralleled, and each of the power supply devices includes a control module, an FPGA fiber optic communication module, and a power supply actuator connected in sequence; each of the FPGA fiber optic communication modules is equipped with a sampling module, and the sampling module is used to collect the operation ADC data output by the corresponding power supply device; each of the FPGA fiber optic communication modules is configured with a RAM unit, and when each of the power supply devices is started, the control module loads a correspondence table and a plurality of actual operation data into the RAM unit; the control module stores a plurality of correspondence tables corresponding to the plurality of power supply devices, and each of the correspondence tables represents a plurality of actual operation data corresponding to the power supply device and a plurality of The corresponding relationship between the running ADC data; the FPGA optical fiber communication module has a first optical fiber transmitting end, a first optical fiber receiving end, a second optical fiber transmitting end and a second optical fiber receiving end; the power actuator is used to output voltage and current according to the power output setting parameters; multiple power supply devices are cyclically set in sequence through the FPGA optical fiber communication module, multiple FPGA optical fiber communication modules are connected in series in sequence through the first optical fiber transmitting end and the first optical fiber receiving end to form a first ring communication link, and multiple FPGA optical fiber communication modules are connected in series in sequence through the second optical fiber transmitting end and the second optical fiber receiving end to form a second ring communication link, and the signal transmission direction of the second ring communication link is opposite to that of the first ring communication link; each FPGA optical fiber communication module is configured as a full-duplex communication module; The power system efficient current balancing method is applied to the power supply device as a host, and the power supply devices other than the host in the power system are slaves. The power system efficient current balancing method includes: Acquire current sharing information, the current sharing information including a set voltage and a set current; the set current is obtained according to the actual operation data output by the host, the actual operation data is obtained by the FPGA optical fiber communication module of the host collecting the operation ADC data of the host through the corresponding relationship table and the sampling module; the set voltage is obtained according to the user preset voltage and the preset voltage increment; At each preset power control cycle, a host setting frame is generated according to the current sharing information, and the host setting frame is transmitted to each of the slaves through the first ring communication link, so that each of the slaves adjusts the voltage and current according to the current sharing information; At each interval of the preset power control cycle, the actual operation data of each slave machine stored in the preset cache area in the control module is obtained, and the actual operation data of multiple slave machines are transmitted to the preset cache area in the control module of the host through the second ring communication link.

[0005] According to the efficient current equalization method for a power supply system of the second aspect of the embodiment of the present application, the power supply system includes a plurality of power supply devices that need to be paralleled, and each of the power supply devices includes a control module, an FPGA fiber optic communication module, and a power supply actuator connected in sequence; each of the FPGA fiber optic communication modules is equipped with a sampling module, and the sampling module is used to collect the operation ADC data output by the corresponding power supply device; each of the FPGA fiber optic communication modules is configured with a RAM unit, and when each of the power supply devices is started, the control module loads a correspondence table and a plurality of actual operation data into the RAM unit; the control module stores a plurality of correspondence tables corresponding to the plurality of power supply devices, and each of the correspondence tables represents a plurality of actual operation data corresponding to the power supply device and a plurality of The corresponding relationship between the running ADC data; the FPGA optical fiber communication module has a first optical fiber transmitting end, a first optical fiber receiving end, a second optical fiber transmitting end and a second optical fiber receiving end, and the power actuator is used to output voltage and current according to the power output setting parameters; multiple power supply devices are cyclically set in sequence through the FPGA optical fiber communication module, multiple FPGA optical fiber communication modules are connected in series in sequence through the first optical fiber transmitting end and the first optical fiber receiving end to form a first ring communication link, and multiple FPGA optical fiber communication modules are connected in series in sequence through the second optical fiber transmitting end and the second optical fiber receiving end to form a second ring communication link, and the signal transmission direction of the second ring communication link is opposite to that of the first ring communication link; each FPGA optical fiber communication module is configured as a full-duplex communication module; The power system efficient current balancing method is applied to any power supply device as a slave, one of the power supply devices is selected as a master in the power system, and all the power supply devices except the master are used as slaves. The power system efficient current balancing method includes: At each preset power control cycle, a host setting frame stored in a preset buffer area in the control module and transmitted by the power supply device at the last position in the first ring communication link is obtained, wherein the host setting frame is generated by the host according to the current sharing information and sent through the first ring communication link; the current sharing information includes a setting voltage and a setting current, wherein the setting current is obtained according to the actual operation data output by the host, and the actual operation data is obtained by the FPGA optical fiber communication module of the host collecting the operation ADC data of the host through the corresponding relationship table and the sampling module; the setting voltage is obtained according to a preset voltage increment and a user preset voltage input by the user through the host; completing voltage adjustment according to the set voltage; completing current adjustment according to the set current; At each interval of the preset power control cycle, the actual operation data stored in the preset cache area in the control module is obtained, and the actual operation data is filled into the corresponding record segment in the slave upload frame, and then the slave upload frame is transmitted to the next power supply device through the second ring communication link; the slave upload frame includes multiple record segments corresponding to multiple slaves, and each record segment is used to write the actual operation data corresponding to the slave.

[0006] According to the power supply system high-efficiency current equalization device of the third aspect embodiment of the present application, the power supply system includes a plurality of power supply devices that need to be paralleled, and each of the power supply devices includes a control module, an FPGA fiber optic communication module, and a power supply actuator connected in sequence; each of the FPGA fiber optic communication modules is equipped with a sampling module, and the sampling module is used to collect the operation ADC data output by the corresponding power supply device; each of the FPGA fiber optic communication modules is configured with a RAM unit, and when each of the power supply devices is started, the control module loads a correspondence table and a plurality of actual operation data into the RAM unit; the control module stores a plurality of correspondence tables corresponding to the plurality of power supply devices, and each of the correspondence tables represents a plurality of actual operation data corresponding to the power supply device and a plurality of The corresponding relationship between the running ADC data; the FPGA optical fiber communication module has a first optical fiber transmitting end, a first optical fiber receiving end, a second optical fiber transmitting end and a second optical fiber receiving end; the power actuator is used to output voltage and current according to the power output setting parameters; multiple power supply devices are cyclically set in sequence through the FPGA optical fiber communication module, multiple FPGA optical fiber communication modules are connected in series in sequence through the first optical fiber transmitting end and the first optical fiber receiving end to form a first ring communication link, and multiple FPGA optical fiber communication modules are connected in series in sequence through the second optical fiber transmitting end and the second optical fiber receiving end to form a second ring communication link, and the signal transmission direction of the second ring communication link is opposite to that of the first ring communication link; each FPGA optical fiber communication module is configured as a full-duplex communication module; The power system high-efficiency current balancing device is applied to the power supply device as the host, and the power supply devices other than the host in the power system are slaves. The power system high-efficiency current balancing device includes: A current sharing information acquisition module, used to acquire current sharing information, wherein the current sharing information includes a set voltage and a set current; the set current is obtained according to the actual operation data output by the host, and the actual operation data is obtained by the FPGA optical fiber communication module of the host collecting the operation ADC data of the host through the corresponding relationship table and the sampling module; the set voltage is obtained according to the user preset voltage and the preset voltage increment; A data output module is provided, which is used to generate a host setting frame according to the current sharing information at each preset power control cycle, and transmit the host setting frame to each of the slaves through the first ring communication link, so that each of the slaves adjusts the voltage and current according to the current sharing information; The upload data receiving module is used to obtain the actual operation data of each slave machine stored in the preset cache area in the control module at each interval of the preset power control cycle, and the actual operation data of multiple slave machines are transmitted to the preset cache area in the control module of the host through the second ring communication link.

[0007] According to the fourth aspect of the embodiment of the present application, the power supply system includes a plurality of power supply devices that need to be connected in parallel, and each of the power supply devices includes a control module, an FPGA fiber optic communication module, and a power supply actuator connected in sequence; each of the FPGA fiber optic communication modules is equipped with a sampling module, and the sampling module is used to collect the operation ADC data output by the corresponding power supply device; each of the FPGA fiber optic communication modules is configured with a RAM unit, and when each of the power supply devices is started, the control module loads a correspondence table and multiple actual operation data into the RAM unit; the control module stores multiple correspondence tables corresponding to the multiple power supply devices, and each of the correspondence tables represents the multiple actual operation data corresponding to the power supply device and multiple The corresponding relationship between the running ADC data; the FPGA optical fiber communication module has a first optical fiber transmitting end, a first optical fiber receiving end, a second optical fiber transmitting end and a second optical fiber receiving end, and the power actuator is used to output voltage and current according to the power output setting parameters; multiple power supply devices are cyclically set in sequence through the FPGA optical fiber communication module, multiple FPGA optical fiber communication modules are connected in series in sequence through the first optical fiber transmitting end and the first optical fiber receiving end to form a first ring communication link, and multiple FPGA optical fiber communication modules are connected in series in sequence through the second optical fiber transmitting end and the second optical fiber receiving end to form a second ring communication link, and the signal transmission direction of the second ring communication link is opposite to that of the first ring communication link; each FPGA optical fiber communication module is configured as a full-duplex communication module; The power system high-efficiency current balancing device is applied to any power supply device as a slave, one of the power supply devices is selected as a master in the power system, and all the power supply devices except the master are used as slaves, and the power system high-efficiency current balancing device includes: A setting data acquisition module is used to obtain, at each preset power control cycle interval, a host setting frame transmitted by the power supply device at the last position in the first ring communication link to the preset buffer area in the control module, wherein the host setting frame is generated by the host according to the current sharing information and sent through the first ring communication link; the current sharing information includes a setting voltage and a setting current, wherein the setting current is obtained according to the actual operation data output by the host, and the actual operation data is obtained by the FPGA optical fiber communication module of the host collecting the operation ADC data of the host through the corresponding relationship table and the sampling module; the setting voltage is obtained according to the preset voltage increment and the user preset voltage input by the user through the host; A voltage adjustment module, used to complete voltage adjustment according to the set voltage; A current adjustment module, used to complete current adjustment according to the set current; The upload data output module is used to obtain the actual operation data stored in the preset cache area in the control module at each interval of the preset power control cycle, and fill the actual operation data into the corresponding record segment in the slave upload frame, and then transmit the slave upload frame to the next power supply device through the second ring communication link; the slave upload frame includes multiple record segments corresponding to multiple slaves, and each record segment is used to write the actual operation data of the corresponding slave.

[0008] According to the computer-readable storage medium of the fifth aspect embodiment of the present application, computer executable instructions are stored, and the computer executable instructions are used to execute the high-efficiency current equalization method for the power supply system as described in the first aspect embodiment above.

[0009] The power system efficient current balancing method, device and storage medium of the present application, by setting a RAM unit in each power supply device, and loading the corresponding relationship table and multiple actual operation data into the RAM unit when the power supply device is started, enables the FPGA fiber optic communication module to have the ability to obtain the actual operation data from the operation ADC data collected by the data sampling module, thereby reducing the time required for data preprocessing of the control module, thereby improving the overall data processing data of the control module, achieving matching with the high-speed communication rate of the fiber optic communication link, improving the response rate as a whole, and better ensuring the dynamic characteristics when a large number of power supply devices are connected in parallel.

[0010] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or may be understood by practicing the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A schematic diagram of the structure of a power supply system provided in one embodiment of the present application; Figure 2 A flow chart of a method for efficiently balancing current in a power supply system provided in one embodiment of the present application; Figure 3 A flow chart of a method for efficiently balancing current in a power supply system provided by another embodiment of the present application; Figure 4 A schematic diagram of the structure of a high-efficiency current balancing device for a power supply system provided in one embodiment of the present application; Figure 5 A schematic structural diagram of a high-efficiency current balancing device for a power supply system provided in another embodiment of the present application. DETAILED DESCRIPTION

[0012] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0013] In the description of this application, if there is a description of first, second, etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0014] In the description of the present application, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0015] In the description of this application, it should be noted that, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meaning of the above terms in this application based on the specific content of the technical solution.

[0016] The technical solution of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described below are only part of the embodiments of the present application, not all of the embodiments.

[0017] In order to better describe the power system efficient current balancing method, device and storage medium of the embodiment of the present invention, a power system is proposed here, such as Figure 1As shown, the system includes a plurality of power supply devices to be paralleled, each power supply device includes a control module, an FPGA (Field Programmable Gate Array) optical fiber communication module, and a power supply actuator connected in sequence; each FPGA optical fiber communication module is built with a sampling module, and the sampling module is used to collect the operation ADC (Analog to Digital Converter) data output by the corresponding power supply device; each FPGA optical fiber communication module is configured with a RAM (Random Access Memor) unit, and each power supply device is loaded with a corresponding relationship table and a plurality of actual operation data to the RAM unit through the control module when it is started; the control module stores a plurality of corresponding relationship tables corresponding to the plurality of power supply devices, and each corresponding relationship table represents the corresponding relationship between the plurality of actual operation data of the corresponding power supply device and the plurality of operation ADC data; the FPGA optical fiber communication module has a first optical fiber transmitting end, a first optical fiber receiving end, a second optical fiber transmitting end, and a second optical fiber receiving end; the power supply actuator is used to output voltage and current according to the power supply output setting parameters; the plurality of power supply devices are set in a cycle in sequence through the FPGA optical fiber communication module, and the plurality of FPGA optical fiber communication modules are connected in series in sequence through the first optical fiber transmitting end and the first optical fiber receiving end to form a first ring communication link (such as Figure 1 LINK1), multiple FPGA optical fiber communication modules are connected in series in sequence through the second optical fiber transmitting end and the second optical fiber receiving end to form a second ring communication link (as shown in FIG. Figure 1 As shown in LINK2), the signal transmission directions of the second ring communication link and the first ring communication link are opposite; each FPGA optical fiber communication module is configured as a full-duplex communication module.

[0018] The above power output setting parameters may include voltage parameters and current parameters, and the power actuator may be used to adjust the output voltage and output current of the power supply device after receiving the voltage parameters and current parameters. Specifically, in the process of parallel connection of multiple power supply devices, the power supply device as the host may send current sharing information to the slave device, and the slave device may obtain the setting current and setting voltage by parsing the current sharing information, and then use the setting current and setting voltage to complete the adjustment of the slave device output.

[0019] Only one of the above-mentioned hosts is set in the power supply system, and the other power supply devices not selected as hosts serve as slaves.

[0020] Each of the above-mentioned power supply devices includes an FPGA optical fiber communication module. The FPGA optical fiber communication module is constructed with FPGA as a core module. RAM units can be constructed in the FPGA, and data storage can be completed using the RAM units.

[0021] The above-mentioned FPGA optical fiber communication module includes a sampling module, and the sampling module can be used to complete the collection of ADC data such as voltage and current at the output end of the power supply device.

[0022] Specifically, the sampling module can use a 16-bit ADC chip, or a higher-precision or lower-precision ADC chip according to actual needs.

[0023] The above-mentioned operation ADC data directly collects the current data and voltage data of the output end of the power supply device, and there are certain collection errors. In order to eliminate the collection errors, it is usually necessary to calibrate the collected operation ADC data using a calibration coefficient. However, if this calibration process is completed using a control module, due to the high sampling frequency, it will inevitably consume a lot of computing power of the control module. If it is implemented by FPGA, it is difficult for FPGA to implement this complex logical calculation process. In this embodiment, a method of predetermining the corresponding operation actual data of each operation ADC data is adopted, that is, the real value corresponding to each sampling value has been predetermined. After a piece of operation ADC data is collected by the sampling module, the operation ADC data can be directly used as the address index to find the predetermined operation actual data. Multiple operation actual data corresponding to multiple operation ADC data can be stored in a specific position of the RAM unit for indexing, and the corresponding relationship table used for indexing can also be predetermined.

[0024] After each power failure, the data stored in the above-mentioned RAM unit will be lost. Therefore, the multiple actual operation data and corresponding relationship tables corresponding to each power supply device will be stored in the control module. Each time the power supply device is powered on, the multiple actual operation data and corresponding relationship tables will be written into a fixed position in the RAM unit through the control module.

[0025] The above-mentioned multiple operating ADC data and multiple actual operating data can be determined before the power supply device is officially put into use, for example, they can be determined directly before leaving the factory, and the multiple actual operating data and the corresponding relationship table are stored in the control module.

[0026] The above-mentioned first ring communication link can be understood as a loop for host data downlink. When the host power supply device needs to transmit data to each slave, it will write key information such as setting current, setting voltage, and startup instructions into the host setting frame, and then transmit it to each slave in turn through the first ring communication link.

[0027] Specifically, the first position of the first ring communication link can be understood as the host, and from the next position to the last position are slaves. The communication process of the first ring communication link will be carried out in a ring form. Taking the current sharing information as an example, the current sharing information in the host setting frame will be first transmitted to the second-ranked slave. The second-ranked slave obtains the current sharing information from the host setting frame and transmits the host setting frame to the third-ranked slave, and repeats the above-mentioned process of obtaining the current sharing information and the forwarding process until the host setting frame is transmitted to the last slave.

[0028] The second ring communication link can be understood as a loop for uploading slave data. The power supply device of the host needs to determine the operating status of each slave in a timely manner. The actual operating data of each slave can be obtained through the corresponding FPGA optical fiber communication module. Then, after receiving the slave upload frame, the actual operating data is stored in the corresponding record segment in the slave upload frame. Each slave will have a corresponding record segment in the slave upload frame.

[0029] Specifically, the communication direction of the second ring communication link is opposite to that of the first ring communication link. The host is the first in the first ring communication link and the last in the second ring communication link. The slave in the first position in the second ring communication link needs to generate a slave upload frame, and write its own actual running data into the slave upload frame, and then upload the slave upload frame to the next slave, and then the slave completes the writing of the actual running data to the slave upload frame, and transmits the slave upload frame to the next slave, until all slaves complete the writing of the actual running data to the slave upload frame data, and finally transmit it to the host.

[0030] A preset cache area will be set in the above-mentioned control module. The host setting frame sent by the host can be stored in the preset cache area of ​​the slave, and the slave upload frame uploaded by the slave can be stored in the preset cache area of ​​the host. At the same time, all power supply devices can store the actual operating data obtained by the FPGA fiber optic communication module in the preset cache area.

[0031] Based on the above power supply system, the power supply parallel synchronous output control method, device and storage medium according to the embodiment of the present invention are described below.

[0032] See also Figure 2 As shown, Figure 2 This is a flow chart of a power system efficient current balancing method provided by an embodiment of the present application. The power system efficient current balancing method is applied to a control module in a power supply device as a host. The power system efficient current balancing method includes: Obtaining current sharing information, which includes setting voltage and setting current; setting current is obtained according to actual operation data output by the host, and the actual operation data is obtained by the host's FPGA optical fiber communication module collecting the host's operation ADC data through the corresponding relationship table and the sampling module; setting voltage is obtained according to the user's preset voltage and preset voltage increment; At each preset power control cycle, a host setting frame is generated according to the current sharing information, and the host setting frame is transmitted to each slave through the first ring communication link, so that each slave performs voltage adjustment and current adjustment according to the current sharing information; At each preset power control cycle, actual operation data of each slave stored in a preset buffer area in the control module is obtained, and the actual operation data of multiple slaves are transmitted to the preset buffer area in the control module of the host through the second ring communication link.

[0033] In this embodiment, by setting a RAM unit in each power supply device and loading the corresponding relationship table and multiple actual operation data into the RAM unit when the power supply device is started, the FPGA fiber optic communication module can have the ability to obtain the actual operation data from the operation ADC data collected by the data sampling module, thereby reducing the time required for data preprocessing of the control module, thereby improving the overall data processing data of the control module, achieving matching with the high-speed communication rate of the fiber optic communication link, and improving the overall response rate, and better ensuring the dynamic characteristics when a large number of power supply devices are connected in parallel.

[0034] The above-mentioned setting current can be continuously obtained through the FPGA optical fiber communication module of the host.

[0035] The above-mentioned set voltage can be obtained by the user's operation on the power supply operation interface. The user enters the user preset voltage through the power supply operation interface. At the same time, in order to ensure that the slave operates in the current loop, a preset voltage increment will be added to the user preset voltage. The preset voltage increment can be set to a fixed value, for example, it can be set to 1V, or the amplitude can be adjusted as needed.

[0036] The above-mentioned host and slave can continuously collect actual operation data through their corresponding FPGA optical fiber communication modules, and can store the actual operation data in a preset buffer area in the control module.

[0037] The above-mentioned host setting frame is generated according to the current sharing information. The generated host setting frame can be transmitted to each slave in turn through the first ring communication link. Each slave will store the host setting frame in a preset buffer area, and after the end of this cycle, use the current sharing information stored in the preset buffer area to complete voltage adjustment and current adjustment.

[0038] Specifically, the host setting frame consists of a frame header, a device ID, an event, a voltage, a current, a checksum, and a frame tail. The meaning of each part can be referred to as follows: Frame header: Use special characters. In order to prevent the possibility of duplication with subsequent voltage and current values, NaN values ​​can be used, such as consecutive 0xDEADBEEF and 0xDEADBEEF. Device ID: The device ID value set by the user. Fill in the device ID when sending. For example, the host ID can be fixed to 0, and the slave ID is 1~N, where N represents the Nth slave. Event: Start command; the start command can indicate whether the output needs to be started or turned off. After receiving the host setting frame, the slave needs to judge the event in the host setting frame. When the slave indicates to turn off the output, it can directly turn off the output without the need to adjust the voltage or current.

[0039] Voltage: indicates the set voltage sent by the host to all slaves; Current: indicates the set current sent by the host to all slaves; Verification: All data in this data frame (except itself) are verified, and CRC16 can be used; Frame tail: Special characters are used. In order to prevent the possibility of duplication with subsequent voltage and current values, NaN values ​​can be used. In order to facilitate the positioning of data frames, it is inconsistent with the frame header, such as continuous 0x55AA55AA, 0x55AA55AA.

[0040] The preset buffer area of ​​the above slaves will store the actual operation data continuously collected by each slave through the FPGA optical fiber communication module. When each slave generates or receives a slave upload frame, it will write the actual operation data into the slave upload frame and transmit it to the next slave using the second ring communication link until the writing of the actual operation data of all slaves is completed and finally transmitted to the host. The host will write the actual operation data corresponding to the host into the slave upload frame and store the slave upload frame in the preset buffer area of ​​the host. The slave upload frame can also be generated and uploaded in cycles.

[0041] The above-mentioned host setting frame downlink and slave upload frame generation and upload are performed periodically. Specifically, they can be performed once at intervals of a preset power control cycle, so that within each preset power control cycle, the data of the host setting frame can be transmitted to each slave, and the data update in the slave setting frame can also be uploaded to the host within the preset power control cycle.

[0042] Specifically, the structure of the slave upload frame includes the frame header, host A status data, slave B status data, slave C status data, checksum and frame tail, and the structure of host A status data, slave B status data and slave C status data includes device ID, event, voltage and current. The meaning of each part can be referred to as follows: Frame header: Use special characters. In order to prevent the possibility of duplication with subsequent voltage and current values, NaN values ​​can be used, such as consecutive 0xDEADBEEF and 0xDEADBEEF. Device ID: The device ID value set by the user. Fill in the device ID when sending. For example, the host ID is fixed to 0, and the slave ID is 1~N, where N represents the Nth slave. Event: indicates various status and fault prompt information of the slave; Voltage: indicates the actual voltage sampling of the slave; Current: indicates the actual current sampling of the slave; Verification: All data in this data frame (except itself) are verified, and CRC16 can be used; Frame tail: Special characters are used. In order to prevent the possibility of duplication with subsequent voltage and current values, NaN values ​​can be used. In order to facilitate the positioning of data frames, it is inconsistent with the frame header, such as continuous 0x55AA55AA, 0x55AA55AA.

[0043] The above-mentioned preset power control period is set according to actual conditions, and the preset power control period can also be adjusted according to actual needs. For example, it can be set to 20us or 50us.

[0044] In some embodiments, each operating ADC data includes operating ADC current data and operating ADC voltage data, each operating actual data includes operating actual current data and operating actual voltage data, each RAM unit includes a RAM current unit and a RAM voltage unit, and the corresponding relationship table corresponding to each power supply device includes a current corresponding sub-table corresponding to the RAM current unit and a voltage corresponding sub-table corresponding to the RAM voltage unit. The current corresponding sub-table corresponds to the correspondence between multiple operating actual current data of the power supply device and multiple operating ADC current data, and the voltage corresponding sub-table corresponds to the correspondence between multiple operating actual voltage data of the power supply device and multiple operating ADC voltage data.

[0045] In this embodiment, the RAM unit is divided into a RAM current unit and a RAM voltage unit, so that the actual operating current data and the actual operating voltage data can be stored respectively, and then the current corresponding sub-table and the voltage corresponding sub-table can be used to index the operating ADC current data and the operating ADC voltage data respectively, thereby improving the indexing efficiency.

[0046] In some embodiments, setting the current is obtained by the following steps: The actual operating current data output by the host is obtained through the FPGA optical fiber communication module of the host; The actual operating current data of the host is divided according to the number of power supply devices in the power supply system to obtain the set current.

[0047] In this embodiment, considering that the power supply system is a parallel system, the current output from the host output end can be directly collected, and the actual operating current data can be quickly determined based on the collected operating ADC current data. The control module can then perform a division operation to quickly determine the set current.

[0048] In some embodiments, the actual operating current data is obtained by the following steps: Acquire the operating ADC current data output by the power supply device through the sampling module; According to the corresponding current corresponding sub-table, the actual operating current data is obtained from the RAM current unit by taking the operating ADC current data as an index.

[0049] In this implementation manner, after the sampling module collects the operating ADC current data output by the power supply device, the corresponding operating actual current data can be directly determined in the RAM current unit using the operating ADC current data as an index.

[0050] In some implementations, the actual operating current data is sequentially stored in the RAM current unit according to the size of the corresponding operating ADC current data, so as to facilitate fast indexing.

[0051] In some embodiments, the actual operating current data is obtained by the following steps: Acquire the operating ADC voltage data output by the power supply device through the sampling module; According to the corresponding voltage corresponding sub-table, the actual operating voltage data is obtained from the RAM current unit using the operating ADC voltage data as an index.

[0052] In this implementation manner, after the sampling module collects the operating ADC voltage data output by the power supply device, the corresponding operating actual voltage data can be directly determined in the RAM current unit using the operating ADC voltage data as an index.

[0053] In some implementations, the actual operating voltage data is stored in the RAM voltage unit in order according to the size of the corresponding operating ADC voltage data, so as to facilitate fast indexing.

[0054] In some implementations, the power system high-efficiency current sharing method further includes: If the actual operation data of the slave machine transmitted by the second ring communication link from the slave machine adjacent to the master machine is not received within the first preset receiving time length, the first communication fault alarm information is generated.

[0055] In this embodiment, considering that the second ring communication link is a ring link and the second ring communication link transmits data in a certain order, the host can quickly determine that a communication failure has occurred when it is determined that the actual operating data of the slave machine has not been received within the allowed length of the first preset receiving time, that is, the upload frame of the slave machine has not been received, and then generate a first communication failure alarm message to issue an alarm.

[0056] In some implementations, the power system high-efficiency current sharing method further includes: If no slave is detected to transmit actual operation data of the slave via the second ring communication link within the preset update time, the serial number information of the slave whose data has not been updated is recorded, and slave fault alarm information is generated.

[0057] In this implementation, when a slave fails to upload data within the preset update time, it can be determined that the slave has a fault, and the slave number needs to be recorded and slave fault alarm information is generated for alarm.

[0058] See also Figure 3 As shown, Figure 3 This is a flow chart of a power system efficient current balancing method provided by an embodiment of the present application. The power system efficient current balancing method is applied to a control module in a power supply device as a slave. The power system efficient current balancing method includes: At each preset power control cycle, a host setting frame stored in a preset buffer area in the control module and transmitted from the previous power supply device in the first ring communication link is obtained, and the host setting frame is generated by the host according to the current sharing information and sent through the first ring communication link; the current sharing information includes a setting voltage and a setting current, and the setting current is obtained according to the actual operation data output by the host, and the actual operation data is obtained by the FPGA optical fiber communication module of the host through the corresponding relationship table and the sampling module to collect the operation ADC data of the host; the setting voltage is obtained according to the preset voltage increment and the user preset voltage input by the user through the host; Complete voltage adjustment according to the set voltage; Complete current adjustment according to the set current; At each preset power control cycle, the actual operation data stored in the preset buffer area in the control module is obtained, and the actual operation data is filled into the corresponding record segment in the slave upload frame, and then the slave upload frame is transmitted to the next power supply device through the second ring communication link; the slave upload frame includes multiple record segments corresponding to multiple slaves, and each record segment is used to write the actual operation data of the corresponding slave.

[0059] The terms such as the host setting frame, slave uploading frame, setting voltage, setting current, preset buffer area, running actual data, running ADC data, etc. have been explained in the above and will not be repeated here.

[0060] The above-mentioned record segment is set in the slave upload frame, each slave has a unique record segment in the slave upload frame, and each record segment has a corresponding storage address, so that the control module completes the index according to the collected running ADC data according to the corresponding relationship table.

[0061] In this embodiment, when each slave receives the host setting frame, it will store the host setting frame or the current sharing information in the host setting frame in a preset buffer area in the control module, and read the current sharing information from the preset buffer area every preset power control cycle, and use the current sharing information to complete the adjustment of current and voltage. In addition, the FPGA optical fiber communication module of the slave will collect the operation ADC data through the sampling module for indexing to obtain the actual operation data. After obtaining the actual operation data, the control module will also store it in the preset buffer area so that the actual operation data can be written into the slave upload frame when it needs to be written.

[0062] In some embodiments, when the slave is at the first position of the second ring communication link, filling the actual operation data into the corresponding record section in the slave upload frame includes: Generate a slave upload frame and fill the actual running data into the corresponding record segment in the slave upload frame.

[0063] In this implementation, the first slave needs to generate a slave upload frame so that it and subsequent slaves and the host can fill data. For the record segments other than the first one, data may not be filled or all filled with 0.

[0064] In some implementations, the power system efficient current sharing method further includes: If the current sharing information transmitted by the host through the second ring communication link is not received within the second preset receiving time allowed length, host fault alarm information is generated.

[0065] In this implementation manner, if the current sharing information is not received, it may mean that the slave has not received the host setting frame sent by the host, so it can be determined that the host has been off-grid, and therefore, it is necessary to generate host fault alarm information for alarm.

[0066] In some real-time modes, if a slave upload frame uploaded by the slave is not received within the third preset receiving time allowable length, it means that a communication link fails, and a second communication failure alarm information can be used to give an alarm.

[0067] In some implementations, current adjustment is performed according to the set current, including: Execute the incremental PID (Proportion Dntegration Differentiation) algorithm on the set current to obtain the current increment; The current output is adjusted based on the current increment and the set current.

[0068] In order to avoid causing output oscillation of the parallel system, an incremental PID algorithm needs to be added to the current output, in which the Kd coefficient can be 0, and the Kp and Ki coefficients are debugged and determined according to the actual parallel situation. The target value of the incremental PID is the set current, and the feedback value is the actual operating current data corresponding to the real-time sampling ADC data of the slave. After the incremental PID operation, the current increment is obtained, and the output current of the slave is adjusted to the current output current of the slave plus the current increment.

[0069] refer to Figure 4 The embodiment of the present application further provides a high-efficiency current balancing device for a power supply system, the high-efficiency current balancing device for a power supply system comprising: A current sharing information acquisition module, used to acquire current sharing information, wherein the current sharing information includes a set voltage and a set current; the set current is obtained according to the actual operation data output by the host, and the actual operation data is obtained by the FPGA optical fiber communication module of the host collecting the operation ADC data of the host through the corresponding relationship table and the sampling module; the set voltage is obtained according to the user preset voltage and the preset voltage increment; A data output module is provided, which is used to generate a host setting frame according to the current sharing information at each preset power control cycle, and transmit the host setting frame to each of the slaves through the first ring communication link, so that each of the slaves adjusts the voltage and current according to the current sharing information; The upload data receiving module is used to obtain the actual operation data of each slave machine stored in the preset cache area in the control module at each interval of the preset power control cycle, and the actual operation data of multiple slave machines are transmitted to the preset cache area in the control module of the host through the second ring communication link.

[0070] refer to Figure 5 The embodiment of the present application further provides a high-efficiency current balancing device for a power supply system, the high-efficiency current balancing device for a power supply system comprising: A setting data acquisition module is used to obtain, at each preset power control cycle interval, a host setting frame transmitted by the power supply device at the last position in the first ring communication link to the preset buffer area in the control module, wherein the host setting frame is generated by the host according to the current sharing information and sent through the first ring communication link; the current sharing information includes a setting voltage and a setting current, wherein the setting current is obtained according to the actual operation data output by the host, and the actual operation data is obtained by the FPGA optical fiber communication module of the host collecting the operation ADC data of the host through the corresponding relationship table and the sampling module; the setting voltage is obtained according to the preset voltage increment and the user preset voltage input by the user through the host; A voltage adjustment module, used to complete voltage adjustment according to the set voltage; A current adjustment module, used to complete current adjustment according to the set current; The upload data output module is used to obtain the actual operation data stored in the preset cache area in the control module at each interval of the preset power control cycle, and fill the actual operation data into the corresponding record segment in the slave upload frame, and then transmit the slave upload frame to the next power supply device through the second ring communication link; the slave upload frame includes multiple record segments corresponding to multiple slaves, and each record segment is used to write the actual operation data of the corresponding slave.

[0071] In addition, an embodiment of the present application also provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are executed by a processor or a control module, so that the above-mentioned processor can execute the power supply system efficient current equalization method in the above-mentioned embodiment, for example, execute the method described above.

[0072] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed methods above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium or a non-transitory medium and a communication medium or a temporary medium. As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk DVD or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0073] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A method for efficiently balancing current in a power supply system, characterized in that: The power supply system includes a plurality of power supply devices to be paralleled, each of which includes a control module, an FPGA optical fiber communication module, and a power supply actuator connected in sequence; each of the FPGA optical fiber communication modules is equipped with a sampling module, which is used to collect the operation ADC data output by the corresponding power supply device; each of the FPGA optical fiber communication modules is equipped with a RAM unit, and each of the power supply devices is loaded with a corresponding relationship table and a plurality of actual operation data into the RAM unit through the control module when starting; The control module stores a plurality of corresponding relationship tables corresponding to the plurality of power supply devices, each of the corresponding relationship tables representing a corresponding relationship between a plurality of the actual operation data corresponding to the power supply device and a plurality of the operation ADC data; The FPGA optical fiber communication module has a first optical fiber transmitting end, a first optical fiber receiving end, a second optical fiber transmitting end, and a second optical fiber receiving end; the power supply actuator is used to output voltage and current according to the power supply output setting parameters; A plurality of the power supply devices are sequentially arranged in a cycle through the FPGA optical fiber communication module, and a plurality of the FPGA optical fiber communication modules are sequentially connected in series through the first optical fiber transmitting end and the first optical fiber receiving end to form a first ring communication link, and a plurality of the FPGA optical fiber communication modules are sequentially connected in series through the second optical fiber transmitting end and the second optical fiber receiving end to form a second ring communication link, and the signal transmission direction of the second ring communication link is opposite to that of the first ring communication link; each of the FPGA optical fiber communication modules is configured as a full-duplex communication module; The power system efficient current balancing method is applied to the power supply device as a host, and the power supply devices other than the host in the power system are slaves. The power system efficient current balancing method includes: Acquire current sharing information, the current sharing information including a set voltage and a set current; the set current is obtained according to the actual operation data output by the host, the actual operation data is obtained by the FPGA optical fiber communication module of the host collecting the operation ADC data of the host through the corresponding relationship table and the sampling module; the set voltage is obtained according to the user preset voltage and the preset voltage increment; At each preset power control cycle, a host setting frame is generated according to the current sharing information, and the host setting frame is transmitted to each of the slaves through the first ring communication link, so that each of the slaves adjusts the voltage and current according to the current sharing information; At each interval of the preset power control cycle, the actual operation data of each slave machine stored in the preset cache area in the control module is obtained, and the actual operation data of multiple slave machines are transmitted to the preset cache area in the control module of the host through the second ring communication link.

2. The high-efficiency current balancing method for a power supply system according to claim 1, characterized in that: Each of the operating ADC data includes operating ADC current data and operating ADC voltage data, each of the actual operating data includes operating actual current data and operating actual voltage data, each of the RAM units includes a RAM current unit and a RAM voltage unit, and the corresponding relationship table corresponding to each of the power supply devices includes a current corresponding sub-table corresponding to the RAM current unit and a voltage corresponding sub-table corresponding to the RAM voltage unit, the current corresponding sub-table corresponds to the correspondence between multiple operating actual current data of the power supply device and multiple operating ADC current data, and the voltage corresponding sub-table corresponds to the correspondence between multiple operating actual voltage data of the power supply device and multiple operating ADC voltage data.

3. The high-efficiency current balancing method for a power supply system according to claim 2, characterized in that: The setting current is obtained by the following steps: Acquiring actual operating current data output by the host through the FPGA optical fiber communication module of the host; The actual operating current data of the host is divided according to the number of power supply devices in the power supply system to obtain the set current.

4. The high-efficiency current balancing method for a power supply system according to claim 2, characterized in that: The actual operating current data is obtained by the following steps: Acquiring the operating ADC current data output by the power supply device through the sampling module; According to the corresponding sub-table of the current, the actual operating current data is obtained from the RAM current unit by taking the operating ADC current data as an index.

5. The high-efficiency current-sharing method for a power supply system according to claim 2, characterized in that: The actual operating current data is obtained by the following steps: Acquiring the operating ADC voltage data output by the power supply device through the sampling module; According to the voltage corresponding sub-table and taking the operating ADC voltage data as an index, the operating actual voltage data is obtained from the RAM current unit.

6. The high-efficiency current balancing method for a power supply system according to claim 2, characterized in that: The power system efficient current sharing method further includes: If the actual operation data of the slave machine transmitted by the slave machine adjacent to the master machine through the second ring communication link is not received within the first preset receiving time allowed length, a first communication fault alarm message is generated.

7. A method for efficiently balancing current in a power supply system, characterized in that: The power supply system includes a plurality of power supply devices to be paralleled, each of which includes a control module, an FPGA optical fiber communication module, and a power supply actuator connected in sequence; each of the FPGA optical fiber communication modules is equipped with a sampling module, which is used to collect the operation ADC data output by the corresponding power supply device; each of the FPGA optical fiber communication modules is equipped with a RAM unit, and each of the power supply devices is loaded with a corresponding relationship table and a plurality of actual operation data into the RAM unit through the control module when starting; The control module stores a plurality of corresponding relationship tables corresponding to the plurality of power supply devices, each of the corresponding relationship tables representing a corresponding relationship between a plurality of the actual operation data corresponding to the power supply device and a plurality of the operation ADC data; The FPGA optical fiber communication module has a first optical fiber transmitting end, a first optical fiber receiving end, a second optical fiber transmitting end, and a second optical fiber receiving end, and the power supply actuator is used to output voltage and current according to power supply output setting parameters; A plurality of the power supply devices are sequentially arranged in a cycle through the FPGA optical fiber communication module, and a plurality of the FPGA optical fiber communication modules are sequentially connected in series through the first optical fiber transmitting end and the first optical fiber receiving end to form a first ring communication link, and a plurality of the FPGA optical fiber communication modules are sequentially connected in series through the second optical fiber transmitting end and the second optical fiber receiving end to form a second ring communication link, and the signal transmission direction of the second ring communication link is opposite to that of the first ring communication link; each of the FPGA optical fiber communication modules is configured as a full-duplex communication module; The power system efficient current balancing method is applied to any power supply device as a slave, one of the power supply devices is selected as a master in the power system, and all the power supply devices except the master are used as slaves. The power system efficient current balancing method includes: At each preset power control cycle, a host setting frame stored in a preset buffer area in the control module and transmitted by the power supply device at the last position in the first ring communication link is obtained, wherein the host setting frame is generated by the host according to the current sharing information and sent through the first ring communication link; the current sharing information includes a setting voltage and a setting current, wherein the setting current is obtained according to the actual operation data output by the host, and the actual operation data is obtained by the FPGA optical fiber communication module of the host collecting the operation ADC data of the host through the corresponding relationship table and the sampling module; the setting voltage is obtained according to a preset voltage increment and a user preset voltage input by the user through the host; completing voltage adjustment according to the set voltage; completing current adjustment according to the set current; At each interval of the preset power control cycle, the actual operation data stored in the preset cache area in the control module is obtained, and the actual operation data is filled into the corresponding record segment in the slave upload frame, and then the slave upload frame is transmitted to the next power supply device through the second ring communication link; the slave upload frame includes multiple record segments corresponding to multiple slaves, and each record segment is used to write the actual operation data corresponding to the slave.

8. A high-efficiency current balancing device for a power supply system, characterized in that: The power supply system includes a plurality of power supply devices to be paralleled, each of which includes a control module, an FPGA optical fiber communication module, and a power supply actuator connected in sequence; each of the FPGA optical fiber communication modules is equipped with a sampling module, which is used to collect the operation ADC data output by the corresponding power supply device; each of the FPGA optical fiber communication modules is equipped with a RAM unit, and each of the power supply devices is loaded with a corresponding relationship table and a plurality of actual operation data into the RAM unit through the control module when starting; The control module stores a plurality of corresponding relationship tables corresponding to the plurality of power supply devices, each of the corresponding relationship tables representing a corresponding relationship between a plurality of the actual operation data corresponding to the power supply device and a plurality of the operation ADC data; The FPGA optical fiber communication module has a first optical fiber transmitting end, a first optical fiber receiving end, a second optical fiber transmitting end, and a second optical fiber receiving end; the power supply actuator is used to output voltage and current according to the power supply output setting parameters; A plurality of the power supply devices are sequentially arranged in a cycle through the FPGA optical fiber communication module, and a plurality of the FPGA optical fiber communication modules are sequentially connected in series through the first optical fiber transmitting end and the first optical fiber receiving end to form a first ring communication link, and a plurality of the FPGA optical fiber communication modules are sequentially connected in series through the second optical fiber transmitting end and the second optical fiber receiving end to form a second ring communication link, and the signal transmission direction of the second ring communication link is opposite to that of the first ring communication link; each of the FPGA optical fiber communication modules is configured as a full-duplex communication module; The power system high-efficiency current balancing device is applied to the power supply device as the host, and the power supply devices other than the host in the power system are slaves. The power system high-efficiency current balancing device includes: A current sharing information acquisition module, used to acquire current sharing information, wherein the current sharing information includes a set voltage and a set current; the set current is obtained according to the actual operation data output by the host, and the actual operation data is obtained by the FPGA optical fiber communication module of the host collecting the operation ADC data of the host through the corresponding relationship table and the sampling module; the set voltage is obtained according to the user preset voltage and the preset voltage increment; A data output module is provided, which is used to generate a host setting frame according to the current sharing information at each preset power control cycle, and transmit the host setting frame to each of the slaves through the first ring communication link, so that each of the slaves adjusts the voltage and current according to the current sharing information; The upload data receiving module is used to obtain the actual operation data of each slave machine stored in the preset cache area in the control module at each interval of the preset power control cycle, and the actual operation data of multiple slave machines are transmitted to the preset cache area in the control module of the host through the second ring communication link.

9. A high-efficiency current balancing device for a power supply system, characterized in that: The power supply system includes a plurality of power supply devices to be paralleled, each of which includes a control module, an FPGA optical fiber communication module, and a power supply actuator connected in sequence; each of the FPGA optical fiber communication modules is equipped with a sampling module, which is used to collect the operation ADC data output by the corresponding power supply device; each of the FPGA optical fiber communication modules is equipped with a RAM unit, and each of the power supply devices is loaded with a corresponding relationship table and a plurality of actual operation data into the RAM unit through the control module when starting; The control module stores a plurality of corresponding relationship tables corresponding to the plurality of power supply devices, each of the corresponding relationship tables representing a corresponding relationship between a plurality of the actual operation data corresponding to the power supply device and a plurality of the operation ADC data; The FPGA optical fiber communication module has a first optical fiber transmitting end, a first optical fiber receiving end, a second optical fiber transmitting end, and a second optical fiber receiving end, and the power supply actuator is used to output voltage and current according to power supply output setting parameters; A plurality of the power supply devices are sequentially arranged in a cycle through the FPGA optical fiber communication module, and a plurality of the FPGA optical fiber communication modules are sequentially connected in series through the first optical fiber transmitting end and the first optical fiber receiving end to form a first ring communication link, and a plurality of the FPGA optical fiber communication modules are sequentially connected in series through the second optical fiber transmitting end and the second optical fiber receiving end to form a second ring communication link, and the signal transmission direction of the second ring communication link is opposite to that of the first ring communication link; each of the FPGA optical fiber communication modules is configured as a full-duplex communication module; The power system high-efficiency current balancing device is applied to any power supply device as a slave, one of the power supply devices is selected as a master in the power system, and all the power supply devices except the master are used as slaves, and the power system high-efficiency current balancing device includes: A setting data acquisition module is used to obtain, at each preset power control cycle interval, a host setting frame transmitted by the power supply device at the last position in the first ring communication link to the preset buffer area in the control module, wherein the host setting frame is generated by the host according to the current sharing information and sent through the first ring communication link; the current sharing information includes a setting voltage and a setting current, wherein the setting current is obtained according to the actual operation data output by the host, and the actual operation data is obtained by the FPGA optical fiber communication module of the host collecting the operation ADC data of the host through the corresponding relationship table and the sampling module; the setting voltage is obtained according to the preset voltage increment and the user preset voltage input by the user through the host; A voltage adjustment module, used to complete voltage adjustment according to the set voltage; A current adjustment module, used to complete current adjustment according to the set current; The upload data output module is used to obtain the actual operation data stored in the preset cache area in the control module at each interval of the preset power control cycle, and fill the actual operation data into the corresponding record segment in the slave upload frame, and then transmit the slave upload frame to the next power supply device through the second ring communication link; the slave upload frame includes multiple record segments corresponding to multiple slaves, and each record segment is used to write the actual operation data of the corresponding slave.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the high-efficiency current sharing method for a power supply system as described in any one of claims 1 to 7.

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