Power supply voltage comparator control circuit and control method suitable for wide voltage range

Abstract

The present invention relates to a power supply voltage comparator control circuit and control method suitable for a wide voltage domain, characterized in that it comprises a voltage stabilizing source, a reference source circuit, a VCC voltage sampling circuit, a signal processing circuit, and a comparator; wherein the reference source circuit is composed of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NMOS tube M1, and a second NMOS tube M2; wherein the VCC voltage sampling circuit is composed of a first capacitor C1 and a second capacitor C2; due to the introduction of the reference source circuit, the VCC voltage sampling circuit and the signal processing circuit, the present invention can maintain a stable output of the OUT output waveform as long as VP, Tr and Td are kept unchanged regardless of the voltage change of the steady-state voltage U0.

Description

Technical Field

[0001] The present invention relates to the field of using the change of power supply voltage VCC as a communication signal, and in particular to a power supply voltage comparator control circuit and a control method suitable for a wide voltage range. Background Art

[0002] Nowadays, the integration of integrated circuits is getting higher and higher, and the number of peripheral devices is getting smaller and smaller. Especially in various sensors, even the entire chip has only two pins: power supply and ground. When the chip receives external information, it can only be realized by changing the power supply voltage VCC. Traditional power supply voltage comparators, such as Figure 3 , will be affected by the size of U0 and can only be used within a limited range. Summary of the invention

[0003] The purpose of the present invention is to provide a power supply voltage comparator control circuit and control method applicable to a wide voltage range, so as to solve the problems raised in the above background technology.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] A power supply voltage comparator control circuit suitable for a wide voltage domain, comprising a voltage stabilizing source, a reference source circuit, a VCC voltage sampling circuit, a signal processing circuit, and a comparator; wherein the voltage stabilizing source provides a stable power supply for the reference source circuit, the signal processing circuit, and the comparator; wherein the reference source circuit is composed of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NMOS transistor M1, and a second NMOS transistor M2, and is used to generate a stable reference source and a hysteresis voltage for the comparator; wherein the VCC voltage sampling circuit is composed of a first capacitor C1 and a second capacitor C2, and is used to sample changes in the VCC voltage; wherein the signal processing circuit is used to isolate the influence of the VCC voltage sampling circuit on the reference source circuit when sampling changes in the VCC voltage and provide a DC operating point for a node N5; the circuit comprises five connection nodes, namely a first node, a second node, a third node, a fourth node, and a fifth node.

[0006] In the reference source circuit, one end of the first resistor R1 away from the first node is connected to the VDD of the voltage regulator source, and one end close to the first node is connected to the first node; the first node is a connection point between one end of the first resistor R1 close to the first node, one end of the second resistor R2 close to the first node, and the drain end of the first NMOS tube M1; one end of the second resistor R2 close to the first node is connected to the first node, and one end away from the first node is connected to the second node; the second node is a connection point between one end of the second resistor R2 close to the second node, one end of the signal processing circuit close to the second node, and one end of the third resistor R3 close to the second node; one end of the third resistor R3 close to the second node is connected to the second node, and one end away from the second node is connected to The second node; the third node is a connection point between one end of the third resistor R3 close to the third node, the drain end of the second NMOS tube M2, and one end of the fourth resistor R4 close to the third node; one end of the fourth resistor R4 close to the third node is connected to the third node, and one end away from the third node is connected to the ground; the drain end of the first NMOS tube M1 is connected to the first node, the gate end is connected to OUTB, and the source end is connected to the fourth node; OUTB is the negative output of the comparator; the fourth node is a connection point between the source end of the first NMOS tube, the source end of the second NMOS tube, and the negative input end of the comparator; the drain end of the second NMOS tube M2 is connected to the third node, the gate end is connected to OUT, and the source end is connected to the fourth node; OUT is the positive output of the comparator.

[0007] In the VCC voltage sampling circuit, one end of the first capacitor C1 away from the fifth node is connected to VCC, and the other end close to the fifth node is connected to the fifth node; the fifth node is a connection point of one end of the first capacitor C1 close to the fifth node, one end of the signal processing close to the fifth node, the positive input end of the comparator, and one end of the second capacitor C2 close to the fifth node; one end of the second capacitor C2 close to the fifth node is connected to the fifth node, and one end away from the fifth node is connected to ground.

[0008] The voltage stabilizing source has an end close to the node VDD connected to VDD, an end close to the VCC node connected to VCC, and an end close to the ground connected to the ground.

[0009] The signal processor has one end close to the fifth node connected to the fifth node, one end close to the second node connected to the second node, and one end close to the ground connected to the ground.

[0010] The negative input terminal of the comparator is connected to the fourth node, the positive input terminal is connected to the fifth node, the negative output terminal is connected to the node OUTB, and the initial state is set to high; the positive output terminal is connected to the node OUT, and the initial state is set to low.

[0011] A control method is provided, wherein the power supply voltage comparator control circuit suitable for a wide voltage domain is used for control, wherein the voltage regulator can achieve a stable output of VDD within the range of VCC=4.5V~30V, thereby ensuring that the reference source circuit can output a stable node voltage VN1 of the first node, a node voltage VN2 of the second node, and a node voltage VN3 of the third node, and further achieving a voltage VN4 at the negative input terminal of the comparator, i.e., the fourth node, with an initial state of VN4=VN1, which is VN4_high.

[0012] The function of the signal processing is to isolate the influence of the fifth node on the fourth node when the VCC voltage changes in AC and to provide a DC operating point of the fifth node when the VCC voltage is in a steady state, that is, VN5_stable=VN4_stable; due to the capacitance characteristics of the first capacitor C1 and the second capacitor C2, the steady-state voltage of VCC can be isolated, so no matter U0 is at any steady-state voltage between 4.5 and 30V, it will not affect the voltage of the fifth node N5.

[0013] In the process that the VCC voltage rises from the first rising edge to the steady-state voltage U0+VP in the time of Tr, a current will be generated in the branches of the first capacitor C1 and the second capacitor C2, which will cause VN5_ to rise instantly, causing the positive output terminal OUT of the comparator to become high and the negative output terminal OUTB to become low, thereby turning off the first NMOS tube and turning on the second NMOS tube. At this time, the node voltage of the fourth node is VN4_low, that is, VN4_low=VN3, further ensuring the stability of OUT being high; the VCC voltage drops from the first falling edge to the steady-state voltage U0+VP in the time of Td. During the steady-state voltage process, current will be generated in the branches of the first capacitor C1 and the second capacitor C2, causing VN5_ to drop instantaneously, causing the positive output terminal OUT of the comparator to become low and the negative output terminal OUTB to become high, thereby turning on the first NMOS tube and turning off the second NMOS tube. At this time, the node voltage of the fourth node is VN4_high, that is, VN4_high=VN1, further ensuring the stability of OUT being low; when the VCC voltage changes with a voltage with an amplitude of VP and a time of Tr=Td, the output terminal OUT of the comparator will be continuously flipped.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] The present invention introduces a reference source circuit, a VCC voltage sampling circuit and a signal processing circuit so that when U0 changes within a wide voltage range, the waveform of the output OUT of the comparator will not be affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is the VCC voltage waveform.

[0017] Figure 2 The present invention provides a power supply voltage comparator control circuit diagram suitable for a wide voltage range.

[0018] Figure 3 This is a traditional power supply voltage comparator circuit diagram. DETAILED DESCRIPTION

[0019] In order to clarify the technical problems, technical solutions, implementation processes and performance demonstrations, the present invention is further described in detail below in conjunction with embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. The exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings do not have to be drawn to scale unless otherwise specified.

[0020] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0021] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following detailed description.

[0022] Those skilled in the art will appreciate that the present disclosure can be implemented without certain specific details. In some instances, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0023] Embodiment 1:

[0024] like Figure 2As shown, a power supply voltage comparator control circuit suitable for a wide voltage domain includes a voltage regulator 101, a reference source circuit 102, a VCC voltage sampling circuit 103, a signal processing circuit 104, and a comparator 105; wherein the voltage regulator 101 provides a stable power supply for the reference source circuit 102, the signal processing circuit 104, and the comparator 105; wherein the reference source circuit 102 is composed of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NMOS transistor M1, and a second NMOS transistor M2, and is used to generate a stable reference source and a hysteresis voltage for the comparator 105; wherein the VCC voltage sampling circuit 103 is composed of a first capacitor C1 and a second capacitor C2, and is used to sample changes in the VCC voltage; wherein the signal processing circuit 104 is used to isolate the influence of the VCC voltage sampling circuit on the reference source circuit 102 when sampling changes in the VCC voltage and provide a DC operating point for the node N5; the circuit includes 5 connection nodes, namely a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5.

[0025] In the reference source circuit 102, one end of the first resistor R1 away from the first node N1 is connected to the VDD of the voltage regulator, and one end close to the first node N1 is connected to the first node N1; the first node N1 is a connection point between one end of the first resistor R1 close to the first node N1, one end of the second resistor R2 close to the first node N1, and the drain end of the first NMOS tube M1; one end of the second resistor R2 close to the first node N1 is connected to the first node N1, and one end away from the first node N1 is connected to the second node N2; the second node N2 is a connection point between one end of the second resistor R2 close to the second node N2, one end of the signal processing circuit close to the second node N2, and one end of the third resistor R3 close to the second node N2; one end of the third resistor R3 close to the second node N2 is connected to the second node N2, and one end away from the second node N2 is connected to the second node N2. The second node N3 is connected; the third node N3 is a connection point between one end of the third resistor R3 close to the third node N3, the drain end of the second NMOS tube M2 and one end of the fourth resistor R4 close to the third node N3; one end of the fourth resistor R4 close to the third node N3 is connected to the third node N3, and one end away from the third node N3 is connected to the ground; the drain end of the first NMOS tube M1 is connected to the third node N1, the gate end is connected to OUTB, and the source end is connected to the fourth node N4; OUTB is the negative output of the comparator 105; the fourth node N4 is a connection point between the source end of the first NMOS tube, the source end of the second NMOS tube and the negative input end of the comparator 105; the drain end of the second NMOS tube M2 is connected to the third node N3, the gate end is connected to OUT, and the source end is connected to the fourth node N4; OUT is the positive output of the comparator 105.

[0026] In the VCC voltage sampling circuit 103, one end of the first capacitor C1 away from the fifth node N5 is connected to VCC, and one end close to the fifth node N5 is connected to the fifth node N5; the fifth node N5 is a connection point between one end of the first capacitor C1 close to the fifth node N5, one end of the signal processing close to the fifth node N5, the positive input end of the comparator, and one end of the second capacitor C2 close to the fifth node N5; one end of the second capacitor C2 close to the fifth node N5 is connected to the fifth node N5, and one end away from the fifth node N5 is connected to ground.

[0027] The voltage stabilizing source 101 has one end close to the node VDD connected to VDD, one end close to the VCC node connected to VCC, and one end close to the ground connected to the ground.

[0028] One end of the signal processing 104 close to the fifth node N5 is connected to the fifth node N5, one end close to the second node N2 is connected to the second node N2, and one end close to the ground is connected to the ground.

[0029] The comparator 105 has a negative input terminal connected to the fourth node N4 , a positive input terminal connected to the fifth node N5 , a negative output terminal connected to the node OUTB, and a positive output terminal connected to the node OUT.

[0030] The principle of the embodiment is specifically described:

[0031] The voltage regulator 101 can achieve VDD in the range of VCC=4.5V~30V, assuming 1.8V, the same below, stable output, which ensures that the reference source circuit 102 can output stable node voltage VN1 of the first node N1, node voltage VN2 of the second node N2, and node voltage VN3 of the third node N3, and further can achieve the negative input terminal of the comparator 105, that is, the voltage VN4 of the fourth node, the initial state VN4=VN1, which is VN4_high.

[0032] The function of the signal processing 104 is to isolate the influence of the fifth node N5 on the fourth node N4 when the VCC voltage changes in AC and to provide a DC operating point of the fifth node N5 when the VCC voltage is in a steady state, that is, VN5_stable=VN4_stable; due to the capacitance characteristics of the first capacitor C1 and the second capacitor C2, the steady-state voltage of VCC can be naturally isolated, so no matter U0 is at any steady-state voltage between 4.5 and 30V, it will not affect the voltage of the fifth node N5, VN5_stable.

[0033] In the process that the VCC voltage rises from the first rising edge to the steady-state voltage U0+VP in the time of Tr, a current will be generated in the branches of the first capacitor C1 and the second capacitor C2, which will cause VN5_ to rise instantly, causing the positive output terminal OUT of the comparator 105 to become high and the negative output terminal OUTB to become low, thereby turning off the first NMOS tube and turning on the second NMOS tube. At this time, the node voltage of the fourth node N4 is VN4_low, VN4_low=VN3, further ensuring the stability of OUT being high; the VCC voltage starts from the first falling edge and rises to the steady-state voltage U0+VP in the time of Td. In the process of decreasing from the steady-state voltage U0 to the steady-state voltage U0, a current will be generated in the branches of the first capacitor C1 and the second capacitor C2, which will cause VN5_ to drop instantaneously, causing the positive output terminal OUT of the comparator 105 to become low and the negative output terminal OUTB to become high, thereby turning on the first NMOS tube and turning off the second NMOS tube. At this time, the node voltage of the fourth node N4 is VN4_high, VN4_high=VN1, further ensuring the stability of OUT being low; when the VCC voltage changes with a voltage of an amplitude of VP and Tr=Td, assuming the same, the same below, as Figure 1 The VCC voltage waveform will cause the output terminal OUT of the comparator 105 to continuously flip, such as Figure 1 OUT voltage waveform.

[0034] The VN5_instantaneous will change only when the VCC voltage changes. The larger the VP is and the shorter the Tr=Td is, the greater the amplitude of the VN5_instantaneous change will be, and it has nothing to do with the size of U0. Therefore, in applications with a wide voltage domain, communication using changes in the VCC power supply voltage will not be affected, and when there is no communication, the VCC voltage sampling circuit and signal processing circuit introduced in the present invention have no power consumption, and are more suitable for applications under low power consumption than traditional circuits.

[0035] The above describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only preferred examples of the present invention and are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A power supply voltage comparator control circuit suitable for a wide voltage range, characterized in that: The invention comprises a voltage stabilizer (101), a reference source circuit (102), a VCC voltage sampling circuit (103), a signal processing circuit (104), and a comparator (105); wherein the voltage stabilizer (101) provides a stable power supply for the reference source circuit (102), the signal processing circuit (104), and the comparator (105); wherein the reference source circuit (102) is composed of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NMOS transistor M1, and a second NMOS transistor M2, and is used to generate a stable reference source and a hysteresis voltage for the comparator (105); wherein the VCC voltage sampling circuit (103) is composed of a first capacitor C1 and a second capacitor C2, and is used to sample The signal processing circuit (104) is used to isolate the influence of the VCC voltage sampling circuit (103) on the reference source circuit (102) when sampling the VCC voltage change and provide a DC operating point for the fifth node (N5); the circuit includes five connection nodes, namely a first node (N1), a second node (N2), a third node (N3), a fourth node (N4) and a fifth node (N5); the end of the first resistor R1 in the reference source circuit (102) away from the first node (N1) is connected to the VDD of the voltage stabilization source, and the end close to the first node (N1) is connected to the first node (N1); the first node (N1) is the first resistor R1 an end close to the first node (N1), an end of the second resistor R2 close to the first node (N1), and a connection point of the drain end of the first NMOS tube M1; an end of the second resistor R2 close to the first node (N1) is connected to the first node (N1), and an end away from the first node (N1) is connected to the second node (N2); the second node (N2) is a connection point of an end of the second resistor R2 close to the second node (N2), an end of the signal processing circuit close to the second node (N2), and an end of the third resistor R3 close to the second node (N2); an end of the third resistor R3 close to the second node (N2) is connected to the second node (N2), one end away from the second node (N2) is connected to the second node (N3); the third node (N3) is a connection point between one end of the third resistor R3 close to the third node (N3), the drain end of the second NMOS tube M2 and one end of the fourth resistor R4 close to the third node (N3); one end of the fourth resistor R4 close to the third node (N3) is connected to the third node (N3), and one end away from the third node (N3) is connected to the ground; the drain end of the first NMOS tube M1 is connected to the first node (N1), the gate end is connected to OUTB, and the source end is connected to the fourth node (N4); OUTB is the negative output of the comparator (105);The fourth node (N4) is a connection point between the source end of the first NMOS tube, the source end of the second NMOS tube and the negative input end of the comparator (105); the drain end of the second NMOS tube M2 is connected to the third node (N3), the gate end is connected to OUT, and the source end is connected to the fourth node (N4); the OUT is the positive output of the comparator (105); the end of the first capacitor C1 in the VCC voltage sampling circuit (103) away from the fifth node (N5) is connected to VCC, and the end close to the fifth node (N5) is connected to the fifth node (N5); the fifth node (N5) is a connection point between the end of the first capacitor C1 close to the fifth node (N5), the end of the signal processing close to the fifth node (N5), the positive input end of the comparator and the end of the second capacitor C2 close to the fifth node (N5); the end of the second capacitor C2 close to the fifth node (N5) is connected to the fifth node (N5), and the end away from the fifth node (N5) is connected to the ground. ; 2. The power supply voltage comparator control circuit applicable to a wide voltage range according to claim 1, characterized in that: The voltage stabilizing source (101) has one end close to the node VDD connected to VDD, one end close to the VCC node connected to VCC, and one end close to the ground connected to the ground.

3. The power supply voltage comparator control circuit applicable to a wide voltage range according to claim 1, characterized in that: The signal processing (104) has one end close to the fifth node (N5) connected to the fifth node (N5), one end close to the second node (N2) connected to the second node (N2), and one end close to the ground connected to the ground.

4. The power supply voltage comparator control circuit applicable to a wide voltage range according to claim 1, characterized in that: The negative input terminal of the comparator (105) is connected to the fourth node (N4), the positive input terminal is connected to the fifth node (N5), the negative output terminal is connected to the node OUTB, and the initial state is set to high; the positive output terminal is connected to the node OUT, and the initial state is set to low.

5. A control method, characterized in that: By using the power supply voltage comparator control circuit suitable for a wide voltage range as described in any one of claims 1 to 4 for control, the voltage regulator (101) can achieve a stable output of VDD in the range of VCC=4.5V~30V, thereby ensuring that the reference source circuit (102) can output a stable node voltage VN1 of the first node (N1), a node voltage VN2 of the second node (N2), and a node voltage VN3 of the third node (N3), and further achieving the voltage VN4 of the negative input terminal of the comparator (105), i.e., the fourth node (N4), with an initial state of VN4=VN1, which is VN4_high.

6. The control method according to claim 5, characterized in that: The function of the signal processing (104) is to isolate the influence of the fifth node (N5) on the fourth node (N4) when the VCC voltage changes in an alternating current and to provide a DC operating point of the fifth node (N5) when the VCC voltage is in a steady state, that is, VN5_steady=VN4_steady; due to the capacitance characteristics of the first capacitor C1 and the second capacitor C2, the steady-state voltage of VCC can be isolated, so no matter whether the steady-state voltage U0 is at any steady-state voltage between 4.5 and 30V, it will not affect the voltage of the fifth node (N5).

7. The control method according to claim 5, characterized in that: In the process that the VCC voltage rises from the first rising edge to the steady-state voltage U0+VP in the time Tr, a current is generated in the branch of the first capacitor C1 and the second capacitor C2, which causes VN5_ to rise instantly, causing the positive output terminal OUT of the comparator (105) to become high and the negative output terminal OUTB to become low, thereby turning off the first NMOS tube and turning on the second NMOS tube. At this time, the node voltage of the fourth node (N4) is VN4_low, that is, VN4_low=VN3, further ensuring the stability of OUT being high; the VCC voltage drops from the first falling edge to the steady-state voltage in the time Td. During the process of (U0), a current will be generated in the branch of the first capacitor C1 and the second capacitor C2, causing VN5_ to drop instantaneously, causing the positive output terminal OUT of the comparator (105) to become low and the negative output terminal OUTB to become high, thereby turning on the first NMOS tube and turning off the second NMOS tube. At this time, the node voltage of the fourth node (N4) is VN4_high, that is, VN4_high=VN1, further ensuring the stability of OUT being low; when the VCC voltage changes with a voltage of an amplitude of VP and a time of Tr=Td, the output terminal OUT of the comparator (105) will be continuously flipped.

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