Gate driver, gate driver system and method for driving power switch

Abstract

The invention discloses a gate driver, a gate driver system and a method for driving a power switch. The gate driver includes a low voltage control logic, a high side switch control circuit and a low side switch control circuit. The low voltage control logic generates an internal pulse high side control signal based on the high side control signal and the common protection function blanking control signal, and generates a low side protection function activation signal based on the low side control signal and the common protection function blanking control signal. The high-side switch control circuit includes a high-side protection function circuit that is enabled based on a first pulse of the internal pulse high-side control signal and activated based on a second pulse of the internal pulse high-side control signal. The low-side switching control circuit includes a low-side protection function circuit that is activated based on a low-side protection function activation signal.

Description

Technical Field

[0001] The present invention relates generally to gate drivers for power switches and, more particularly, to submitting timing information between different voltage domains of such gate drivers. Background Art

[0002] When switching a power switch using a gate driver, voltage and / or current events may occur, which may erroneously trigger protection functions of the gate driver, such as desaturation detection or over-current protection (OCP) functions. In order to avoid erroneous triggering of protection functions, the gate driver may adopt a blanking time, i.e., a time during which the protection function is prohibited from detecting its corresponding triggering condition. However, the blanking time needs to strike a balance between preventing false triggering, which may be caused, for example, by a blanking time that is too short, and delayed triggering, which may be caused, for example, by a blanking time that is too long. For example, if the blanking time is too long, the driven power switch may be damaged or destroyed.

[0003] In order to set the blanking time, the gate driver can be configured to be coupled to passive components so that the blanking time can be fixedly set by the size of the passive components during the design phase of the control circuit containing the gate driver. However, this method requires circuit area due to the size of the passive components. If the gate driver is to drive at least one phase of a three-phase inverter, the required circuit area may be further increased because high voltage isolation may be required between the passive components that define the blanking time for the three phases. In addition, the method requires approximation of all possible situations in which triggering should be prohibited, because the blanking time cannot be changed after the control circuit containing the gate driver is deployed. Such an approximation may be inaccurate considering the many possible situations that may occur during switching of the power switch, which may also depend on the load coupled to the power switch.

[0004] In addition to the protection functions as described above, other functions provided by the gate driver may also utilize the timing information. Examples of such other functions are sensing functions or data transmission functions.

[0005] More generally, a gate driver may include various circuit systems operating in different voltage domains. Transmitting information such as timing information between different voltage domains may be useful in various situations. However, conventional solutions to this problem may require complex circuit systems, have large area consumption, or be economically unfeasible. Summary of the invention

[0006] The present disclosure provides a gate driver configured to drive a high-side switch. The gate driver includes a low voltage control logic configured to receive a high-side control signal and a timing control signal, and to generate an internal pulse high-side control signal based on the high-side control signal and the timing control signal. The gate driver also includes a high-side switch control circuit coupled to the low voltage control logic and configured to control the high-side switch based on the internal pulse high-side control signal, the high-side switch control circuit including a high-side support function circuit, wherein the high-side support function circuit is configured to be enabled based on a first pulse of the internal pulse high-side control signal and activated based on a second pulse of the internal pulse high-side control signal.

[0007] The present disclosure also provides a system comprising: a half-bridge arrangement including a high-side switch and a low-side switch; and a gate driver configured to drive the half-bridge arrangement. The gate driver comprises a low-voltage control logic configured to receive a high-side control signal, a low-side control signal, and a timing control signal, to generate an internal pulse high-side control signal based on the high-side control signal and the timing control signal, and to generate a low-side support function activation signal based on the low-side control signal and the timing control signal. The gate driver also comprises a high-side switch control circuit coupled to the low-voltage control logic and coupled to the control terminal of the high-side switch, and configured to control the high-side switch based on the internal pulse high-side control signal, the high-side switch control circuit comprising a high-side support function circuit, wherein the high-side support function circuit is configured to be enabled based on a first pulse of the internal pulse high-side control signal, and activated based on a second pulse of the internal pulse high-side control signal. The gate driver also includes a low-side switch control circuit, which is coupled to the low voltage control logic and to the control terminal of the low-side switch and is configured to control the low-side switch based on the low-side control signal, the low-side switch control circuit includes a low-side support function circuit, wherein the low-side support function circuit is configured to be activated based on the low-side support function activation signal.

[0008] The present disclosure also provides a gate driver system, which includes: a timing control signal input terminal, which is configured to receive a timing control signal; a timing control signal distribution line, which is connected to a timing control signal output terminal; and a plurality of gate drivers. Each gate driver is configured to drive a corresponding high-side switch. Each of the plurality of gate drivers includes a low voltage control logic, which is configured to receive a high-side control signal, and receives the timing control signal via the timing control signal distribution line, and generates an internal pulse high-side control signal based on the high-side control signal and the timing control signal. Each gate driver also includes a high-side switch control circuit, which is coupled to the low voltage control logic and is configured to control the corresponding high-side switch based on the internal pulse high-side control signal, and the high-side switch control circuit includes a high-side support function circuit, wherein the high-side support function circuit is configured to be enabled based on a first pulse of the internal pulse high-side control signal, and activated based on a second pulse of the internal pulse high-side control signal.

[0009] The present disclosure also provides a method for driving a high-side switch. The method includes receiving a high-side control signal and a timing control signal, generating an internal pulse high-side control signal based on the high-side control signal and the timing control signal, controlling the high-side switch based on the internal pulse high-side control signal, enabling a high-side support function circuit based on a first pulse of the internal pulse high-side control signal, and activating the high-side support function circuit based on a second pulse of the internal pulse high-side control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Examples of the present disclosure will be described with reference to the following drawings, wherein like reference numerals refer to like elements throughout.

[0011] Figures 1A to 1C A gate driver according to an example of the present disclosure is shown.

[0012] Figure 2A and Figure 2B Provided are examples of Figures 1A to 1C Examples of internal and external signals for a gate driver.

[0013] Figure 3A and Figure 3B A flow chart of a method for driving a half-bridge according to an example of the present disclosure is provided.

[0014] Figure 4 A gate driver system according to an example of the present disclosure is shown.

[0015] It should be understood that the above-mentioned drawings are in no way intended to limit the present disclosure. On the contrary, these drawings are provided to help understand the present disclosure. Those skilled in the art will readily appreciate that the various aspects of the present invention shown in one drawing may be combined with the various aspects in another drawing or may be omitted without departing from the scope of the present disclosure. DETAILED DESCRIPTION

[0016] The present disclosure generally provides a gate driver and corresponding method for controlling a high-side switch based on a timing control signal in addition to a high-side control signal. The timing control signal is used to control the activation time (eg, blanking time) of a high-side support function circuit.

[0017] More precisely, the internal pulse high-side control signal is generated based on the high-side control signal and the timing control signal. The first pulse of the internal pulse high-side control signal enables the high-side support function circuit, that is, the power supply of the high-side support function circuit is operable. The second pulse of the internal pulse high-side control signal activates the high-side support function, that is, the power supply of the high-side support function circuit provides power to the high-side support function circuit. The first pulse and the second pulse of the internal pulse high-side control signal thus define the beginning and end of the blanking time of the high-side support function circuit. In addition, the first pulse turns on the high-side switch. The high-side support function circuit can implement protection functions, sensing functions, data transmission functions and / or other support functions that can support efficient and safe operation of the high-side switch.

[0018] The proposed gate driver and method can also be configured to drive a half-bridge including a high-side switch and a low-side switch. Here, the low-voltage control logic can be configured to receive a low-side control signal, and generate a low-side support function activation signal based on the low-side control signal and the timing control signal. The gate driver also includes a low-side switch control circuit coupled to the low-voltage control logic and configured to control the low-side switch based on the low-side control signal. The low-side switch control circuit can also include a low-side support function circuit configured to be activated based on the low-side support function activation signal. After the low-side control signal has indicated that the low-side switch is to be turned on, once the blanking time expires, the low-side support function activation signal causes the low-side support function circuit to be activated. In addition, for example, the low-side switch is directly turned on by forwarding the low-side control signal.

[0019] The present disclosure also provides a gate driver and a corresponding method, which, in addition to the low-side control signal and the high-side control signal, controls the high-side switch and the low-side switch of the half-bridge based on a common protection function blanking control signal. The common protection function blanking control signal is used to control the blanking time of both the high-side protection function circuit and the low-side protection function circuit. In other words, the common protection function blanking control signal is a reference signal that limits the blanking time of both the high-side protection function circuit and the low-side protection function circuit.

[0020] More precisely, the internal pulse high-side control signal is generated based on the high-side control signal and the common protection function blanking control signal. The first pulse of the internal pulse high-side control signal enables the high-side protection function, i.e., makes the power supply of the high-side protection function operable. The second pulse of the internal pulse high-side control signal activates the high-side protection function, i.e., makes the power supply of the high-side protection function circuit provide power to the high-side protection function circuit, thereby making the high-side protection function circuit operable to detect the triggering condition of the high-side protection function. The first pulse and the second pulse of the internal pulse high-side control signal thus define the beginning and the end of the blanking time of the high-side control signal. In addition, the first pulse turns on the high-side switch.

[0021] In addition, a low-side protection function activation signal is generated based on the low-side control signal and the common protection function blanking control signal. After the low-side control signal has indicated that the low-side switch is to be turned on, once the blanking time expires, the low-side protection function activation signal activates the low-side protection function circuit. In addition, the low-side switch is directly turned on, for example, by forwarding the low-side control signal.

[0022] The general concept will be described with reference to the accompanying drawings, in which: Figures 1A to 1C An example of a gate driver is shown, and FIG. 2A to FIG. 2B Provided Figures 1A to 1C Examples of internal and external signals for the gate driver. Figure 3A and Figure 3B The corresponding method is shown.

[0023] In the following detailed description, the gate driver is implemented as a half-bridge gate driver by way of example. However, this should not be construed as restrictive, and the gate driver can be configured only as a high-side driver (e.g., without a low-side switch control circuit). In addition, the support function circuit is described as a protection function circuit by way of example and without loss of generality. However, this should not be construed as restrictive, and the following examples can also be practiced using support function circuits that implement different support functions. An example is a sensing function circuit that can be configured to sense at least one operating parameter of a controlled switch (e.g., a high-side switch or a low-side switch) such as voltage, current, temperature or other such parameters, or a data transmission function circuit that can be configured to control a data transmission function such as realizing a data transmission between a low-voltage control logic and a high-side switch control circuit. In addition, the timing control signal may be referred to as a common protection function blanking control signal hereinafter. This is to indicate that the timing control signal can be used together to control the blanking time of both the high-side protection function circuit and the low-side protection function circuit.

[0024] Figure 1AThe gate driver 100 is shown coupled to a half-bridge 200 including a high-side switch 201 and a low-side switch 202 coupled between a supply voltage VDD (eg, the supply voltage may be in a range between 450V and 1800V) and a ground voltage.

[0025] The high-side switch 201 and the low-side switch 202 can be any kind of power switch configured to have a high voltage blocking capability. For example, the high-side switch 201 and the low-side switch 202 can be capable of blocking a voltage of at least 400V or more, such as 450V, 900V, 1200V or 1800V. In order to achieve such a voltage blocking capability, the high-side switch 201 and the low-side switch 202 can be, for example, a silicon or silicon carbide (SiC) metal oxide field effect transistor (MOSFET), a silicon or SiC insulated gate bipolar transistor (IGBT) or a gallium nitride high electron mobility transistor (GaN-HEMT). It should be understood that the voltage levels and technology types discussed about the high-side switch 201 and the low-side switch 202 are provided only as examples. Other high voltage levels and other power switch technologies other than those mentioned herein can be used to practice the present disclosure.

[0026] The gate driver 100 is coupled to the control terminal of the high-side switch 201 and to the control terminal of the low-side switch 202. In addition, for example, Figures 1A to 1C As shown in , the gate driver 100 can be coupled to a first load terminal of the high-side switch 201 and to a first load terminal of the low-side switch 202, and for example, as Figures 1A to 1C As shown in , it can also be coupled to the second load terminal of the high-side switch 201, and to the second load terminal of the low-side switch 202. As will be discussed in further detail below, whether the gate driver 100 is coupled to the corresponding first load terminal and the second load terminal and to which of the corresponding first load terminal and the second load terminal it is coupled can depend on one or more protection functions included in the gate driver 100.

[0027] Figure 1A The gate driver 100 includes a low voltage control logic 110 , a high-side switch control circuit 130 , and a low-side switch control circuit 150 . In addition, the gate driver 100 may include a high-side signal forwarding circuit 120 .

[0028] Since the high voltage level is to be switched by the half bridge 200, the gate driver 100 may be separated into at least a low voltage region and a high voltage region in some examples of the present disclosure. To this end, the gate driver 100 may include an insulation barrier between the low voltage control logic and the high side switch control circuit, the insulation barrier being Figures 1A to 1CIndicated as two adjacent dashed lines in the figure. The isolation barrier can be configured to electrically isolate the low voltage region and the high voltage region. The low voltage control logic 110 can be located in the low voltage region, and the high side switch control circuit 130 can be located in the high voltage region. Therefore, the isolation barrier can be configured to isolate the low voltage control logic 110 from the high side switch control circuit 130. The low side switch control circuit 150 can also be located in the low voltage region. The isolation barrier can therefore be configured to isolate the low voltage control logic 110 and the low side switch control circuit 150 from the high side switch control circuit 130. This concept is as shown in FIG. Figure 1A and Figure 1B As shown in . Depending on the isolation safety level required by the environment in which the gate driver 100 is to be employed, the low-side switch control circuit 150 may also be located in a medium voltage region separated from both the high voltage region and the low voltage region by an isolation barrier. The isolation barrier may thus be configured to isolate the low voltage control logic 110, the high-side switch control circuit 130, and the low-side switch control circuit 150 from each other. This concept is shown in Figure 1C . It should be understood that the isolation barrier does not need to be continuous to provide isolation between the low voltage region, the medium voltage region and the high voltage region. Instead, depending on the actual implementation of the gate driver 100, the isolation barrier can also be provided as two or three separate isolation barriers.

[0029] As can be seen from the discussion of the isolation barrier above, the low voltage in the name of the low voltage control logic 110 refers to the fact that the low voltage control logic 110 is isolated from the high voltage to be switched by the gate driver 100 .

[0030] More precisely, the low voltage control logic 110 is configured to receive the high-side control signal S HS , low side control signal S LS and common protection function blanking control signal S PBL .

[0031] High-side control signal S HS The low-side control signal S indicates when the high-side switch 201 is to be turned on and off by the gate driver 100. LS The low-side switch 202 is instructed when to be turned on and off by the gate driver 100 .

[0032] Common protection function blanking control signal S PBL Indicates the blanking time for the high-side protection function and the low-side protection function of the gate driver 100, ie, the time when both the high-side protection function and the low-side protection function in the gate driver 100 are to be disabled. More precisely, the common protection function blanking control signal S PBLis a reference signal that defines the duration of the blanking time for both the high-side protection function and the low-side protection function of the gate driver 100. In other words, the common protection function blanking control signal S PBL A common blanking time is defined for both protection functions. In other implementations, the common protection function blanking control signal is configured as a timing signal that can be used by a support function circuit of a corresponding gate driver that is different from the protection function circuit.

[0033] High-side control signal S HS , low side control signal S LS and common protection function blanking control signal S PBL This may be provided by a microcontroller or some other logic that determines when to turn on and off the high-side switch 201 and the low-side switch 202 and how long to disable the protection functions of the gate driver 100 .

[0034] Based on the received high-side control signal S HS and the received common protection function blanking control signal S PBL , the low voltage control logic 110 is configured to generate an internal pulse high-side control signal S HS,int The internal pulse high-side control signal S HS,int Is a pulse signal, that is, the internal pulse high-side control signal S HS,int Based on pulse transmission information. Therefore, the internal pulse high-side control signal S HS,int Based on the pulse control high-side switch 201 and the high-side protection function of the gate driver 100. To this end, the low voltage control logic 110 generates an internal pulse high-side control signal S HS,int The first pulse turns on the high-side switch 201 and enables the protection function of the gate driver 100, that is, makes the power supply of the high-side protection function circuit operable. In addition, the low voltage control logic 110 generates an internal pulse high-side control signal S HS,int The second pulse activates the high-side protection function of the gate driver 100, that is, causes the power supply of the high-side protection function circuit to provide power to the high-side protection circuit.

[0035] Based on the received low-side control signal S LS and the received common protection function blanking control signal S PBL , the low voltage control logic 110 is configured to generate a low side protection function activation signal S LS,PA Once the control signal S is blanked by the common protection function PBL When the defined blanking time expires, the low-side protection function activates the signal S LS,PA The low-side protection function of the gate driver 100 is activated.

[0036] The low voltage control logic 110 may also be configured to generate a high side switch control circuit reset signal S HS,res , S HS,res The high-side switch controller 130 may be reset and thus turn off the high-side switch 201 and the high-side protection function of the gate driver 100. The low voltage control logic 110 may be based on the high-side control signal S HS and more accurately based on the high-side control signal S HS The high-side switch control circuit reset signal S is generated by the instruction HS,res To turn off the high-side switch 201 .

[0037] The high-side switch control circuit 130 is coupled to the low voltage control logic 110 and includes a high-side protection function. The high-side switch control circuit 130 is configured to be based on the internal pulse high-side control signal S HS,int and more accurately based on the internal pulsed high-side control signal S HS,int The first pulse of the high-side switch 201 is used to control the high-side switch 201. To this end, the high-side switch control circuit 130 provides a high-side control output signal S to the control terminal of the high-side switch 201. HO In addition, as mentioned above regarding the internal pulse high-side control signal S HS,int As discussed above, the high-side switch control circuit 130 is configured to control the high-side switch based on the internal pulse high-side control signal S HS,int The first pulse of the high-side protection function circuit is enabled, and based on the internal high-side pulse control signal S HS,int The second pulse activates the high-side protection function.

[0038] The low-side switch control circuit 150 is coupled to the low voltage control logic 110 and includes a low-side protection function circuit. The low-side switch control circuit 150 is configured to LS To control the low-side switch 202. To this end, the low-side switch control circuit 150 provides a low-side control output signal S to the control terminal of the low-side switch 202. LO In addition, as mentioned above regarding the internal pulse high-side control signal S HS,int As discussed above, the low-side switch control circuit 150 is configured to activate the low-side protection function based on the second pulse of the low-side protection function. LS,PA To activate the low-side protection function circuit. In other words, the low-side protection function activation signal S LS,PA It can be used, for example, as a power supply for a low-side protection functional circuit, or can activate the power supply for a low-side protection functional circuit.

[0039] In an implementation of the gate driver 100 including an insulation barrier, the high-side signal forwarding circuit 120 may be coupled between the low-voltage control logic 110 and the high-side switch control circuit 130. The high-side signal forwarding circuit 120 may be configured to provide an internal pulsed high-side control signal S from the low-voltage control logic 110 to the high-side switch control circuit 130 across the insulation barrier. HS,int In other words, the high-side signal forwarding circuit 120 transmits the internal pulse high-side control signal S across the isolation barrier. HS,int Forwarded from the low voltage control logic 110 to the high side switch control circuit 130 .

[0040] Now refer to Figure 1B and Figure 1C The discussion details examples of how the above-discussed functionality of the low voltage control logic 110 , the high-side signal forwarding circuit 120 , the high-side switch control circuit 130 , and the low-side switch control circuit 150 may be implemented.

[0041] In order to HS Generates an internal pulse high-side control signal S HS,int The low voltage control logic 110 may be based on the high side control signal S HS The leading edge of the internal pulse generates the high-side control signal S HS,int Therefore, due to the high-side control signal S HS The leading edge of indicates that the high-side switch 201 is to be turned on, so as indicated by the high-side control signal S HS As indicated, based on the high-side control signal S HS The generation of the first pulse of the leading edge enables the gate driver 100 to turn on the high-side switch 201 .

[0042] Figure 2A and Figure 2B The high-side control signal S HS Generates an internal pulse high-side control signal S HS,int Example of the first pulse. Figure 2A and Figure 2B Shown in Figure 2A and Figure 2B The high-side control signal S indicated by the first vertical dashed line in HS The leading edge of the internal pulse high-side control signal S HS,int In addition, Figure 2A and Figure 2B shows the internal pulsed high-side control signal S HS,int The first pulse of the high-side control output signal S HO The voltage becomes a value that turns on the high-side switch 201 .

[0043] To generate the first pulse as discussed above, the low voltage control logic 110 may include a first high-side edge-triggered pulse generator 1131. The first high-side edge-triggered pulse generator 1131 may be configured to generate a first pulse based on the high-side control signal S HS The leading edge of the internal pulse generates the high-side control signal S HS,int The first pulse.

[0044] The first high-side edge-triggered pulse generator 1131 can also be configured to be based on the high-side control signal S HS The trailing edge of the high-side switch control circuit generates a reset signal S HS,res And more accurately generate the high-side switch control circuit reset signal S HS,res The pulse is based on the high-side control signal S HS The trailing edge of the high-side switch control circuit generates a reset signal S HS,res , once the high-side control signal S HS Indicates that the high-side switch 201 is to be turned off, and the high-side switch control circuit resets the signal S HS,res The high-side switch control circuit 130 can then turn off the high-side switch 201 and disable the high-side protection function.

[0045] For example, in Figure 2A The corresponding generated high-side switch control circuit reset signal S is shown in HS,res Example. Figure 2A The third vertical dashed line indicates the high-side control signal S HS As can be seen, when the high-side control signal S HS The high-side switch control circuit resets the signal S at the trailing edge of HS,res Therefore, the high-side control signal S HO The voltage becomes a value that turns off the high-side switch 201 .

[0046] In order to HS and common protection function blanking control signal S PBL Generates an internal pulse high-side control signal S HS,int The second pulse of the low voltage control logic 110 can be obtained by comparing the high side ramp signal S HS,ramp and common protection function blanking control signal S PBL To generate the internal pulse high-side control signal S HS,int The second pulse.

[0047] Upon receiving the high-side control signal S HS At the leading edge of the high side ramp-up signal S HS,ramp can have a non-zero signal slope. In the context of the present disclosure, a non-zero signal slope refers to making the high-side ramp-up signal S HS,rampThe slope of the value of changes from an initial value to a final value at a constant rate. The initial value can be zero. Depending on whether the low voltage control logic 110 is implemented with positive logic (i.e., logic that indicates a logical "1" with a positive value) or negative logic (i.e., logic that indicates a logical "1" with a negative value), the final value can be a positive value or a negative value. Therefore, depending on the type of logic used by the low voltage control logic 110, the non-zero slope can be a positive slope or a negative slope. Based on the non-zero slope, the high side ramp-up signal S HS,ramp The value of the high-side control signal S HS increases after the leading edge.

[0048] The low voltage control logic 110 can increase the high side ramp signal S HS,ramp With the blanking control signal S by the common protection function PBL The reference value is provided for comparison. HS,ramp The value of the high-side control signal S HS The high-side ramp-up signal S HS,ramp The value may eventually exceed the value of the common protection function blanking control signal S PBL Provides a reference value. Once the high-side ramp-up signal S HS,ramp The value exceeds the blanking control signal S by the common protection function PBL Provided the reference value, the low voltage control logic 110 can generate an internal pulse high-side control signal S HS,int The second pulse.

[0049] Figure 2A and Figure 2B The high-side control signal S HS and common protection function blanking control signal S PBL Generates an internal pulse high-side control signal S HS,int As discussed above, in Figure 2A and Figure 2B The high-side control signal S is indicated by the first vertical dashed line HS Therefore, Figure 2A and Figure 2B The high-side ramp signal S HS,ramp The value of the first vertical dashed line is related to the high-side ramp-up signal S HS,ramp The intersection points begin to increase.

[0050] By using the common protection function blanking control signal S PBL as a reference value and compare it with the leading edge triggered high side ramp signal S HS,ramp By comparison, the control signal S can be blanked based on the common protection function PBL The value of the internal pulse high-side control signal S HS,intThe time between the first pulse and the second pulse. If the common protection function blanks the control signal S PBL The value is chosen to be close to the high-side ramp signal S HS,ramp The initial value of the high-side ramp-up signal S HS,ramp Earlier than the common protection function blanking control signal S PBL If the common protection function blanks the control signal S PBL The value is chosen to be close to the high-side ramp signal S HS,ramp The final value of the high-side ramp-up signal S HS,ramp Later than the common protection function blanking control signal S PBL Therefore, the control signal S can be blanked based on the common protection function PBL The value of the high-side ramp signal S HS,ramp Exceeding the common protection function blanking control signal S PBL This in turn determines the time point at which the internal pulse high-side control signal S is generated. HS,int In other words, the common protection function blanks the control signal S PBL The reference value provided determines the internal pulse high-side control signal S HS,int The time point of the second pulse of , which determines the duration of the blanking time.

[0051] In order to HS and common protection function blanking control signal S PBL Generates an internal pulse high-side control signal S HS,int The low voltage control logic 110 may include a high side protection function activation signal circuit. The high side protection function activation signal circuit may include a high side leading edge trigger ramp circuit 1111, a high side ramp signal comparator 1121, and a second high side edge trigger pulse generator 1132. The high side leading edge trigger ramp circuit 1111 may be configured to respond to the high side control signal S HS The leading edge provides a high-side ramp-up signal S HS,ramp The high-side ramp signal comparator 1121 may be configured to convert the high-side ramp signal S HS,ramp With the common protection function blanking control signal S PBL Based on the comparison, the high-side ramp signal comparator 1121 may be configured to output a high-side comparison signal S HS,comp For example, Figure 2A and Figure 2B As shown in the figure, the high side comparison signal S HS,comp Indicates the high side ramp-up signal S HS,ramp Whether it exceeds the blanking control signal S by the common protection function PBL More precisely, the high-side comparison signal SHS,comp The leading edge of the high-side ramp-up signal S HS,ramp exceeds the blanking control signal S by the common protection function PBL The time point of the reference value provided, and thus indicates the end of the blanking time. Therefore, the second high-side edge-triggered pulse generator 1132 can be configured to be based on the high-side comparison signal S HS,comp The leading edge of the internal pulse generates the high-side control signal HS,int The second pulse.

[0052] In order to provide the outputs of the first high-side edge-triggered pulse generator 1131 and the second high-side edge-triggered pulse generator 1132 as a single output of the low voltage control logic 110, and thus as an internal pulse high-side control signal S HS,int The low voltage control logic 110 may include a high-side OR gate 1151. The high-side OR gate 1151 may have two inputs coupled to the first high-side edge-triggered pulse generator 1131 and the second high-side edge-triggered pulse generator 1132, respectively. Therefore, the high-side OR gate 1151 may output two pulses as the internal pulse high-side control signal S HS,int .

[0053] As discussed above, in order to LS and common protection function blanking control signal S PBL Generates low-side protection function activation signal S LS,PA , the low voltage control logic 110 can compare the low side ramp signal S LS,ramp and common protection function blanking control signal S PBL After receiving the low-test control signal S LS The leading edge of the low-side ramp-up signal S LS,ramp has a non-zero signal slope. Therefore, once the low-side ramp-up signal S LS,ramp The value has exceeded the blanking control signal S PBL Provides the reference value, low side protection function activation signal S LS,PA In other words, the low-side protection function activation signal S LS,PA Can be similar to the internal pulse high-side control signal S HS,int The second pulse of the low side protection function activation signal S is generated by omitting the second high side edge trigger pulse generator 1132. More precisely, the low side protection function activation signal S LS,PA Therefore, the high-side comparison signal S HS,comp is generated in the same way and can therefore also be referred to as the low-side comparison signal S LS,comp .exist Figure 1B By carrying the low side comparison signal S LS,compThe signal line is designated as the external low-side protection function activation signal S of the low voltage control logic 110. LS,PA shows this fact.

[0054] Therefore, the low voltage control logic 110 may include a logic circuit configured to generate the low side protection function activation signal S as discussed above. LS,PA To this end, the low-side protection function activation signal circuit may include a low-side leading edge trigger ramp-up circuit 1112 and a low-side ramp-up signal comparator 1122. The low-side leading edge trigger ramp-up circuit 1112 may be configured to respond to the low-side control signal S LS The leading edge provides a low-side ramp-up signal S LS,ramp The low-side ramp signal comparator 1122 may be configured to convert the low-side ramp signal S LS,ramp With the common protection function blanking control signal S PBL A comparison is performed and a low-side protection function activation signal S is output based on the comparison. LS,PA .

[0055] Regarding the low-side control signal S LS , Figure 1B The low voltage control logic 110 of the example may be configured to convert the low side control signal S LS forwarded to the control terminal of the low-side switch 202 as an internal pulsed low-side control signal S LS,int .

[0056] Figure 1B It shows that due to Figure 1B The fact that no isolation barrier is provided between the low voltage control logic 110 and the low side switch control circuit 150 in the gate driver 100 is used to generate the internal pulse high side control signal S HS,int Different ways of low side protection function activation signal S LS,PA The generation and low-side control signal S LS In an example of the gate driver 100 of the present disclosure in which an isolation barrier is also provided between the low voltage control logic 110 and the low side switch control circuit 150, the low voltage control logic 110 may generate a high side control signal S HS,int Similar low-side protection function activation signal S LS,PA In such an example of the gate driver 100 of the present disclosure, the low-side protection function activation signal S LS,PA Correspondingly, it can also be called the internal pulse low-side control signal S LS,int , internal pulse low side control signal S LS,int can have an internal pulsed high-side control signal S HS,intIn addition, in such an example of the gate driver 100, the low voltage control logic 110 may be similar to the high side switch control circuit reset signal S HS,res The generation of the low-side switch control circuit reset signal S LS,res . Figure 1C An example of such a gate driver 100 is shown in .

[0057] In addition to the already Figure 1B In addition to the components of the low voltage control logic 110 discussed above, Figure 1C The low voltage control logic 110 further includes a first low side edge trigger pulse generator 1133, a second low side edge trigger pulse generator 1134 and a low side OR gate 1152, which correspond to the first high side edge trigger pulse generator 1131, the second high side edge trigger pulse generator 1132 and the high side OR gate 1151, respectively. Therefore, the second low side edge trigger pulse generator 1134 can be included in the low side protection function activation signal circuit.

[0058] exist Figure 1A and Figure 1B In the example of , the high-side signal forwarding circuit 120 is implemented using a level shifter including a high-side set transistor 121 and a high-side reset transistor 122. The high-side set transistor 121 receives the internal pulse high-side control signal S at the control terminal of the high-side set transistor 121. HS,int , and thus the voltage source V B is coupled to the high-side switch control circuit 130. Therefore, the high-side set transistor 121 turns the internal pulse high-side control signal S HS,int Shift to voltage source V B The voltage level of the high-side reset transistor 122 is set to the high-side reset transistor 122, and the low voltage control logic 110 is isolated from the high-side switch control circuit 130 based on the isolation between the control terminal of the high-side reset transistor 121 and the load path. Similarly, the high-side reset transistor 122 receives the high-side switch control circuit reset signal S at the control terminal of the high-side reset transistor 122. HS,res , and reset the high-side switch control circuit signal S HS,res Shift to voltage source V B The voltage level of the high-side switch control circuit 130 is isolated from the low-voltage control logic 110.

[0059] It should be understood that Figure 1B and Figure 1C The implementation of the high-side signal forwarding circuit 120 as a level conversion circuit is provided as an example only. The high-side signal forwarding circuit 120 can also be implemented as a coreless transformer, an optocoupler, a solid-state relay, or a high-side control signal S capable of transmitting an internal pulse across the isolation barrier. HS,intand the high-side switch control circuit reset signal S HS,res Any other type of circuitry that also ensures isolation of the low voltage control logic 110 from the high side switch controller circuit 130 .

[0060] like Figure 1C As shown in , if an isolation barrier also exists between the low voltage control logic 110 and the low-side switch control circuit 150 , the gate driver 100 may further include a low-side signal forwarding circuit 140 . Figure 1C The low-side signal forwarding circuit 140 in the example of is implemented in the same manner as the high-side signal forwarding circuit 120, namely as a circuit including receiving an internal pulse low-side control signal S at a control terminal of a low-side set transistor 141. LS,int The low-side set transistor 141 and the low-side reset transistor 142 receive the low-side switch control circuit reset signal S at the control terminal. LS,res The low-side reset transistor 142 is a level conversion circuit. Similar to the high-side signal forwarding circuit 120, the low-side signal forwarding circuit 140 can be composed of a low-side control signal S that can forward an internal pulse across the isolation barrier. LS,int and the low-side switch control circuit reset signal S LS,res The invention can be implemented by any type of circuit that simultaneously ensures isolation of the low voltage control logic 110 from the low side switch control circuit 150 .

[0061] As mentioned above Figure 1A As discussed, the high-side switch control circuit 130 is configured to be based on the internal pulse high-side control signal S HS,int The first pulse of turns on the high-side switch 201 and enables the high-side protection function, and based on the internal pulse high-side control signal S HS,int The second pulse of activates the high-side protection function. To this end, the high-side switch control circuit 130 can be configured to latch the internal pulse high-side control signal S HS,int The first pulse of the internal pulse high-side control signal S HS,int In addition, if the internal pulse high-side control signal S is latched HS,int The high-side switch control circuit 130 may also be configured to respond to the high-side switch control circuit reset signal S HS,res The first pulse and the second pulse are unlocked to turn off the high-side switch 201 and disable the high-side protection function circuit.

[0062] In order to latch and unlock the internal pulse high-side control signal S HS,intIn some examples of the present disclosure, the high-side switch control circuit 130 may include a high-side protection function trigger 131 and a high-side switch control trigger 134. In addition, the high-side switch control circuit 130 may include a high-side protection function circuit 132, a high-side delay block 133, and a high-side driver stage 135.

[0063] The high-side switch control flip-flop 134 may have a set input, a reset input, and an output. The set input of the high-side switch control flip-flop 134 may be configured to receive the internal pulse high-side control signal S HS,int The reset input of the high-side switch control flip-flop 134 may be configured to receive a high-side switch control circuit reset signal S HS,res The output of the high-side switch control trigger 134 can be coupled to the control terminal of the high-side switch 201. Therefore, as long as the high-side switch control trigger 134 latches the internal pulse high-side control signal S HS,int With the first pulse of , the output of the high-side switch controller trigger 134 keeps the high-side switch 201 turned on.

[0064] The high-side protection function trigger 131 may have a set input, a reset input, an enable input, and an output coupled to the high-side protection function circuit 132. The set input of the high-side protection function trigger 131 may be configured to receive the internal pulse high-side control signal S HS,int The reset input of the high-side protection function trigger 131 can be configured to receive the high-side switch control circuit reset signal S HS,res The enable input of the high-side protection function trigger 131 may be configured to receive the output of the high-side switch control trigger 134. Thus, the high-side protection function trigger 131 may be configured to be activated based on the internal pulse high-side control signal S HS,int This is because the output of the high-side switch control trigger 134 can be enabled only after the high-side switch control trigger 134 has latched the internal pulse high-side control signal S HS,int The fact that the first pulse of the high-side protection function trigger 131 is provided to enable the high-side protection function trigger 131. Since the high-side protection function trigger 131 is controlled by the internal pulse high-side control signal S HS,int The first pulse of the high-side protection function is enabled, therefore, the trigger 131 is set to the internal pulse high-side control signal S when it receives the internal pulse high-side control signal S at the set input. HS,int When the first pulse of the high-side protection function is not enabled, the high-side protection function trigger 131 can only latch the internal pulse high-side control signal S HS,int Once the high-side protection function trigger 131 has latched the internal pulse high-side control signal S HS,intThe high-side protection function trigger 131 provides a signal value at the output to activate the high-side protection function circuit 132. In other words, the high-side protection function trigger 131 can be considered as the power supply of the high-side protection function circuit 132, and the high-side protection function circuit 132 is controlled by the internal pulse high-side control signal S HS,int The first pulse enables and based on the internal pulse high-side control signal S HS,int The second pulse is activated.

[0065] To further ensure that the high-side protection function trigger 131 only latches the internal pulse high-side control signal S HS,int The high side delay block 133 may be coupled between the output of the high side switch control trigger 134 and the enable input of the high side protection function trigger 131. The high side delay block 133 may delay the transition of the signal provided at the output of the high side switch control trigger 134. Thus, the high side delay block 133 may be based on the latched internal pulse high side control signal S HS,int The first pulse of the trigger 131 is used to delay enabling the high-side protection function.

[0066] The high-side protection function circuit 132 can be configured to detect desaturation of the high-side switch 201 and turn off the high-side switch 201 based on the detected desaturation. To this end, the high-side protection function circuit 132 can be coupled to the first load terminal of the high-side switch 201 to monitor the load current I L,201 In addition, the high-side protection function circuit 132 can be coupled to the high-side driver stage 135. Once the high-side protection function circuit 132 detects the load current I L,201 Exceeding the desaturation threshold I TH,DESAT , the high-side protection function circuit 132 provides a high-side disable signal S to the high-side driver stage 135. 132 In order to disable the high-side driver stage 135 and turn off the high-side switch 201, regardless of the internal pulse high-side control signal S HS,int , and therefore regardless of the high-side control signal S HS .

[0067] It will be understood that the high-side protection function circuit 132 can be any kind of protection function configured to detect a fault condition of the high-side switch 201. Therefore, the high-side protection function circuit 132 is only described as desaturation detection as an example. The gate driver 100 can adopt any kind of protection function suitable for protecting the high-side switch 201. In addition, it will be understood that in some examples of the present disclosure, the gate driver 100 may include more than one high-side protection function circuit 132, which can all be based on a common protection function blanking control signal S PBL Defined blanking time control.

[0068] The high-side driver stage 135 may be coupled between the high-side switch control trigger 134 and the control terminal of the high-side switch 201. In response to the latched internal pulse high-side control signal S HS,int The first pulse of the internal pulse high-side control signal S HS,int The second pulse is the high-side disable signal S 132 Override, otherwise as long as the high-side switch control trigger 134 provides the latched internal pulse high-side control signal S to the high-side driver stage 135 HS,int The high-side driver stage 135 can provide a high-side control output signal S to the control terminal of the high-side switch 201 at a value that turns on the high-side switch 201 and keeps it turned on. HO .

[0069] Figure 2A and Figure 2B Examples of the various signals discussed above with respect to exemplary functionality of the high-side switch control circuit 130 are provided. More specifically, Figure 2A and Figure 2B The signal provided at the enable input of the high-side protection function trigger 131 (ie, the enable signal 131E), the signal provided at the output of the high-side protection function trigger 131 (ie, the activation signal 131Q), the high-side switch load current I L,201 , high side disable signal S 132 and the high-side control output signal S HO .

[0070] Figure 2A and Figure 2B The enable signal 131E in both is relative to the internal pulse high-side control signal S HS,int The first pulse of del Since the signal 131E is based on the internal pulse high-side control signal S latched by the high-side switch control flip-flop 134 HS,int The first pulse of the enable signal 131E is maintained at the value of enabling the high-side protection function trigger 131 until the high-side switch control trigger 134 is reset by the high-side switch control circuit reset signal S HS Reset. Figure 2A and Figure 2B The third dashed line and the delay time t del As shown, the reset may also be delayed by a high side delay block 133 .

[0071] The activation signal 131Q as the output signal of the high-side protection function trigger 131 is connected to the latched internal pulse high-side control signal S HS,int The second pulse corresponds to Figure 2A and Figure 2BThe second dotted line in the two shows that the activation signal 131Q appears when the internal pulse high-side control signal S HS,int The activation signal 131Q is maintained at this value until the high-side protection function trigger 131 is reset by the high-side switch control circuit reset signal S HS,res Reset.

[0072] Once the activation signal 131Q assumes a value that causes the high-side protection function circuit 132 to activate, the high-side protection function circuit 132 can detect the desaturation of the high-side switch 201. Therefore, the high-side protection function circuit 132 starts to monitor the high-side switch load current I L,201 .exist Figure 2A Mid- and high-side switch load current I L,201 When the high-side switch 201 is turned on, it starts to increase slowly but never reaches the desaturation threshold I TH,DESAT , until the high-side control signal S HS Indicates that the high-side switch 201 is to be turned off. Therefore, Figure 2A The high-side disable signal S 132 There is no indication to the high-side driver stage 135 that the high-side switch 201 is to be turned off. The high-side switch 201 is therefore only turned off when the high-side control signal S HS The high-side switch 201 is turned off only when it is instructed to be turned off.

[0073] exist Figure 2B Mid- and high-side switch load current I L,201 When the high-side switch 201 is turned on, the desaturation threshold I TH,DESAT However, in order to avoid erroneous shutdown during the switching of the high-side switch 201, the high-side disable signal S 132 There is no indication to the high-side driver stage 135 that the high-side switch 201 is to be turned off until the blanking time t blank has expired. During the blanking time t blank At maturity, Figure 2B The high-side switch load current I L,201 Still exceeds the desaturation threshold I TH,DESAT Therefore, since the high-side protection circuit 132 is in the blanking time t blank is activated when it expires, so the high-side protection function circuit 132 outputs the high-side disable signal S at a value indicating to the high-side driver stage 135 that the high-side switch 201 is to be turned off. 132 Regardless of the latched internal pulse high-side control signal S HS,int This is controlled by the high-side output signal S HO The shaded area shows where the high-side control output signal S HO has a value that turns off the high-side switch 201, regardless of the high-side control signal S HSIndicates that the high-side switch 201 should be turned on.

[0074] In conclusion, Figure 2A 1 shows an example of the signals of the gate driver 100, wherein the high-side protection function circuit 132 is blanked by the common protection function control signal S PBL Defined blanking time t blank After the expiration, no desaturation event of the high-side switch 201 is detected. Figure 2B 1 shows an example of the signals of the gate driver 100, wherein the high-side protection function circuit 132 is blanked by the common protection function control signal S PBL Defined blanking time t blank After the expiration, a desaturation event of the high-side switch 201 is detected.

[0075] Depending on the isolation requirements between the low voltage control logic 110 and the low side switch control circuit 150, the low side switch control circuit 150 may be, for example, Figure 1B As shown in or Figure 1C This is done as shown in Figure 1B In the embodiment, the low-side switch control circuit 150 may include a low-side protection function circuit 152 and a low-side driver stage 155 corresponding to the high-side protection function circuit 132 and the high-side driver stage 135, respectively. LS,PA To activate the low-side protection function circuit 152, and if the low-side protection function circuit 152 detects the desaturation of the low-side switch 202, the low-side protection function circuit 152 may generate a low-side disable signal S 152 to deactivate the low-side driver stage 155. Figure 1C , the low-side switch control circuit 150 may further include a low-side protection function trigger 151, a low-side delay block 153, and a low-side switch control trigger 154 corresponding to the high-side protection function trigger 131, the high-side delay block 133, and the high-side switch control trigger 134, respectively. In other words, similar to the high-side switch control circuit 130 and the internal pulse high-side control signal S discussed above, HS,int , Figure 1C The low-side switch control circuit 150 is configured to latch the internal pulse low-side control signal S based on LS,int The first pulse and the second pulse of the low-side protection function circuit 152 are activated and the low-side switch 202 is controlled.

[0076] Although Figure 2A and Figure 2B The example signals of are related to the high-side switch control circuit 130 , but it will be understood that these examples apply equally to the corresponding signals of the low-side switch control circuit 150 .

[0077] It should be noted that the foregoing discussion of exemplary implementations of the high-side switch control circuit 130 and the low-side switch control circuit 150 is provided only as an example of an implementation based on the internal pulse high-side control signal S HS,int , low side protection function activation signal S LS,PA and common protection function blanking control signal S PBL An example of controlling the high-side switch 201 and the low-side switch 202. HS and the low-side control signal S LS to control the half bridge 200 and to blank the control signal S by the common protection function PBL The reference value defines the blanking time t blank The high-side switch control circuit 130 and the low-side switch control circuit 150 can be implemented in any manner to activate their corresponding protection functions after expiration. For example, the function of the high-side switch control circuit 130 does not need to be based on latching the internal pulse high-side control signal S HS,int However, other means of maintaining the value associated with the pulse may be used to control the high-side switch 201 and activate and enable the high-side protection function circuit 132 until the high-side control signal S HS It is indicated to turn off the high-side switch 201 and deactivate the high-side protection function circuit 132 .

[0078] Figure 3A and Figure 3B A method 300 for driving the half-bridge 200 is shown. The method 300 may be performed by Figures 1A to 1C The gate driver 100 adopts.

[0079] In step 301, the method 300 receives a high-side control signal S HS , low side control signal S LS and common protection function blanking control signal S PBL .

[0080] In step 302 , the method 300 performs a control based on the high-side control signal S HS and common protection function blanking control signal S PBL Generates an internal pulse high-side control signal S HS,int Step 302 may include step 302a, in which the method 300 may be based on the high-side control signal S HS The leading edge of the internal pulse generates the high-side control signal S HS,int Step 302 may further include step 302b, in which the method 300 may compare the high side ramp signal S HS,ramp and common protection function blanking control signal S PBL To generate the internal pulse high-side control signal S HS,int The second pulse.

[0081] In step 303 , method 300 performs a control based on the low-side control signal S LS and common protection function blanking control signal S PBL To generate the low side protection function activation signal S LS,PA Step 303 may include step 303a, in which the method 300 may compare the low-side ramp-up signal S LS,ramp and common protection function blanking control signal S PBL .

[0082] In step 304 , method 300 performs a control based on the internal pulse high-side control signal S HS,int To control the high-side switch 201. Step 304 may include step 304a, in which the method 300 may be based on latching the internal pulse high-side control signal S HS,int The first pulse of the high-side switch 201 is turned on. Step 304 may also include step 304b, in which the method 300 may unlock the internal pulse high-side control signal S based on the unlocking HS,int The first pulse of is used to turn off the high-side switch 201 .

[0083] In step 305 , method 300 performs a control based on the internal pulse high-side control signal S HS,int The first pulse of the high-side protection function circuit 132 is enabled. The enabling of the high-side protection function circuit 132 in step 305 can also be based on the latched internal pulse high-side control signal S HS,int The first pulse.

[0084] In step 306 , method 300 controls the internal high-side pulse control signal S HS,int The second pulse of the high-side protection function circuit 132 is activated. The activation of the high-side protection function circuit 132 in step 306 can also be based on the latched internal pulse high-side control signal S HS,int The second pulse.

[0085] In step 307 , method 300 performs a control based on the low-side control signal S LS To control the low side switch 202 .

[0086] In step 308 , the method 300 activates the low-side protection function based on the signal S LS,PA To activate the low-side protection function circuit 152. It should be noted that the method 300 can also be based on the low-side protection function activation signal S LS,PA to disable the low-side protection function circuit 152.

[0087] In step 309, the method 300 may generate a high-side switch control circuit reset signal S HS,res, which can be configured to reset the high-side switch control circuit 130 .

[0088] In step 310, the method 300 may generate a low-side switch control circuit reset signal S LS,res , which can be configured to reset the low-side switch control circuit 150 .

[0089] In step 311, method 300 may be based on responding to a high-side switch control circuit reset signal S HS,res The unlocking internal pulse high-side control signal S HS,int The first pulse and the internal pulse high-side control signal S HS,int The second pulse is used to disable the high-side protection function circuit 132.

[0090] It will be appreciated that in the examples of the present disclosure, the definition of the method 300 is limited to the internal pulse high-side control signal S HS,int The steps of latching and unlocking the first pulse and the second pulse of the storage can also be performed by the method 300, wherein the low-side protection function activation signal S LS,PA is implemented as an internal pulsed low-side control signal S LS,int .

[0091] Figure 4 A gate driver system 400 having multiple gate drivers 100_1, 100_2, 100_3 is shown. In this example, three gate drivers are shown, but the disclosure is not limited to this number. In addition, as an example, the three gate drivers are implemented as high-side drivers. In other embodiments, one or more low-side gate drivers may be present in the gate driver system 400. Figures 1A to 1C Each gate driver in the gate drivers 100_1, 100_2, and 100_3 is implemented in the manner described above.

[0092] Furthermore, in this example, three gate drivers 100_1, 100_2, 100_3 are integrated on a single chip having one low voltage region and a high voltage region corresponding to each gate driver. In an alternative implementation, the gate drivers may be integrated on different chips. In this case, the gate drivers may be integrated in the same package.

[0093] The gate driver system 400 includes a gate driver configured to receive a timing control signal S PBL The timing control signal input terminal is coupled to the timing control signal distribution line 401, and the timing control signal distribution line 401 is configured to transmit the timing control signal S PBLDistribution to multiple components. This may be particularly useful where the gate driver and / or other functional circuits are integrated on different chips in one package or arrangement, as this may help reduce the number of external pins that may be required to provide timing control signals to the respective circuits.

[0094] Each of the gate drivers 100_1, 100_2, 100_3 includes a corresponding low voltage control logic 110_1, 110_2, 110_3, and the low voltage control logic 110_1, 110_2, 110_3 is respectively configured to generate a corresponding high-side control signal S HS1 , S HS2 , S HS3 and receives the timing control signal S via the timing control signal distribution line 401 as part of the gate driver system 400 PBL Each corresponding low voltage control logic 110_1, 110_2, 110_3 is also configured to be based on the corresponding high side control signal S HS1 , S HS2 , S HS3 and timing control signal S PBL Generates the corresponding internal pulse high-side control signal S HS1,int , S HS2,int , S HS3,int In addition, each of the gate drivers 100_1, 100_2, 100_3 includes a corresponding high-side switch control circuit 130_1, 130_2, 130_3, which is coupled to the corresponding low-voltage pressure control logic 110_1, 110_2, 110_3 and is configured to control the high-side control signal S based on the corresponding internal pulse. HS1,int , S HS2,int , S HS3,int The corresponding drive signal output S HO1 , S HO2 , S HO3 To control the corresponding high-side switch ( Figure 4 Each high-side switch control circuit 130_1, 130_2, 130_3 includes a corresponding high-side support function circuit ( Figure 4 ), the high-side support function circuit is configured to be based on the corresponding internal pulse high-side control signal S HS1,int , S HS2,int , S HS3,int The first pulse is enabled and based on the corresponding internal high-side pulse control signal S HS1,int , S HS2,int , S HS3,int The second pulse is activated.

[0095] Figure 4 Also shown is an insulation barrier between the low voltage control logic 110_1, 110_2, 110_3 and the corresponding high side switch control circuit 130_1, 130_2, 130_3, which is configured to electrically isolate the low voltage control logic 110_1, 110_2, 110_3 from the corresponding high side switch control circuit 130_1, 130_2, 130_3. In addition, in this example, since different high side switch control circuits 130_1, 130_2, 130_3 of different gate drivers are integrated in one chip, an insulation barrier is provided between these circuits.

[0096] Each gate driver 100_1, 100_2, 100_3 further includes a corresponding high-side signal forwarding circuit 120_1, 120_2, 120_3 coupled between the corresponding low voltage control logic 110_1, 110_2, 110_3 and the corresponding high-side switch control circuit 130_1, 130_2, 130_3. The corresponding high-side signal forwarding circuit 120_1, 120_2, 120_3 is configured to transmit the corresponding internal pulse high-side control signal S across the insulation barrier. HS1,int , S HS2,int , S HS3,int Provided from the corresponding low voltage control logic 110_1 , 110_2 , 110_3 to the corresponding high side switch control circuit 130_1 , 130_2 , 130_3 .

[0097] On the other hand, a gate driver having a first voltage domain and a second voltage domain is proposed. The first voltage domain and the second voltage domain are electrically isolated from each other. The first voltage domain and the second voltage domain may refer to different reference potentials. The gate driver includes a first circuit residing in the first voltage domain, and includes a second circuit residing in the second voltage domain. The first circuit is configured to receive a first control signal and a timing control signal, and generate an internal pulse control signal based on the first control signal and the timing control signal. The internal pulse control signal may include a first pulse and a second pulse, wherein the time interval between the first pulse and the second pulse may be determined based on the timing control signal. The first circuit may include a signal forwarding circuit coupled between the first voltage domain and the second voltage domain and configured to transmit the internal pulse control signal from the first voltage domain to the second voltage domain. The second circuit is configured to receive the internal pulse control signal, and process, transmit and / or operate based on the internal pulse control signal. The second circuit may be configured to perform a control function based on the internal pulse control signal, for example, to control the switching state of a transistor, control the operating state of a protection function and / or a sensing function and / or a data transmission function residing in the second voltage domain.

[0098] For example, the first voltage domain may reference a common ground potential shared between the gate driver and other external electrical devices electrically connected to the gate driver, and the second voltage domain may reference a floating node that may have a variable potential that may depend on the operating state of the gate driver and / or other external devices electrically connected to the gate driver.

[0099] In some implementations, the signal forwarding circuit may be one of a level conversion circuit, a coreless transformer, an optocoupler, and a solid-state relay.

[0100] In some embodiments, a logic circuit such as a programmable logic array (PLC), a field programmable gate array (FPGA), a microcontroller unit (MCU), or an application-specific integrated circuit (ASIC) can be arranged in a first voltage domain and / or a second voltage domain and can be at least partially controlled based on a first control signal, a timing control signal, and / or an internal pulse control signal.

[0101] In some embodiments, the second circuit may be configured to determine the timing information based on receiving the internal pulse control signal. For example, the second circuit may determine the time interval between the first pulse and the second pulse or the time interval between other consecutive pulses as the timing information.

[0102] In some embodiments, the second circuit can be configured to latch the timing information and perform a function based on the timing information. In other embodiments, the second circuit can perform a function exactly once, or a predetermined number of times, or repeatedly based on the timing information until new timing information is determined according to the internal pulse control signal.

[0103] In some embodiments, the first voltage domain and the second voltage domain are electrically isolated from each other. In other embodiments, the isolation rating of the isolation region disposed between the first voltage domain and the second voltage domain can be at least 600V, or at least 1200V, or at least 2000V and can be as high as 5600V.

[0104] In some embodiments, the first circuit can be implemented corresponding to the low voltage control logic described herein. In some embodiments, the second circuit can be implemented corresponding to the high side switch control circuit described herein.

[0105] In some embodiments, the gate driver is monolithically integrated in a single chip. "Monolithically integrated" means, for example, that the gate driver is implemented on a single silicon (or other suitable material) substrate.

[0106] The present invention can also be illustrated by the following examples.

[0107] In an example, a gate driver is configured to drive a high-side switch, the gate driver comprising:

[0108] Low voltage control logic, which is configured to:

[0109] receiving a high-side control signal and a timing control signal; and

[0110] generating an internal pulsed high-side control signal based on the high-side control signal and the timing control signal;

[0111] A high-side switch control circuit is coupled to the low voltage control logic and is configured to control the high-side switch based on an internal pulse high-side control signal, the high-side switch control circuit including a high-side support function circuit, wherein the high-side support function circuit is configured to be enabled based on a first pulse of the internal pulse high-side control signal and to be activated based on a second pulse of the internal pulse high-side control signal.

[0112] Example gate drivers also include:

[0113] an insulation barrier between the low voltage control logic and the high side switch control circuit, the insulation barrier being configured to electrically isolate the low voltage control logic from the high side switch control circuit; and

[0114] A high-side signal forwarding circuit is coupled between the low voltage control logic and the high-side switch control circuit.

[0115] Therein, the high-side signal forwarding circuit is configured to provide an internal pulsed high-side control signal from the low voltage control logic to the high-side switch control circuit across the insulation barrier.

[0116] An example gate driver wherein the high-side signal forwarding circuit is one of a level shifting circuit, a coreless transformer, an optocoupler, and a solid-state relay.

[0117] The example gate driver according to any of the foregoing, wherein the low voltage control logic is further configured to:

[0118] generating a first pulse of the internal pulse high-side control signal based on the leading edge of the high-side control signal; and

[0119] By comparing the high-side ramp-up signal and the timing control signal (S PBL ) to generate the second pulse of the internal pulse high-side control signal. When the leading edge of the high-side control signal is received, the high-side ramp-up signal (S HS,ramp ) has a non-zero signal slope.

[0120] An example gate driver wherein the low voltage control logic comprises:

[0121] a first high-side edge-triggered pulse generator configured to generate a first pulse of the internal pulse high-side control signal based on a leading edge of the high-side control signal; and

[0122] A high-side support function activation signal circuit is configured to generate a second pulse of the internal pulse high-side control signal, the high-side support function activation signal circuit comprising:

[0123] a high-side leading-edge triggered ramp circuit configured to provide a high-side ramp signal in response to a leading edge of the high-side control signal;

[0124] a high-side ramp signal comparator configured to compare the high-side ramp signal with the timing control signal and output a high-side comparison signal based on the comparison; and

[0125] The second high-side edge-triggered pulse generator is configured to generate a second pulse of the internal pulse high-side control signal based on the leading edge of the high-side comparison signal.

[0126] An example gate driver wherein the low voltage control logic is further configured to generate a high side switch control circuit reset signal configured to reset the high side switch control circuit.

[0127] An example gate driver wherein the first high-side edge triggered pulse generator is further configured to generate a high-side switch control circuit reset signal based on a trailing edge of the high-side control signal.

[0128] An example gate driver wherein the high-side switch control circuit is further configured to:

[0129] turning on the high-side switch and enabling the high-side support function circuit based on the first pulse of the latched internal pulse high-side control signal; and

[0130] The high-side support function circuit is activated based on the second pulse of the latched internal pulse high-side control signal.

[0131] An example gate driver wherein the high-side switch control circuit is further configured to:

[0132] Based on unlocking the first pulse of the internal pulsed high side control signal and the second pulse of the internal pulsed high side control signal in response to the high side switch control circuit reset signal, the high side switch is turned off and the high side support function circuit is disabled.

[0133] An example gate driver wherein the high-side switch control circuit further comprises:

[0134] a high-side switch control flip-flop having a set input and a reset input and configured to receive an internal pulsed high-side control signal at the set input and a high-side switch control circuit reset signal at the reset input; and

[0135] A high-side support function flip-flop has a set input, a reset input, and an enable input, and is configured to receive an internal pulse high-side control signal at the set input, a high-side switch control circuit reset signal at the reset input, and an output of the high-side switch control flip-flop at the enable input.

[0136] Example gate driver where:

[0137] The high-side support function circuit is configured to detect desaturation of the high-side switch and turn off the high-side switch based on the detected desaturation.

[0138] The example gate driver according to any of the preceding items, further configured to drive a half-bridge comprising a high-side switch and a low-side switch, wherein the low voltage control logic is further configured to:

[0139] receiving a low-side control signal; and

[0140] generating a low-side support function activation signal based on the low-side control signal and the timing control signal;

[0141] And the gate driver also includes:

[0142] A low-side switch control circuit is coupled to the low voltage control logic and is configured to control the low-side switch based on the low-side control signal, the low-side switch control circuit includes a low-side support function circuit, wherein the low-side support function circuit is configured to be activated based on the low-side support function activation signal.

[0143] An example gate driver wherein the low voltage control logic is further configured to:

[0144] The low-side support function activation signal is generated by comparing the low-side ramp-up signal and the timing control signal, the low-side ramp-up signal having a non-zero signal slope when a leading edge of the low-side control signal is received.

[0145] An example gate driver wherein the low voltage control logic further comprises:

[0146] A low-side support function activation signal circuit is configured to generate a low-side support function activation signal, the low-side support function activation signal circuit comprising:

[0147] a low-side leading edge triggered ramp circuit configured to provide a low-side ramp signal in response to a leading edge of the low-side control signal; and

[0148] A low-side ramp-up signal comparator is configured to compare the low-side ramp-up signal with the timing control signal and output a low-side support function activation signal based on the comparison.

[0149] An example gate driver according to any of the foregoing, wherein the high-side support function circuit is configured as a high-side protection function circuit, and / or the low-side control function circuit is configured as a low-side protection function circuit, and the timing control signal is configured as a common protection function blanking control signal.

[0150] The example gate driver as in any preceding description, wherein the gate driver is monolithically integrated in a single chip.

[0151] In another example, a system includes:

[0152] a half-bridge arrangement, which includes a high-side switch and a low-side switch, and

[0153] A gate driver configured to drive a half-bridge arrangement, comprising:

[0154] Low voltage control logic, which is configured to:

[0155] receiving a high-side control signal, a low-side control signal and a timing control signal;

[0156] generating an internal pulsed high-side control signal based on the high-side control signal and the timing control signal; and

[0157] generating a low-side support function activation signal based on the low-side control signal and the timing control signal;

[0158] a high-side switch control circuit coupled to the low voltage control logic and to a control terminal of the high-side switch and configured to control the high-side switch based on an internal pulsed high-side control signal, the high-side switch control circuit comprising a high-side support function circuit, wherein the high-side support function circuit is configured to be enabled based on a first pulse of the internal pulsed high-side control signal and activated based on a second pulse of the internal pulsed high-side control signal; and

[0159] A low-side switch control circuit is coupled to the low voltage control logic and to the control terminal of the low-side switch and is configured to control the low-side switch based on a low-side control signal, the low-side switch control circuit including a low-side support function circuit, wherein the low-side support function circuit is configured to be activated based on a low-side support function activation signal.

[0160] In another example, a gate driver system includes:

[0161] a timing control signal input terminal configured to receive a timing control signal;

[0162] a timing control signal distribution line connected to the timing control signal input terminal, and

[0163] A plurality of gate drivers, each gate driver being configured to drive a corresponding high-side switch. Each gate driver of the plurality of gate drivers comprises:

[0164] The low voltage control logic is configured as:

[0165] receiving a high-side control signal and receiving a timing control signal via a timing control signal distribution line; and

[0166] generating an internal pulsed high-side control signal based on the high-side control signal and the timing control signal; and

[0167] A high-side switch control circuit is coupled to the low voltage control logic and is configured to control the corresponding high-side switch based on the internal pulse high-side control signal, the high-side switch controller circuit includes a high-side support function circuit, wherein the high-side support function circuit is configured to be enabled based on a first pulse of the internal pulse high-side control signal and to be activated based on a second pulse of the internal pulse high-side control signal.

[0168] An example method for driving a high-side switch includes:

[0169] receiving a high-side control signal and a timing control signal;

[0170] generating an internal pulsed high-side control signal based on the high-side control signal and the timing control signal;

[0171] Controlling the high-side switch based on an internal pulsed high-side control signal;

[0172] enabling a high-side support function circuit based on a first pulse of an internal pulsed high-side control signal; and

[0173] The high-side support function circuit is activated based on the second pulse of the internal pulse high-side control signal.

[0174] In an example, the method further comprises:

[0175] generating a first pulse of the internal pulsed high-side control signal based on the leading edge of the high-side control signal;

[0176] A second pulse of the internal pulsed high-side control signal is generated by comparing the high-side ramp signal and the timing control signal, the high-side ramp signal having a non-zero signal slope upon receiving a leading edge of the high-side control signal.

[0177] In another example, an example gate driver is configured to drive a half-bridge including a high-side switch and a low-side switch, the example gate driver including: a low-voltage control logic configured to receive a high-side control signal, a low-side control signal, and a common protection function blanking control signal, generate an internal pulse high-side control signal based on the high-side control signal and the common protection function blanking control signal, and generate a low-side protection function activation signal based on the low-side control signal and the common protection function blanking control signal; a high-side switch control circuit coupled to the low-voltage control logic and configured to control the high-side switch based on the internal pulse high-side control signal, the high-side switch control circuit including a high-side protection function circuit, wherein the high-side protection function circuit is configured to be enabled based on a first pulse of the internal pulse high-side control signal and to be activated based on a second pulse of the internal pulse high-side control signal; and a low-side switch control circuit coupled to the low-voltage control logic and configured to control the low-side switch based on the low-side control signal, the low-side switch control circuit including a low-side protection function circuit, wherein the low-side protection function circuit is configured to be activated based on the low-side protection function activation signal.

[0178] The example gate driver may also include an insulation barrier between the low voltage control logic and the high side switch control circuit, the insulation barrier being configured to electrically isolate the low voltage control circuit from the high side switch control circuit, and a high side signal forwarding circuit coupled between the low voltage control logic and the high side switch control circuit, wherein the high side signal forwarding circuit may be configured to provide an internal pulsed high side control signal from the low voltage control logic to the high side switch control circuit across the insulation barrier.

[0179] In an example gate driver, the signal forwarding circuit may be one of a level shifting circuit, a coreless transformer, an optocoupler, and a solid-state relay.

[0180] In an example gate driver, the low voltage control logic may also be configured to generate a first pulse of the internal pulsed high side control signal based on a leading edge of the high side control signal, and to generate a second pulse of the internal pulsed high side control signal by comparing the high side ramp signal and the common protection function blanking control signal, the high side ramp signal having a non-zero signal slope when the leading edge of the high side control signal is received.

[0181] In an example gate driver, the low voltage control logic may include: a first high-side edge triggered pulse generator, which is configured to generate a first pulse of an internal pulse high-side control signal based on a leading edge of a high-side control signal; and a high-side protection function activation signal circuit, which is configured to generate a second pulse of the internal pulse high-side control signal, including: a high-side leading edge triggered ramp circuit, which is configured to provide a high-side ramp signal in response to a leading edge of the high-side control signal, a high-side ramp signal comparator, which is configured to compare the high-side ramp signal with a common protection function blanking control signal and output a high-side comparison signal based on the comparison, and a second high-side edge triggered pulse generator, which is configured to generate a second pulse of the internal pulse high-side control signal based on the leading edge of the high-side comparison signal.

[0182] In an example gate driver, the low voltage control logic may be further configured to generate a high side switch control circuit reset signal configured to reset the high side switch control circuit.

[0183] In an example gate driver, the first high-side edge-triggered pulse generator may be further configured to generate a high-side switch control circuit reset signal based on a trailing edge of the high-side control signal.

[0184] In an example gate driver, the high-side switch control circuit can also be configured to turn on the high-side switch and enable the high-side protection function circuit based on a first pulse of a latched internal pulse high-side control signal, and to activate the high-side protection function circuit based on a second pulse of a latched external pulse high-side control signal.

[0185] In an example gate driver, the high-side switch control circuit may also be configured to turn off the high-side switch and disable the high-side protection function circuit based on unlocking a first pulse of the internal pulse high-side control signal and a second pulse of the internal pulse high-side control signal in response to a high-side switch controller reset signal.

[0186] In an example gate driver, the high-side switch control circuit may further include: a high-side switch control trigger having a set input and a reset input, and configured to receive an internal pulse high-side control signal at the set input and a high-side switch control circuit reset signal at the reset input; and a high-side protection function trigger having a set output, a reset input, and an enable input, and configured to receive the internal pulse high-side control signal at the set input, the high-side switch control circuit reset signal at the reset input, and the output of the high-side switch control trigger at the enable input.

[0187] In an example gate driver, the high-side protection functional circuit may be configured to detect desaturation of the high-side switch and turn off the high-side switch based on the detected desaturation, and the low-side protection functional circuit may be configured to detect desaturation of the low-side switch and turn off the low-side switch based on the detected desaturation.

[0188] In the example gate driver, the low voltage control logic may be further configured to generate a low side protection function activation signal by comparing a low side ramp signal with a common protection function blanking control signal, the low side ramp signal having a non-zero signal slope upon receiving a leading edge of the low side control signal.

[0189] In an example gate driver, the low voltage control logic may further include a low side protection function activation signal circuit configured to generate a low side protection function activation signal, the low side protection function activation signal circuit including: a low side leading edge triggered ramp-up circuit, the low side leading edge triggered ramp-up circuit being configured to provide a low side ramp-up signal in response to a leading edge of the low side control signal; and a low side ramp-up signal comparator, which is configured to compare the low side ramp-up signal with a common protection function blanking control signal, and output the low side protection function activation signal based on the comparison.

[0190] In an example, a method for driving a half-bridge including a high-side switch and a low-side switch includes: receiving a high-side control signal, a low-side control signal, and a common protection function blanking control signal, generating an internal pulse high-side control signal based on the high-side control signal and the common protection function blanking control signal, generating a low-side protection function activation signal based on the low-side control signal and the common protection function blanking control signal, controlling the high-side switch based on the internal pulse high-side control signal, enabling the high-side protection function circuit based on a first pulse of the internal pulse high-side control signal, activating the high-side protection function circuit based on a second pulse of the internal pulse high-side control signal, controlling the low-side switch based on the low-side control signal, and activating the low-side protection function circuit based on the low-side protection function activation signal.

[0191] The example method may also include generating a first pulse of the internal pulse high-side control signal based on a leading edge of the high-side control signal, and generating a second pulse of the internal pulse high-side control signal by comparing the high-side ramp-up signal and a common protection function blanking control signal, wherein the high-side ramp-up signal has a non-zero signal slope when the leading edge of the high-side control signal is received.

[0192] In an example method, controlling the high-side switch may include turning on the high-side switch based on a first pulse of a latched internal pulse high-side control signal, enabling a high-side protection function circuit based on the first pulse of the latched internal pulse high-side control signal, and activating the high-side protection function circuit based on a second pulse of the latched internal pulse high-side control signal.

[0193] The exemplary method may also include generating a high-side switch control circuit reset signal configured to reset the high-side switch control circuit, and generating a low-side switch control circuit reset signal configured to reset the low-side switch control circuit.

[0194] In an exemplary method, controlling the high-side switch may also include turning off the high-side switch based on unlocking a first pulse of an internal pulse high-side control signal, and the exemplary method may also include disabling a high-side protection function circuit based on unlocking the first pulse of the internal pulse high-side control signal and a second pulse of the internal pulse high-side control signal in response to a reset signal of the high-side switch control circuit.

[0195] In this example method, generating the low side protection function activation signal may include comparing a low side ramp up signal and a common protection function blanking control signal, the low side ramp up signal having a non-zero signal slope upon receiving a leading edge of the low side control signal.

[0196] The foregoing description has been provided to illustrate a gate driver and method for driving a power switch using blanking time control. It should be understood that the description is in no way meant to limit the scope of the present disclosure to the precise embodiments discussed throughout the description. On the contrary, those skilled in the art will appreciate that the examples of the present disclosure may be combined, modified or compressed without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A gate driver (100) configured to drive a high-side switch (201), include: A low voltage control logic (110) configured to: Receives high-side control signal (S HS ) and timing control signal (S PBL ); as well as Based on the high-side control signal (S HS ) and the timing control signal (S PBL ) to generate the internal pulse high-side control signal (S HS,int ); A high-side switch control circuit (130) is coupled to the low voltage control logic (110) and is configured to control the internal pulse high-side control signal (S HS,int ) to control the high-side switch (201), the high-side switch control circuit (130) comprising a high-side support function circuit (132), wherein the high-side support function circuit (132) is configured to HS,int ) is enabled by the first pulse of the internal pulse high-side control signal (S HS,int ) and is activated by the second pulse.

2. The gate driver (100) according to claim 1, further comprising: include: an insulation barrier between the low voltage control logic (110) and the high side switch control circuit (130), the insulation barrier being configured to electrically isolate the low voltage control logic (110) from the high side switch control circuit (130); and A high-side signal forwarding circuit (120) is coupled between the low voltage control logic (110) and the high-side switch control circuit (130), The high-side signal forwarding circuit (120) is configured to transmit the internal pulse high-side control signal (S HS,int ) is provided from the low voltage control logic (110) to the high side switch control circuit (130).

3. The gate driver (100) according to any one of the preceding claims, in, The high-side signal forwarding circuit (120) is one of a level conversion circuit, a coreless transformer, an optical coupler and a solid-state relay.

4. The gate driver (100) according to any one of the preceding claims, in, The low voltage control logic (110) is further configured to: Based on the high-side control signal (S HS ) generates the internal pulse high-side control signal (S HS,int ) of the first pulse; as well as By comparing the high-side ramp signal (S HS,ramp ) and the timing control signal (S PBL ) to generate the internal pulse high-side control signal (S HS,int ) of the second pulse, upon receiving the high-side control signal (S HS ) at the leading edge of the high-side ramp-up signal (S HS,ramp ) has a non-zero signal slope.

5. The gate driver (100) according to claim 4, in, The low voltage control logic (110) comprises: The first high-side edge-triggered pulse generator (113 1 ), which is configured to be based on the high-side control signal (S HS ) to generate the internal pulse high-side control signal (S HS,int ) of the first pulse; and The high-side support function activates the signal circuit, which is configured to generate the internal pulse high-side control signal (S HS,int ), the high-side support function activation signal circuit comprises: High side leading edge triggered ramp circuit (111 1 ), the high side leading edge trigger ramp circuit (111 1 ) is configured to respond to the high-side control signal (S HS ) to provide the high-side ramp-up signal (S HS,ramp ); High side ramp signal comparator (112 1 ), which is configured to convert the high-side ramp-up signal (S HS,ramp ) and the timing control signal (S PBL ) is compared, and a high-side comparison signal (S HS,comp );as well as The second high-side edge-triggered pulse generator (113 2 ), which is configured to be based on the high-side comparison signal (S HS,comp ) generates the internal pulse high-side control signal (S HS,int ) of the second pulse.

6. The gate driver (100) according to any one of the preceding claims, in, The low voltage control logic (110) is further configured to generate a high side switch control circuit reset signal (S HS,res ), the high-side switch control circuit reset signal (S HS,res ) is configured to reset the high-side switch control circuit (130).

7. The gate driver (100) according to claim 6, in, The first high-side edge-triggered pulse generator (113 1 ) is also configured to be based on the high-side control signal (S HS ) to generate the high-side switch control circuit reset signal (S HS,res ).

8. The gate driver (100) according to any one of the preceding claims, in, The high-side switch control circuit (130) is further configured to: Based on latching the internal pulse high-side control signal (S HS,int ) to turn on the high-side switch (201) and enable the high-side support function circuit (132); as well as Based on latching the internal pulse high-side control signal (S HS,int ) to activate the high-side support functional circuit (132).

9. The gate driver (100) according to claim 8, in, The high-side switch control circuit (130) is further configured to: Based on the high-side switch control circuit in response to the reset signal (S HS,res ) while unlocking the internal pulse high-side control signal (S HS,int ) of the first pulse and the internal pulse high-side control signal (S HS,int ), turning off the high-side switch (201) and disabling the high-side support functional circuit (132).

10. The gate driver (100) according to any one of claims 8 and 9, in, The high-side switch control circuit (130) further includes: A high-side switch control flip-flop (134) having a set input and a reset input and configured to receive the internal pulse high-side control signal (S HS,int ) and receiving the high-side switch control circuit reset signal (S HS,res );as well as A high-side support function flip-flop (131) having a set input, a reset input and an enable input, and configured to receive the internal pulse high-side control signal (S) at the set input HS,int ), receiving the high-side switch control circuit reset signal at the reset input (S HS,res ) and receiving the output of the high-side switch control trigger (134) at the enable input.

11. The gate driver (100) according to any one of the preceding claims, in: The high-side support function circuit (132) is configured to detect desaturation of the high-side switch (201) and to turn off the high-side switch (201) based on the detected desaturation.

12. The gate driver (100) according to any one of the preceding claims, further configured to drive a half-bridge (200) comprising the high-side switch (201) and the low-side switch (202), in, The low voltage control logic (110) is further configured to: Receives low-side control signal (S LS );as well as Based on the low-side control signal (S LS ) and the timing control signal (S PBL ) to generate the low-side support function activation signal (S LS,PA ); And the gate driver (100) further comprises: A low-side switch control circuit (150) is coupled to the low voltage control logic (110) and is configured to control the low-side switch based on the low-side control signal (S LS ) to control the low-side switch (202), the low-side switch control circuit (150) comprising a low-side support function circuit (152), wherein the low-side support function circuit (152) is configured to activate the low-side support function based on the low-side support function activation signal (S LS,PA ) and is activated.

13. The gate driver (100) according to claim 12, in, The low voltage control logic (110) is further configured to: By comparing the low-side ramp-up signal (S LS,ramp ) and the timing control signal (S PBL ) to generate the low side support function activation signal (S LS,PA ), upon receiving the low-side control signal (S LS ) at the leading edge of the low-side ramp-up signal (S LS,ramp ) has a non-zero signal slope.

14. The gate driver (100) according to claim 13, in, The low voltage control logic (110) further includes: A low side support function activation signal circuit is configured to generate the low side support function activation signal (S LS,PA ), the low-side support function activation signal circuit comprises: Low-side leading edge triggered ramp circuit (111 2 ), the low side leading edge trigger ramp circuit (111 2 ) is configured to respond to the low-side control signal (S LS ) to provide the low-side ramp-up signal (S LS,ramp );as well as Low-side ramp signal comparator (112 2 ), which is configured to convert the low-side ramp-up signal (S LS,ramp ) and the timing control signal (S PBL ) is compared, and based on the comparison, the low-side support function activation signal (S LS,PA ).

15. The gate driver (100) according to any one of the preceding claims, in, The high-side support function circuit (132) is configured as a high-side protection function circuit, and / or the low-side support function circuit (152) is configured as a low-side protection function circuit, and the timing control signal (S PBL ) is configured as a common protection function blanking control signal.

16. The gate driver (100) according to any one of the preceding claims, in, The gate driver (100) is monolithically integrated in a single chip.

17. A system, include: a half-bridge arrangement comprising a high-side switch (201) and a low-side switch (202), and a gate driver configured to drive the half-bridge arrangement, the gate driver comprising: A low voltage control logic (110) configured to: Receives high-side control signal (S HS ), low-side control signal (S LS ) and timing control signal (S PBL ); Based on the high-side control signal (S HS ) and the timing control signal (S PBL ) to generate the internal pulse high-side control signal (S HS,int );as well as Based on the low-side control signal (S LS ) and the timing control signal (S PBL ) to generate the low-side support function activation signal (S LS,PA ); A high-side switch control circuit (130) is coupled to the low voltage control logic (110) and to a control terminal of the high-side switch (201), and is configured to control the high-side switch (201) based on the internal pulse high-side control signal (S HS,int ) to control the high-side switch (201), the high-side switch control circuit (130) comprising a high-side support function circuit (132), wherein the high-side support function circuit (132) is configured to HS,int ) is enabled by the first pulse of the internal pulse high-side control signal (S HS,int ) is activated by a second pulse; and A low-side switch control circuit (150) is coupled to the low voltage control logic (110) and to a control terminal of the low-side switch (202) and is configured to control the low-side switch (202) based on the low-side control signal (S LS ) to control the low-side switch (202), the low-side switch control circuit (150) comprising a low-side support function circuit (152), wherein the low-side support function circuit (152) is configured to activate the low-side support function based on the low-side support function activation signal (S LS,PA ) and is activated.

18. A gate driver system (400), include: a timing control signal input terminal configured to receive a timing control signal; a timing control signal distribution line (401) connected to the timing control signal input terminal, and A plurality of gate drivers (100), each gate driver being configured to drive a corresponding high-side switch, each gate driver of the plurality of gate drivers comprising: A low voltage control logic (110) configured to: Receive the corresponding high-side control signal (S HS ), and receives the timing control signal (S PBL );as well as Based on the high-side control signal (S HS ) and the timing control signal (S PBL ) to generate the internal pulse high-side control signal (S HS,int );as well as A high-side switch control circuit (130) is coupled to the low voltage control logic (110) and is configured to control the internal pulse high-side control signal (S HS,int ) to control the corresponding high-side switch (201), the high-side switch control circuit (130) comprising a high-side support function circuit (132), wherein the high-side support function circuit (132) is configured to control the corresponding high-side switch (201) based on the internal pulse high-side control signal (S HS,int ) is enabled by the first pulse of the internal pulse high-side control signal (S HS,int ) and is activated by the second pulse.

19. A method (300) for driving a high-side switch (201), include: Receive (301) a high-side control signal (S HS ) and timing control signal (S PBL ); Based on the high-side control signal (S HS ) and the timing control signal (S PBL ) to generate (302) an internal pulse high-side control signal (S HS,int ); Based on the internal pulse high-side control signal (S HS,int ) to control (304) the high-side switch (201); Based on the internal pulse high-side control signal (S HS,int ) to enable (305) the high-side support functional circuit (132); and Based on the internal pulse high-side control signal (S HS,int ) is used to activate (306) the high-side support functional circuit (132).

20. The method (300) of claim 19, further comprising: include: Based on the high-side control signal (S HS ) to generate (302a) the internal pulse high-side control signal (S HS,int ) of the first pulse; as well as By comparing the high-side ramp signal (S HS,ramp ) and the timing control signal (S PBL ) to generate (302b) the internal pulse high-side control signal (S HS,int ) of the second pulse, upon receiving the high-side control signal (S HS ) at the leading edge of the high-side ramp-up signal (S HS,ramp ) has a non-zero signal slope.

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