Level conversion circuit, chip and electronic device

Abstract

The present application is applicable to the field of electronic circuit technology, and provides a level conversion circuit, a chip and an electronic device. The level conversion circuit includes a first switch module, a second switch module, a latch module and a logic module, the source of the first PMOS tube and the source of the second PMOS tube in the latch module are both used to receive a first voltage, the gate of the first PMOS tube is respectively connected to the gate of the first NMOS tube, the drain of the second NMOS tube, the drain of the second PMOS tube, the logic module and the second switch module in the latch module, the drain of the first PMOS tube is respectively connected to the gate of the second PMOS tube, the gate of the second NMOS tube, the drain of the first NMOS tube and the first switch module, the source of the first NMOS tube and the source of the second NMOS tube are both used to connect to a first ground, the first switch module and the second switch module are both used to receive an input signal, and the first switch module and the second switch module are also both used to connect to a second ground.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits, and in particular, relates to a level conversion circuit, a chip and an electronic device. Background Art

[0002] In high-voltage DC-DC (Direct Current-Direct Current) power management chips, since the Rdson per unit area of ​​NMOS tubes (i.e., on-resistance, which refers to the resistance between the drain and source when the field effect tube is in the on state) is more than twice that of PMOS (positive channel Metal Oxide Semiconductor), NMOS tubes have the advantages of small area and low cost. Therefore, NMOS (N-Metal-Oxide-Semiconductor) tubes are often used as upper bridge switch tubes. Since NMOS tubes are high-voltage tubes, a level conversion circuit is required to convert the signal in the low-voltage domain VIN-GND into the signal in the high-voltage domain BOOT-SW to control the NMOS tube.

[0003] The minimum BOOT-SW voltage for the normal operation of the current level conversion circuit is the sum of the voltage between the gate and source of the low-voltage PMOS tube and the voltage between the gate and source of the high-voltage PMOS tube. Since the BOOT voltage is generated by the power supply voltage VIN according to the corresponding circuit, there is a minimum power supply voltage. Only when the power supply voltage VIN is greater than or equal to the minimum power supply voltage can the level conversion circuit work properly. Since the power supply voltage VIN will change, when the power supply voltage VIN is relatively low and less than the minimum power supply voltage of the level conversion circuit, the level conversion circuit cannot work properly. Therefore, it is urgent to develop a level conversion circuit that can work normally under low power supply voltage. Summary of the invention

[0004] The embodiments of the present application provide a level conversion circuit, a chip, and an electronic device, which can solve the problem that the current level conversion circuit cannot work normally under low power supply voltage.

[0005] In a first aspect, an embodiment of the present application provides a level conversion circuit, including a first switch module, a second switch module, a latch module and a logic module, wherein the source of a first PMOS tube and the source of a second PMOS tube in the latch module are both used to receive a first voltage, the gate of the first PMOS tube is respectively connected to the gate of a first NMOS tube, the drain of a second NMOS tube, the drain of the second PMOS tube, the logic module and the second switch module in the latch module, the drain of the first PMOS tube is respectively connected to the gate of the second PMOS tube, the gate of the second NMOS tube, the drain of the first NMOS tube and the first switch module, the source of the first NMOS tube and the source of the second NMOS tube are both used to connect to a first ground, the first switch module and the second switch module are both used to receive an input signal, and the first switch module and the second switch module are also both used to connect to a second ground;

[0006] When the input signal is at a high level, the second switch module is disconnected; the first switch module is turned on and provides a first level to the latch module; the latch module provides a second level to the logic module according to the first level; the logic module outputs a first target level according to the second level; when the input signal is at a low level, the first switch module is disconnected; the second switch module is turned on and provides a third level to the latch module; the latch module provides a fourth level to the logic module according to the third level; the logic module outputs a second target level according to the fourth level.

[0007] In a possible implementation manner of the first aspect, the level conversion circuit further includes a third switch module and a fourth switch module, the third switch module is arranged between the first switch module and the second ground, the fourth switch module is arranged between the second switch module and the second ground, the third switch module is used to receive the first signal, and the fourth switch module is used to receive the second signal;

[0008] When the input signal changes from a low level to a high level, the fourth switch module is disconnected according to the second signal; the third switch module is turned on according to the first signal and provides the first level to the latch module, and then is disconnected when the on-time reaches a first preset time; when the input signal changes from a high level to a low level, the third switch module is disconnected according to the first signal; the fourth switch module is turned on according to the second signal and provides the third level to the latch module, and then is disconnected when the on-time reaches a second preset time.

[0009] In a possible implementation manner of the first aspect, the level conversion circuit further includes a first signal generating module and a second signal generating module, the first signal generating module is connected to the third switch module, and the second signal generating module is connected to the fourth switch module;

[0010] The first signal generating module is used to receive the input signal and the clock signal, and generate a third signal according to the input signal and the clock signal; the second signal generating module is used to receive the input signal and the clock signal, and generate a fourth signal according to the input signal and the clock signal;

[0011] When the input signal is at a high level, the fourth switch module is disconnected according to the fourth signal; the third switch module is periodically turned on according to the third signal, and provides the first level to the latch module when turned on; when the input signal is at a low level, the third switch module is disconnected according to the third signal; the fourth switch module is periodically turned on according to the fourth signal, and provides the third level to the latch module when turned on.

[0012] In a possible implementation of the first aspect, the first signal generating module includes a NAND gate, a third PMOS tube, a third NMOS tube, a first resistor, a first capacitor and a first NOR gate, the first input end of the NAND gate is used to receive the input signal, the second input end of the NAND gate is used to receive the clock signal, the output end of the NAND gate is respectively connected to the gate of the third PMOS tube, the gate of the third NMOS tube and the first input end of the first NOR gate, the source of the third PMOS tube receives a power supply voltage, the drain of the third PMOS tube is connected to the first end of the first resistor, the second end of the first resistor is respectively connected to the drain of the third NMOS tube, the first end of the first capacitor and the second input end of the first NOR gate, the output end of the first NOR gate is connected to the third switch module, and the source of the third NMOS tube and the second end of the first capacitor are both connected to the second ground.

[0013] In a possible implementation manner of the first aspect, the second signal generating module includes a second NOR gate, a third NOR gate, a first inverter, a fourth PMOS tube, a fourth NMOS tube, a second resistor and a second capacitor, the first input end of the second NOR gate is used to receive the input signal, the second input end of the second NOR gate is used to receive the clock signal, the output end of the second NOR gate is connected to the input end of the first inverter, the output end of the first inverter is respectively connected to the gate of the fourth PMOS tube, the gate of the fourth NMOS tube and the first input end of the third NOR gate, the source of the fourth PMOS tube receives a power supply voltage, the drain of the fourth PMOS tube is connected to the first end of the second resistor, the second end of the second resistor is respectively connected to the drain of the fourth NMOS tube, the first end of the second capacitor and the second input end of the third NOR gate, the output end of the third NOR gate is connected to the fourth switch module, and the source of the fourth NMOS tube and the second end of the second capacitor are both connected to the second ground.

[0014] In a possible implementation of the first aspect, the third switch module includes a fifth NMOS tube, a gate of the fifth NMOS tube is used to receive the first signal, a drain of the fifth NMOS tube is connected to the first switch module, and a source of the fifth NMOS tube is used to connect to a second ground.

[0015] In a possible implementation of the first aspect, the fourth switch module includes a sixth NMOS tube, a gate of the sixth NMOS tube is used to receive the second signal, a drain of the sixth NMOS tube is connected to the second switch module, and a source of the sixth NMOS tube is used to connect to the second ground.

[0016] In a possible implementation of the first aspect, the first switch module includes a seventh NMOS tube, a gate of the seventh NMOS tube is used to receive the input signal, a drain of the seventh NMOS tube is respectively connected to the drain of the first PMOS tube, the gate of the second PMOS tube, the drain of the first NMOS tube and the gate of the second NMOS tube, and a source of the seventh NMOS tube is used to connect to the second ground.

[0017] In a second aspect, an embodiment of the present application provides a chip, comprising the level conversion circuit described in any one of the first aspects.

[0018] In a third aspect, an embodiment of the present application provides an electronic device, comprising the level conversion circuit described in any one of the first aspects.

[0019] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0020] An embodiment of the present application provides a level conversion circuit, including a first switch module, a second switch module, a latch module and a logic module, wherein the source of a first PMOS tube and the source of a second PMOS tube in the latch module are both used to receive a first voltage BOOT, the gate of the first PMOS tube is respectively connected to the gate of a first NMOS tube, the drain of a second NMOS tube, the drain of a second PMOS tube, the logic module and the second switch module in the latch module, the drain of the first PMOS tube is respectively connected to the gate of the second PMOS tube, the gate of the second NMOS tube, the drain of the first NMOS tube and the first switch module, the source of the first NMOS tube and the source of the second NMOS tube are both used to connect to a first ground SW, the first switch module and the second switch module are both used to receive an input signal, the input signal is a signal in a low voltage domain VIN-GND, and the first switch module and the second switch module are also both used to connect to a second ground GND.

[0021] When the input signal is at a high level, the second switch module is disconnected; the first switch module is turned on and provides the first level to the latch module; the latch module provides the second level to the logic module according to the first level; the logic module outputs the first target level according to the second level, and the first target level is the high level in the high voltage domain BOOT-SW. When the input signal is at a low level, the first switch module is disconnected; the second switch module is turned on and provides the third level to the latch module; the latch module provides the fourth level to the logic module according to the third level; the logic module outputs the second target level according to the fourth level, and the second target level is the low level in the high voltage domain BOOT-SW. It can be seen from the above that the level conversion circuit provided in the embodiment of the present application converts the signal in the low voltage domain VIN-GND into the signal in the high voltage domain BOOT-SW to control the upper bridge switch tube in the DC-DC power management chip.

[0022] At the same time, the present application improves the structure of the level conversion circuit so that the minimum BOOT-SW voltage for the normal operation of the level conversion circuit provided by the present application becomes the voltage between the gate and source of a PMOS tube in the latch module. Compared with the existing level conversion circuit, the minimum BOOT-SW voltage for the normal operation is the sum of the voltage between the gate and source of the low-voltage PMOS tube and the voltage between the gate and source of the high-voltage PMOS tube. The present application reduces the minimum BOOT-SW voltage for the normal operation of the level conversion circuit. In addition, since the BOOT voltage is generated by the power supply voltage VIN according to the corresponding circuit, when the minimum BOOT-SW voltage for the normal operation of the level conversion circuit is reduced, the minimum power supply voltage for the normal operation of the level conversion circuit will also become lower. Therefore, when the power supply voltage VIN becomes relatively low, it is still greater than the minimum power supply voltage of the level conversion circuit, and the level conversion circuit can still work normally. Therefore, the level conversion circuit provided in the embodiment of the present application can work normally under low power supply voltage.

[0023] It can be understood that the beneficial effects of the second to third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0025] Figure 1 It is a circuit connection diagram of an existing level conversion circuit;

[0026] Figure 2 This is a schematic diagram of the circuit connection for generating BOOT voltage;

[0027] Figure 3 is a principle block diagram of a level conversion circuit provided in an embodiment of the present application;

[0028] Figure 4 1 is a circuit connection diagram of a level conversion circuit provided in an embodiment of the present application;

[0029] Figure 5 is a principle block diagram of a level conversion circuit provided in another embodiment of the present application;

[0030] Figure 6 is the timing of the input signal, the first signal, the second signal and the output signal in this application Figure 1 ;

[0031] Figure 7 is the timing of the input signal, the first signal, the second signal and the output signal in this application Figure 2 ;

[0032] Figure 8 is the timing of the input signal, the first signal, the second signal and the output signal in this application Figure 3 ;

[0033] Fig. 9 is a circuit connection diagram of a level conversion circuit provided by another embodiment of the present application;

[0034] Fig.10 is a principle block diagram of a level conversion circuit provided in another embodiment of the present application;

[0035] Fig.11 is the timing of the input signal, clock signal, third signal, fourth signal and output signal in this application Figure 1 ;

[0036] Fig.12 is the timing of the input signal, clock signal, third signal, fourth signal and output signal in this application Figure 2 ;

[0037] Fig.13 is the timing of the input signal, clock signal, third signal, fourth signal and output signal in this application Figure 3 ;

[0038] Fig.14 is a circuit connection diagram of the first signal generating module in the present application;

[0039] Fig.15 It is a circuit connection diagram of the second signal generating module in this application.

[0040] In the figure: 10, a first switch module; 20, a second switch module; 30, a latch module; 40, a logic module; 50, a third switch module; 60, a fourth switch module; 70, a first signal generating module; 80, a second signal generating module. DETAILED DESCRIPTION

[0041] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0042] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0043] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0044] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0045] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0046] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0047] The circuit structure of the existing level conversion circuit is as follows Figure 1 As shown, it is used to convert the signal in the low-voltage domain VIN-GND into the signal in the high-voltage domain BOOT-SW, wherein P01-P04 are low-voltage PMOS tubes, N01-N02 are low-voltage NMOS tubes, PHV1-PHV2 are high-voltage PMOS tubes, and NHV1-NHV2 are high-voltage NMOS tubes. Figure 1 It can be seen that the minimum BOOT-SW voltage for the normal operation of the existing level conversion circuit is VGS_P02+VGS_PHV1, that is, the sum of the gate-source voltage of a low-voltage PMOS tube and the gate-source voltage of a high-voltage PMOS tube. Among them, VGS_P02 is the gate-source voltage of the P02 tube, and VGS_PHV1 is the gate-source voltage of the PHV1 tube. The BOOT voltage is usually generated by the power supply voltage VIN charging the capacitor C0 through the NVH3 tube (i.e., the high-voltage NMOS tube), see Figure 2 The structure shown. Therefore, the minimum power supply voltage for the normal operation of the level conversion circuit is the voltage between the gate and source of a low-voltage PMOS tube + the voltage between the gate and source of a high-voltage PMOS tube + the voltage between the gate and source of a high-voltage NMOS tube. And because the power supply voltage VIN will change, when the power supply voltage VIN is relatively low and less than the minimum power supply voltage of the level conversion circuit, the level conversion circuit cannot work properly.

[0048] In view of the above problems, the present application provides a level conversion circuit, such as Figure 3As shown, the level conversion circuit includes a first switch module 10, a second switch module 20, a latch module 30 and a logic module 40. The source of the first PMOS tube P1 and the source of the second PMOS tube P2 in the latch module 30 are both used to receive the first voltage BOOT. The gate of the first PMOS tube P1 is respectively connected to the gate of the first NMOS tube N1, the drain of the second NMOS tube N2, the drain of the second PMOS tube P2, the logic module 40 and the second switch module 20 in the latch module 30. The drain of the first PMOS tube P1 is respectively connected to the gate of the second PMOS tube P2, the gate of the second NMOS tube N2, the drain of the first NMOS tube N1 and the first switch module 10. The source of the first NMOS tube N1 and the source of the second NMOS tube N2 are both used to connect to the first ground SW. The first switch module 10 and the second switch module 20 are both used to receive the input signal IN, and the input signal is a signal in the low voltage domain VIN-GND. The first switch module 10 and the second switch module 20 are also used to connect to the second ground GND. It should be noted that the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1 and the second NMOS transistor N2 in the latch module 30 are all low voltage transistors. The logic module 40 works in the high voltage domain BOOT-SW.

[0049] Specifically, when the input signal IN is at a high level, the second switch module 20 is disconnected. The first switch module 10 is turned on and provides a first level to the latch module 30, wherein the first level is a low level. The latch module 30 provides a second level to the logic module 40 according to the first level, wherein the second level is a high level. More specifically, since the first level is a low level, according to the specific circuit structure of the latch module 30, the first PMOS tube P1 is disconnected, the second PMOS tube P2 is turned on, the first NMOS tube N1 is turned on, and the second NMOS tube N2 is disconnected, thereby latching the level at the drain of the first PMOS tube P1 at a low level, and latching the level at the drain of the second PMOS tube P2 at a high level, that is, providing a high level (i.e., a second level) to the logic module 40. The logic module 40 outputs a first target level according to the second level, wherein the first target level is a high level in the high voltage domain BOOT-SW, that is, a high level in the output signal OUT.

[0050] When the input signal IN is at a low level, the first switch module 10 is turned off. The second switch module 20 is turned on and provides a third level to the latch module 30, wherein the third level is a low level. The latch module 30 provides a fourth level to the logic module 40 according to the third level, wherein the fourth level is a low level. More specifically, according to the specific circuit structure of the latch module 30, the first PMOS tube is turned on, the second PMOS tube P2 is turned off, the first NMOS tube N1 is turned off, and the second NMOS tube N2 is turned on, thereby latching the level at the drain of the first PMOS tube P1 at a high level, and latching the level at the drain of the second PMOS tube P2 at a low level, that is, providing a low level (i.e., the fourth level) to the logic module 40. The logic module 40 outputs a second target level according to the fourth level, wherein the second target level is a low level in the high voltage domain BOOT-SW, that is, a low level in the output signal OUT.

[0051] As can be seen from the above, the level conversion circuit provided in the embodiment of the present application converts the signal in the low-voltage domain VIN-GND into the signal in the high-voltage domain BOOT-SW to control the upper bridge switch tube in the high-voltage DC-DC power management chip.

[0052] At the same time, the present application improves the structure of the level conversion circuit so that the minimum BOOT-SW voltage for the normal operation of the level conversion circuit provided by the present application becomes the voltage between the gate source of a low-voltage PMOS tube in the latch module 30. Compared with the minimum BOOT-SW voltage for the normal operation of the existing level conversion circuit, which is the sum of the voltage between the gate source of the low-voltage PMOS tube and the voltage between the gate source of the high-voltage PMOS tube, the present application reduces the minimum BOOT-SW voltage for the normal operation of the level conversion circuit. In addition, since the BOOT voltage is generated by the power supply voltage VIN according to the corresponding circuit, when the minimum BOOT-SW voltage for the normal operation of the level conversion circuit is reduced, the minimum power supply voltage for the normal operation of the level conversion circuit will also become lower, becoming the voltage between the gate source of a low-voltage PMOS tube + the voltage between the gate source of a high-voltage NMOS tube. Therefore, when the power supply voltage VIN becomes relatively low, it is still greater than the minimum power supply voltage of the level conversion circuit, and the level conversion circuit can still work normally. Therefore, the level conversion circuit provided in the embodiment of the present application can work normally under low power supply voltage.

[0053] In some embodiments, Figure 4As shown, the first switch module 10 includes a seventh NMOS transistor N7, the gate of the seventh NMOS transistor N7 is used to receive the input signal IN, the drain of the seventh NMOS transistor N7 is respectively connected to the drain of the first PMOS transistor P1, the gate of the second PMOS transistor P2, the drain of the first NMOS transistor N1 and the gate of the second NMOS transistor N2, and the source of the seventh NMOS transistor N7 is used to connect to the second ground GND. The seventh NMOS transistor N7 is a high-voltage transistor.

[0054] Specifically, when the input signal IN is at a high level, the seventh NMOS transistor N7 is turned on and provides the first level (ie, low level) to the latch module 30. When the input signal IN is at a low level, the seventh NMOS transistor N7 is turned off.

[0055] In some embodiments, Figure 4 As shown, the second switch module 20 includes a second inverter NOT2 and an eighth NMOS tube N8, the input end of the second inverter NOT2 is used to receive an input signal IN, the power supply end of the second inverter NOT2 receives a power supply voltage VIN, the ground end of the second inverter NOT2 is used to connect to the second ground GND, the output end of the second inverter NOT2 is connected to the gate of the eighth NMOS tube N8, and the drain of the eighth NMOS tube N8 is respectively connected to the gate of the first PMOS tube P1, the gate of the first NMOS tube N1, the drain of the second PMOS tube P2, the drain of the second NMOS tube N2 and the logic module 40. The source of the eighth NMOS tube N8 is used to connect to the second ground GND. Among them, the eighth NMOS tube N8 is a high-voltage tube.

[0056] Specifically, when the input signal IN is at a high level, the input signal IN is inverted by the second inverter NOT2 to become a low level, and the eighth NMOS transistor N8 is turned off. When the input signal IN is at a low level, the input signal IN is inverted by the second inverter NOT2 to become a high level, and the eighth NMOS transistor N8 is turned on and provides the third level (i.e., low level) to the latch module 30.

[0057] In some embodiments, Figure 4 As shown, the logic module 40 includes a third inverter NOT3 and a fourth inverter NOT4, the input end of the third inverter NOT3 is respectively connected to the gate of the first PMOS tube P1, the gate of the first NMOS tube N1, the drain of the second PMOS tube P2, the drain of the second NMOS tube N2 and the drain of the eighth NMOS tube N8, the output end of the third inverter NOT3 is connected to the input end of the fourth inverter NOT4, the signal output by the output end of the fourth inverter NOT4 is the output signal OUT, the power supply end of the third inverter NOT3 and the power supply end of the fourth inverter NOT4 both receive the first voltage BOOT, and the ground end of the third inverter NOT3 and the ground end of the fourth inverter NOT4 are both connected to the first ground SW.

[0058] Specifically, when the input signal IN is at a high level, the latch module 30 provides the second level to the logic module 40, wherein the second level is a high level, and the second level still outputs a high level after passing through the third inverter NOT3 and the fourth inverter NOT4 in sequence, that is, the first target level, that is, the high level in the output signal OUT. When the input signal IN is at a low level, the latch module 30 provides the fourth level to the logic module 40, wherein the fourth level is a low level, and the fourth level still outputs a low level after passing through the third inverter NOT3 and the fourth inverter NOT4 in sequence, that is, the second target level, that is, the low level in the output signal OUT.

[0059] In some embodiments, Figure 4 As shown, both the first NMOS tube N1 and the second NMOS tube have body diodes. When the input signal IN is at a high level, the seventh NMOS tube N7 is turned on. When the voltage at the first ground SW is higher than the voltage at the second ground GND, a static current will flow through the body diode in the first NMOS tube N1, resulting in an increase in the power consumption of the level conversion circuit. When the input signal IN is at a low level, the eighth NMOS tube N8 is turned on. When the voltage at the first ground SW is higher than the voltage at the second ground GND, a static current will flow through the body diode in the second NMOS tube N2, resulting in an increase in the power consumption of the level conversion circuit.

[0060] In order to avoid continuous consumption of static current, the present application adds a third switch module 50 and a fourth switch module 60 to the level conversion circuit. Figure 5 As shown, the level conversion circuit provided in the embodiment of the present application further includes a third switch module 50 and a fourth switch module 60. The third switch module 50 is arranged between the first switch module 10 and the second ground GND, and the fourth switch module 60 is arranged between the second switch module 20 and the second ground GND. The third switch module 50 is used to receive the first signal on-pulse1, and the fourth switch module 60 is used to receive the second signal off-pulse2. The first signal on-pulse1 and the second signal off-pulse2 are both generated by the input signal IN. Figure 6 As shown, the high level of the output signal OUT is the first voltage BOOT, the low level of the output signal OUT is the voltage at the second ground SW, the first signal on-pulse1 generates a pulse signal at each rising edge of the input signal IN, and the second signal off-pulse2 generates a pulse signal at each falling edge of the input signal IN. Figure 7As shown, the high level of the output signal OUT is the first voltage BOOT, the low level of the output signal OUT is the voltage at the second ground SW, the first signal on-pulse1 generates a pulse signal at the rising edge of the input signal IN, and since the input signal IN has no falling edge, the second signal off-pulse2 does not generate a pulse signal and always maintains a low level. Figure 8 As shown, the high level of the output signal OUT is the first voltage BOOT, the low level of the output signal OUT is the voltage at the second ground SW, and the second signal off-pulse2 generates a pulse signal at the falling edge of the input signal IN. Since the input signal IN has no rising edge, no pulse signal is generated in the first signal on-pulse1, which always maintains a low level.

[0061] Specific, combined Figure 6 , when the input signal IN changes from a low level to a high level, it means that the input signal IN has a rising edge but no falling edge, then the first signal on-pulse1 will generate a pulse, and the second signal off-pulse2 will remain at a low level. The fourth switch module 60 is disconnected according to the second signal off-pulse2. The third switch module 50 is turned on according to the first signal on-pulse1 and provides the first level to the latch module 30, so that the latch module 30 latches and provides the second level to the logic module 40, and then disconnects when the on time reaches the first preset time. Among them, the first preset time is set according to actual needs, as long as it can be ensured that the third switch module 50 can provide the first level to the latch module 30 when it is turned on. It can be seen from the above that after the third switch module 50 provides the first level to the latch module 30 when it is turned on, it is disconnected, so that no path is formed between the first ground SW and the second ground GND. Therefore, no static current is generated on the body diode in the first NMOS tube N1, thereby reducing the power consumption of the level conversion circuit.

[0062] When the input signal IN changes from a high level to a low level, it means that the input signal IN has a falling edge but no rising edge, then the first signal on-pulse1 maintains a low level, and the second signal off-pulse2 generates a pulse.

[0063] The third switch module 50 is disconnected according to the first signal on-pulse1. The fourth switch module 60 is turned on according to the second signal off-pulse2 and provides the third level to the latch module 30, so that the latch module 30 is latched and provides the fourth level to the logic module 40, and then disconnected when the on time reaches the second preset time. Among them, the second preset time is set according to actual needs, as long as it can be ensured that the fourth switch module 60 can provide the third level to the latch module 30 when it is turned on. It can be seen from the above that after the fourth switch module 60 provides the third level to the latch module 30 when it is turned on, it is disconnected, so that no path is formed between the first ground SW and the second ground GND, so that no static current is generated on the body diode in the second NMOS tube N2, thereby reducing the power consumption of the level conversion circuit.

[0064] In some embodiments, Fig. 9 As shown, the third switch module 50 includes a fifth NMOS transistor N5, the gate of the fifth NMOS transistor N5 is used to receive the first signal on-pulse1, the drain of the fifth NMOS transistor N5 is connected to the source of the seventh NMOS transistor N7 in the first switch module 10, and the source of the fifth NMOS transistor N5 is used to connect to the second ground GND. Among them, the fifth NMOS transistor N5 is a low-voltage transistor.

[0065] Specific, combined Figure 6 , when the input signal IN changes from a low level to a high level, it indicates that the input signal IN has a rising edge, then the first signal on-pulse1 will generate a pulse, the fifth NMOS tube N5 is turned on at the pulse of the first signal on-pulse1 and provides the first level to the latch module 30, so that the latch module 30 latches and provides the second level to the logic module 40, and then disconnects when the on time reaches the first preset time. As can be seen from the above, after the fifth NMOS tube N5 provides the first level to the latch module 30 when it is turned on, it is disconnected, so that no path is formed between the first ground SW and the second ground GND, so that no static current is generated on the body diode in the first NMOS tube N1, thereby reducing the power consumption of the level conversion circuit.

[0066] When the input signal IN changes from a high level to a low level, it means that the input signal IN has a falling edge but no rising edge, so the first signal on-pulse1 maintains a low level, and the fifth NMOS transistor N5 is turned off.

[0067] In some embodiments, Fig. 9As shown, the fourth switch module 60 includes a sixth NMOS transistor N6, the gate of the sixth NMOS transistor N6 is used to receive the second signal off-pulse2, the drain of the sixth NMOS transistor N6 is connected to the source of the eighth NMOS transistor N8 in the second switch module 20, and the source of the sixth NMOS transistor N6 is used to connect to the second ground GND. Among them, the sixth NMOS transistor N6 is a low-voltage transistor.

[0068] Specific, combined Figure 6 When the input signal IN changes from a low level to a high level, it means that the input signal IN has a rising edge but no falling edge, so the second signal off-pulse2 maintains a low level. The sixth NMOS transistor N6 is turned off.

[0069] When the input signal IN changes from a high level to a low level, it indicates that the input signal IN has a falling edge, and the second signal off-pulse2 will generate a pulse. The sixth NMOS tube N6 is turned on at the pulse of the second signal off-pulse2 and provides the third level to the latch module 30, so that the latch module 30 latches and provides the fourth level to the logic module 40, and then disconnects when the on time reaches the second preset time. As can be seen from the above, after the sixth NMOS tube N6 provides the third level to the latch module 30 when it is turned on, it is disconnected, so that no path is formed between the first ground SW and the second ground GND, so that no static current is generated on the body diode in the second NMOS tube N2, thereby reducing the power consumption of the level conversion circuit.

[0070] In some embodiments, Figure 7 and Figure 8 In the scenario where the output signal OUT is incorrectly flipped due to internal or external abnormal interference, the level conversion circuit will be locked in the wrong state, causing the upper bridge switch tube in the DC-DC power management chip to be incorrectly in the normally closed or normally open state. In the worst case, the chip will be locked and need to be powered off and restarted to be released. In the worst case, the chip and its load will be damaged.

[0071] In order to avoid the locking problem of the level conversion circuit, the present application introduces an anti-lock mechanism so that even if an error occurs, the error can be resolved at the next clock signal and the normal working state can be restored.

[0072] like Fig.10 As shown, the level conversion circuit provided in the embodiment of the present application further includes a first signal generating module 70 and a second signal generating module 80 . The first signal generating module 70 is connected to the third switch module 50 , and the second signal generating module 80 is connected to the fourth switch module 60 .

[0073] Specifically, the first signal generating module 70 is used to receive the input signal IN and the clock signal CLK, and generate the third signal on-pulse3 according to the input signal IN and the clock signal CLK. The second signal generating module 80 is used to receive the input signal IN and the clock signal CLK, and generate the fourth signal off-pulse4 according to the received input signal IN and the clock signal CLK. Fig.11 As shown, when the input signal IN is at a high level, the third signal on-pulse3 generates a pulse signal at each rising edge of the clock signal CLK, and the fourth signal off-pulse4 always maintains a low level. Fig.12 As shown, when the input signal IN is at a low level, the third signal on-pulse3 always maintains a low level, and the fourth signal off-pulse4 generates a pulse signal at each falling edge of the clock signal CLK. Fig.13 This is a timing diagram of the normal operation of the present application. The third signal on-pulse3 generates a pulse signal at each rising edge of the input signal IN, and the fourth signal off-pulse4 generates a pulse signal at each falling edge of the input signal IN. The output signal OUT flips with the input signal IN.

[0074] More specifically, combined Fig.11 , when the input signal IN is at a high level, the third signal on-pulse3 generates a pulse signal at each rising edge of the clock signal CLK, and the fourth signal off-pulse4 maintains a low level. The sixth NMOS transistor N6 in the fourth switch module 60 is turned off according to the fourth signal off-pulse4. The fifth NMOS transistor N5 in the third switch module 50 is periodically turned on according to the third signal on-pulse3, and provides the first level to the latch module 30 when it is turned on, so that the latch module 30 performs periodic latching, and provides the second level to the logic module 40 in each cycle. As can be seen from the above, when the internal or external abnormal interference causes the output signal OUT to flip to a low level (such as Fig.11 When the output is at the position indicated by the circle in the middle), the error is resolved when the next clock signal arrives and the output is restored to a high level.

[0075] Combination Fig.12, when the input signal IN is at a low level, the third signal on-pulse3 remains at a low level, and the fourth signal off-pulse4 generates a pulse signal at each falling edge of the clock signal CLK. The fifth NMOS transistor N5 in the third switch module 50 is turned off according to the third signal on-pulse3. The sixth NMOS transistor N6 in the fourth switch module 60 is periodically turned on according to the fourth signal off-pulse4, and provides the third level to the latch module 30 when it is turned on, so that the latch module 30 performs periodic latching, and provides the fourth level to the logic module 40 in each cycle. As can be seen from the above, when the internal or external abnormal interference causes the output signal OUT to flip to a high level (such as Fig.12 When the output is at the position indicated by the circle in the middle), the error is resolved when the next clock signal arrives and the output is restored to a low level.

[0076] In some embodiments, Fig.14 As shown, the first signal generating module 70 includes a NAND gate NA, a third PMOS transistor P3, a third NMOS transistor N3, a first resistor R1, a first capacitor C1 and a first NOR gate XOR1. The first input end of the NAND gate NA is used to receive an input signal IN, the second input end of the NAND gate NA is used to receive a clock signal CLK, the output end of the NAND gate NA is respectively connected to the gate of the third PMOS transistor P3, the gate of the third NMOS transistor N3 and the first input end of the first NOR gate XOR1, the source of the third PMOS transistor P3 receives a power supply voltage VIN, the drain of the third PMOS transistor P3 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is respectively connected to the drain of the third NMOS transistor N3, the first end of the first capacitor C1 and the second input end of the first NOR gate XOR1, the output end of the first NOR gate XOR1 is connected to the gate of the fifth NMOS transistor N5 in the third switch module 50, and the source of the third NMOS transistor N3 and the second end of the first capacitor C1 are both connected to the second ground GND. The third PMOS transistor P3 and the third NMOS transistor N3 are both low-voltage transistors.

[0077] Specifically, the first signal generating module 70 generates the third signal on-pulse3 by using the logic characteristics of the logic device, the switching characteristics of the switch device and the charging characteristics of the capacitor.

[0078] In some embodiments, Fig.15As shown, the second signal generating module 80 includes a second NOR gate XOR2, a third NOR gate XOR3, a first inverter NOT1, a fourth PMOS transistor P4, a fourth NMOS transistor N4, a second resistor R2 and a second capacitor C2, a first input end of the second NOR gate XOR2 is used to receive an input signal IN, a second input end of the second NOR gate XOR2 is used to receive a clock signal CLK, an output end of the second NOR gate XOR2 is connected to an input end of the first inverter NOT1, and an output end of the first inverter NOT1 is connected to a gate of the fourth PMOS transistor P4, a gate of the ... gate of the fourth NMOS transistor N4, a gate of the fourth PMOS transistor P4, a gate of the fourth NMOS transistor N4, a gate of the fourth NMOS transistor N4, a gate of the fourth NMOS transistor N4, a gate of the fourth NMOS transistor P4, a gate of the fourth NMOS transistor N4, a gate of the fourth NMOS transistor N4, a gate of the fourth NMOS transistor P4, a gate of the fourth NMOS transistor N4, a gate of the fourth NMOS transistor N4, a gate of the fourth NMOS transistor P4, a gate of the fourth NMOS transistor N4, a gate of the fourth NMOS transistor N4, a gate of the fourth NMOS transistor P4, a gate of the fourth NMOS transistor N4, a gate of the fourth NMOS transistor The gate of the S transistor N4 is connected to the first input end of the third NOR gate XOR3, the source of the fourth PMOS transistor P4 receives the power supply voltage, the drain of the fourth PMOS transistor P4 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is respectively connected to the drain of the fourth NMOS transistor N4, the first end of the second capacitor C2 and the second input end of the third NOR gate XOR3, the output end of the third NOR gate XOR3 is connected to the gate of the sixth NMOS transistor N6 in the fourth switch module 60, the source of the fourth NMOS transistor N4 and the second end of the second capacitor C2 are both connected to the second ground GND. Among them, the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are both low-voltage transistors.

[0079] Specifically, the second signal generating module 80 generates the fourth signal off-pulse4 by using the logic characteristics of the logic device, the switching characteristics of the switch device and the charging characteristics of the capacitor.

[0080] In summary, the level conversion circuit provided in the embodiment of the present application can operate under a low power supply voltage and has a lower static current. At the same time, a cycle-by-cycle unlocking timing is introduced. When the output signal OUT is abnormally locked, the error can be immediately released when the next clock signal arrives, thereby preventing the chip from being locked and the chip and the load from being damaged.

[0081] The present application also provides a chip including the level conversion circuit described above. Since the chip provided in the present application adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0082] Exemplarily, the chip may be a high-voltage DC-DC power management chip or the like.

[0083] The embodiment of the present application also provides an electronic device, including the level conversion circuit described above. Since the electronic device provided by the embodiment of the present application adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0084] Exemplarily, the electronic device may be a power supply, a frequency converter, etc.

[0085] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0086] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A level conversion circuit, characterized in that: It comprises a first switch module, a second switch module, a latch module and a logic module, wherein the source of the first PMOS tube and the source of the second PMOS tube in the latch module are both used to receive a first voltage, the gate of the first PMOS tube is respectively connected to the gate of the first NMOS tube, the drain of the second NMOS tube, the drain of the second PMOS tube, the logic module and the second switch module in the latch module, the drain of the first PMOS tube is respectively connected to the gate of the second PMOS tube, the gate of the second NMOS tube, the drain of the first NMOS tube and the first switch module, the source of the first NMOS tube and the source of the second NMOS tube are both used to connect to a first ground, the first switch module and the second switch module are both used to receive an input signal, and the first switch module and the second switch module are also both used to connect to a second ground; When the input signal is at a high level, the second switch module is disconnected; the first switch module is turned on and provides a first level to the latch module; the latch module provides a second level to the logic module according to the first level; The logic module outputs a first target level according to the second level; when the input signal is at a low level, the first switch module is disconnected; the second switch module is turned on and provides a third level to the latch module; The latch module provides a fourth level to the logic module according to the third level; the logic module outputs a second target level according to the fourth level; The level conversion circuit further includes a third switch module and a fourth switch module, wherein the third switch module is arranged between the first switch module and the second ground, and the fourth switch module is arranged between the second switch module and the second ground, and the third switch module is used to receive a first signal, and the fourth switch module is used to receive a second signal; When the input signal changes from a low level to a high level, the fourth switch module is disconnected according to the second signal; the third switch module is turned on according to the first signal and provides the first level to the latch module, and then is disconnected when the on-time reaches a first preset time; when the input signal changes from a high level to a low level, the third switch module is disconnected according to the first signal; the fourth switch module is turned on according to the second signal and provides the third level to the latch module, and then is disconnected when the on-time reaches a second preset time.

2. The level conversion circuit according to claim 1, characterized in that: The level conversion circuit further includes a first signal generating module and a second signal generating module, the first signal generating module is connected to the third switch module, and the second signal generating module is connected to the fourth switch module; The first signal generating module is used to receive the input signal and the clock signal, and generate a third signal according to the input signal and the clock signal; the second signal generating module is used to receive the input signal and the clock signal, and generate a fourth signal according to the input signal and the clock signal; When the input signal is at a high level, the fourth switch module is disconnected according to the fourth signal; the third switch module is periodically turned on according to the third signal, and provides the first level to the latch module when turned on; when the input signal is at a low level, the third switch module is disconnected according to the third signal; the fourth switch module is periodically turned on according to the fourth signal, and provides the third level to the latch module when turned on.

3. The level conversion circuit according to claim 2, characterized in that: The first signal generating module includes a NAND gate, a third PMOS tube, a third NMOS tube, a first resistor, a first capacitor and a first NOR gate. The first input end of the NAND gate is used to receive the input signal, the second input end of the NAND gate is used to receive the clock signal, the output end of the NAND gate is respectively connected to the gate of the third PMOS tube, the gate of the third NMOS tube and the first input end of the first NOR gate, the source of the third PMOS tube receives the power supply voltage, the drain of the third PMOS tube is connected to the first end of the first resistor, the second end of the first resistor is respectively connected to the drain of the third NMOS tube, the first end of the first capacitor and the second input end of the first NOR gate, the output end of the first NOR gate is connected to the third switch module, and the source of the third NMOS tube and the second end of the first capacitor are both connected to the second ground.

4. The level conversion circuit according to claim 2, characterized in that: The second signal generating module includes a second NOR gate, a third NOR gate, a first inverter, a fourth PMOS tube, a fourth NMOS tube, a second resistor and a second capacitor. The first input end of the second NOR gate is used to receive the input signal, the second input end of the second NOR gate is used to receive the clock signal, the output end of the second NOR gate is connected to the input end of the first inverter, the output end of the first inverter is respectively connected to the gate of the fourth PMOS tube, the gate of the fourth NMOS tube and the first input end of the third NOR gate, the source of the fourth PMOS tube receives the power supply voltage, the drain of the fourth PMOS tube is connected to the first end of the second resistor, the second end of the second resistor is respectively connected to the drain of the fourth NMOS tube, the first end of the second capacitor and the second input end of the third NOR gate, the output end of the third NOR gate is connected to the fourth switch module, and the source of the fourth NMOS tube and the second end of the second capacitor are both connected to the second ground.

5. The level conversion circuit according to claim 1, characterized in that: The third switch module includes a fifth NMOS tube, a gate of the fifth NMOS tube is used to receive the first signal, a drain of the fifth NMOS tube is connected to the first switch module, and a source of the fifth NMOS tube is used to connect to a second ground.

6. The level conversion circuit according to claim 1, characterized in that: The fourth switch module includes a sixth NMOS tube, a gate of the sixth NMOS tube is used to receive the second signal, a drain of the sixth NMOS tube is connected to the second switch module, and a source of the sixth NMOS tube is used to connect to the second ground.

7. The level conversion circuit according to claim 1, characterized in that: The first switch module includes a seventh NMOS tube, a gate of the seventh NMOS tube is used to receive the input signal, a drain of the seventh NMOS tube is respectively connected to the drain of the first PMOS tube, the gate of the second PMOS tube, the drain of the first NMOS tube and the gate of the second NMOS tube, and a source of the seventh NMOS tube is used to connect to the second ground.

8. A chip, characterized in that: The level conversion circuit comprises the level conversion circuit described in any one of claims 1 to 7.

9. An electronic device, characterized in that: The level conversion circuit comprises the level conversion circuit described in any one of claims 1 to 7.

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