Acceleration unit, computing device, system-on-chip and related methods

Abstract

The embodiment of the invention provides an acceleration unit, a computing device, a system on chip and a related method, and the acceleration unit comprises a receiving subunit which is used for receiving a first network message through a network; the message writing subunit is used for writing the first network message into a first memory buffer area allocated by a host; the verification subunit is used for verifying the first network message; and the queue writing subunit is used for writing the state information of the first memory buffer area into a completion queue after the first network message passes the verification, so that a message receiving end on a host reads the first network message from the first memory buffer area according to the completion queue, and sends the first network message to the first memory buffer area. And when the verification of the first network message is not passed, not writing the state information of the first memory buffer area into the completion queue. According to the scheme, the efficiency of checking the network message can be improved, so that the efficiency of writing the network message into the memory buffer area is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to an acceleration unit, a computing device, a system on chip, and related methods. Background Art

[0002] In the cloud computing scenario, the network needs to be virtualized. The host builds multiple virtual machines (VMs). After receiving the network message, the infrastructure processor (IPU) writes the network message into the memory buffer allocated by the virtual machine. Then the virtual machine can read the network message from the memory buffer and perform corresponding processing.

[0003] Currently, when an infrastructure processor writes a network message to a memory buffer, it first stores the message in the cache, then verifies the message in the cache, writes the message that passes the verification to the memory buffer, and discards the message that fails the verification.

[0004] However, since it takes a long time to write the message into the cache first and then write it from the cache into the memory buffer, the time delay of writing the network message into the memory buffer is high, and the efficiency of writing the network message into the memory buffer is low. Summary of the invention

[0005] In view of this, embodiments of the present application provide an acceleration unit, a computing device, a system on a chip and related methods to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of an embodiment of the present application, an acceleration unit is provided, including: a receiving subunit, used to receive a first network message through a network; a message writing subunit, used to write the first network message into a first memory buffer allocated by a host; a checking subunit, used to check the first network message; a queue writing subunit, used to write status information of the first memory buffer into a completion queue after the first network message is checked, so that a message receiving end on the host reads the first network message from the first memory buffer according to the completion queue, and does not write the status information of the first memory buffer into the completion queue when the first network message fails to be checked.

[0007] According to a second aspect of an embodiment of the present application, a computing device is provided, comprising: a processing unit for constructing a host, the host being used to allocate multiple memory buffers; and an acceleration unit according to the first aspect above.

[0008] According to a third aspect of an embodiment of the present application, a system on chip is provided, comprising an acceleration unit according to the first aspect above.

[0009] According to a fourth aspect of an embodiment of the present application, a server is provided, which is deployed in a data center and is provided with an acceleration unit as described in the first aspect above.

[0010] According to a fifth aspect of an embodiment of the present application, a data center is provided, comprising a server according to the fourth aspect above.

[0011] According to the sixth aspect of the embodiment of the present application, an Internet network is provided, comprising: a message receiving device and at least one message sending device; the message receiving device comprises an acceleration unit as described in the first aspect above; the message sending device is connected to the acceleration unit included in the message receiving device through a network, and the message sending device is used to send a message sent to a message receiving end on the message receiving device to the acceleration unit.

[0012] According to the seventh aspect of the embodiment of the present application, a message transmission acceleration method is provided, including: receiving a first network message through a network; writing the first network message into a first memory buffer allocated by a host; verifying the first network message; after the first network message passes the verification, writing the status information of the first memory buffer into a completion queue, so that a message receiving end on the host reads the first network message from the first memory buffer according to the completion queue, and when the first network message fails the verification, the status information of the first memory buffer is not written into the completion queue.

[0013] According to the scheme provided in the embodiment of the present application, after the receiving subunit receives the first network message, the message writing subunit can write the first network message into the first memory buffer, thereby eliminating the step of storing the network message in the cache, the checking subunit can verify the first network message, and the queue writing subunit can write the status information of the first memory buffer into the completion queue according to the verification result of the checking subunit, and then the message receiving end on the host can read the first network message from the first memory buffer according to the status information in the completion queue, thereby realizing the verification process of the network message, and by writing the status information of the memory buffer where the network message is located into the completion queue after the network message verification passes, and not writing the status information when the network message verification fails, the erroneous network message is discarded, and the step of storing the network message in the cache is eliminated during the verification process, thereby reducing the time spent on network message verification, reducing the time delay of writing the network message into the memory buffer, and improving the efficiency of writing the network message into the memory buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0015] Figure 1 is a schematic diagram of a data center according to an embodiment of the present application;

[0016] Figure 2 is a schematic diagram of a server according to an embodiment of the present application;

[0017] Figure 3 is a schematic diagram of an Internet network according to an embodiment of the present application;

[0018] Figure 4 is a schematic diagram of an acceleration unit according to an embodiment of the present application;

[0019] Figure 5 It is a schematic diagram of a network message verification process in the related art;

[0020] Figure 6 It is a schematic diagram of a network message verification process of an embodiment of the present application;

[0021] Figure 7 is a schematic diagram of a network message verification process of another embodiment of the present application;

[0022] Figure 8 It is a schematic diagram of a network message verification process of yet another embodiment of the present application;

[0023] Fig. 9 is a schematic diagram of a process of writing status information according to an embodiment of the present application;

[0024] Fig.10 This is a flowchart of a method for accelerating message transmission according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, and flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0026] First, some nouns or terms that appear in the process of describing the embodiments of the present application are subject to the following explanations.

[0027] Infrastructure Processor: Infrastructure Processing Units (IPU) is a special processor designed for cloud data centers. It connects to physical computing, storage, and network resources, quickly cloudifies and performs hardware acceleration, and connects to the cloud operating system to manage and control the servers in the cloud data center. The infrastructure processor can solve the problem of data migration bandwidth and can also cloudify and virtualize the data center.

[0028] Host: A host is a cloud server, physical server, or virtual host that has a virtualized environment deployed. A host can create multiple virtual machines and provide software and hardware support for the operation of virtual machines. A host can also include a bare metal server, which is a hardware device with the characteristics of a traditional physical server and the virtualization function of cloud computing technology. It is a combination of hardware and software advantages.

[0029] Virtual Machine: A virtual machine (VM) is a complete computer system that is simulated by software and has complete hardware system functions and runs in an isolated environment.

[0030] Message receiving end: The message receiving end is the main body on the host that receives and processes network messages. The message receiving end can be a virtual machine or a bare metal server. After the network message is stored in the memory buffer, the virtual network card can notify the message receiving end that the network message has been written to the memory buffer by writing to the completion queue (CQ). Then, the message receiving end can read the network message from the memory buffer.

[0031] Memory buffer: A memory buffer is a storage space of a specified size reserved in the memory for temporary storage of input / output (I / O) data. The memory buffer in the embodiment of the present application refers to a storage space reserved in the memory for storing network messages.

[0032] System on chip: System on a chip (SoC) refers to a technology that integrates a complete system on a single chip and groups all or part of the necessary electronic circuits. The so-called complete system generally includes a processor (CPU) or an acceleration unit, memory, and peripheral circuits. SoC is developed in parallel with other technologies, such as Silicon on Insulator (SOI), which can provide enhanced clock frequencies and thus reduce the power consumption of microchips.

[0033] Data Center

[0034] Data centers are a globally collaborative network of specific devices used to transmit, accelerate, display, calculate, and store data information on the Internet network infrastructure. In the future, data centers will also become competitive assets for enterprises. With the widespread application of data centers, virtualization technology is increasingly being applied to data centers. As an important support for virtualization technology, infrastructure processors have been widely used in input / output virtualization scenarios in data centers.

[0035] In traditional large data centers, the network structure is usually as follows Figure 1 As shown in the figure, it is the hierarchical inter-networking model. This model includes the following parts:

[0036] Server 140 : Each server 140 is a processing and storage entity of the data center. The processing and storage of a large amount of data in the data center are completed by these servers 140 .

[0037] Access switch 130: Access switch 130 is used to connect servers 140 to the switch in the data center. One access switch 130 connects to multiple servers 140. Access switches 130 are usually located at the top of the rack, so they are also called top of rack switches, and they are physically connected to the servers.

[0038] Aggregation switch 120: Each aggregation switch 120 connects to multiple access switches 130 and provides other services, such as firewall, intrusion detection, network analysis, etc.

[0039] Core switch 110: The core switch 110 provides high-speed forwarding for packets entering and leaving the data center, and provides connectivity for the aggregation switch 120. The network of the entire data center is divided into an L3 layer routing network and an L2 layer routing network. The core switch 110 usually provides a flexible L3 layer routing network for the network of the entire data center.

[0040] Generally, the aggregation switch 120 is the demarcation point between the L2 and L3 layer routing networks. The network below the aggregation switch 120 is the L2 network, and the network above is the L3 network. Each group of aggregation switches manages a delivery point (POD), and the POD is an independent VLAN network. The server does not need to modify the IP address and default gateway when migrating within the POD, because one POD corresponds to one L2 broadcast domain.

[0041] The spanning tree protocol (Spanning Tree Protocol, STP) is usually used between the aggregation switch 120 and the access switch 130. STP makes only one aggregation switch 120 available for a VLAN network, and other aggregation switches 120 are used only when a failure occurs. In other words, horizontal expansion cannot be achieved at the level of the aggregation switch 120, because even if multiple aggregation switches 120 are added, only one is still working.

[0042] The embodiments of the present application can be applied to input / output virtualization scenarios. A virtualization environment can be deployed on the server 140, and multiple virtual machines and / or bare metal servers can be created based on the virtualization environment. Network packets can be sent through the network between virtual machines, between virtual machines and bare metal servers, between bare metal servers, between virtual machines and clients, or between bare metal servers and clients.

[0043] server

[0044] The computing device in the embodiment of the present application may be a server 140 included in a data center. The server 140 is a real processing device in the data center. Figure 2 The structure block diagram of the inside of a server 140 is shown. The server 140 includes a memory 210, a processing unit cluster 270 and an acceleration unit cluster 280 connected by a bus. The processing unit cluster 270 includes a plurality of processing units 220. The acceleration unit cluster 280 includes a plurality of acceleration units 230. The acceleration unit 230 in the embodiment of the present application is mainly a special processor designed to accelerate the writing of network packets into the memory, which can be embodied as a graphics processing unit (GPU) specially designed for input / output virtualization, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a cloud infrastructure processor (Cloud Infrastructure Processing Units, CIPU), an infrastructure processor (IPU) or a data processing unit (DPU), etc.

[0045] The architecture design of the traditional processing unit makes the control unit and the storage unit occupy a large part of the space in the architecture, while the space occupied by the computing unit is insufficient. Therefore, it is very effective in terms of logic control, but not efficient enough in terms of large-scale parallel computing. Therefore, various special acceleration units have been developed to more effectively improve the processing speed of calculations for different functions and different fields. In the embodiment of the present application, the acceleration unit 230 is a hardware accelerator designed specifically for accelerating the input / output speed of the message receiving end. After receiving the network message, the acceleration unit 230 can directly write the network message into the memory buffer allocated by the host, and verify the network message, update the completion queue corresponding to the memory buffer when the network message verification passes, and do not update the completion queue corresponding to the memory buffer when the network message verification fails, thereby eliminating the process of storing the message in the cache, thereby reducing the time spent on the network message verification, and improving the efficiency of verifying the network message and writing it into the memory buffer, which will be described in detail below.

[0046] The processing unit 220 is used to construct a host, and the host may include multiple message receiving ends, and the message receiving ends perform input / output through the acceleration unit 230. For example, the message receiving end receives network messages through the acceleration unit 230. The host can be constructed based on one or more processing units 220, and the message receiving end may include multiple virtual machines. Multiple virtual machines can be created based on one processing unit 220. Multiple virtual machines created in the same host can perform input / output through one or more acceleration units 230. Multiple virtual machines that perform input / output through one acceleration unit 230 can be created based on the same processing unit 220 or based on different processing units 220. In an embodiment of the present application, the host constructed by the processing unit 220 can allocate a memory buffer. After the acceleration unit 230 writes the network message into the memory buffer, the message receiving end on the host can read the network message from the memory buffer.

[0047] The embodiment of the present application mainly focuses on the structure and configuration of the acceleration unit 230 , and the structure and configuration of the acceleration unit 230 will be described in detail hereinafter.

[0048] Internet

[0049] Figure 3 is a schematic diagram of an Internet network according to an embodiment of the present application, such as Figure 3 As shown, the internetwork includes a message receiving device 301 and at least one message sending device 302 ( Figure 3Two message sending devices 302 are shown, but those skilled in the art should understand that the Internet may also include other numbers of message sending devices 302). The message receiving device 301 includes an acceleration unit 230, and the message sending device 302 is connected to the acceleration unit 230 included in the message receiving device 301 through a network. The message sending device 302 can send the message sent to the message receiving end on the message receiving device 301 to the acceleration unit 230.

[0050] A virtualization environment is deployed on the message receiving device 301, and multiple virtual machines and / or bare metal servers are created based on the virtualization environment. The message sending device 302 can send messages to the virtual machines and / or bare metal servers on the message receiving device 301 through the network. The message sending device 302 sends the message to be sent to the virtual machine and / or bare metal server to the acceleration unit 230 through the network, and the acceleration unit 230 sends the received message to the corresponding virtual machine and / or bare metal server.

[0051] After receiving the message, the acceleration unit 230 needs to verify the message. In the related technology, the message is first written into the cache on the acceleration unit 230, and then the message in the cache is written into the memory buffer on the message receiving device 301 after the message verification passes. The virtual machine and / or bare metal server reads the verified message from the memory buffer. Since the message needs to be written into the cache first and then written into the memory buffer after the verification passes, this will result in low efficiency in transmitting messages by the acceleration unit 230.

[0052] In an embodiment of the present application, after receiving a message, the acceleration unit 230 directly writes the message into a memory buffer on the message receiving device 301, and synchronously verifies the message during the writing process. After obtaining the verification result, if the message verification passes, a write operation is performed on the completion queue, so that the virtual machine and / or bare metal server reads the verified message from the memory buffer according to the completion queue. If the message verification fails, no write operation is performed on the completion queue, so that the virtual machine and / or bare metal server will not read the message that fails the verification in the memory buffer, thereby saving the time of writing the message into the cache on the acceleration unit 230, thereby improving the efficiency of the acceleration unit 230 in transmitting the message.

[0053] The embodiment of the present application mainly focuses on the structure and configuration of the acceleration unit 230 , and the structure and configuration of the acceleration unit 230 will be described in detail hereinafter.

[0054] Internal structure of the acceleration unit

[0055] Combine the following Figure 4 The internal structure diagram of the acceleration unit 230 shown in FIG. 2 specifically illustrates how the acceleration unit 230 works.

[0056] like Figure 4 As shown, the acceleration unit 230 includes a receiving subunit 231, a message writing subunit 232, a checking subunit 233 and a queue writing subunit 234. The receiving subunit 231 can receive a first network message through a network, and the message writing subunit 232 can write the first network message into a first memory buffer allocated by the host. The checking subunit 233 can check the first network message, and the queue writing subunit 234 can write the status information of the first memory buffer into the completion queue after the first network message passes the check, so that the message receiving end on the host reads the first network message from the first memory buffer according to the completion queue, and does not write the status information of the first memory buffer into the completion queue when the first network message fails the check.

[0057] One or more message receiving terminals are running on the host. After receiving the first network message sent to a certain message receiving terminal, the acceleration unit 230 needs to verify the first network message and write the verified first network message into the memory buffer on the host. Then the corresponding message receiving terminal can read the first network message from the memory buffer and perform corresponding processing according to the read first network message. The host pre-allocates multiple memory buffers for caching network messages, and the memory buffers are located in the main memory (also called memory, internal memory) of the host.

[0058] The message receiving end running on the host can be connected to multiple virtual network cards, and the virtual network cards are virtualized and generated by the acceleration unit 230. Before receiving packets in the virtual network, the network card driver of the message receiving end can allocate one or more queues for receiving packets to the virtual network card, and each queue includes multiple memory buffers. When the virtual network card receives the first network message, it can write the received first network message into the queue allocated to it, and then the message receiving end to which the virtual network card belongs can read the first network message from the queue.

[0059] After the network card driver on the host allocates a memory buffer for the message receiving end, the host will store the address of the memory buffer in the submission queue (SQ). The submission queue includes multiple data, each of which includes the address of a memory buffer, and the position of each data in the submission queue indicates the writing order of the corresponding memory buffer. After receiving the first network message, the acceleration unit 230 will determine the writing order of each memory buffer according to the submission queue, and determine the first memory buffer to which the first network message needs to be written.

[0060] After the receiving subunit 231 receives the first network message, the message writing subunit 232 writes the first network message into the first memory buffer. When the verification subunit 233 passes the verification of the first network message, the queue writing subunit 234 can write the status information of the first memory buffer into the completion queue (Completion Queue, CQ). Then, the message receiving end can find the first memory buffer that caches the first network message according to the status information recorded in the completion queue, and read the data of the first network message.

[0061] When the verification subunit 233 verifies that the first network message fails, the queue writing subunit 234 does not write the status information of the first memory buffer into the completion queue. At this time, since the completion queue is not updated, the message receiving end will not read the first network message from the first memory buffer. The message receiving end does not obtain the first network message, which is equivalent to the first network message being discarded, thereby achieving the discarding of the erroneous message.

[0062] The verification subunit 233 can verify the first network message that has been written into the first memory buffer, or can verify the first network message during the writing process of the message writing subunit 232 writing the first network message into the first memory buffer. The verification subunit 233 can verify the first network message in a variety of ways, such as by calculating a checksum, a hash value, etc. to verify the first network message, and the specific verification method is not limited in the embodiments of the present application.

[0063] Figure 5 It is a schematic diagram of the network message verification process in the related technology, such as Figure 5 As shown, the host is allocated with memory buffers S0 to S4, and the acceleration unit receives network message 0, network message 1 and network message 2 in sequence. After receiving network message 0, the acceleration unit first stores network message 0 in the cache on the acceleration unit, then verifies network message 0 in the cache, and determines whether the verification is passed. If network message 0 is verified, the network message 0 in the cache is written into the memory buffer S0 allocated by the host, and the status information 0 of memory buffer S0 is written into the completion queue. After receiving network message 1, the acceleration unit stores network message 1 in the cache on the acceleration unit, then verifies network message 1 in the cache, and determines whether the verification is passed. If network message 1 is verified, network message 1 is directly discarded in the cache. After receiving network message 2, the acceleration unit stores network message 2 in the cache on the acceleration unit, then verifies network message 2 in the cache and determines whether the verification passes. If network message 2 passes the verification, the network message 2 in the cache is written into the memory buffer S1 allocated by the host, and the status information 1 of the memory buffer S1 is written into the completion queue.

[0064] Depend on Figure 5 It can be seen from the process shown that when the acceleration unit in the related technology verifies the network message, it is necessary to first write the network message into the cache of the acceleration unit, but it takes a long time to write the network message into the cache and write it from the cache to the memory buffer allocated by the host according to the verification result. Therefore, the efficiency of network message verification is low, resulting in a high time delay for the message receiving end to receive the network message.

[0065] Figure 6 to Figure 7 Schematic diagram of the network message verification process of the embodiment of the present application. The host is allocated with S0 to the memory buffer S4, and the acceleration unit 230 receives network message 0, network message 1 and network message 2 in sequence. Figure 6 As shown, after receiving network message 0, the acceleration unit 230 stores network message 0 in the memory buffer S0 allocated by the host, and verifies network message 0. When network message 0 passes the verification, the status information 0 of the memory buffer S0 is written into the completion queue. At this time, the message receiving end can read network message 0 from the memory buffer S0 according to the status information 0 in the completion queue. Figure 7 As shown, after receiving the network message 1, the acceleration unit 230 stores the network message 1 in the memory buffer S1 allocated by the host. When the network message 1 fails the verification, the status information 1 of the memory buffer S1 is not written into the completion queue. At this time, the message receiving end will not read the network message 1 from the memory buffer S1, so it is equivalent to discarding the network message 1.

[0066] Depend on Figure 6 and Figure 7 As can be seen from the process shown, in the process of verifying the network message, the verification of the network message can be achieved without writing the network message into the cache, so relative to Figure 5 The network message verification process shown in omits the process of writing the message into the cache, thereby reducing the time spent on network message verification and improving the efficiency of writing the network message into the memory buffer.

[0067] In an embodiment of the present application, after the receiving subunit 231 receives the first network message, the message writing subunit 232 can write the first network message into the first memory buffer, thereby eliminating the step of storing the network message in the cache, and the checking subunit 233 can check the first network message. The queue writing subunit 234 can write the status information of the first memory buffer into the completion queue according to the verification result of the checking subunit 233, and then the message receiving end on the host can read the first network message from the first memory buffer according to the status information in the completion queue, thereby realizing the verification process of the network message, and by writing the status information of the memory buffer where the network message is located into the completion queue after the network message verification passes, and not writing the status information when the network message verification fails, the erroneous network message is discarded, and the step of storing the network message in the cache is eliminated during the verification process, thereby reducing the time spent on network message verification, reducing the time delay of writing the network message into the memory buffer, and improving the efficiency of writing the network message into the memory buffer.

[0068] In a possible implementation, the receiving subunit 231 can receive a second network message through the network, and the second network message is a subsequent message of the first network message. When the first network message fails to be verified, the message writing subunit 232 can write the second network message into the first memory buffer to replace the first network message cached in the first memory buffer.

[0069] After writing the first network message into the first memory buffer, the receiving subunit 231 receives the second network message through the network. The second network message is a subsequent message of the first network message. At this time, if the first network message fails the verification, the message writing subunit 232 writes the second network message into the first memory buffer where the first network message is located, thereby replacing the first network message.

[0070] It should be understood that after the second network message is written into the memory buffer, or during the writing process, the verification subunit 233 will verify the second network message, and the queue writing subunit 234 can write the status information of the memory buffer where the second network message is located into the completion queue after the second network message is verified, so that the message receiving end on the host can read the second network message from the memory buffer where the second network message is located according to the completion queue, and when the second network message fails to be verified, the status information of the memory buffer where the second network message is located will not be written into the completion queue.

[0071] It should be noted that when the subsequent third network message is received, the same judgment process as when the second network message is received will be executed, that is, when the second network message fails the verification, the third network message will be overwritten to the memory buffer where the second network message is located. The above process will be executed for subsequent messages and will not be repeated here.

[0072] In one example, Figure 8 Figure 2 shows the process of processing subsequent messages when network message verification fails. Figure 8 As shown, in Figure 6 and Figure 7 Based on the network message verification process shown, after determining that network message 1 fails the verification, network message 2 is written into memory buffer S1 to overwrite network message 1 in memory buffer S1. After network message 2 passes the verification, status information 1 of memory buffer S1 is written into the completion queue. At this time, the message receiving end can read network message 2 from memory buffer S1 according to status information 1 in the completion queue.

[0073] In an embodiment of the present application, a subsequent second network message is written to a memory buffer where a first network message that fails verification is located, and the first network message in the memory buffer can be replaced, thereby discarding the erroneous message. In addition, the step of storing the network message in the cache is omitted during the verification process, and the erroneous network message can be discarded. Therefore, the time spent on network message verification is reduced, the time delay for writing the network message to the memory buffer is reduced, and the efficiency of writing the network message to the memory buffer is improved.

[0074] In a possible implementation, the message writing subunit 232 may write the second network message into a second memory buffer allocated by the host when the first network message passes verification.

[0075] When the first network message is verified, the received subsequent second network message is written into the second memory buffer allocated by the host, and the second network message is verified by the verification subunit 233. In addition, the queue writing subunit 234 can write the status information of the second memory buffer where the second network message is located into the completion queue after the second network message is verified, so that the message receiving end on the host can read the second network message from the second memory buffer according to the completion queue, and when the second network message fails to be verified, the status information of the second memory buffer where the second network message is located is not written into the completion queue.

[0076] like Figure 7 In the case shown, network message 1 is used as the subsequent message of network message 0. After network message 0 passes the verification and network message 1 is received, network message 1 is written into the memory buffer S1. It should be noted that when writing network messages into the memory buffer, the memory buffer allocated by the host can be used in sequence (such as Figure 7As shown, network messages are written into each memory buffer in the order of memory buffers S0 to S4), or the memory buffers allocated by the host can be used out of order, for example, after network message 0 is written into memory buffer S0, the subsequent message of network message 0 is written into memory buffer S2, which is not limited to the embodiments of the present application.

[0077] In an embodiment of the present application, when the first network message passes the verification, the second network message is written into the second memory buffer allocated by the host, so that the network messages that pass the verification can be written into different memory buffers, ensuring that the message receiving end can read each verified network message from the memory buffer, thereby ensuring the normal progress of the communication process.

[0078] In a possible implementation, the checking subunit may check the first network message while the message writing subunit writes the first network message into the first memory buffer, so as to obtain a checking result when writing the first network message into the first memory buffer is completed.

[0079] The verification subunit can verify the first network message during the process of writing the first network message into the first memory buffer. For example, the checksum of the first network message can be calculated during the process of writing the first network message, thereby verifying the network message during the network message transmission process.

[0080] In an embodiment of the present application, the verification subunit can verify the first network message while the message writing subunit writes the first network message into the first memory buffer area, thereby realizing on-the-way verification of the network message, and thus obtaining the verification result when the first network message is written into the first memory buffer. Compared with the scheme of verifying the network message after writing the network message into the memory buffer, the verification time is saved, and the time for writing the network message into the memory buffer can be reduced, thereby improving the efficiency of writing the network message into the memory buffer.

[0081] In one possible implementation, the acceleration unit 230 also includes a first retransmission subunit, which can send a first retransmission instruction to the sender of the first network message through the network when the first network message fails verification, so that the sender of the first network message resends the first network message.

[0082] When the message check subunit 233 fails to check the first network message, the acceleration unit 230 can send a first retransmission instruction to the sender of the first network message through the first retransmission subunit. After receiving the first retransmission instruction, the sender of the first network message will resend the first network message to the acceleration unit 230. At this time, the acceleration unit 230 will continue to perform relevant verification steps on the first network message to continue to check the retransmitted first network message.

[0083] Optionally, a retransmission threshold can be set. When the number of times the first network message triggers a retransmission instruction reaches the retransmission threshold, it means that the first network message itself is an erroneous message, or the sender of the first network message mistakenly sends a message to another host to the current host. At this time, the first retransmission instruction is no longer sent to the sender of the first network message.

[0084] In an embodiment of the present application, when the first network message fails the verification, the first retransmission subunit sends a first retransmission instruction to the sender of the first network message through the network, thereby realizing the re-receiving of the first network message, which can prevent the host from missing important network messages, and can replace the processor of the message receiving end in the host to send the retransmission instruction, thereby reducing the computing pressure of the processor.

[0085] In one possible implementation, the acceleration unit 230 also includes a second retransmission subunit, which can receive a second retransmission instruction sent by the message receiving end when the first network message fails to be verified, and send the second retransmission instruction to the sending end of the first network message, so that the sending end of the first network message resends the first network message.

[0086] When the message receiving end detects that the first message has not been received, including but not limited to the message receiving end detecting that the first network message verification has failed, or detecting that the first network message is overwritten by a subsequent message, etc., the message receiving end will send a second retransmission instruction to the acceleration unit 230. After the second retransmission subunit in the acceleration unit 230 receives the second retransmission instruction, it will send the second retransmission instruction to the sender of the first network message through the network. At this time, the sender of the first network message will resend the first network message after receiving the second retransmission instruction.

[0087] In an embodiment of the present application, when the first network message verification fails, the second retransmission subunit receives a second retransmission instruction sent by the message receiving end, and sends the second retransmission instruction to the sending end of the first network message through the network, thereby achieving the reception of the first network message resent by the sending end of the first network message, which can prevent the host from missing important network messages.

[0088] In one possible implementation, the queue writing subunit 234 can write the address information and occupied length information of the first memory buffer as status information into the completion queue after the first network message passes the verification, so that the message receiving end can read the first network message from the first memory buffer according to the address information and occupied length information of the first memory buffer stored in the completion queue.

[0089] The status information of the memory buffer includes the address of the memory buffer and the occupied length of the data stored in the memory buffer. The address of the memory buffer can indicate the location of the memory buffer, and the occupied length of the stored data can indicate the length of the data read by the message receiving end from the first memory buffer. When the first network message passes the verification, the queue writing subunit 234 writes the address of the first memory buffer where the first network message is located and the occupied length of the first network message into the completion queue, so that the message receiving end reads the first network message from the first memory buffer according to the address information and occupied length information of the first memory buffer stored in the completion queue.

[0090] In one example, Fig. 9 Schematic diagram of write status information of an embodiment of the present application. After the host allocates a memory buffer, the address of the memory buffer is stored in a submission queue (SQ), such as Fig. 9 As shown, the submission queue records the addresses of memory buffers S0 to S4. It can be seen from the submission queue that when writing network packets to the memory buffers, the memory buffers are written in the order from S0 to S4. The address of S0 is Desc0, the address of S1 is Desc1, the address of S2 is Desc2, the address of S3 is Desc3, and the address of S4 is Desc4.

[0091] The memory buffer S0 stores the verified network message 0 (such as Figure 7 As shown), since the network message 0 has passed the verification, at this time, the queue writing subunit 234 writes the address Desc0 of the memory buffer S0 and the occupied length of the network message 0, for example, the occupied length is 1024 bytes, into the completion queue. At this time, the message receiving end can find the location of the memory buffer S0 according to the address Desc0 in the completion queue, and read 1024 bytes of data from the memory buffer 0 according to the occupied length of 1024 bytes, thereby realizing the reception of the network message 0, and when receiving the subsequent message 1, since the network message 0 has passed the verification, the network message 1 is written into the memory buffer S1 according to the order of the submission queue, and since the network message 1 has not passed the verification, the address and occupied length of the memory buffer S1 are not written into the completion queue. At this time, the message receiving end cannot receive the network message 1.

[0092] In an embodiment of the present application, the queue writing subunit 234 can write the address and occupied length of the first memory buffer where the first network message is located into the completion queue after the first network message is verified, and then the message receiving end on the host can read the first network message from the first memory buffer according to the address and occupied length in the completion queue. In this way, the first network message that has passed the verification is transmitted to the message receiving end, and the address and occupied length of the memory buffer where the network message is located are written to the completion queue only after the network message is verified. When the verification fails, the address and occupied length of the memory buffer are not written, so that the wrong network message is discarded, so that the verification of the network message can be realized. In addition, the step of storing the network message in the cache is omitted during the verification process, thereby reducing the time spent on the network message verification, reducing the time delay of writing the network message into the memory buffer, and improving the efficiency of writing the network message into the memory buffer.

[0093] System on Chip

[0094] An embodiment of the present application further provides a system on chip, which includes the acceleration unit 230 in any of the above embodiments.

[0095] It should be noted that the application of the acceleration unit 230 in the embodiment of the present application is not limited to the system on chip, but can also be applied in various other suitable ways. For example, the acceleration unit 230 and the processing unit (CPU), main memory and other interactive components are deployed on a printed circuit board, and the acceleration unit 230 interacts with the processing unit (CPU), main memory, etc. through a bus on the printed circuit board.

[0096] Message transmission acceleration method

[0097] The acceleration unit 230 in the aforementioned embodiment can be applied to a network virtualization scenario to realize the transmission of network packets to the packet receiving end. The acceleration unit 230 writes the received network packets into a memory buffer allocated by the host. The following is an example of a packet transmission acceleration method to illustrate the working process of the acceleration unit 230 in a network virtualization scenario.

[0098] Fig.10 FIG. 1 is a flow chart of a method for accelerating message transmission according to an embodiment of the present application. Fig.10 As shown, the message transmission acceleration method includes the following steps:

[0099] Step 901: receiving a first network message through a network;

[0100] Step 902: Write the first network message into a first memory buffer allocated by the host;

[0101] Step 903: verify the first network message;

[0102] Step 904: after the first network message is verified, the status information of the first memory buffer is written into the completion queue, so that the message receiving end on the host reads the first network message from the first memory buffer according to the completion queue, and when the first network message is verified not, the status information of the first memory buffer is not written into the completion queue.

[0103] In an embodiment of the present application, after receiving the first network message, the first network message is written into the first memory buffer, thereby eliminating the step of storing the network message in the cache, and the first network message is verified, and according to the verification result, the status information of the first memory buffer is written into the completion queue, and then the message receiving end on the host can read the first network message from the first memory buffer according to the status information in the completion queue, thereby realizing the verification process of the network message, and by writing the status information of the memory buffer where the network message is located into the completion queue after the network message verification passes, and not writing the status information when the network message verification fails, the erroneous network message is discarded, and the step of storing the network message in the cache is eliminated during the verification process, thereby reducing the time spent on network message verification, reducing the time delay of writing the network message into the memory buffer, and improving the efficiency of writing the network message into the memory buffer.

[0104] It should be noted that the message transmission acceleration method of the embodiment of the present application is a specific application of the acceleration unit 230 in the aforementioned embodiment in the network virtualization scenario. The specific message transmission acceleration method can be found in the description in the aforementioned acceleration unit embodiment, which will not be repeated here.

[0105] The commercial value of the present application embodiment

[0106] In the embodiment of the present application, after receiving the network message, the acceleration unit can directly write the network message into the memory buffer allocated by the host, and verify the network message, update the completion queue corresponding to the memory buffer when the network message verification passes, and do not update the completion queue corresponding to the memory buffer when the network message verification fails, thereby eliminating the process of storing the message in the cache, thereby reducing the time spent on network message verification and improving the efficiency of verifying the network message and writing it into the memory buffer. This solution can be applied to network virtualization scenarios, such as data centers, and has good market prospects.

[0107] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used to train the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0108] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the method described in the device and system embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of other embodiments.

[0109] It should be understood that the above is a description of a specific embodiment of the present specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0110] It should be understood that an element described in singular form herein or shown in the drawings as only one does not limit the number of the element to one. In addition, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be split into multiple modules or elements.

[0111] It should also be understood that the terms and expressions used herein are for description only, and one or more embodiments of this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or parts thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, changes and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.

Claims

1. An acceleration unit, comprising: A receiving subunit, configured to receive a first network message through a network; A message writing subunit, used for writing the first network message into a first memory buffer allocated by the host; A verification subunit, used to verify the first network message; The queue writing subunit is used to write the status information of the first memory buffer into the completion queue after the first network message is verified, so that the message receiving end on the host reads the first network message from the first memory buffer according to the completion queue, and when the first network message fails to be verified, the status information of the first memory buffer is not written into the completion queue.

2. The acceleration unit according to claim 1, wherein: The receiving subunit is used to receive a second network message through a network, where the second network message is a subsequent message of the first network message; The message writing subunit is used to write the second network message into the first memory buffer to replace the first network message cached in the first memory buffer when the first network message fails to pass the verification.

3. The acceleration unit according to claim 2, wherein: The message writing subunit is used to write the second network message into the second memory buffer allocated by the host when the first network message passes the verification.

4. The acceleration unit according to claim 1, wherein: The verification subunit is used to verify the first network message during the process of the message writing subunit writing the first network message into the first memory buffer area, so as to obtain a verification result when the first network message is written into the first memory buffer area.

5. The acceleration unit according to claim 1, further comprising: The first retransmission subunit is used to send a first retransmission instruction to a sender of the first network message through a network when the first network message fails verification, so that the sender of the first network message resends the first network message.

6. The acceleration unit according to claim 1, further comprising: The second retransmission subunit is used to receive a second retransmission instruction sent by the message receiving end when the first network message verification fails, and send the second retransmission instruction to the sending end of the first network message, so that the sending end of the first network message resends the first network message.

7. The acceleration unit according to any one of claims 1 to 6, wherein: The queue writing subunit is used to write the address information and occupied length information of the first memory buffer as the status information into the completion queue after the first network message is verified, so that the message receiving end can read the first network message from the first memory buffer according to the address information and occupied length information of the first memory buffer stored in the completion queue.

8. A computing device, comprising: A processing unit for constructing a host, wherein the host is used to allocate a memory buffer; An acceleration unit according to any one of claims 1 to 7.

9. A system on chip, comprising: An acceleration unit according to any one of claims 1 to 7.

10. A server deployed in a data center, provided with an acceleration unit as claimed in any one of claims 1 to 7.

11. A data center, comprising: The server according to claim 10.

12. An Internet network comprising: A message receiving device and at least one message sending device; The message receiving device comprises an acceleration unit as described in any one of claims 1 to 7; The message sending device is connected to the acceleration unit included in the message receiving device through a network, and the message sending device is used to send the message sent to the message receiving end on the message receiving device to the acceleration unit.

13. A method for accelerating message transmission, comprising: Receiving a first network message through a network; Writing the first network message into a first memory buffer allocated by the host; Verifying the first network message; After the first network message is verified, the status information of the first memory buffer is written into the completion queue, so that the message receiving end on the host reads the first network message from the first memory buffer according to the completion queue, and when the first network message is verified, the status information of the first memory buffer is not written into the completion queue.

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