Automatic processing method, device and equipment for board frame on circuit board and medium

Abstract

The invention discloses an automatic processing method and device for a board frame on a circuit board, equipment and a medium. The method comprises the steps that a first type of pattern and a second type of pattern on a target circuit board are acquired, the first type of pattern is a closed area with a non-locking attribute in a board frame layer, and the second type of pattern is a closed area with a locking attribute and lines in the board frame layer; determining an initial main body board frame corresponding to the target circuit board according to the first type of pattern; in response to the fact that the second type of pattern is embedded in the initial main body plate frame, unlocking and deleting operation is carried out on the second type of pattern, and the second type of pattern is copied to the plate frame layer again; and forming a corresponding target main body plate frame based on the second type pattern re-copied to the plate frame layer and the initial main body plate frame after the second type pattern is deleted. Therefore, the problem that in the prior art, the lines and the closed area of the plate frame layer need to be manually modified and adjusted is solved, and the effect of rapidly, accurately and automatically processing the redundant lines of the plate frame layer is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board design, and in particular to an automatic processing method, device, equipment and medium for a board frame on a circuit board. Background Art

[0002] Before the PCB design engineer outputs the file to the structural engineer for inspection, it is necessary to manually check whether there are any problems with the devices on the edge of the board frame. If there are no problems, the board frame layer lines added by the packaging engineer in the package need to be unlocked and deleted. If there are problems, the board frame layer needs to be modified and adjusted to make the board frame layer in the PCB file unique. After operating the board frame, it is also necessary to modify the no-routing area on the edge of the board and the ground copper foil and vias around the board frame to prevent radiation. However, manual operation is prone to missing components for inspection, and the operation is cumbersome, and the manually modified board frame is uneven, affecting the appearance. Summary of the invention

[0003] The present invention provides a method, device, equipment and medium for automatically processing a board frame on a circuit board, so as to solve the problem in the prior art that the lines and closed areas of the board frame layer need to be manually modified and adjusted.

[0004] According to one aspect of the present invention, there is provided a method for automatically processing a board frame on a circuit board, comprising:

[0005] Acquire a first type of pattern and a second type of pattern on a target circuit board, wherein the first type of pattern is a closed area with a non-locked attribute in a board frame layer on the target circuit board, and the second type of pattern is a closed area and lines with a locked attribute in a board frame layer on the target circuit board;

[0006] Determine an initial main board frame corresponding to the target circuit board according to the first type pattern;

[0007] In response to the second type of pattern being embedded in the initial main body frame, performing unlocking and deleting operations on the second type of pattern, and re-copying the second type of pattern to the frame layer;

[0008] The corresponding target main body frame is composed based on the second type pattern copied to the frame layer and the initial main body frame after deleting the second type pattern.

[0009] According to another aspect of the present invention, there is provided an automatic processing device for a board frame on a circuit board, comprising:

[0010] A first acquisition module is used to acquire a first type of pattern and a second type of pattern on a target circuit board, wherein the first type of pattern is a closed area of ​​a non-locked attribute in a board frame layer on the target circuit board, and the second type of pattern is a closed area and lines of a locked attribute in a board frame layer on the target circuit board;

[0011] A first determination module, used to determine an initial main board frame corresponding to a target circuit board according to a first type of pattern;

[0012] a copy module, for performing unlocking and deleting operations on the second type of pattern in response to the second type of pattern being embedded in the initial main body frame, and recopying the second type of pattern to the frame layer;

[0013] The first generating module is used to form a corresponding target main body frame based on the second type pattern copied to the frame layer and the initial main body frame after deleting the second type pattern.

[0014] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0015] at least one processor; and

[0016] a memory communicatively connected to at least one processor; wherein,

[0017] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the automatic processing method of the board frame on the circuit board described in any embodiment of the present invention.

[0018] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the automatic processing method of a board frame on a circuit board described in any embodiment of the present invention when executed.

[0019] The technical solution of the embodiment of the present invention automatically traverses all patterns on the target circuit board through a program language, finds out the first type of pattern and the second type of pattern on the target circuit board, and avoids the problem of missing inspection and processing of the target circuit board; at the same time, a unified program language is used to unlock and delete the second type of pattern on the target circuit board, which solves the problem of cumbersome operation and low efficiency caused by manual unlocking and deleting of lines and closed areas of the board frame layer in the prior art, and achieves the effect of quickly and accurately automatically processing redundant lines of the board frame layer.

[0020] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 It is a schematic diagram showing the relative position between a terminal and a PCB board provided by the prior art;

[0023] Figure 2 It is another schematic diagram showing the relative position between the terminal and the PCB board provided by the prior art;

[0024] Figure 3 It is a schematic diagram showing lines in a board frame layer on a PCB board provided by the prior art;

[0025] Figure 4 It is a flow chart of a method for automatically processing a board frame on a circuit board provided by an embodiment of the present invention;

[0026] Figure 5 It is a flow chart of another method for automatically processing a board frame on a circuit board provided by an embodiment of the present invention;

[0027] Figure 6 is a flow chart of another method for automatically processing a board frame on a circuit board provided by an embodiment of the present invention;

[0028] Figure 7 is an overall display schematic diagram of a PCB board including a second type of pattern provided by an embodiment of the present invention;

[0029] Figure 8 is a partial display schematic diagram of another PCB board including a second type of pattern provided by an embodiment of the present invention;

[0030] Fig. 9 is a partial display schematic diagram of another PCB board including a second type of pattern provided by an embodiment of the present invention;

[0031] Fig.10 A display schematic diagram of a target main body frame provided by an embodiment of the present invention;

[0032] Fig.11 It is a schematic diagram showing the overall display of a PCB board including an initial forbidden area and a second type of pattern provided by an embodiment of the present invention;

[0033] Fig.12 It is a partial display schematic diagram of a PCB board including an initial forbidden area and a second type of pattern provided by an embodiment of the present invention;

[0034] Fig.13 It is a schematic diagram of the overall display of a target prohibited area provided by an embodiment of the present invention;

[0035] Fig.14 It is a partial display schematic diagram of a target prohibited deployment area provided by an embodiment of the present invention;

[0036] Fig.15 It is a schematic diagram showing the overall display of an initial top and bottom layer ground network provided by an embodiment of the present invention;

[0037] Fig.16 It is a partial display schematic diagram of an initial top and bottom layer ground network provided by an embodiment of the present invention;

[0038] Fig.17 It is a display schematic diagram of a target top and bottom layer network provided by an embodiment of the present invention;

[0039] Fig.18 A schematic diagram of the structure of an automatic processing device for a plate frame on a circuit board provided in Embodiment 3 of the present invention;

[0040] Fig.19 It is a structural block diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", "initial", "target", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] In the research and development stage of hardware products, after completing the design of the PCB board, the PCB design engineer outputs the 2D and 3D drawings of the PCB design and sends the drawings to the structural engineer for proofreading. After the inspection of all parties is completed, the production drawing Gerber file is issued to the board making factory for production. In the design process of the PCB board, the design of the board frame is very important. The board frame generally places the coastline terminals, various interfaces, and some buttons, lights and other devices. If the edge design of the board frame is unreasonable, it will cause problems in the welding and assembly of the most important functional terminals on the edge of the board. Such a PCB design fails to complete the most important functional design of the hardware product, which is a serious problem. Therefore, PCB design engineers need to pay great attention to the design of the board frame edge of the board. After the inspection of the PCB board is done, there will be no problem in the output to the structural engineer and the factory production, and production and welding assembly can be carried out. In the design process of the product, the general coastline terminals are placed according to the product appearance. The structural engineer extends the terminal out of the board for a certain distance according to the shell of the product, or goes deeper into the board for a certain distance.

[0044] Figure 1 It is a schematic diagram showing the relative position between a terminal and a PCB board provided by the prior art. Figure 2 Another schematic diagram showing the relative position between the terminal and the PCB board provided by the prior art. Figure 1 and 2 As shown, the actual terminals cannot extend into the PCB board without limit. Some terminal structures will extend below the plane of the board. If the board frame is still square without any changes, it is easy to cause problems in the mounting of the device. Figure 3 This is a schematic diagram showing the lines in the frame layer of a PCB board provided by the prior art. Figure 3 As shown, on the device side, the packaging engineer reminds the PCB design engineer not to place the device into the board by adding lines or closed lines on the board frame layer. At the same time, the distance into the board cannot exceed this line, otherwise the board frame layer needs to be modified according to this line.

[0045] In the prior art, it is generally necessary to manually check whether there are any problems with the devices at the edge of the board frame layer, and manually modify and adjust the devices with problems, resulting in the following defects:

[0046] First, it is easy to miss. During the inspection process, because there are many devices on the edge of the board frame, it is easy to miss the device for inspection. At the same time, because of the manual inspection, some devices have their own board frame layer lines that overlap with the PCB board frame, so it is difficult to check. No matter what kind of omission, as long as the board frame layer in the PCB file is not handled properly to make it unique, the PCB design software cannot accurately identify the unique board frame during the process of outputting the file to the structural engineer for inspection, and a variety of strange file phenomena will appear, such as the inability to directly output the structure file, the output 3D file does not have a physical board frame, or there are multiple board frames in the output file. When the PCB is output to the structural engineer for inspection, the problems that can be found by the structural engineer can be intercepted. However, some problems that are not found by the inspection will flow to the board making factory. At this time, the factory that causes engineering ambiguity will raise engineering questions to make the EQ engineer and PCB engineer respond, thereby delaying the efficiency of board making. What is more serious is the board frame error problem that flows to the factory. If the factory does not identify the problem and directly produces according to the drawing, some devices in the subsequent PCB production process may not be able to be welded normally.

[0047] Second, the operation is cumbersome. Regardless of whether there are any problems in the PCB inspection, the board frame layer lines in the package need to be unlocked and deleted. Therefore, all the components around the basic board frame need to be operated once, and the operation steps are basically the same, which is cumbersome and inefficient.

[0048] Third, the manually modified board edge is uneven and has a low standard aesthetics. For PCB boards, there is generally a circle of prohibited wiring area, which is mainly based on the inward shrinkage of the board frame edge by about 0.5mm to prevent the wiring from being too close to the board edge, resulting in the possibility of being scratched by the machine during the production process. Further inward shrinkage of the board, that is, the real wiring area, the outermost circle will normally have a circle of ground copper foil and punch holes at the same time to form a shield to prevent radiation from outward or external radiation from inward affecting the signal. After checking the devices on the edge of the board, if there are any modifications, you need to manually modify the outline of the board edge, and you also need to manually modify the prohibited wiring area, as well as the ground copper foil and vias on the edge of the board. Manual modifications have problems such as non-standard and unsightly.

[0049] In view of this, an embodiment of the present invention provides an automatic processing method for a board frame on a circuit board, so as to quickly and accurately process redundant lines on the board frame layer.

[0050] In one embodiment, Figure 4This is a flowchart of a method for automatically processing a frame on a circuit board provided by an embodiment of the present invention. This embodiment is applicable to the case of automatically processing lines on a frame layer on a circuit board. The method can be executed by an automatic processing device for a frame on a circuit board. The automatic processing device for a frame on a circuit board can be implemented in the form of hardware and / or software. The automatic processing device for a frame on a circuit board can be configured in an electronic device. A Skill application is installed in the electronic device, and the Skill application is called to automatically process the lines on the frame layer on the circuit board. Figure 4 As shown, the method includes:

[0051] S110, acquiring a first type of pattern and a second type of pattern on a target circuit board.

[0052] The first type of pattern is a closed area with a non-locking attribute in the board frame layer on the target circuit board, and the second type of pattern is a closed area and lines with a locking attribute in the board frame layer on the target circuit board.

[0053] The properties of each pattern (such as the first type pattern or the second type pattern) on the target circuit board may include: non-locked properties or locked properties. In actual operation, you can view the properties by clicking on each pattern. When lock is displayed, it means that the pattern has a locked property; when lock is not displayed, it means that the pattern has a non-locked property.

[0054] In an embodiment, a filter in a Skill application is called to filter out all packaging areas of the board frame layer. Since the closed area of ​​the locked attribute may be provided by the device on the target circuit board, the filter can be used to filter out the closed area of ​​the locked attribute, and the closed area of ​​the non-locked attribute can be used as the first type of pattern; and the filter is called to filter out the closed area and lines of the locked attribute as the second type of pattern.

[0055] S120, determining an initial main board frame corresponding to the target circuit board according to the first type pattern.

[0056] The initial main board frame is used to represent the initial frame of the target circuit board.

[0057] In one embodiment, S120 includes S1201-S1202:

[0058] S1201: Obtain the area size of each first type pattern.

[0059] In an embodiment, one or more first-type patterns may be included on the target circuit board. The first-type pattern may be understood as a closed area of ​​a non-locking attribute in the frame layer on the target circuit board, or may be understood as a shape of a non-locking attribute. In actual operation, the first-type pattern may include: a slot, a large opening, or a main body frame of an edge in the frame layer on the target circuit board.

[0060] S1202: Use the first type pattern with the largest area size as an initial main board frame corresponding to the target circuit board.

[0061] In the actual operation process, there are grooves or large openings in the frame layer of the target circuit board. In order to ensure the accuracy of the confirmation of the main frame, the area sizes of all first-type patterns in the frame layer of the target circuit board are directly compared, and the first-type pattern with the largest area size is used as the initial main frame corresponding to the target circuit board.

[0062] S130 , in response to the second type pattern being embedded in the initial main body frame, performing unlocking and deleting operations on the second type pattern, and re-copying the second type pattern to the frame layer.

[0063] In an embodiment, the area function can be called to determine whether the second type pattern is within the initial main body frame, that is, whether part or all of the lines in each second type pattern are in the middle of the initial main body frame. If it is detected that there is a second type pattern embedded in the initial main body frame, the copy function is called to copy the second type pattern embedded in the initial main body frame on the frame layer, and all the second type patterns are unlocked and deleted, that is, the locked attribute of all the second type patterns is changed to the unlocked attribute.

[0064] S140 , forming a corresponding target main body frame based on the second type pattern copied to the frame layer and the initial main body frame after deleting the second type pattern.

[0065] In one embodiment, S140 includes: S1401-S1404:

[0066] S1401, identifying and extracting non-intersecting patterns in the second type of patterns copied to the board frame layer, wherein the non-intersecting patterns are patterns that do not intersect with the initial main board frame.

[0067] S1402: Extend the non-intersecting pattern until it intersects with the initial main body frame.

[0068] S1403: Perform a cutting operation on the initial main body frame after deleting the second type of pattern and the redundant pattern extending outside the initial main body frame based on the intersecting coordinates.

[0069] S1404, forming a corresponding target main frame based on all patterns in the frame layer.

[0070] In the embodiment, it is determined whether the second type of pattern intersects with the initial main body frame. If there is an unintersected pattern, an extension operation is performed on the unintersected pattern until it is extended to the position intersecting with the nearest board edge in the initial main body frame, and the initial main body frame and the redundant pattern extending outside the initial main body frame are cut by the intersecting coordinates. After the cutting operation, the entire initial main body frame is composed of disconnected lines. A filter can be used to filter out all the lines in the frame layer, and a combination function can be called to combine all the lines into the corresponding target main body frame, thereby obtaining a complete main body frame on the target circuit board.

[0071] The technical solution of this embodiment automatically traverses all patterns on the target circuit board through a program language, finds out the first type of patterns and the second type of patterns on the target circuit board, and avoids the problem of missing inspection and processing of the target circuit board; at the same time, a unified program language is used to unlock and delete the second type of patterns on the target circuit board, which solves the problem of cumbersome operation and low efficiency caused by manual unlocking and deletion of lines and closed areas of the board frame layer in the prior art, and achieves the effect of quickly and accurately automatically processing redundant lines of the board frame layer.

[0072] In one embodiment, Figure 5 1 is a flowchart of another method for automatically processing a board frame on a circuit board provided by an embodiment of the present invention. This embodiment is based on the above embodiment and describes the generation process of the forbidden area, the annular copper foil and the via. Figure 5 As shown, the method includes:

[0073] S210 , obtaining a first type of pattern and a second type of pattern on a target circuit board.

[0074] The first type of pattern is a closed area with a non-locking attribute in the board frame layer on the target circuit board, and the second type of pattern is a closed area and lines with a locking attribute in the board frame layer on the target circuit board.

[0075] S220: Determine an initial main board frame corresponding to the target circuit board according to the first type pattern.

[0076] S230 , in response to the second type pattern being embedded in the initial main body frame, performing unlocking and deleting operations on the second type pattern, and re-copying the second type pattern to the frame layer.

[0077] S240: compose a corresponding target main body frame based on the second type pattern copied to the frame layer and the initial main body frame.

[0078] S250, obtaining an initial forbidden area in a forbidden area layer in a target circuit board.

[0079] The initial forbidden wiring area refers to the maximum area on the target circuit board where wiring is allowed. It can be understood that wiring is not allowed outside the initial forbidden wiring area and outside the initial main board frame.

[0080] S260: Generate a target prohibited layout area corresponding to the target circuit board according to the target main frame and a pre-configured first retracted distance.

[0081] The first retracted distance refers to a pre-configured distance that needs to be reduced inward based on the target main body frame. In an embodiment, a copy function is called, and the target main body frame is copied to the forbidden layer using the first retracted distance to obtain a new forbidden area on the target circuit board as the corresponding target forbidden area.

[0082] S270: Delete the initial prohibited area, and deploy the target prohibited area in the prohibited area layer.

[0083] S280, obtaining an initial top-layer ground network corresponding to a top copper layer in a target circuit board, and an initial bottom-layer ground network corresponding to a bottom copper layer.

[0084] In an embodiment, a filter is called to open the top copper layer and the bottom copper layer, and a closed area closest to the coordinates corresponding to the initial forbidden area is selected as the corresponding initial top ground network and initial bottom ground network.

[0085] In an embodiment, the deletion function is called to delete the copper foil corresponding to the initial top-layer ground network and the initial bottom-layer ground network.

[0086] S290: Generate a corresponding target top-layer ground-enclosing network and a target bottom-layer ground-enclosing network according to the pre-generated target prohibited area and the pre-configured second shrinkage distance.

[0087] In one embodiment, S290 includes: S2901-S2905:

[0088] S2901. Generate a corresponding annular copper skin according to a pre-generated target prohibited area and a pre-configured second retracted distance.

[0089] In an embodiment, the second retraction distance refers to a pre-configured distance that needs to be reduced inward based on the target prohibited area. In an embodiment, the second retraction distance can be the same as the first retraction distance, thereby ensuring the aesthetics of the target circuit board. Of course, the first retraction distance and the second retraction distance can also be different, and can be adjusted according to the actual design of the target circuit board. In an embodiment, a copy function is called, and the target prohibited area is copied to the top copper layer and the bottom copper layer using the second retraction distance to generate a ring-shaped copper skin with the same shape as the target prohibited area and reduced inward by the second retraction distance.

[0090] S2902: Generate corresponding target vias based on the annular copper sheet and the pre-configured via spacing distance.

[0091] The via spacing distance refers to the relative distance between two vias. The via spacing distance can be configured according to the function of the target circuit board. Generally speaking, the via spacing distance is at least 0.5 mm. In an embodiment, the matrix punching function is called to place the vias according to the shape of the annular copper sheet and the via spacing distance to obtain the corresponding target vias.

[0092] S2903, calling the network assignment function to adjust the annular copper foil and the target via to a ground network, and obtaining a corresponding target top-layer ground network and a target bottom-layer ground network.

[0093] In an embodiment, the network assignment function is called to adjust the annular copper skin and the target via to ground networks at the same time, and the ground network corresponding to the annular copper skin and the ground network corresponding to the target via are used as the corresponding target top-layer ground network and target bottom-layer ground network.

[0094] S2904, obtaining initial vias on an initial top-layer ground network and an initial bottom-layer ground network in a target circuit board.

[0095] In an embodiment, after the initial top-layer ground package network and the initial bottom-layer ground package network are obtained by using a filter, the via holes on the initial top-layer ground package network and the initial bottom-layer ground package network are obtained by using a filter as corresponding initial via holes.

[0096] S2905. Delete the initial via.

[0097] S2906. Deploy the target via in the target top-layer ground network and the target bottom-layer ground network.

[0098] In an embodiment, the deletion function is called to delete the initial via from the initial top-level ground network and the initial bottom-level ground network, and the target via is deployed in the target top-level ground network and the target bottom-level ground network.

[0099] S2100. Delete the initial top-level land-enclosed network and the initial bottom-level land-enclosed network.

[0100] S2110 . Deploy the target top-layer ground-enclosed network on the top-layer copper layer, and deploy the target bottom-layer ground-enclosed network on the bottom-layer copper layer.

[0101] In an embodiment, the initial top-level ground network in the top copper layer is deleted, and the target top-level ground network is deployed in the top copper layer; at the same time, the initial bottom-level ground network in the bottom copper layer is deleted, and the target bottom-level ground network is deployed in the bottom copper layer.

[0102] The technical solution of this embodiment, based on the above-mentioned embodiment, automatically generates a corresponding target forbidden area according to the target main frame and the first retracted distance, generates a corresponding annular copper foil according to the target forbidden area and the second retracted distance, and generates a corresponding target via based on the annular copper foil and the via spacing distance, thereby being able to quickly and accurately handle the problem of copper foil modification caused by frame sunkenness, and improving the processing efficiency of the frame while ensuring the accuracy and aesthetics of the modification.

[0103] In one embodiment, Figure 6 It is a flowchart of another method for automatically processing a frame on a circuit board provided by an embodiment of the present invention. This embodiment is based on the above embodiment and is used as a preferred embodiment to illustrate the automatic processing process of a frame on a circuit board. In this embodiment, the target circuit board is a PCB board, the closed area is a shape, the line is a line, the first retracted distance and the second retracted distance are both 0.5mm, and the second type of pattern includes a shape and a line with a locking attribute as an example to illustrate the automatic processing process of a frame on a circuit board. Figure 6 As shown, this embodiment includes the following steps:

[0104] S310, calling the Skill application to obtain the shape of the maximum area size of the non-locked attribute of the board frame layer on the PCB board, and determining the initial main board frame according to the shape of the maximum area size.

[0105] S320, obtaining a line or shape of a locked attribute of a device in a board frame layer.

[0106] In one embodiment, Figure 7 FIG. 1 is a schematic diagram showing an overall display of a PCB board including a second type of pattern provided by an embodiment of the present invention. Figure 7 As shown, the filter is called to filter out the lines and shapes with locked attributes. Among them, line 1 refers to the shape with locked attributes, and line 2 is composed of lines with locked attributes.

[0107] S330, determine whether the line or shape with the locked attribute is in the main frame shape, if so, execute S340; if not, end.

[0108] S340, copy the line or shape with locked attribute once in the target main body frame to the frame layer, and unlock and delete all the acquired lines or shapes belonging to the device lock.

[0109] In one embodiment, Figure 8 FIG. 1 is a partial schematic diagram of another PCB board including a second type of pattern provided by an embodiment of the present invention. Figure 8 As shown, the board frame layer on the PCB board is displayed, and other layers except the board frame layer are hidden, wherein line 1 and line 2 on the target main board frame are copied to the board frame layer.

[0110] S350, extending the copied line or shape until it intersects with the target main body frame, and cutting and deleting the original redundant lines of the target main body frame and the line or shape extending outside the target main body frame.

[0111] In one embodiment, Fig. 9 is a partial display schematic diagram of another PCB board including a second type of pattern provided by an embodiment of the present invention. Figure 8 On the basis of , the line that does not intersect with the target main frame (i.e. line 2) is extended until it intersects with the target main frame, and the following is obtained: Fig. 9 The pattern shown.

[0112] S360, the copied line or shape is combined with the cut target main body frame line to form a new shape to obtain the target main body frame.

[0113] In one embodiment, Fig.10 A display schematic diagram of a target main body frame provided by an embodiment of the present invention. Fig. 9 Based on the above, the redundant lines in the target main frame and the lines or shapes extending outside the target main frame are cut and deleted to obtain the following Fig.10 The target body frame shown.

[0114] S370, obtaining the initial prohibited area, deleting it, and generating a new target prohibited area by shrinking the entire target main body frame by 0.5 mm.

[0115] In one embodiment, Fig.11 1 is a schematic diagram showing the overall display of a PCB board including an initial forbidden area and a second type of pattern provided by an embodiment of the present invention. Fig.11As shown, call the filter to open the forbidden area layer, and select the shape type to obtain the initial forbidden area. Fig.12 1 is a partial display schematic diagram of a PCB board including an initial forbidden area and a second type of pattern provided by an embodiment of the present invention. Fig.12 As shown, the shape of the closed area in the second type of pattern intersects with the initial forbidden area, and the line does not intersect with the initial forbidden area.

[0116] In one embodiment, Fig.13 It is a schematic diagram of the overall display of a target prohibited area provided by an embodiment of the present invention; Fig.14 FIG. 1 is a schematic diagram of a partial display of a target prohibited deployment area provided by an embodiment of the present invention. Fig.13 As shown, call the copy function and use the parameter of shrinking 0.5mm to copy the target main frame to the forbidden layer, and get the following Fig.13 At the same time, the shape of the target forbidden area is the same as the shape of the target main body frame, such as Fig.14 shown.

[0117] S380, obtaining the top and bottom layer ground network shapes and the initial vias on the shapes, and deleting the top and bottom layer ground network and the initial vias, generating new target top and bottom layer ground networks according to the newly generated target forbidden areas, and punching target vias at the same time.

[0118] In an embodiment, Fig.15 It is a schematic diagram showing the overall display of an initial top and bottom layer ground network provided by an embodiment of the present invention; Fig.16 The following is a partial display diagram of an initial top and bottom layer ground network provided by an embodiment of the present invention. The filter is called to open the top copper layer and the bottom copper layer, and the shape with the coordinates closest to the initial forbidden area is selected as the initial top and bottom layer ground network. Fig.15 and Fig.16 The arrows shown are pointing to the lines.

[0119] Fig.17 This is a display diagram of a target top and bottom layer ground network provided by an embodiment of the present invention. Then, the copy function is called, and the target forbidden area is copied to the top copper layer and the bottom copper layer using the function of shrinking 0.5mm to generate a ring copper layer with the same shape as the target forbidden area, and the matrix punching function is called to place the target vias according to the shape of the ring copper layer and the via spacing distance.

[0120] In one embodiment, Fig.18 This is a schematic diagram of the structure of an automatic processing device for a board frame on a circuit board provided in the third embodiment of the present invention. Fig.18As shown, the device includes: a first acquisition module 410, a first determination module 420, a copy module 430 and a first generation module 440.

[0121] The first acquisition module 410 is used to acquire a first type of pattern and a second type of pattern on the target circuit board, wherein the first type of pattern is a closed area with a non-locked attribute in the board frame layer on the target circuit board, and the second type of pattern is a closed area and lines with a locked attribute in the board frame layer on the target circuit board;

[0122] A first determination module 420 is used to determine an initial main board frame corresponding to the target circuit board according to the first type of pattern;

[0123] The copy module 430 is used for performing unlocking and deleting operations on the second type of pattern in response to the second type of pattern being embedded in the initial main body frame, and re-copying the second type of pattern to the frame layer;

[0124] The first generating module 440 is used to form a corresponding target main body frame based on the second type pattern copied to the frame layer and the initial main body frame after deleting the second type pattern.

[0125] In one embodiment, the automatic processing device for the frame on the circuit board further includes:

[0126] A second acquisition module is used to acquire an initial forbidden area in a forbidden area layer in a target circuit board;

[0127] The second generating module is used to generate a target prohibited layout area corresponding to the target circuit board according to the target main board frame and the pre-configured first retracted distance;

[0128] The first deletion deployment module is used to delete the initial prohibited area and deploy the target prohibited area in the prohibited area layer.

[0129] In one embodiment, the automatic processing device for the frame on the circuit board further includes:

[0130] A third acquisition module is used to acquire an initial top-layer ground network corresponding to a top copper layer in a target circuit board, and an initial bottom-layer ground network corresponding to a bottom copper layer;

[0131] The third generation module is used to generate a corresponding target top-layer ground-enclosing network and a target bottom-layer ground-enclosing network according to a pre-generated target prohibited area and a pre-configured second shrinkage distance;

[0132] The first deletion module is used to delete the initial top-level land-enclosing network and the initial bottom-level land-enclosing network;

[0133] The first deployment module is used to deploy the target top-layer ground-enclosed network on the top copper layer, and to deploy the target bottom-layer ground-enclosed network on the bottom copper layer.

[0134] In one embodiment, the third generation module includes:

[0135] A first generating unit is used to generate a corresponding annular copper skin according to a pre-generated target prohibited area and a pre-configured second retracted distance;

[0136] A second generating unit is used to generate corresponding target vias based on the annular copper skin and the pre-configured via spacing distance;

[0137] The adjustment unit is used to call the network assignment function to adjust the annular copper foil and the target via hole to a ground network, and obtain the corresponding target top-layer ground network and target bottom-layer ground network.

[0138] In one embodiment, the third generation module further includes:

[0139] An acquisition unit, used for acquiring initial vias on an initial top-layer ground network and an initial bottom-layer ground network in a target circuit board;

[0140] Delete unit, used to delete the initial via;

[0141] The deployment unit is used to deploy the target via in the target top-layer ground network and the target bottom-layer ground network.

[0142] In one embodiment, the first determining module 420 includes:

[0143] An acquisition unit, used for acquiring the area size of each first type pattern;

[0144] The determination unit is used to use the first type pattern with the largest area size as an initial main board frame corresponding to the target circuit board.

[0145] In one embodiment, the first generating module 440 includes:

[0146] An identification and extraction unit, used for identifying and extracting non-intersecting patterns in the second type of pattern copied to the plate frame layer, wherein the non-intersecting patterns are patterns that do not intersect with the initial main plate frame;

[0147] An extension unit, used for performing an extension operation on the non-intersecting pattern until it intersects with the initial main body frame;

[0148] A cutting unit, configured to cut the initial main frame after deleting the second type of pattern and the redundant pattern extending outside the initial main frame based on the intersecting coordinates;

[0149] The first generating unit is used for forming a corresponding target main frame based on all patterns in the frame layer.

[0150] The automatic processing device for a frame on a circuit board provided in an embodiment of the present invention can execute the automatic processing method for a frame on a circuit board provided in any embodiment of the present invention, and has functional modules and beneficial effects corresponding to the execution method.

[0151] In one embodiment, Fig.19 is a structural block diagram of an electronic device provided by an embodiment of the present invention. Fig.19 As shown, a schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0152] like Fig.19 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0153] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0154] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as an automatic processing method for a board frame on a circuit board.

[0155] In some embodiments, the automatic processing method of the board frame on the circuit board can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the automatic processing method of the board frame on the circuit board described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the automatic processing method of the board frame on the circuit board by any other appropriate means (for example, by means of firmware).

[0156] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0157] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0158] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0159] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0160] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0161] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0162] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0163] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for automatically processing a frame on a circuit board, It is characterized in that include: Acquire a first type of pattern and a second type of pattern on a target circuit board, wherein the first type of pattern is a closed area with a non-locked attribute in a board frame layer on the target circuit board, and the second type of pattern is a closed area and lines with a locked attribute in a board frame layer on the target circuit board; Determine an initial main board frame corresponding to the target circuit board according to the first type of pattern; In response to the second type of pattern being embedded in the initial main body frame, performing unlocking and deleting operations on the second type of pattern, and re-copying the second type of pattern to the frame layer; The corresponding target main body frame is composed based on the second type pattern copied to the frame layer and the initial main body frame after deleting the second type pattern.

2. The method according to claim 1, It is characterized in that The method further comprises: Acquire an initial forbidden area in a forbidden area layer in the target circuit board; Generate a target prohibited layout area corresponding to the target circuit board according to the target main frame and a pre-configured first retracted distance; The initial forbidden area is deleted, and the target forbidden area is deployed in the forbidden area layer.

3. The method according to claim 1, It is characterized in that The method further comprises: Obtaining an initial top-layer ground network corresponding to a top copper layer in the target circuit board, and an initial bottom-layer ground network corresponding to a bottom copper layer; Generate a corresponding target top-layer ground-enclosing network and a target bottom-layer ground-enclosing network according to a pre-generated target forbidden area and a pre-configured second retracted distance; Deleting the initial top-level network and the initial bottom-level network; The target top-layer ground network is deployed on the top copper layer, and the target bottom-layer ground network is deployed on the bottom copper layer.

4. The method according to claim 3, It is characterized in that The method of generating a corresponding target top-layer ground-enclosing network and a target bottom-layer ground-enclosing network according to a pre-generated target prohibited area and a pre-configured second shrinkage distance includes: Generate a corresponding annular copper skin according to a pre-generated target prohibited area and a pre-configured second retracted distance; Generate corresponding target vias based on the annular copper sheet and a pre-configured via spacing distance; The network assignment function is called to adjust the annular copper foil and the target via hole to a ground network, and obtain a corresponding target top-layer ground network and a target bottom-layer ground network.

5. The method according to claim 4, It is characterized in that Also includes: Obtain initial vias on an initial top-layer ground network and an initial bottom-layer ground network in a target circuit board; Deleting the initial via; The target vias are disposed in the target top-layer ground network and the target bottom-layer ground network.

6. The method according to any one of claims 1 to 5, It is characterized in that The step of determining an initial main board frame corresponding to the target circuit board according to the first type of pattern includes: Obtaining the area size of each of the first-type patterns; The first type pattern with the largest area size is used as the initial main board frame corresponding to the target circuit board.

7. The method according to any one of claims 1 to 5, It is characterized in that The forming of a corresponding target main frame based on the second type pattern copied to the frame layer and the initial main frame after deleting the second type pattern comprises: Identifying and extracting non-intersecting patterns in the second type of patterns copied back to the board frame layer, wherein the non-intersecting patterns are patterns that do not intersect with the initial main board frame; Performing an extension operation on the non-intersecting pattern until it intersects with the initial main body frame; Performing a cutting operation on the initial main body frame after deleting the second type of pattern and the redundant pattern extending outside the initial main body frame based on the intersecting coordinates; The target main frame is formed based on all the patterns in the frame layer.

8. An automatic processing device for the frame of a circuit board, It is characterized in that include: A first acquisition module is used to acquire a first type of pattern and a second type of pattern on a target circuit board, wherein the first type of pattern is a closed area of ​​a non-locked attribute in a board frame layer on the target circuit board, and the second type of pattern is a closed area and lines of a locked attribute in a board frame layer on the target circuit board; A first determining module, configured to determine an initial main board frame corresponding to the target circuit board according to the first type of pattern; a copy module, configured to, in response to the second type of pattern being embedded in the initial main body frame, perform unlocking and deleting operations on the second type of pattern, and recopy the second type of pattern to the frame layer; A generating module is used to form a corresponding target main body frame based on the second type pattern copied to the frame layer and the initial main body frame after deleting the second type pattern.

9. An electronic device, It is characterized in that The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the method for automatically processing a board frame on a circuit board according to any one of claims 1-7.

10. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method for automatically processing a board frame on a circuit board according to any one of claims 1 to 7 when executed.

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