Memory device

Abstract

A memory device having a row decoder circuit architecture is provided. The memory device includes a peripheral circuit structure and a cell array structure disposed on and vertically overlapping the peripheral circuit structure. The cell array structure may include a plurality of memory blocks including a plurality of vertical channel transistor structures and a plurality of capacitor structures respectively connected to the vertical channel transistor structures. The peripheral circuit structure includes a row decoder connected to a plurality of word lines of the plurality of memory blocks, and the row decoder includes: a first circuit group commonly connected to the plurality of memory blocks; and a second circuit group connected to each of the plurality of memory blocks.

Description

Technical Field

[0001] Apparatuses and methods consistent with embodiments of the present disclosure relate to a semiconductor device, and more particularly, to a memory device having a row decoder architecture for reducing a chip size of the memory device. Background Art

[0002] Recently, with the multifunctionalization of information and communication devices, storage devices with larger capacity and higher integration are needed. As the size of the storage unit is reduced to facilitate high integration, the operation circuit and / or wiring structure for the operation and electrical connection of the storage device in the storage device becomes more complicated. Therefore, a storage device with improved integration and excellent electrical characteristics is needed. In order to improve the storage capacity and integration of the storage device, instead of relying on a planar channel transistor formed on a semiconductor substrate, a vertical channel transistor formed vertically on a semiconductor substrate is introduced.

[0003] For example, a memory device such as a dynamic random access memory (DRAM) includes a plurality of memory cells, and the plurality of memory cells include vertical channel transistors and capacitors. The memory device operates by reading and writing data using the charge stored in the capacitor. The memory cell is connected to a word line and a bit line. In a DRAM, during a read operation or a refresh operation, a row decoder decodes a given row address to select a word line corresponding to the row address, and applies a word line drive voltage of a high voltage VPP to the selected word line. In addition, the sense amplifier can read the voltage level of the bit line corresponding to the column address from the bit line of the memory cell connected to the selected word line.

[0004] A DRAM may have a cell over periphery (COP) structure including a cell array structure and a peripheral circuit structure overlapping each other in a vertical direction. The cell array structure may include a memory cell array including a plurality of memory cells, and the peripheral circuit structure may include a peripheral circuit. The plurality of memory cells include vertical channel transistors and capacitors, and the peripheral circuit includes a row decoder and a sense amplifier. As memory processes continue to shrink, the proportion of the area occupied by the peripheral circuit area increases relative to the area occupied by the memory cell array area. Therefore, the chip size of a DRAM having a COP structure depends primarily on the area occupied by the peripheral circuit area.

[0005] In order to reduce the chip size of DRAM, it is necessary to reduce the area occupied by the peripheral circuit region. Reducing the area allocated to the row decoder can achieve a reduction in the chip size of DRAM. Summary of the invention

[0006] One or more example embodiments provide a memory device having a row decoder circuit architecture associated with a plurality of memory cells including vertical channel transistors and reducing a chip size of the memory device.

[0007] According to one aspect of the present disclosure, a memory device may include: a peripheral circuit structure; and a cell array structure, the cell array structure being disposed on the peripheral circuit structure and overlapping the peripheral circuit structure in a vertical direction, wherein the cell array structure may include a plurality of memory blocks arranged in a first horizontal direction. Each of the plurality of memory blocks includes: a memory cell area, the memory cell area including a plurality of word lines and a plurality of bit lines, each of the plurality of word lines extending in the first horizontal direction, and each of the plurality of bit lines extending in a second horizontal direction perpendicular to the first horizontal direction, wherein the peripheral circuit structure may include a row decoder, the row decoder being connected to the plurality of word lines of each of the plurality of memory blocks. The row decoder may include: a first circuit group, the first circuit group being configured to generate a main word line drive signal and a sub-word line drive signal, the first circuit group being commonly connected to the plurality of memory blocks; and a second circuit group, the second circuit group being configured to generate a local main word line drive signal and a local sub-word line drive signal, being connected to each of the plurality of memory blocks, and activating one word line among the plurality of word lines of a memory block selected from the plurality of memory blocks.

[0008] According to another aspect of the present disclosure, a memory device may include: a peripheral circuit structure; and a cell array structure, which is arranged on the peripheral circuit structure and overlaps with the peripheral circuit structure in a vertical direction, wherein the cell array structure may include a plurality of memory blocks arranged in a first horizontal direction. Each of the multiple storage blocks includes: a storage cell area, the storage cell area includes multiple word lines and multiple bit lines, each of the multiple word lines extends in the first horizontal direction, and each of the multiple bit lines extends in a second horizontal direction perpendicular to the first horizontal direction, wherein the peripheral circuit structure may include a row decoder, the row decoder is connected to the even word lines and odd word lines among the multiple word lines of each of the multiple storage blocks, and the row decoder includes: a first circuit group, the first circuit group is commonly connected to the multiple storage blocks and is configured to generate a main word line drive signal and a sub-word line drive signal associated with the even word line and the odd word line based on a row address signal; and a second circuit group, the second circuit group is commonly connected to the multiple storage blocks and is configured to generate a local main word line drive signal and a local sub-word line drive signal associated with the even word line and the odd word line based on the row address signal, and activates one word line among the even word lines and the odd word lines of a storage block selected from the multiple storage blocks.

[0009] According to another aspect of the present disclosure, a memory device is provided, the memory device comprising: a memory cell array, the memory cell array comprising a plurality of memory cells connected to a plurality of word lines, wherein the memory cell array comprises a plurality of memory blocks; and a row decoder, the row decoder being connected to a plurality of word lines of each of the plurality of memory blocks. The row decoder comprises: a first circuit group, the first circuit group being configured to generate a main word line drive signal and a sub-word line drive signal based on a row address signal, the first circuit group being commonly connected to the plurality of memory blocks; and a second circuit group, the second circuit group being respectively connected to the plurality of memory blocks and being configured to generate a local main word line drive signal and a local sub-word line drive signal, and activating one word line among a plurality of word lines of a memory block selected from the plurality of memory blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 and Figure 2 is a diagram for describing a memory device according to an embodiment;

[0012] Figure 3 is a block diagram for describing a row decoder according to an embodiment;

[0013] Figure 4A and Figure 4B Is used to describe Figure 3 A circuit diagram of a main word line drive signal generating circuit;

[0014] Figure 5A , Figure 5B and Figure 5C Is used to describe Figure 3 A circuit diagram of a sub-word line drive signal generating circuit;

[0015] Figure 6 Is used to describe Figure 3 A circuit diagram of a local main word line drive signal generating circuit;

[0016] Figure 7 Is used to describe Figure 3 A circuit diagram of a first local sub-word line drive signal generating circuit;

[0017] Figure 8 Is used to describe Figure 3 A circuit diagram of a second local sub-word line drive signal generating circuit;

[0018] Fig. 9 Is used to describe Figure 3 A circuit diagram of a sub-word line driving circuit;

[0019] Fig.10 is used to describe Figure 3 A diagram of a row decoder architecture in which a row decoder of is disposed in a memory device;

[0020] Fig.11 is a block diagram for describing a row decoder according to an embodiment;

[0021] Fig. 12A and Fig. 12B Is used to describe Fig.11 A circuit diagram of a second sub-word line drive signal generating circuit;

[0022] Fig.13A and Fig. 13B Is used to describe Fig.11 A circuit diagram of a third sub-word line drive signal generating circuit;

[0023] Fig.14A and Fig. 14B Is used to describe Fig.11 A circuit diagram of a first local sub-word line drive signal generating circuit;

[0024] Fig.15A and Fig. 15B Is used to describe Fig.11 A circuit diagram of a second local sub-word line drive signal generating circuit;

[0025] Fig.16A and Fig. 16B Is used to describe Fig.11 A circuit diagram of a sub-word line driving circuit;

[0026] Fig.17 is used to describe Fig.11 A diagram of a row decoder architecture in which a row decoder of is disposed in a memory device;

[0027] Fig.18 is a diagram for describing a sense amplifier according to an embodiment;

[0028] Fig.19 is a diagram for describing a structure of a memory device according to an embodiment; and

[0029] Fig. 20 is a block diagram for describing a system of an electronic device including a memory device according to an embodiment. DETAILED DESCRIPTION

[0030] Figure 1 and Figure 2 is a diagram for describing a memory device according to an embodiment. Figure 2 Is used to describe Figure 1 FIG. 1 is a diagram showing a semiconductor structure of a memory device 10 .

[0031] refer to Figure 1 , the memory device 10 may include a peripheral circuit 100 and a memory cell array 200 connected to each other through a plurality of word lines WL and a plurality of bit lines BL. The peripheral circuit 100 may include a voltage generating circuit 110, a sense amplifier 120, a row decoder 130, and a column decoder 140. The peripheral circuit 100 may also include a control logic circuit, a data input / output circuit, a command decoder, a mode register, etc. According to an embodiment, the memory device 10 may be a dynamic random access memory (DRAM) including a plurality of memory cells, each memory cell including a vertical channel transistor and a capacitor. Hereinafter, the "memory device" will refer to the DRAM.

[0032] The memory cell array 200 may be connected to the row decoder 130 through the word line WL, and may be connected to the sense amplifier 120 through the bit line BL. In the memory cell array 200, a plurality of memory blocks BLK1, BLK2, . . . and BLKi ( Figure 2 ) (where "i" represents a positive integer) can be a DRAM memory cell. The memory cell array 200 includes a plurality of word lines WL and a plurality of bit lines BL ( Fig.18 ). The memory cell MC may include a cell transistor CT and a cell capacitor CC. The cell transistor CT may be implemented as a reference Fig.19The cell structure CS described above and the cell capacitor CC may be implemented as the capacitor structure 1990. The gate of the cell transistor CT is connected to one of the multiple word lines WL. One end of the cell transistor CT is connected to one of the multiple bit lines BL. The cell capacitor CC may store an amount of charge corresponding to a single bit of data or multiple bits of data.

[0033] The voltage generating circuit 110 may generate various internal voltages for driving the circuits of the memory device 10. The voltage generating circuit 110 may generate a high voltage VPP, a negative voltage VBB, an internal power supply voltage VINTA and a bit line precharge voltage VEQ, a reference voltage, a body bias voltage, etc. by using a power supply voltage (e.g., VDD) applied from the outside of the memory device 10.

[0034] For example, a high voltage VPP higher than the power supply voltage VDD is provided to the row decoder 130 and can be used for the word line driving circuit ( Figure 4A and Figure 5A ) to turn on the N-type metal oxide semiconductor (NMOS) cell transistor connected to the word line WL. The negative voltage VBB has a negative (-) voltage level lower than the voltage level of the power supply voltage VDD, and can be used to increase the data retention time by increasing the threshold voltage Vth of the NMOS cell transistor. The negative voltage VBB is applied to the well region in which the NMOS cell transistor is formed, and is generally referred to as a body bias voltage or a reverse bias voltage. In the sense amplifier 120 ( Fig.18 ) before generating a voltage difference between the bit line BL and the complementary bit line BLB, the bit line precharge voltage VEQ can equalize the voltage of the bit line BL and the complementary bit line BLB. The internal power supply voltage VINTA can be provided to the first read drive voltage line LA and the second read drive voltage line LAB of the sense amplifier 120. The sense amplifier 120 can sense and amplify the voltage difference between the bit line BL and the complementary bit line BLB according to the first read drive voltage line LA and the second read drive voltage line LAB. The reference voltage can be used to compare with the voltage of the signal received from the command / address bus to determine the logic value of the signal received from the memory controller.

[0035] The sense amplifier 120 may sense the data stored in the memory cell MC and transmit the sensed data to the data input / output circuit to output the sensed data to the outside of the memory device 10 through the data pad(s). The data input / output circuit may receive data to be written to the memory cell MC from the outside and transmit the data to the memory cell array 200. The data input / output circuit may output the read data by using a data line amplifier that receives and amplifies the data sensed by the sense amplifier 120. The read data may be output to the outside of the memory device 10 through the data pad(s).

[0036] The row decoder 130 may select at least one memory block from among the plurality of memory blocks BLK1, BLK2, . . . , and BLKi by decoding a row address provided to the memory device 10 and select a word line WL of the selected memory block. The row decoder 130 may provide a high voltage VPP for performing a storage operation to the selected word line WL.

[0037] The column decoder 140 may decode a column address provided to the memory device 10 and provide a column selection signal CSL for selecting a bit line BL corresponding to the column address. The bit line BL selected by the column selection signal CSL may be connected to a data input / output circuit.

[0038] refer to Figure 2 , the memory device 10 may include a cell array structure CAS and a peripheral circuit structure PCS overlapping each other in a vertical direction (Z direction). The cell array structure CAS may include Figure 1 The peripheral circuit structure PCS may include Figure 1 For the convenience of description, the row decoder 130 is shown in the peripheral circuit structure PCS. Figure 3 and Fig.11 The row decoder 130 is described.

[0039] The cell array structure CAS may include a plurality of memory blocks BLK1, BLK2, ..., and BLKi (where "i" represents a positive integer). The plurality of memory blocks BLK1, BLK2, ..., and BLKi may include a plurality of memory cells, and the plurality of memory cells include vertical channel transistors and capacitors. Fig.19 The cell array structure CAS and the peripheral circuit structure PCS are described in detail.

[0040] Figures 3 to 10 is a diagram for describing a row decoder according to an embodiment. Figure 3 is used to describe the corresponding Figure 1 8 is a block diagram of a row decoder 130 a of the row decoder 130 shown in FIG. Figure 4A and Figure 4B Is used to describe Figure 3 1 is a circuit diagram of a main word line drive signal generating circuit 310. FIG. 5A to FIG. 5C Is used to describe Figure 3 1 is a circuit diagram of a sub-word line driving signal generating circuit 320. Figure 6 Is used to describe Figure 3 1 is a circuit diagram of a local main word line drive signal generating circuit 330. Figure 7 Is used to describe Figure 3 1 is a circuit diagram of a first local sub-word line driving signal generating circuit 340. Figure 8 Is used to describe Figure 3 1 is a circuit diagram of a second local sub-word line driving signal generating circuit 350. Fig. 9 Is used to describe Figure 3 A circuit diagram of a sub-word line driving circuit 360 is shown. Fig.10 is used to describe Figure 3 1 is a diagram of a row decoder architecture 130a in which a row decoder is provided in the memory device 10. Hereinafter, letters attached to reference numerals ("a" in 130a and "b" in 130b, etc.) are used to distinguish multiple circuits having the same or substantially the same function.

[0041] refer to Figure 3 , the row decoder 130a may select and Figure 2 The word line WL corresponding to the row address RA of the selected storage block among the multiple storage blocks BLK1, BLK2, ..., and BLKi. In the following embodiments, for ease of explanation, each of the multiple storage blocks BLK1, BLK2, ..., and BLKi includes 1024 word lines WL, and the row decoder 130a may have a circuit configuration for selecting a word line WL from the 1024 word lines WL by decoding the row address RA<0:9>. According to the present embodiment, although it is described that each of the multiple storage blocks BLK1, BLK2, ..., and BLKi includes 1024 word lines configured according to 10 row addresses RA<0:9> signals, the embodiment is not limited thereto and may include various numbers of word lines. For example, multiple storage blocks BLK1, BLK2, ..., and BLKi may each include 2048 or 4096 word lines according to 11 row addresses RA<0:10> signal configurations or 12 row addresses RA<0:11> signal configurations.

[0042] The row decoder 130a may include a main word line drive signal generating circuit 310, a sub word line drive signal generating circuit 320, a local main word line drive signal generating circuit 330, a first local sub word line drive signal generating circuit 340, a second local sub word line drive signal generating circuit 350, and a sub word line drive circuit 360.

[0043] refer to Figure 3 , the circuit components of the row decoder 130a can be classified into a first circuit group and a second circuit group. The first circuit group may include a main word line drive signal generation circuit 310 and a sub-word line drive signal generation circuit 320. The main word line drive signal generation circuit 310 may generate a first main word line drive signal (e.g., NWE0<0:7>) and a second main word line drive signal (e.g., NWE1<0:7>) based on a signal from a more significant bit group among the row address signal. The sub-word line drive signal generation circuit 320 may generate a first sub-word line drive signal (e.g., PXID<0:3>), a second sub-word line drive signal (e.g., MPXI<0:3>), and a third sub-word line drive signal (e.g., PXIB<0:3>) based on a signal from a less significant bit group among the row address signal. The second circuit group may include a local main word line drive signal generation circuit 330, a first local sub-word line drive signal generation circuit 340, a second local sub-word line drive signal generation circuit 350, and a sub-word line drive circuit 360. The local main word line drive signal generation circuit 330 may generate a local main word line drive signal (e.g., LNWEIB<0:63>) based on the first main word line drive signal (e.g., NWE0<0:7>) and the second main word line drive signal (e.g., NWE1<0:7>). The first local sub-word line drive signal generation circuit 340 may generate a first local sub-word line drive signal (e.g., LPXID<0:15>) based on the first sub-word line drive signal (e.g., PXID<0:3>) and the second sub-word line drive signal (e.g., MPXI<0:3>). The second local sub-word line drive signal generation circuit 350 may generate a second local sub-word line drive signal (e.g., LPXIB<0:15>) based on the second sub-word line drive signal (e.g., MPXI<0:3>) and the third sub-word line drive signal (e.g., PXIB<0:3>). The sub-word line drive circuit 360 can be connected to the word line WL<0:1023> and can activate one word line among multiple word lines of a memory block selected from multiple memory blocks based on a local main word line drive signal (e.g., LNWEIB<0:63>), a first local sub-word line drive signal (e.g., LPXID<0:15>), and a second local sub-word line drive signal (e.g., LCXIB<0:15>).

[0044] The main word line drive signal generating circuit 310 may generate a first main word line drive signal NWE0<0:7> and a second main word line drive signal NWE1<0:7> based on a signal from the most significant bit (MSB) group among the row address RA<0:9> signals. The signal from the MSB group among the row address RA<0:9> signals may be set to the RA<4:9> row address. The RA<4:9> row address may include an RA<7:9> row address (hereinafter referred to as the "RA789" row address) corresponding to a more significant bit group and an RA<4:6> row address (hereinafter referred to as the "RA456" row address) corresponding to a less significant bit group. The less significant bit group may represent a lower order bit of the row address, and the more significant bit group may represent a higher order bit of the row address. The terms "lower" and "higher" are relative in the context of the bit group, where the least significant bit (LSB) is the rightmost bit, and the most significant bit (MSB) is the leftmost bit. The main word line driving signal generating circuit 310 may include a first main word line driving signal generating circuit 311 for generating a first main word line driving signal NWE0<0:7> by decoding a row address RA789 and a second main word line driving signal generating circuit 312 for generating a second main word line driving signal NWE1<0:7> by decoding a row address RA456. Although the following describes an example in which the main word line drive signal generating circuit 310 according to the present embodiment divides the MSB signal RA<4:9> from among the row address RA<0:9> signals into two groups (e.g., RA789 and RA456) and generates eight first main word line drive signals NWE0<0:7> and eight second main word line drive signals NWE1<0:7> based on the MSB signals of the two groups RA789 and RA456, the embodiment is not limited thereto, and the main word line drive signal generating circuit 310 may also generate four of each of the first to third main word line drive signals based on the MSB signals of the three groups (e.g., RA89, RA67, and RA45). In summary, the first to nth main word line drive signals may be generated based on the MSB signals of the row address signals of n groups ("n" is a natural number). According to other embodiments, the main word line drive signal generating circuit 310 can change the decoding used to generate multiple main word line drive signals NWE0, NWE1, ..., and NWEn-1 ("n" is a natural number) based on the number of bits (e.g., 5, 6 or 7) of the MSB group signal from the row address signal according to the configuration of each of the multiple storage blocks BLK1, BLK2, ..., and BLKi (i.e., the number of word lines; for example, 2048, 4096).At this time, when the number of signals constituting the main word line drive signal NWEk ​​(k is an integer equal to or greater than 0 and less than n) from among the plurality of main word line drive signals is num_k, the value obtained by multiplying all the numbers from num_0 to num_n-1 may be equal to the value obtained by multiplying 2 by itself by the number of bits of the MSB group signal num_MSB times. That is, it may be 2num_MSB=num_0x num_1x ... x num_n-1. For example, when num_MSB=7 and n=3, it may be determined that num_0=8, num_1=4, num_2=4, etc.

[0045] Figure 4A The first main word line drive signal generating circuit 311 may include first to fourth transistors 401 to 404 connected in series between a high voltage VPP line and a ground voltage VSS line, and may include an inverter 406 connected to a connection node 405 of the first transistor 401 and the second transistor 402. The first transistor 401 may be configured as a P-type metal oxide semiconductor (PMOS) transistor having a precharge signal PCGB connected to its gate, and the second transistor 402 may be configured as an NMOS transistor having a precharge signal PCGB connected to its gate. The precharge signal PCGB is provided based on a precharge command and may serve as a signal for activating the row decoder 130a. The row decoder 130a may be activated by a logic high level precharge signal PCGB, and the row decoder 130a may be deactivated by a logic low level precharge signal PCGB. The third transistor 403 may be configured as an NMOS transistor having a decoded RA789<0:7> row address signal connected to its gate, and the fourth transistor 404 may be configured as an NMOS transistor having a block select signal BLK_SELECT connected to its gate. A block selection signal BLK_SELECT may be provided to select a memory block from a plurality of memory blocks BLK1, BLK2, ..., and BLKi. For example, a logic high first block selection signal may be provided to select a first memory block BLK1. An inverter 406 connected to a connection node 405 of the first transistor 401 and the second transistor 402 may output a first main word line drive signal NWE0<0:7>.

[0046] The eight first main word line drive signal generating circuits 311 can each output the first main word line drive signal NWE0<0:7> in response to the decoded RA789<0:7> row address signal. Since the configuration of the decoded RA789<0:7> row address signal has eight cases (i.e., 000, 001, 010, 011, 100, 101, 110, and 111), the first main word line drive signal NWE0<0:7> can also have eight configurations. That is, a logic high level can be assigned to the first main word line drive signal NWE0 according to the decoded RA789<0:7> row address signal. <0> 、NWE0 <1> 、NWE0 <2> 、NWE0 <3> 、NWE0 <4> 、NWE0 <5> 、NWE0 <6> and NWE0 <7> The first main word line driving signal NWE0<0:7> of a logic high level may have a voltage level of a high voltage VPP and may be provided to a local main word line driving signal generating circuit 330 connected to each of the plurality of memory blocks BLK1, BLK2, . . . , and BLKi.

[0047] Figure 4B The second main word line drive signal generating circuit 312 may be composed of a series connection of first to fourth transistors 411 to 414 connected between a high voltage VPP line and a ground voltage VSS line, and may include an inverter 416 connected to a connection node 415 of the first transistor 411 and the second transistor 412. The second main word line drive signal generating circuit 312 has Figure 4A The first main word line driving signal generating circuit 311 has the same configuration, except that the decoded RA456<0:7> row address signal is connected to the gate of the third transistor 413 and the inverter 416 outputs the second main word line driving signal NWE1<0:7>.

[0048] The eight second main word line drive signal generating circuits 312 can each output the second main word line drive signal NWE1<0:7> in response to the decoded RA456<0:7> row address signal. Since the configuration of the decoded RA456<0:7> row address signal has eight cases (i.e., 000, 001, 010, 011, 100, 101, 110, and 111), the second main word line drive signal NWE1<0:7> can also have eight configurations. That is, a logic high level can be assigned to the first main word line drive signal NWE1<0:7> according to the decoded RA456<0:7> row address signal. <0> 、NWE1 <1> 、NWE1 <2> 、NWE1 <3> 、NWE1 <4> 、NWE1 <5> 、NWE1 <6> and NWE1 <7> The second main word line driving signal NWE1<0:7> of a logic high level may have a voltage level of a high voltage VPP and may be provided to a local main word line driving signal generating circuit 330 connected to each of the plurality of memory blocks BLK1, BLK2, . . . , and BLKi.

[0049] like Fig.10 As shown, the main word line drive signal generating circuit 310 may include eight first main word line drive signal generating circuits 311 and eight second main word line drive signal generating circuits 312, that is, a total of sixteen (16) first main word line drive signal generating circuits 311 and second main word line drive signal generating circuits 312. The main word line drive signal generating circuit 310 may be disposed in the peripheral circuit structure PCS, and the first main word line drive signal NWE0<0:7> and the second main word line drive signal NWE1<0:7> outputted from the main word line drive signal generating circuit 310 may be commonly connected to a plurality of memory blocks BLK1, BLK2, ..., and BLKi.

[0050] Figure 3The sub-word line drive signal generating circuit 320 may generate the first to third sub-word line drive signals MPXI<0:3>, PXID<0:3>, and PXIB<0:3> based on the signals from the least significant bit (LSB) group among the row address RA<0:9> signals. The signals from the LSB group among the row address RA<0:9> signals may be set to the RA<0:3> row address. The RA<0:3> row address may include the RA<0:1> row address corresponding to the lower significant bit group (hereinafter referred to as the "RA01" row address) and the RA<2:3> row address corresponding to the higher significant bit group (hereinafter referred to as the "RA23" row address). The sub-word line drive signal generating circuit 320 may include a first sub-word line drive signal generating circuit 321 for generating a first sub-word line drive signal MPXI<0:3> by decoding the RA01 row address, a second sub-word line drive signal generating circuit 323 for generating a second sub-word line drive signal PXID<0:3> by decoding the RA23 row address, and a third sub-word line drive signal generating circuit 325 for generating a third sub-word line drive signal PXIB<0:3> by decoding the RA23 row address.

[0051] Although an example is described below in which the sub-word line drive signal generating circuit 320 according to the present embodiment divides the LSB signal RA<0:3> from among the line address RA<0:9> signals into two groups (e.g., RA23 and RA01) and generates four of each of the sub-word line drive signals MPXI<0:4>, PXID<0:3>, and PXIB<0:3> based on the LSB signals of the two groups RA23 and RA01, the embodiment is not limited thereto, and the sub-word line drive signal generating circuit 320 may generate an even-numbered sub-word line drive signal PXID<0:3>. <0> 、PXID <2> 、PXIB <0> and PXIB <2> Two of each of the odd sub-word line drive signals PXID <1> 、PXID <3> 、PXIB <1> and PXIB <3> According to other embodiments, the sub word line drive signal generating circuit 320 may change the decoding for generating the plurality of sub word line drive signals MPXIi, PXIDj and PXIBk (i, k and k are natural numbers) based on the number of bits (e.g., 3, 4 or 5) of the LSB group signal from among the row address signals according to the configuration of each of the plurality of memory blocks BLK1, BLK2, ..., and BLKi (i.e., the number of word lines; for example, 2048, 4096, etc.).

[0052] Figure 5AThe first sub-word line drive signal generating circuit 321 may include first to fourth transistors 501 to 504 connected in series between a high voltage VPP line and a ground voltage VSS line, and may include a first inverter 506 and a second inverter 507 connected in series to a connection node 505 of the first transistor 501 and the second transistor 502, respectively. The first transistor 501 may be configured as a PMOS transistor having a precharge signal PCGB connected to its gate, and the second transistor 502 may be configured as an NMOS transistor having a precharge signal PCGB connected to its gate. The third transistor 503 may be configured as an NMOS transistor having a decoded RA01<0:3> row address signal connected to its gate, and the fourth transistor 504 may be configured as an NMOS transistor having a block select signal BLK_SELECT connected to its gate. The second inverter 507 may output the first sub-word line drive signal MPXI<0:3>.

[0053] The four first sub-word line drive signal generating circuits 321 may each output the first sub-word line drive signal MPXI<0:3> in response to the decoded RA01<0:3> row address signal. Since the configuration of the decoded RA01<0:3> row address signal has four cases (i.e., 00, 01, 10, and 11), the activated first sub-word line drive signal MPXI<0:3> may also have four configurations. That is, according to the decoded RA01<0:3> row address signal, a logic low level may be assigned to the first sub-word line drive signal MPXI<0:3>. <0> 、MPIX <1> 、MPIX <2> and MPIX <3> The first sub word line driving signal MPXI<0:3> of a logic low level may have a voltage level of a ground voltage VSS and may be provided to a first local sub word line driving signal generating circuit 340 and a second local sub word line driving signal generating circuit 350 connected to each of a plurality of memory blocks BLK1, BLK2, . . . , and BLKi.

[0054] Figure 5B The second sub-word line drive signal generating circuit 323 may include first to fourth transistors 511 to 514 connected in series between the high voltage VPP line and the ground voltage VSS line, and may include first inverters 516 and second inverters 517 connected in series to a connection node 515 of the first transistor 511 and the second transistor 512, respectively. The second sub-word line drive signal generating circuit 323 has Figure 5A The first sub word line driving signal generating circuit 321 has the same configuration, except that the decoded RA23<0:3> row address signal is connected to the gate of the third transistor 513 and the second inverter 517 outputs the second sub word line driving signal PXID<0:3>.

[0055] The four second sub-word line drive signal generating circuits 323 can each output the second sub-word line drive signal PXID<0:3> in response to the decoded RA23<0:3> row address signal. Because the configuration of the decoded RA23<0:3> row address signal has four cases (i.e., 00, 01, 10, and 11), the activated second sub-word line drive signal PXID<0:3> can also have four configurations. That is, a logic low level can be assigned to the second sub-word line drive signal PXID<0:3> according to the decoded RA23<0:3> row address signal. <0> 、PXID <1> 、PXID <2> and PXID <3> The second sub word line driving signal PXID<0:3> of a logic low level may have a voltage level of a ground voltage VSS and may be provided to the first local sub word line driving signal generating circuits 340 respectively connected to the plurality of memory blocks BLK1, BLK2, . . . , and BLKi.

[0056] Figure 5C The third sub-word line drive signal generating circuit 325 may include first to fourth transistors 521 to 524 connected in series between the high voltage VPP line and the ground voltage VSS line, and may include an inverter 526 connected to a connection node 525 of the first transistor 521 and the second transistor 522. The third sub-word line drive signal generating circuit 325 has a Figure 5B The second sub word line drive signal generating circuit 323 has the same configuration, except that an inverter 526 connected to a connection node 525 of the first transistor 521 and the second transistor 522 outputs a third sub word line drive signal PXIB<0:3>. The second sub word line drive signal PXID<0:3> and the third sub word line drive signal PXIB<0:3> have opposite logic levels to each other.

[0057] The four third sub-word line drive signal generating circuits 325 can each output the third sub-word line drive signal PXIB<0:3> in response to the decoded RA23<0:3> row address signal. Because the configuration of the decoded RA23<0:3> row address signal has four cases (i.e., 00, 01, 10, and 11), the activated third sub-word line drive signal PXIB<0:3> can also have four configurations. That is, a logic high level can be assigned to the third sub-word line drive signal PXIB<0:3> according to the decoded RA23<0:3> row address signal. <0> 、PXIB <1> 、PXIB <2> and PXIB <3> The third sub word line driving signal PXIB<0:3> of a logic high level may have a voltage level of a high voltage VPP and may be provided to the second local sub word line driving signal generating circuit 350 respectively connected to the plurality of memory blocks BLK1, BLK2, . . . , and BLKi.

[0058] like Fig.10 As shown, the sub-word line drive signal generating circuit 320 may include four first sub-word line drive signal generating circuits 321, four second sub-word line drive signal generating circuits 323, and four third sub-word line drive signal generating circuits 325, that is, a total of 12 first to third sub-word line drive signal generating circuits 321, 323, and 325. The sub-word line drive signal generating circuit 320 may be disposed in the peripheral circuit structure PCS, and the first sub-word line drive signal MPXI<0:3>, the second sub-word line drive signal PXID<0:3>, and the third sub-word line drive signal PXIB<0:3> outputted from the sub-word line drive signal generating circuit 320 may be commonly connected to a plurality of memory blocks BLK1, BLK2, . . . , and BLKi.

[0059] Figure 3 The local main word line drive signal generating circuit 330 can be connected to each of the multiple memory blocks BLK1, BLK2, ..., and BLKi, and generate a local main word line drive signal LNWEIB<0:63> based on the first main word line drive signal NWE0<0:7> and the second main word line drive signal NWE1<0:7> provided by the main word line drive signal generating circuit 310.

[0060] Figure 6 The local main word line drive signal generating circuit 330 may constitute a NAND logic circuit including first to fourth transistors 601 to 604 connected between the high voltage VPP line and the negative voltage VBB line. The first transistor 601 and the second transistor 602 may be configured as PMOS transistors connected in parallel between the high voltage VPP line and the connection node 605 of the first to third transistors 601 to 603, the first main word line drive signal NWE0<0:7> may be connected to the gate of the first transistor 601, and the second main word line drive signal NWE1<0:7> may be connected to the gate of the second transistor 602. The third transistor 603 and the fourth transistor 604 may be configured as NMOS transistors connected in series between the connection node 605 and the negative voltage VBB line, the first main word line drive signal NWE0<0:7> may be connected to the gate of the third transistor 603, and the second main word line drive signal NWE1<0:7> may be connected to the gate of the fourth transistor 604. The local main word line driving signal LNWEIB<0:63> may be output from a connection node 605 of the first to third transistors 601 to 603 .

[0061] like Fig.10As shown, 63 local main word line drive signal generation circuits 330 each outputting a local main word line drive signal LNWEIB<0:63> in response to the first main word line drive signal NWE0<0:7> and the second main word line drive signal NWE1<0:7> may be arranged in the portion of the peripheral circuit structure PCS corresponding to the plurality of memory blocks BLK1, BLK2, ..., and BLKi, respectively. The local main word line drive signal generation circuit 330 may activate any one of the 64 local main word line drive signals LNWEIB<0:63> to a logic low level in response to the logic high level of the activated first main word line drive signal NWE0<0:7> and the activated second main word line drive signal NWE1<0:7>. The local main word line drive signal LNWEIB<0:63> of the logic low level may have a voltage level of the negative voltage VBB and may be provided to the sub-word line drive circuit 360 connected to each of the plurality of memory blocks BLK1, BLK2, ..., and BLKi.

[0062] Figure 3 The first local sub-word line drive signal generating circuit 340 can be connected to each of a plurality of storage blocks BLK1, BLK2, ..., and BLKi, and generates a first local sub-word line drive signal LPXID<0:15> based on the first sub-word line drive signal MPXI<0:3> provided by the first sub-word line drive signal generating circuit 321 and the second sub-word line drive signal PXID<0:3> provided by the second sub-word line drive signal generating circuit 323.

[0063] Figure 7 The first local sub-word line drive signal generating circuit 340 may constitute a NOR logic circuit including first to fourth transistors 701 to 704 connected between the high voltage VPP line and the negative voltage VBB line. The first transistor 701 and the second transistor 702 may be configured as PMOS transistors connected in parallel between the high voltage VPP line and the connection node 705 of the second to fourth transistors 702 to 704, the first sub-word line drive signal MPXI<0:3> may be connected to the gate of the first transistor 701, and the second sub-word line drive signal PXID<0:3> may be connected to the gate of the second transistor 702. The third transistor 703 and the fourth transistor 704 may be configured as NMOS transistors connected in parallel between the connection node 705 of the second to fourth transistors 702 to 704 and the negative voltage VBB line, the second sub-word line drive signal PXID<0:3> may be connected to the gate of the third transistor 703, and the first sub-word line drive signal MPXI<0:3> may be connected to the gate of the fourth transistor 704. The first local sub word line driving signal LPXID<0:15> may be output from a connection node 705 of the second to fourth transistors 702 to 704 .

[0064] like Fig.10 As shown, sixteen (16) first local sub-word line drive signal generation circuits 340 each outputting a first local sub-word line drive signal LPXID<0:15> in response to a first sub-word line drive signal MPXI<0:3> and a second sub-word line drive signal PXID<0:3> may be arranged in portions of the peripheral circuit structure PCS corresponding to a plurality of memory blocks BLK1, BLK2, ..., and BLKi, respectively. The first local sub-word line drive signal generation circuit 340 may activate any one of the 16 first local sub-word line drive signals LPXID<0:15> to a logic high level in response to a logic low level of the activated first sub-word line drive signal MPXI<0:3> and the activated second sub-word line drive signal PXID<0:3>. The logic high level first local sub-word line drive signal LPXID<0:15> may have a voltage level of a high voltage VPP and may be provided to a sub-word line drive circuit 360 connected to each of the plurality of memory blocks BLK1, BLK2, ..., and BLKi.

[0065] Figure 3 The second local sub-word line drive signal generating circuit 350 can be connected to each of the multiple storage blocks BLK1, BLK2, ..., and BLKi, and generate a second local sub-word line drive signal LCXIB<0:15> based on the first sub-word line drive signal MPXI<0:3> provided by the first sub-word line drive signal generating circuit 321 and the third sub-word line drive signal PXIB<0:3> provided by the third sub-word line drive signal generating circuit 325.

[0066] Figure 8The second local sub-word line drive signal generating circuit 350 may include first to sixth transistors 801 to 806 connected between a high voltage VPP line and a negative voltage VBB line, wherein the first transistor 801 and the second transistor 802 may constitute an inverter circuit, and the third to sixth transistors 803 to 806 may constitute a NAND logic circuit. The first transistor 801 may be configured as a PMOS transistor connected between the high voltage VPP line and a connection node 807 of the first transistor 801 and the second transistor 802, and the first sub-word line drive signal MPXI<0:3> is applied to the gate of the first transistor 801. The second transistor 802 may be configured as an NMOS transistor connected between a connection node 807 of the first transistor 801 and the second transistor 802 and the negative voltage VBB line, and the first sub-word line drive signal MPXI<0:3> is applied to the gate of the second transistor 802. The third transistor 803 and the fourth transistor 804 may be configured as PMOS transistors connected in parallel between the high voltage VPP line and a connection node 808 of the third to fifth transistors 803 to 805, wherein the third sub word line drive signal PXIB<0:3> may be connected to the gate of the third transistor 803, and a connection node 807 of the first transistor 801 and the second transistor 802 may be connected to the gate of the fourth transistor 804. The fifth transistor 805 and the sixth transistor 806 may be configured as NMOS transistors connected in parallel between a connection node 808 of the third to fifth transistors 803 to 805 and a negative voltage VBB line, wherein the third sub word line drive signal PXIB<0:3> may be connected to the gate of the fifth transistor 805, and a connection node 807 of the first transistor 801 and the second transistor 802 may be connected to the gate of the sixth transistor 806. The second local sub word line drive signal LXIB<0:15> may be output from a connection node 808 of the third to fifth transistors 803 to 805.

[0067] like Fig.10As shown, sixteen (16) second local sub-word line drive signal generation circuits 350 each outputting a second local sub-word line drive signal LXIB<0:15> in response to the first sub-word line drive signal MPXI<0:3> and the third sub-word line drive signal PXBD<0:3> may be arranged in portions of the peripheral circuit structure PCS corresponding to the plurality of memory blocks BLK1, BLK2, . . . , and BLKi, respectively. The second local sub-word line drive signal generation circuit 350 may activate any one of the 16 second sub-word line drive signals LXIB<0:15> to a logic low level in response to the logic low level of the activated first sub-word line drive signal MPXI<0:3> and the logic high level of the activated third sub-word line drive signal PXI<0:3>. The second local sub word line driving signal LXIB<0:15> of a logic low level may have a voltage level of a negative voltage VBB and may be provided to the sub word line driving circuit 360 connected to each of the plurality of memory blocks BLK1 , BLK2 , . . . , and BLKi.

[0068] Figure 3 The sub-word line driving circuit 360 is connected to each of the multiple storage blocks BLK1, BLK2, ..., and BLKi, and selects a word line from the word lines WL<0:1023> based on the local main word line driving signal LNWEIB<0:63> provided by the local main word line driving signal generating circuit 330, the first local sub-word line driving signal LPXID<0:15> provided by the first local sub-word line driving signal generating circuit 340, and the second local sub-word line driving signal LXIB<0:15> provided by the second local sub-word line driving signal generating circuit 350, and drives the selected word line by using the high voltage VPP.

[0069] Fig. 9The sub-word line driving circuit 360 may include first to third transistors 901 to 903. The first transistor 901 may be configured as a PMOS transistor, wherein a line of a first local sub-word line driving signal LPXID<0:15> is connected to a source of the first transistor 901, a connection node 904 of the first to third transistors 901 to 903 is connected to a drain of the first transistor 901, and a local main word line driving signal LNWEIB<0:63> is applied to a gate of the first transistor 901. The second transistor 902 may be configured as an NMOS transistor, wherein a negative voltage VBB line is connected to a source of the second transistor 902, a connection node 904 of the first to third transistors 901 to 903 is connected to a drain of the second transistor 902, and a local main word line driving signal LNWEIB<0:63> is applied to a gate of the second transistor 902. The third transistor 903 may be configured as an NMOS transistor, in which a negative voltage VBB line is connected to a source of the third transistor 903, a connection node 904 of the first to third transistors 901 to 903 is connected to a drain of the third transistor 903, and a second local sub word line drive signal LCXIB<0:15> is applied to a gate of the third transistor 903. The connection node 904 of the first to third transistors 901 to 903 may be connected to a word line WL<0:1023> of each of the plurality of memory blocks BLK1, BLK2, . . . , and BLKi.

[0070] like Fig.10 As shown, the sub-word line driving circuit 360 may be provided in a portion of the peripheral circuit structure PCS corresponding to the plurality of memory blocks BLK1, BLK2, ..., and BLKi, respectively. 1024 sub-word line driving circuits 360 may be arranged to be connected to the word lines WL<0:1023>, respectively, in response to the local main word line driving signal LNWEIB<0:63>, the first local sub-word line driving signal LPXID<0:15>, and the second local sub-word line driving signal LCXIB<0:15>. The sub-word line driving circuit 360 may select any one word line from the 1024 word lines WL<0:1023> in response to the logic low level of the activated local main word line driving signal LNWEIB<0:63>, the logic high level of the activated first local sub-word line driving signal LPXID<0:15>, and the logic low level of the activated second local sub-word line driving signal LCXIB<0:15>, and activate the selected word line to a logic high level. A word line selected from among the word lines WL<0:1023> may be activated to the level of the high voltage VPP of the first local sub word line driving signal LPXID<0:15> of a logic high level.

[0071] refer to Fig.10, a region R1 is shown, which is a region of the peripheral circuit structure PCS corresponding to a portion of the first memory block BLK1 remaining after the local main word line drive signal generating circuit 330, the first local sub word line drive signal generating circuit 340, the second local sub word line drive signal generating circuit 350, and the sub word line drive circuit 360 are arranged. Power supply lines (e.g., VPP, VSS, and VBB) of the memory device 10 may be arranged in the region R1 to stabilize the power of the memory device 10. Therefore, the operation performance of the memory device 10 may be improved.

[0072] Figures 11 to 17 is a diagram for describing a row decoder according to an embodiment. Fig.11 Is used to describe Figure 1 130b is a block diagram of a row decoder 130b. Fig. 12A and Fig. 12B Is used to describe Fig.11 1123 is a circuit diagram of a second sub-word line drive signal generating circuit 1123. Fig.13A and Fig. 13B Is used to describe Fig.11 1125 is a circuit diagram of a third sub-word line drive signal generating circuit 1125. Fig.14A and Fig. 14B Is used to describe Fig.11 1140 is a circuit diagram of a first local sub-word line driving signal generating circuit 1140. Fig.15A and Fig. 15B Is used to describe Fig.11 1150 is a circuit diagram of a second local sub-word line drive signal generating circuit 1150. Fig.16A and Fig. 16B Is used to describe Fig.11 A circuit diagram of a sub-word line driving circuit 1160. Fig.17 is used to describe Fig.11 FIG. 1 is a diagram of a row decoder architecture in which a row decoder 130 b is provided in the memory device 10 .

[0073] refer to Fig.11 ,and Figure 3Unlike the row decoder 130a, in the row decoder 130b, the second sub-word line drive signal generating circuit 1123 and the third sub-word line drive signal generating circuit 1125, the first local sub-word line drive signal generating circuit 1140, the second local sub-word line drive signal generating circuit 1150, and the sub-word line drive circuit 1160 in the sub-word line drive signal generating circuit 1120 are classified into first circuits (e.g., 1124, 1126, 1142, 1152 and 1162) associated with the even word line WL<0:1022:2> and second circuits (e.g., 1121, 1127, 1143, 1153 and 1163) associated with the odd word line WL<0:1023:2>. For ease of explanation, the first circuits 1123, 1126, 1142, 1152, and 1162 may be referred to as even circuits, and the second circuits 1121, 1127, 1143, 1153, and 1163 may be referred to as odd circuits. Figure 3 The same description is given as that about the row decoder 130b.

[0074] Fig.11 The second sub word line driving signal generating circuit 1123 may include an even circuit 1124 and an odd circuit 1121 configured to generate the second sub word line driving signal PXID<0:3> by decoding the RA23 row address.

[0075] Similar to Figure 5B The second sub-word line driving signal generating circuit 323, Fig. 12A The even circuit 1124 of the second sub-word line drive signal generating circuit 1123 includes first to fourth transistors 511 to 514, a first inverter 516 and a second inverter 517, and the decoded RA23 <0> and RA23 <2> The row address signal is connected to the gate of the third transistor 513. However, Figure 5B Different from the second sub-word line drive signal generating circuit 323, Fig. 12AIn the even circuit 1124 of the second sub-word line drive signal generating circuit 1123, the second inverter 517 outputs the second sub-word line drive signal PXID <0> and PXID <2> The two even circuits 1124 of the second sub-word line drive signal generating circuit 1123 may be provided to respectively respond to the decoded RA23 <0> and RA23 <2> The row address signal outputs the second sub-word line drive signal PXID <0> and PXID <2> The second sub-word line driving signal PXID <0> and PXID <2> According to the decoded RA23 <0> and RA23 <2> The logic high level of the row address signal is activated to a logic low level. The second sub word line driving signal PXID of the logic low level <0> and PXID <2> May have a voltage level of the ground voltage VSS and may be provided to the even circuits 1142 of the first local sub word line drive signal generating circuits 1140 respectively connected to the plurality of memory blocks BLK1 , BLK2 , . . . , and BLKi.

[0076] Similar to Figure 5B The second sub-word line driving signal generating circuit 323, Fig. 12B The odd circuit 1121 of the second sub-word line drive signal generating circuit 1123 includes first to fourth transistors 511 to 514, a first inverter 516 and a second inverter 517, and the decoded RA23 <1> and RA23 <3> The row address signal is connected to the gate of the third transistor 513. However, Figure 5B Different from the second sub-word line drive signal generating circuit 323, Fig. 12B In the odd circuit 1121 of the second sub-word line drive signal generating circuit 1123, the second inverter 517 outputs the second sub-word line drive signal PXID <1> and PXID <3> Two odd circuits 1121 of the second sub-word line drive signal generating circuit 1123 may be provided to respectively respond to the decoded RA23 <1> and RA23 <3> The row address signal outputs the second sub-word line drive signal PXID <1> and PXID <3> The second sub-word line driving signal PXID <1> and PXID <3> According to the decoded RA23 <1> and RA23 <3> The logic high level of the row address signal is activated to a logic low level. The second sub word line driving signal PXID of the logic low level <1> and PXID <3> May have a voltage level of the ground voltage VSS and may be provided to the odd circuits 1143 of the first local sub word line drive signal generating circuits 1140 respectively connected to the plurality of memory blocks BLK1 , BLK2 , . . . , and BLKi.

[0077] Fig.11The third sub word line driving signal generating circuit 1125 may include an even circuit 1126 and an odd circuit 1127 configured to generate the third sub word line driving signal PXIB<0:3> by decoding the RA23 row address.

[0078] Similar to Figure 5C The third sub-word line drive signal generating circuit 325, Fig.13A The even circuit 1126 of the third sub-word line drive signal generating circuit 1125 includes first to fourth transistors 521 to 524 and an inverter 526, and the decoded RA23 <0> and RA23 <2> The row address signal is connected to the gate of the third transistor 523. However, Figure 5C The third sub-word line drive signal generating circuit 325 is different from that of Fig.13A In the even circuit 1126 of the third sub-word line drive signal generating circuit 1125, the inverter 526 outputs the third sub-word line drive signal PXIB <0> and PXIB <2> Two even circuits 1126 of the third sub-word line drive signal generating circuit 1125 may be provided to respectively respond to the decoded RA23 <0> and RA23 <2> Row address signal output third sub-word line drive signal PXIB <0> and PXIB <2> The second sub-word line drive signal PXIB <0> and PXIB <2> According to the decoded RA23 <0> and RA23 <2> The logic high level of the row address signal is activated to a logic high level. The logic high level of the third sub-word line drive signal PXIB <0> and PXIB <2> May have a voltage level of the high voltage VPP and may be provided to the even circuits 1152 of the second local sub word line drive signal generating circuits 1150 respectively connected to the plurality of memory blocks BLK1 , BLK2 , . . . , and BLKi.

[0079] Similar to Figure 5C The second sub-word line drive signal generating circuit 1123, Fig. 13B The odd circuit 1127 of the third sub-word line drive signal generating circuit 1125 includes first to fourth transistors 521 to 524 and an inverter 526, and the decoded RA23 <1> and RA23 <3> The row address signal is connected to the gate of the third transistor 523. However, Figure 5C Different from the second sub-word line drive signal generating circuit 1123, Fig. 13BIn the odd circuit 1127 of the third sub-word line drive signal generating circuit 1125, the inverter 526 outputs the third sub-word line drive signal PXIB <1> and PXIB <3> The two odd circuits 1127 of the third sub-word line drive signal generating circuit 1125 may be provided to respectively respond to the decoded RA23 <1> and RA23 <3> Row address signal output third sub-word line drive signal PXIB <1> and PXIB <3> The second sub-word line drive signal PXIB <1> and PXIB <3> According to the decoded RA23 <1> and RA23 <3> The logic high level of the row address signal is activated to a logic high level. The logic high level of the third sub-word line drive signal PXIB <1> and PXIB <3> May have a voltage level of the high voltage VPP and may be provided to the odd circuits 1153 of the second local sub word line drive signal generating circuits 1150 respectively connected to the plurality of memory blocks BLK1 , BLK2 , . . . , and BLKi.

[0080] like Fig.17 As shown, the sub-word line drive signal generating circuit 1120 may include four first sub-word line drive signal generating circuits 321, four second sub-word line drive signal generating circuits 1123, and four third sub-word line drive signal generating circuits 1125, that is, a total of 12 first to third sub-word line drive signal generating circuits 321, 1123, and 1125. The four second sub-word line drive signal generating circuits 1123 may include two even circuits 1124 and two odd circuits 1121, and the four third sub-word line drive signal generating circuits 1125 may include two even circuits 1126 and two odd circuits 1127. The sub-word line drive signal generating circuit 1120 may be provided in the peripheral circuit structure PCS, and the first sub-word line drive signal MPXI<0:3>, the second sub-word line drive signal PXID<0:3>, and the third sub-word line drive signal PXIB<0:3> output from the sub-word line drive signal generating circuit 1120 may be commonly connected to a plurality of storage blocks BLK1, BLK2, ..., and BLKi.

[0081] Fig.11 The first local sub-word line drive signal generating circuit 1140 may include an even circuit 1142 and an odd circuit 1143 configured to generate a first local sub-word line drive signal LPXID<0:15> based on the first sub-word line drive signal MPXI<0:3> provided by the first sub-word line drive signal generating circuit 321 and the second sub-word line drive signal PXID<0:3> provided by the second sub-word line drive signal generating circuit 1123.

[0082] Similar to Figure 7 The first local sub-word line driving signal generating circuit 340, Fig.14AThe even circuit 1142 of the first local sub-word line drive signal generating circuit 1140 includes first to fourth transistors 701 to 704, and the second sub-word line drive signal PXID <0> and PXID <2> is connected to the gates of the second transistor 702 and the third transistor 703. However, Figure 7 Different from the first local sub-word line drive signal generating circuit 340, Fig.14A In the even circuit 1142 of the first local sub word line drive signal generating circuit 1140, the first local sub word line drive signal LPXID<0:14:2> is output from the connection node 705 of the second to fourth transistors 702 to 704. Eight even circuits 1142 of the first local sub word line drive signal generating circuit 1140 may be provided to respond to the first sub word line drive signal MPXI<0:3> and the second sub word line drive signal PXID <0> and PXID <2> The first local sub-word line drive signal LPXID is output respectively <0> LPXID <2> LPXID <4> LPXID <6> LPXID <8> LPXID <10> LPXID <12> and LPXID <14> The even circuit 1142 of the first local sub word line driving signal generating circuit 1140 may respond to the activated first sub word line driving signal MPXI<0:3> and the activated second sub word line driving signal PXID. <0> and PXID <2> The logic low level of the first local sub word line driving signal LPXID<0:14:2> activates any one of the eight first local sub word line driving signals LPXID<0:14:2> to a logic high level. The logic high level first local sub word line driving signal LPXID<0:14:2> may have a voltage level of the high voltage VPP and may be provided to the even circuit 1162 of the sub word line driving circuit 1160 connected to each of the plurality of memory blocks BLK1, BLK2, . . . , and BLKi.

[0083] Similar to Figure 7 The first local sub-word line driving signal generating circuit 340, Fig. 14B The odd circuit 1143 of the first local sub-word line drive signal generating circuit 1140 includes the first to fourth transistors 701 to 704, and the second sub-word line drive signal PXID <1> and PXID <3> is connected to the gates of the second transistor 702 and the third transistor 703. However, Figure 7 Different from the first local sub-word line drive signal generating circuit 340, Fig. 14BIn the odd circuits 1143 of the first local sub word line drive signal generating circuit 1140, the first local sub word line drive signal LPXID<1:15:2> is output from the connection node 705 of the second to fourth transistors 702 to 704. Eight odd circuits 1143 of the first local sub word line drive signal generating circuit 1140 may be provided to respond to the first sub word line drive signal MPXI<0:3> and the second sub word line drive signal PXID <1> and PXID <3> The first local sub-word line drive signal LPXID is output respectively <1> LPXID <3> LPXID <5> LPXID <7> LPXID <9> LPXID <11> LPXID <13> and LPXID <15> The odd circuit 1143 of the first local sub word line driving signal generating circuit 1140 may respond to the activated first sub word line driving signal MPXI<0:3> and the activated second sub word line driving signal PXID. <1> and PXID <2> The logic low level of the first local sub word line driving signal LPXID<1:15:2> activates any one of the eight first local sub word line driving signals LPXID<1:15:2> to a logic high level. The logic high level first local sub word line driving signal LPXID<1:15:2> may have a voltage level of the high voltage VPP and may be provided to the odd circuit 1163 of the sub word line driving circuit 1160 connected to each of the plurality of memory blocks BLK1, BLK2, . . . , and BLKi.

[0084] like Fig.17 As shown, the first local sub-word line drive signal generating circuit 1140 may be provided in the peripheral circuit structure PCS corresponding to the plurality of memory blocks BLK1, BLK2, ..., and BLKi. The first local sub-word line drive signal generating circuit 1140 may include a circuit for responding to the first sub-word line drive signal MPXI<0:3> and the second sub-word line drive signal PXID <0> and PXID <2> Eight even circuits 1142 respectively output the first local sub-word line drive signals LPXID<0:14:2> and are used to respond to the first sub-word line drive signals MPXI<0:3> and the second sub-word line drive signals PXID <1> and PXID <3> Eight odd circuits 1143 respectively output the first local sub word line driving signals LPXID<1:15:2>.

[0085] Fig.11 The second local sub-word line drive signal generating circuit 1150 may include an even circuit 1152 and an odd circuit 1153 configured to generate a second local sub-word line drive signal LCXIB<0:15> based on the first sub-word line drive signal MPXI<0:3> provided by the first sub-word line drive signal generating circuit 321 and the third sub-word line drive signal PXIB<0:3> provided by the third sub-word line drive signal generating circuit 1125.

[0086] Similar to Figure 8 The second local sub-word line driving signal generating circuit 350, Fig.15A The even circuit 1152 of the second local sub-word line drive signal generating circuit 1150 includes the first to sixth transistors 801 to 806, and the third sub-word line drive signal PXIB <0> and PXIB <2> is connected to the gates of the third transistor 803 and the fifth transistor 805. However, Figure 8 Different from the second local sub-word line drive signal generating circuit 350, Fig.15A In the even circuit 1152 of the second local sub word line drive signal generating circuit 1150, the second local sub word line drive signal LXIB<0:14:2> is output from the connection node 808 of the third to fifth transistors 803 to 805. Eight even circuits 1152 of the second local sub word line drive signal generating circuit 1150 may be provided to respond to the first sub word line drive signal MPXI<0:3> and the third sub word line drive signal PXIB<0:14:2>. <0> and PXIB <2> The second local sub-word line drive signal LPXIB is output respectively <0> ,LPXIB <2> ,LPXIB <4> ,LPXIB <6> ,LPXIB <8> ,LPXIB <10> ,LPXIB <12> and LPXIB <14> The even circuit 1152 of the second local sub word line driving signal generating circuit 1150 may respond to the logic low level of the activated first sub word line driving signal MPXI<0:3> and the activated third sub word line driving signal PXIB. <0> and PXIB <2> The logic high level of the second local sub-word line driving signal LCXIB<0:14:2> may activate any one of the eight first local sub-word line driving signals LCXIB<0:14:2> to a logic low level. The second local sub-word line driving signal LCXIB<0:14:2> of the logic low level may have a voltage level of the negative voltage VBB and may be provided to the sub-word line driving circuit 360 connected to each of the plurality of memory blocks BLK1, BLK2, . . . , and BLKi.

[0087] Similar to Figure 8 The second local sub-word line driving signal generating circuit 350, Fig. 15B The odd circuit 1153 of the second local sub-word line driving signal generating circuit 1150 includes the first to sixth transistors 801 to 806, and the third sub-word line driving signal PXIB <1> and PXIB <3> is connected to the gates of the third transistor 803 and the fifth transistor 805. However, Figure 8 Different from the second local sub-word line drive signal generating circuit 350, Fig. 15BIn the odd circuits 1153 of the second local sub word line drive signal generating circuit 1150, the second local sub word line drive signal LXIB<1:15:2> is output from the connection node 808 of the third to fifth transistors 803 to 805. Eight odd circuits 1153 of the second local sub word line drive signal generating circuit 1150 may be provided to respond to the first sub word line drive signal MPXI<0:3> and the third sub word line drive signal PXIB<1:15:2>. <1> and PXIB <3> The second local sub-word line drive signal LPXIB is output respectively <1> ,LPXIB <3> ,LPXIB <5> ,LPXIB <7> ,LPXIB <9> ,LPXIB <11> ,LPXIB <13> and LPXIB <15> The odd circuit 1153 of the second local sub word line driving signal generating circuit 1150 may respond to the logic low level of the activated first sub word line driving signal MPXI<0:3> and the activated third sub word line driving signal PXIB <1> and PXIB <2> The logic high level of the second local sub-word line driving signal LCXIB<1:15:2> may activate any one of the eight first local sub-word line driving signals LCXIB<1:15:2> to a logic low level. The second local sub-word line driving signal LCXIB<1:15:2> of the logic low level may have a voltage level of the negative voltage VBB and may be provided to the sub-word line driving circuit 360 connected to each of the plurality of memory blocks BLK1, BLK2, . . . , and BLKi.

[0088] like Fig.17 As shown, the second local sub-word line drive signal generating circuit 1150 may be provided in the peripheral circuit structure PCS corresponding to the plurality of memory blocks BLK1, BLK2, ..., and BLKi. The second local sub-word line drive signal generating circuit 1150 may include a circuit for responding to the first sub-word line drive signal MPXI<0:3> and the third sub-word line drive signal PXIB <0> and PXIB <2> Eight even circuits 1152 output the second local sub-word line drive signals LPXID<0:14:2> respectively, and are used to respond to the first sub-word line drive signal MPXI<0:3> and the third sub-word line drive signal PXIB <1> and PXIB <3> Eight odd circuits 1153 respectively output first local sub-word line driving signals LCXIB<1:15:2>.

[0089] Fig.11The sub-word line driving circuit 1160 may include an even circuit 1162 and an odd circuit 1163 configured to select a word line from the word lines WL<0:1023> based on a local main word line driving signal LNWEIB<0:63> provided by the local main word line driving signal generating circuit 330, a first local sub-word line driving signal LPXID<0:15> provided by the first local sub-word line driving signal generating circuit 1140, and a second local sub-word line driving signal LXIB<0:15> provided by the second local sub-word line driving signal generating circuit 1150, and drive the selected word line by using a high voltage VPP.

[0090] Similar to Fig. 9 The sub-word line driving circuit 360, Fig.16A The even circuit 1162 of the sub-word line driving circuit 1160 includes first to third transistors 901 to 903, the line of the first local sub-word line driving signal LPXID<0:14:2> is connected to the source of the first transistor 901, and the line of the second local sub-word line driving signal LPXIB<0:14:2> is connected to the gate of the third transistor 903. However, Fig. 9 The sub-word line driving circuit 360 is different from Fig.16A In the even circuit 1162 of the sub word line driving circuit 1160, the even word line WL<0:1022:2> is connected to the connection node 904 of the first to third transistors 901 to 903. The 512 even circuits 1162 of the sub word line driving circuit 1160 may be provided to be connected to the even word line WL<0:1022:2> in response to the local main word line driving signal LNWEIB<0:63>, the first local sub word line driving signal LPXID<0:14:2>, and the second local sub word line driving signal LCXIB<0:14:2>, respectively. <0> , WL <2> , ..., and WL <1022> The even circuit 1162 of the sub-word line driving circuit 1160 may select any one word line from among the 512 word lines WL<0:1022:2> in response to the logic low level of the activated local main word line driving signal LNWEIB<0:63>, the logic high level of the activated first local sub-word line driving signal LPXID<0:14>, and the logic low level of the activated second local sub-word line driving signal LCXIB<0:14>, and activate the selected word line to a logic high level. The word line selected from among the word lines WL<0:1022:2> may be activated to the level of the high voltage VPP of the first local sub-word line driving signal LPXID<0:14:2> of the logic high level.

[0091] Similar to Fig. 9 The sub-word line driving circuit 360, Fig. 16BThe odd circuit 1163 of the sub-word line driving circuit 1160 includes first to third transistors 901 to 903, the line of the first local sub-word line driving signal LPXID<1:15:2> is connected to the source of the first transistor 901, and the line of the second local sub-word line driving signal LPXIB<1:15:2> is connected to the gate of the third transistor 903. However, Fig. 9 The sub-word line driving circuit 360 is different from Fig. 16B In the odd circuits 1163 of the sub-word line driving circuit 1160, the odd word lines WL<1:1023:2> are connected to the connection node 904 of the first to third transistors 901 to 903. The 512 odd circuits 1163 of the sub-word line driving circuit 1160 may be provided to be connected to the odd word lines WL<1:1023:2> in response to the local main word line driving signal LNWEIB<0:63>, the first local sub-word line driving signal LPXID<1:15:2>, and the second local sub-word line driving signal LCXIB<1:15:2>, respectively. <1> , WL <3> , ..., and WL <1023> The odd circuit 1163 of the sub word line driving circuit 1160 may select any one word line from among the 512 word lines WL<0:1023:2> in response to the logic low level of the activated local main word line driving signal LNWEIB<0:63>, the logic high level of the activated first local sub word line driving signal LPXID<1:15:2>, and the logic low level of the activated second local sub word line driving signal LXIIB<1:15:2>, and activate the selected word line to a logic high level. The word line selected from among the word lines WL<0:1023:2> may be activated to the level of the high voltage VPP of the first local sub word line driving signal LPXID<1:15:2> of the logic high level.

[0092] like Fig.17As shown, the sub word line driving circuit 1160 may be provided at portions of the peripheral circuit structure PCS respectively corresponding to the plurality of memory blocks BLK1 , BLK2 , . . . , and BLKi. The sub-word line driving circuit 1160 may include 512 even circuits 1162 for selecting any one even word line from 512 even word lines WL<1:1022:2> based on the local main word line driving signal LNWEIB<0:63>, the first local sub-word line driving signal LPXID<0:14:2>, and the second local sub-word line driving signal LCXIB<0:14:2>, and activating the selected word line to a logic high level, and 512 odd circuits 1163 for selecting any one odd word line from 512 odd word lines WL<1:1023:2> based on the local main word line driving signal LNWEIB<0:63>, the first local sub-word line driving signal LCXIB<1:15:2>, and the second local sub-word line driving signal LCXIB<1:15:2>, and activating the selected word line to a logic high level.

[0093] refer to Fig.17 , a region R2 is shown, which is a region of the peripheral circuit structure PCS corresponding to a portion of the first memory block BLK1 remaining after the local main word line drive signal generating circuit 330, the first local sub word line drive signal generating circuit 1140, the second local sub word line drive signal generating circuit 1150, and the sub word line drive circuit 1160 are arranged. Power lines (e.g., VPP, VSS, and VBB) of the memory device 10 may be arranged in the region R1 to stabilize the power of the memory device 10, thereby improving the operation performance of the memory device 10. In addition, in the region R2, the first local sub word line drive signal generating circuit 1140, the second local sub word line drive signal generating circuit 1150, and the sub word line drive circuit 1160 corresponding to the first memory block BLK1 are divided into even circuits and odd circuits, and thus the region R2 may be relatively larger than the region R1. The number of power lines arranged in the region R2 may be greater than the number of power lines of the region R1. Alternatively, the power lines arranged in region R2 may have a greater width than the power lines in region R1. Therefore, the memory device 10 may improve its operation performance by using more stable power.

[0094] Fig.18 is a diagram for describing the sense amplifier 120 according to the embodiment.

[0095] refer to Figure 1 and Fig.18 The sense amplifier 120 may include a bit line sense amplifier circuit SA and a precharge and equalization circuit EQ. The bit line sense amplifier circuit SA may include a P-type sense amplifier PSA including a PMOS transistor and an N-type sense amplifier NSA including an NMOS transistor.

[0096] The P-type sense amplifier PSA includes a first PMOS transistor P11 and a second PMOS transistor P12 connected in series between a bit line BL and a complementary bit line BLB. A first sense drive voltage line LA is connected to the sources of the first PMOS transistor P11 and the second PMOS transistor P12, a complementary bit line BLB is connected to the gate of the first PMOS transistor P11, and the bit line BL is connected to the gate of the second PMOS transistor P12. According to an embodiment, the sizes of the first PMOS transistor P11 and the second PMOS transistor P12 may be the same or different from each other. A first sense drive voltage is supplied through the first sense drive voltage line LA, wherein the first sense drive voltage of the bit line sense amplifier circuit SA may be an internal power supply voltage VINTA supplied for the operation of the memory cell array 200, and may be a voltage generated by the voltage generating circuit 110 inside the memory device 10. The P-type sense amplifier PSA connected to the first sense drive voltage line LA supplies a high-level voltage, which is amplified by the data sensing and amplification operation of the memory cell connected to the bit line BL.

[0097] The N-type sense amplifier NSA includes a first NMOS transistor N11 and a second NMOS transistor N12 connected in series between a bit line BL and a complementary bit line BLB. A second sense drive voltage line LAB is connected to the sources of the first NMOS transistor N11 and the second NMOS transistor N12, the complementary bit line BLB is connected to the gate of the first NMOS transistor N11, and the bit line BL is connected to the gate of the second NMOS transistor N12. According to an embodiment, the sizes of the first NMOS transistor N11 and the second NMOS transistor N12 may be the same or different from each other. A second sense drive voltage is supplied through the second sense drive voltage line LAB, wherein the second sense drive voltage of the bit line sense amplifier circuit SA may be the ground voltage VSS of the memory device 10. The N-type sense amplifier NSA connected to the second sense drive voltage line LAB supplies a low-level voltage, which is amplified by the data sensing and amplification operation of the memory cell connected to the bit line BL0.

[0098] The precharge and voltage equalization circuit EQ equalizes the bit line BL and the complementary bit line BLB to the level of the bit line precharge voltage VEQ in response to the voltage equalization signal PEQ. The precharge and voltage equalization circuit EQ includes a third NMOS transistor N13 connected between the bit line precharge voltage VEQ and the bit line BL, a fourth NMOS transistor N14 connected between the bit line precharge voltage VEQ and the complementary bit line BLB, and a fifth NMOS transistor N15 connected between the bit line BL and the complementary bit line BLB. According to some embodiments, the precharge and voltage equalization circuit EQ may include any one of the third NMOS transistor N13 and the fourth NMOS transistor N14, and may include a fifth NMOS transistor N15.

[0099] The gates of the third to fifth NMOS transistors N13 to N15 are connected to the voltage equalization signal PEQ. The voltage equalization signal PEQ may be provided from the control logic circuit based on a command provided to the memory device 10. During the precharge operation of the bit line sense amplifier circuit SA, the voltage equalization signal PEQ is applied at a logic high level, turns on the first to third NMOS transistors N13 to N15, and precharges the bit line BL and the complementary bit line BLB to the level of the bit line precharge voltage VEQ. During the read operation, the voltage equalization signal PEQ is applied at a logic low level, and turns off the first to third NMOS transistors N13 to N15.

[0100] Fig.19 is a diagram for describing a structure of a memory device according to an embodiment. Fig.19 It is along Fig.17 A cross-sectional view taken along line X1-X2.

[0101] refer to Figure 1 , Fig.11 , Fig.17 and Fig.19 , the memory device 10 may include a cell array structure CAS and a peripheral circuit structure PCS overlapping each other in a vertical direction (Z direction). The cell array structure CAS may include a memory cell array 200. The peripheral circuit structure PCS may include a peripheral circuit 100. Therefore, the memory device 10 may have a structure in which the memory cell array 200 is disposed above the peripheral circuit 100, that is, a cell on periphery (COP) structure.

[0102] The cell array structure CAS may include a plurality of memory blocks BLK1, BLK2, ..., and BLKi. The plurality of memory blocks BLK1, BLK2, ..., and BLKi may each include a plurality of memory cells including vertical channel transistors. In the cell array structure CAS, a plurality of bit lines BL may extend in a first horizontal direction (X direction), and a plurality of word lines WL may extend in a second horizontal direction (Y direction).

[0103] The peripheral circuit structure PCS may include a semiconductor substrate, and the peripheral circuit 100 may be formed by forming semiconductor devices such as transistors and patterns for distributing devices on the semiconductor substrate. After the peripheral circuit 100 is formed in the peripheral circuit structure PCS, a cell array structure CAS including a memory cell array 200 may be formed, and a pattern for electrically connecting word lines WL and bit lines BL of the memory cell array 200 to the peripheral circuit 100 formed in the peripheral circuit structure PCS may be formed.

[0104] refer to Fig.19 , the peripheral circuit structure PCS may include a lower substrate 1910, an interlayer insulating layer 1915, a plurality of circuit elements 1912a and 1912b formed on the lower substrate 1910, first metal layers 1914a and 1914b respectively connected to the plurality of circuit elements 1912a and 1912b, second metal layers 1916a and 1916b formed on the first metal layers 1914a and 1914b, and a metal pattern 1918 formed on the uppermost metal layer of the peripheral circuit structure PCS. According to an embodiment, the first metal layers 1914a and 1914b may include tungsten having a relatively high resistance, and the second metal layers 1916a and 1916b may include copper having a relatively low resistance.

[0105] Although only the first metal layers 1914a and 1914b and the second metal layers 1916a and 1916b are shown and described in this specification, the embodiment is not limited thereto, and one or more metal layers may be further formed on the second metal layers 1916a and 1916b. At least some of the one or more metal layers formed on the second metal layers 1916a and 1916b may include a material such as aluminum having a lower resistance than copper constituting the second metal layers 1916a and 1916b. An interlayer insulating layer 1915 is provided on the lower substrate 1910 to cover the plurality of circuit elements 1912a and 1912b, the first metal layers 1914a and 1914b, and the second metal layers 1916a and 1916b, and may include an insulating material such as silicon oxide or silicon nitride.

[0106] The plurality of circuit elements 1912a and 1912b may be connected to at least one circuit element among the circuit elements constituting the peripheral circuit 100. For ease of explanation, the first circuit element 1912a may be included in the reference circuit. Figure 3 and Fig.11 Any of the transistors in the row decoders 130a and 130b described above (eg, 401 to 404 of FIG. 4), and the second circuit element 1912b may be connected to the reference Fig.18 Any one of the transistors P11 and N11 of the bit line BL in the sense amplifier 120 is described.

[0107] The cell array structure CAS may include an upper substrate 1920, an inter-line insulating layer 1925, a conductive line 1930 located on the inter-line insulating layer 1925, a through-hole electrode 1922 located below the conductive line 1930, a cell structure CS located on the conductive line 1930, and a plurality of capacitor structures 1990 located on the cell structure CS. The cell array structure CAS may include a plurality of conductive lines 1930, wherein the inter-line insulating layer 1925 may be formed to surround the bottom surface and the side surface of each of the plurality of conductive lines 1930 and fill the space between the plurality of conductive lines 1930. The plurality of conductive lines 1930 may each extend in a first horizontal direction (X direction). The plurality of conductive lines 1930 may be spaced apart from each other in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction), and each extend in the first horizontal direction (X direction). The via electrode 1922 is formed to penetrate the upper substrate 1920 and extend to the metal pattern 1918 of the peripheral circuit structure PCS in the vertical direction (Z direction), and can electrically connect the conductive line 1930 to the second circuit element 1912b of the sense amplifier 120. The conductive line 1930 can be used as a bit line BL of the memory device 10.

[0108] A separation insulating layer 1935 may be formed on the conductive line 1930. The separation insulating layer 1935 may include a channel trench 1935T extending in a first horizontal direction (X direction), and a plurality of insulating patterns spaced apart from each other by the channel trench 1935T may be formed. A channel layer 1936 may be formed in the channel trench 1935T. The channel layer 1936 may extend along the side surface and the bottom surface of the channel trench 1935T and be electrically connected to the conductive line 1930. A gate dielectric layer 1940 may be formed on the channel layer 1936 in the channel trench 1935T. The gate dielectric layer 1940 may be disposed between the channel layer 1936 and the gate electrode 1950. The gate electrode 1950 may be formed on the gate dielectric layer 1940 in the channel trench 1935T. According to some embodiments, the gate electrode 1950 may include a first gate electrode 1950A and a second gate electrode 1950B facing each other in one channel trench 1935T. In this case, two transistor structures may be implemented per channel layer 1936. The first gate electrode 1950A may be used as a first word line of the memory cell array 200, and the second gate electrode 1950B may be used as a second word line of the memory cell array 200.

[0109] According to some embodiments, a blocking insulating layer 1962 and a gap-filling insulating layer 1964 may be formed between the first gate electrode 1950A and the second gate electrode 1950B. The first gate electrode 1950A and the second gate electrode 1950B may be separated from each other by the blocking insulating layer 1962 and the gap-filling insulating layer 1964. The gap-filling insulating layer 1964 may be formed on the blocking insulating layer 1962 to fill a region between the first gate electrode 1950A and the second gate electrode 1950B.

[0110] The unit structure CS may include a plurality of vertical channel transistor structures. A vertical channel transistor may refer to a structure in which the channel length of a channel layer 1936 extends in a vertical direction (Z direction) perpendicular to the top surface of the upper substrate 1920. A vertical channel transistor may include a channel layer 1936, a gate electrode 1950, and a gate dielectric layer 1940 disposed between the channel layer 1936 and the first gate electrode 1950A. The channel layer 1936 of the vertical channel transistor may include a first source / drain region and a second source / drain region arranged in a vertical direction (Z direction). For example, the lower portion of the channel layer 1936 may be used as a first source / drain region, and the upper portion of the channel layer 1936 may be used as a second source / drain region. A portion of the channel layer 1936 between the first source / drain region and the second source / drain region may be used as a channel region.

[0111] A contact layer 1970 may be formed on the channel layer 1936, and the contact layer 1970 may be connected to a top surface of the channel layer 1936. The contact layer 1970 may interconnect the channel layer 1936 and the capacitor structure 1990. A top surface of the channel layer 1936 adjacent to the first gate electrode 1950A may be connected to one contact layer 1970, and a top surface of the channel layer 1936 adjacent to the second gate electrode 1950B may be connected to another contact layer 1970.

[0112] The capacitor structure 1990 may be formed on the separation insulating layer 1935 and the contact layer 1970. The capacitor structure 1990 may be connected to the top surface of the contact layer 1970. The capacitor structure 1990 may be controlled to store data by the conductive line 1930 and the gate electrode 1950. The capacitor structure 1990 may include a lower electrode 1992, a capacitor dielectric layer 1994, and an upper electrode 1996. The capacitor structure 1990 may store charges in the capacitor dielectric layer 1994 by using a potential difference generated between the lower electrode 1992 and the upper electrode 1996.

[0113] One of the plurality of vertical channel transistor structures and one of the capacitor structures 1990 may constitute a memory cell MC ( Fig.18), and thus the cell array structure CAS may include a plurality of memory cells MC including a plurality of cell structures CS and a plurality of capacitor structures 1990.

[0114] Fig. 20 is a block diagram for describing a system 2000 of an electronic device including a memory device according to an embodiment.

[0115] refer to Fig. 20 , the system 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAMs 2500a and 2500b, flash memories 2600a and 2600b, I / O devices 2700a and 2700b, and an application processor (hereinafter referred to as "AP") 2800. The system 2000 may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a wearable device, a healthcare device, or an IoT device. Moreover, the system 2000 may be implemented as a server or a PC.

[0116] The camera 2100 may capture a still image or a video according to the control of the user, and may store the captured image / video data or send the captured image / video data to the display 2200. The audio processor 2300 may process the audio data or network content included in the flash memory 2600a and 2600b. The modem 2400 may send a modulated signal for wired / wireless data transmission / reception to a receiver, and the modulated signal may be demodulated by the receiver to restore the original signal. The I / O devices 2700a and 2700b may include devices that provide a digital input function and / or a digital output function, such as a Universal Serial Bus (USB), a storage device, a digital camera, a Secure Digital (SD) card, a Digital Versatile Disc (DVD), a network adapter, a touch screen, etc.

[0117] The AP 2800 may control the overall operation of the system 2000. The AP 2800 may include a controller block 2810, an accelerator block or an accelerator chip 2820, and an interface block 2830. The AP 2800 may control the display 2200 so that a portion of the content stored in the flash memories 2600a and 2600b is displayed on the display 2200. When a user input is received through the I / O devices 2700a and 2700b, the AP 2800 may perform a control operation corresponding to the user input. The AP 2800 may include an accelerator block that is a circuit dedicated to calculation of artificial intelligence (AI) data, or may include an accelerator chip 2820 separated from the AP 2800. The DRAM 2500b may be additionally provided in the accelerator or accelerator chip 2820. The accelerator block is a functional block specialized in performing specific functions of the AP 2800, and may include a GPU as a functional block specialized in processing graphic data, a neural processing unit (NPU) as a block specialized in AI calculation and reasoning, and a data processing unit (DPU) as a block specialized in data transmission.

[0118] The system 2000 may include a plurality of DRAMs 2500a and 2500b. The AP 2800 may establish a DRAM interface protocol and communicate with the DRAMs 2500a and 2500b to control the DRAMs 2500a and 2500b through commands that comply with the Joint Electron Device Engineering Council (JEDEC) standard and mode register (MRS) settings, or use company-specific functions such as low voltage / high speed / reliability and cyclic redundancy check (CRC) / error correction code (ECC) functions. For example, the AP 2800 may communicate with the DRAM 2500a (such as LPDDR4 and LPDDR5) through an interface that complies with the JEDEC standard, and the accelerator block or accelerator chip 2820 may set and use a new DRAM interface protocol to control the DRAM 2500b for the accelerator, which has a greater bandwidth than the DRAM 2500a.

[0119] although Fig. 20Only DRAM 2500a and 2500b are shown, but the embodiment is not limited thereto. As long as the bandwidth, response speed and voltage conditions of AP 2800 or accelerator chip 2820 are met, any memory such as PRAM, SRAM, MRAM, RRAM, FRAM or hybrid RAM can be used. Compared with I / O devices 2700a and 2700b or flash memory 2600a and 2600b, DRAM 2500a and 2500b have relatively small delay and bandwidth. When system 2000 is powered on and OS and application data are loaded thereon, DRAM 2500a and 2500b are initialized, and thus DRAM 2500a and 2500b can be used as a temporary storage device for OS and application data, or can be used as a running space for various software codes.

[0120] In DRAM 2500a and 2500b, four arithmetic operations (i.e., addition, subtraction, multiplication, and division), vector calculations, address calculations, or Fast Fourier Transform (FFT) calculations can be performed. Moreover, in DRAM 2500a and 2500b, functions for inferring operations can be performed. Here, artificial neural networks can be used to perform inferences in deep learning algorithms. The deep learning algorithm may include training operations for learning models through various data and reasoning operations for identifying data using trained models. According to an embodiment, the image captured by the user through the camera 2100 is signal processed and stored in the DRAM 2500b, and the accelerator block or accelerator chip 2820 can use the data stored in the DRAM 2500b and the function for inferring to perform AI data calculations for identifying data.

[0121] The system 2000 may include a plurality of storage devices or flash memories 2600a and 2600b having a larger capacity than the DRAM 2500a and 2500b. The accelerator block or accelerator chip 2820 may use the flash memories 2600a and 2600b to perform training operations and AI data calculations. According to an embodiment, the flash memories 2600a and 2600b may include a storage controller 2610 and a flash memory device 2620, and by using an arithmetic unit included in the storage controller 2610, the training operations and inference AI data calculations performed by the AP 2800 and / or the accelerator chip 2820 may be performed more efficiently. The flash memories 2600a and 2600b may store images captured by the camera 2100 or data transmitted over a data network. For example, the flash memories 2600a and 2600b may store augmented reality / virtual reality content, high definition (HD) content, or ultra high definition (UHD) content.

[0122] In the system 2000, DRAM 2500a and 2500b may include the above reference Figures 1 to 19 The memory device described herein may include a peripheral circuit structure formed on a semiconductor substrate and a cell array structure located on the peripheral circuit structure and vertically overlapping the peripheral circuit structure. The cell array structure may include a plurality of memory blocks in a memory cell area, in which a plurality of vertical channel transistor structures and a plurality of capacitor structures respectively connected to the vertical channel transistor structures are formed. The peripheral circuit structure includes a row decoder connected to a plurality of word lines of each of the plurality of memory blocks, and the row decoder may be divided into a first circuit group connected to the plurality of memory blocks in common and a second circuit group connected to each of the plurality of memory blocks. The first circuit group may include: a main word line drive signal generating circuit for generating a first main word line drive signal and a second main word line drive signal based on a signal from a more significant bit group among the row address signals; and a sub-word line drive signal generating circuit for generating a first sub-word line drive signal, a second sub-word line drive signal and a third sub-word line drive signal based on a signal from a less significant bit group among the row address signals. The second circuit group may include: a local main word line drive signal generation circuit for generating a local main word line drive signal based on a first main word line drive signal and a second main word line drive signal; a first local sub-word line drive signal generation circuit for generating a first local sub-word line drive signal based on a first word line drive signal and a second sub-word line drive signal; a second local sub-word line drive signal generation circuit for generating a second local sub-word line drive signal based on a first sub-word line drive signal and a third sub-word line drive signal; and a sub-word line drive circuit for activating one word line among a plurality of word lines of a storage block selected from a plurality of storage blocks based on the local main word line drive signal, the first local sub-word line drive signal and the second local sub-word line drive signal. In a storage device, since a row decoder circuit is divided and arranged in a peripheral circuit structure, an area occupied by the row decoder circuit can be reduced, thereby reducing a chip size of the storage device. Furthermore, by reducing the number of conductive lines connected to the divided row decoder circuits and arranging power supply lines in an area secured by reducing the number of conductive lines, power supply of the memory device can be stabilized, thereby improving operation performance of the memory device.

[0123] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, the storage device include: Peripheral circuit structure; as well as a cell array structure, the cell array structure being disposed on the peripheral circuit structure and overlapping with the peripheral circuit structure in a vertical direction, The cell array structure includes a plurality of storage blocks arranged in a first horizontal direction, and at least one storage block among the plurality of storage blocks includes: a memory cell region, the memory cell region comprising a plurality of word lines and a plurality of bit lines, the plurality of word lines extending in the first horizontal direction, the plurality of bit lines extending in a second horizontal direction perpendicular to the first horizontal direction, Wherein, the peripheral circuit structure includes a row decoder, the row decoder is connected to a plurality of word lines of each of the plurality of storage blocks, and the row decoder includes: a first circuit group configured to generate a main word line drive signal and a sub word line drive signal, the first circuit group being commonly connected to the plurality of memory blocks; and A second circuit group is respectively connected to the plurality of memory blocks and is configured to generate a local main word line drive signal and a local sub word line drive signal and activate one word line among a plurality of word lines of a memory block selected from among the plurality of memory blocks.

2. The memory device according to claim 1, in, The row address signal of the row decoder is classified into a more significant bit group and a less significant bit group, and Wherein, the first circuit group includes: a main word line drive signal generating circuit configured to generate a first main word line drive signal and a second main word line drive signal based on a row address signal belonging to the more significant bit group, wherein the main word line drive signal includes the first main word line drive signal and the second main word line drive signal; and A sub-word line drive signal generating circuit, wherein the sub-word line drive signal generating circuit is configured to generate a first sub-word line drive signal, a second sub-word line drive signal and a third sub-word line drive signal based on a row address signal belonging to the less significant bit group among the row address signals, wherein the sub-word line drive signals include the first sub-word line drive signal, the second sub-word line drive signal and the third sub-word line drive signal.

3. The memory device according to claim 2, in, The main word line drive signal generating circuit comprises: a first main word line drive signal generating circuit configured to generate the first main word line drive signal based on at least one signal among the row address signals belonging to the more significant bit group; and A second main word line drive signal generating circuit is configured to generate the second main word line drive signal based on at least one other signal among the row address signals belonging to the more significant bit group.

4. The memory device according to claim 2, in, The sub-word line drive signal generating circuit comprises: a first sub word line drive signal generating circuit configured to generate the first sub word line drive signal based on at least one signal among the row address signals belonging to the less significant bit group; a second sub word line drive signal generating circuit configured to generate the second sub word line drive signal based on at least one other signal among the row address signals belonging to the less significant bit group; and A third sub word line drive signal generating circuit is configured to generate the third sub word line drive signal based on the at least one other signal among the row address signals belonging to the less significant bit group.

5. The memory device according to claim 2, in, The second circuit group includes: a local main word line drive signal generating circuit, the local main word line drive signal generating circuit being configured to generate a local main word line drive signal based on the first main word line drive signal and the second main word line drive signal; a first local sub-word line drive signal generating circuit, the first local sub-word line drive signal generating circuit being configured to generate a first local sub-word line drive signal based on the first sub-word line drive signal and the second sub-word line drive signal; a second local sub word line drive signal generating circuit configured to generate a second local sub word line drive signal based on the first sub word line drive signal and the third sub word line drive signal; and A sub word line driving circuit is configured to activate one word line among a plurality of word lines of a selected memory block based on the local main word line driving signal, the first local sub word line driving signal and the second local sub word line driving signal.

6. The memory device according to claim 5, in, The local main word line drive signal generating circuit includes a NAND logic circuit configured to input the first main word line drive signal and the second main word line drive signal, and the NAND logic circuit is connected to a high voltage line and a negative voltage line of the memory device.

7. The memory device according to claim 5, in, The first local sub-word line drive signal generating circuit includes an NOR logic circuit configured to input the first sub-word line drive signal and the second sub-word line drive signal, and the NOR logic circuit is connected to a high voltage line and a negative voltage line of the memory device.

8. The memory device according to claim 5, in, The second local sub-word line drive signal generating circuit comprises: an inverter circuit configured to input the first sub-word line driving signals respectively; and A NAND logic circuit is configured to input the output signal of the inverter circuit and the third sub word line driving signal and is connected to the high voltage line and the negative voltage line of the memory device.

9. The memory device according to claim 5, in, The sub-word line driving circuit comprises: a first PMOS transistor, wherein the PMOS transistor is a P-type metal oxide semiconductor transistor, a source of the first PMOS transistor is respectively connected to the first local sub-word line drive signal, and a gate of the first PMOS transistor is respectively connected to the local main word line drive signal; a first NMOS transistor, wherein the NMOS transistor is an N-type metal oxide semiconductor transistor, a source of the first NMOS transistor is connected to a negative voltage line of the memory device, and a gate of the first NMOS transistor is respectively connected to the local main word line drive signal; and a second NMOS transistor, wherein a source of the second NMOS transistor is connected to the negative voltage line, and a gate of the second NMOS transistor is respectively connected to the second local sub-word line drive signal, and The plurality of word lines are respectively connected to the drain of the first PMOS transistor and the drains of the first NMOS transistor and the second NMOS transistor.

10. A storage device, the storage device include: Peripheral circuit structure; as well as a cell array structure, the cell array structure being disposed on the peripheral circuit structure and overlapping with the peripheral circuit structure in a vertical direction, The cell array structure includes a plurality of storage blocks arranged in a first horizontal direction, and at least one storage block among the plurality of storage blocks includes: a memory cell region, the memory cell region comprising a plurality of word lines and a plurality of bit lines, the plurality of word lines extending in the first horizontal direction, the plurality of bit lines extending in a second horizontal direction perpendicular to the first horizontal direction, Wherein, the peripheral circuit structure includes a row decoder, the row decoder is connected to the even word lines and the odd word lines of the plurality of word lines of the plurality of storage blocks, and the row decoder includes: a first circuit group commonly connected to the plurality of memory blocks and configured to generate a main word line drive signal and sub word line drive signals associated with the even word lines and the odd word lines based on a row address signal; and A second circuit group, the second circuit group is respectively connected to the multiple storage blocks and is configured to generate a local main word line drive signal and a local sub-word line drive signal associated with the even word line and the odd word line based on the row address signal, and activate a word line among the even word line and the odd word line of a storage block selected from the multiple storage blocks.

11. The memory device according to claim 10, in, The row address signal of the row decoder is classified into a more significant bit group and a less significant bit group, and Wherein, the first circuit group includes: a main word line drive signal generating circuit configured to generate a first main word line drive signal and a second main word line drive signal based on a row address signal belonging to the more significant bit group, wherein the main word line drive signal includes the first main word line drive signal and the second main word line drive signal; and A sub-word line drive signal generating circuit, wherein the sub-word line drive signal generating circuit is configured to generate a first sub-word line drive signal, a second sub-word line drive signal and a third sub-word line drive signal based on a row address signal belonging to the lower significant bit group, wherein the sub-word line drive signal includes the first sub-word line drive signal, the second sub-word line drive signal and the third sub-word line drive signal.

12. The memory device according to claim 11, in, The main word line drive signal generating circuit comprises: a first main word line drive signal generating circuit configured to generate the first main word line drive signal based on at least one signal among the row address signals belonging to the more significant bit group; and A second main word line drive signal generating circuit is configured to generate the second main word line drive signal based on at least one other signal among the row address signals belonging to the more significant bit group.

13. The memory device according to claim 11, in, The sub-word line drive signal generating circuit comprises: a first sub word line drive signal generating circuit configured to generate the first sub word line drive signal based on at least one signal among the row address signals belonging to the less significant bit group; a second sub-word line drive signal generating circuit configured to generate the second sub-word line drive signal based on at least one other signal among the row address signals belonging to the less significant bit group, wherein the second sub-word line drive signal is divided into a signal associated with the even word line and a signal associated with the odd word line; and A third sub-word line drive signal generating circuit is configured to generate the third sub-word line drive signal based on the at least one other signal among the row address signals belonging to the lower significant bit group, wherein the third sub-word line drive signal is divided into a signal associated with the even word line and a signal associated with the odd word line.

14. The memory device according to claim 11, in, The second circuit group includes: a local main word line drive signal generating circuit, the local main word line drive signal generating circuit being configured to generate a local main word line drive signal based on the first main word line drive signal and the second main word line drive signal; a first local sub-word line drive signal generating circuit, the first local sub-word line drive signal generating circuit being configured to generate a first local sub-word line drive signal based on the first sub-word line drive signal and the second sub-word line drive signal; a second local sub word line drive signal generating circuit configured to generate a second local sub word line drive signal based on the first sub word line drive signal and the third sub word line drive signal; and A sub word line driving circuit is configured to activate one word line among a plurality of word lines of a selected memory block based on the local main word line driving signal, the first local sub word line driving signal and the second local sub word line driving signal.

15. The memory device according to claim 14, in, The local main word line drive signal generating circuit includes a NAND logic circuit configured to input the first main word line drive signal and the second main word line drive signal, and the NAND logic circuit is connected to a high voltage line and a negative voltage line of the memory device.

16. The memory device according to claim 14, in, The first local sub-word line drive signal generating circuit includes an NOR logic circuit configured to input the first sub-word line drive signal and the second sub-word line drive signal, and the NOR logic circuit is connected to a high voltage line and a negative voltage line of the memory device.

17. The memory device according to claim 14, in, The second local sub-word line drive signal generating circuit comprises: an inverter circuit configured to input the first sub-word line driving signals respectively; and A NAND logic circuit is configured to input the output signal of the inverter circuit and the third sub word line driving signal and is connected to the high voltage line and the negative voltage line of the memory device.

18. The memory device according to claim 14, in, The sub-word line driving circuit comprises: a first PMOS transistor, wherein the PMOS transistor is a P-type metal oxide semiconductor transistor, a source of the first PMOS transistor is respectively connected to the first local sub-word line drive signal, and a gate of the first PMOS transistor is respectively connected to the local main word line drive signal; a first NMOS transistor, wherein the NMOS transistor is an N-type metal oxide semiconductor transistor, a source of the first NMOS transistor is connected to a negative voltage line of the memory device, and a gate of the first NMOS transistor is respectively connected to the local main word line drive signal; and a second NMOS transistor, wherein a source of the second NMOS transistor is connected to the negative voltage line, and a gate of the second NMOS transistor is respectively connected to the second local sub-word line drive signal, and The plurality of word lines are respectively connected to the drain of the first PMOS transistor and the drains of the first NMOS transistor and the second NMOS transistor.

19. A storage device, the storage device include: a memory cell array, the memory cell array comprising a plurality of memory cells connected to a plurality of word lines, wherein the memory cell array comprises a plurality of memory blocks; and a row decoder connected to a plurality of word lines of the plurality of memory blocks, Wherein, the row decoder comprises: a first circuit group commonly connected to the plurality of memory blocks and configured to generate a main word line drive signal and a sub word line drive signal based on a row address signal; and A second circuit group, the second circuit group is respectively connected to the multiple storage blocks and is configured to generate a local main word line drive signal and a local sub-word line drive signal based on the row address signal, and activate one word line among multiple word lines of a storage block selected from the multiple storage blocks.

20. The memory device according to claim 19, in, The row decoder generates the sub-word line drive signal and the local sub-word line drive signal as a signal associated with an even word line among the multiple word lines and a signal associated with an odd word line among the multiple word lines, and activates one word line among the even word line and the odd word line of the selected memory block.

Images