Electronic device

Abstract

An electronic device is provided. The electronic device includes: a base layer; at least one transistor including a semiconductor pattern on the base layer and a gate electrode on the semiconductor pattern; a connection electrode on the at least one transistor; at least one insulating layer between the semiconductor pattern and the connection electrode; a side light shielding pattern located on the same layer as the connection electrode; and a light emitting element on the connection electrode and electrically connected to the at least one transistor. The connection electrode passes through the at least one insulating layer to be connected to the semiconductor pattern, and the side light shielding pattern passes through the at least one insulating layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0077739 filed in the Korean Intellectual Property Office on June 16, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more embodiments of the present disclosure described herein relate to an electronic device, for example, to an electronic device including a transmissive region having a relatively high transmittance. Background Art

[0003] The electronic device may include a device including one or more suitable electronic components (such as a display panel and / or an electronic module). The electronic module may include a camera, an infrared sensor and / or a proximity sensor, etc. The electronic module may be arranged below the display panel. The transmittance of a partial area of ​​the display panel may be higher than the transmittance of another partial area of ​​the display panel. The electronic module may receive an external input through a partial area of ​​the display panel and / or provide an output through a partial area of ​​the display panel. Summary of the invention

[0004] One or more embodiments of the present disclosure provide an electronic device having improved display quality while including a transmissive region having a relatively high transmittance within a display region.

[0005] According to one or more embodiments, an electronic device includes: a base layer; at least one transistor, including a semiconductor pattern on the base layer and a gate electrode on the semiconductor pattern; a connecting electrode on the at least one transistor; at least one insulating layer between the semiconductor pattern and the connecting electrode; a side shading pattern on the same layer as the connecting electrode; and a light-emitting element on the connecting electrode and electrically connected to the at least one transistor, wherein the connecting electrode passes through at least one insulating layer and is electrically connected to the semiconductor pattern, and the side shading pattern passes through at least one insulating layer.

[0006] The side light-shielding pattern may extend in one direction on a plane, and the semiconductor pattern may overlap the side light-shielding pattern when viewed in a direction defining the plane together with the one direction and intersecting the one direction.

[0007] The electronic device may further include: a lower light-shielding pattern located between the base layer and the semiconductor pattern, wherein the at least one transistor overlaps the lower light-shielding pattern on a plane.

[0008] The electronic device may further include: a lower insulating layer between the lower light shielding pattern and the semiconductor pattern, wherein the side light shielding pattern overlaps the lower light shielding pattern on a plane and further passes through the lower insulating layer to contact the lower light shielding pattern.

[0009] The electronic device may further include a light absorption pattern at the same layer as the semiconductor pattern and including the same material as that of the semiconductor pattern, wherein the side light shielding pattern contacts the light absorption pattern.

[0010] The side light shielding pattern may include: a first side pattern and a second side pattern extending in a first direction on a plane and spaced apart from each other in a second direction crossing the first direction on the plane, with at least one transistor interposed therebetween.

[0011] When viewed in the second direction, at least one transistor may overlap the first side pattern and the second side pattern.

[0012] The electronic device may further include: a first light absorption pattern and a second light absorption pattern, which are spaced apart from each other in the second direction, and at least one transistor is placed between the first light absorption pattern and the second light absorption pattern, each of the first light absorption pattern and the second light absorption pattern extends in the first direction and is arranged on the same layer as the semiconductor pattern, wherein the first side pattern overlaps with the first light absorption pattern and contacts with the first light absorption pattern, and the second side pattern overlaps with the second light absorption pattern and contacts with the second light absorption pattern.

[0013] The light-emitting element includes a plurality of light-emitting elements, and the plurality of light-emitting elements may include: a first light-emitting element, each of which is configured to emit a light beam having a first color to a first light-emitting area; a second light-emitting element, each of which is configured to emit a light beam having a second color different from the first color to a second light-emitting area; and a third light-emitting element, each of which is configured to emit a light beam having a third color different from the first color and the second color to a third light-emitting area, one first pixel element in the first light-emitting element, two second pixel elements in the second light-emitting element, and one third pixel element in the third light-emitting element may be arranged in a pixel group, and one pixel group may be repeatedly arranged in a pixel row along a first direction.

[0014] In a pixel group, the first light-emitting area of ​​a first pixel element and the third light-emitting area of ​​a third pixel element can be spaced apart from each other in a first direction, and the second light-emitting areas of two second pixel elements can be spaced apart from each other in a direction intersecting the first direction and the second direction, and the third light-emitting area of ​​a third pixel element is placed between the second light-emitting areas of the two second pixel elements.

[0015] The base layer may include: a component area including a transmission area and an element area; and a main display area adjacent to the component area, and the light emitting element may overlap the element area and the main display area, and may not overlap the transmission area.

[0016] A plurality of transmission regions including a transmission region and a plurality of element regions including an element region may be arranged in the base layer, and the transmission regions and the element regions may be arranged to alternate with each other in the second direction inside the component region, and one pixel row may overlap the element region.

[0017] The first side pattern and the second side pattern may be arranged to overlap each of the element regions.

[0018] The electronic device may also include: a first pixel circuit electrically connected to a corresponding first light-emitting element among the first light-emitting elements; a second pixel circuit electrically connected to a corresponding second light-emitting element among the second light-emitting elements; and a third pixel circuit electrically connected to a corresponding third light-emitting element among the third light-emitting elements, wherein each of the first to third pixel circuits includes at least one transistor and a connecting electrode, and in a pixel group, one of the first pixel circuits, one of the two second pixel circuits, one of the third pixel circuit, and the other of the two second pixel circuits are arranged along the first direction.

[0019] The electronic device may also include: an upper shading pattern overlapping at least a portion of the semiconductor pattern on a plane, wherein the light-emitting element includes a first electrode on the connecting electrode and electrically connected to the connecting electrode, a light-emitting layer on the first electrode, and a second electrode on the light-emitting layer, and the upper shading pattern is on the same layer as the first electrode.

[0020] The electronic device may further include: an upper connecting electrode located between the connecting electrode and the light emitting element and electrically connected between the connecting electrode and the light emitting element; and an upper light shielding pattern overlapping at least a portion of the semiconductor pattern on a plane and located at the same layer as the upper connecting electrode.

[0021] The at least one insulating layer may include a first insulating layer between the semiconductor pattern and the gate electrode and a second insulating layer between the gate electrode and the connection electrode, and the side light shielding pattern may continuously pass through the first insulating layer and the second insulating layer.

[0022] The electronic device may also include: at least one additional transistor, including an additional semiconductor pattern located between the gate electrode and the connecting electrode and an additional gate electrode located between the additional semiconductor pattern and the connecting electrode, wherein the at least one insulating layer further includes: a third insulating layer located between the gate electrode and the additional semiconductor pattern; a fourth insulating layer located between the additional semiconductor pattern and the additional gate electrode; and a fifth insulating layer located between the additional gate electrode and the connecting electrode, and the side shading pattern continuously passes through the first insulating layer to the fifth insulating layer.

[0023] The side light shielding pattern may include the same material as that of the connection electrode.

[0024] According to one or more embodiments, an electronic device includes: a pixel circuit including at least one transistor, the at least one transistor including a semiconductor pattern and a gate electrode on the semiconductor pattern; a light-emitting element electrically connected to the pixel circuit; and a side shading pattern including a first side pattern and a second side pattern, the first side pattern and the second side pattern being spaced apart from each other in one direction on a plane, and the pixel circuit being placed between the first side pattern and the second side pattern, wherein the semiconductor pattern overlaps with each of the first side pattern and the second side pattern when viewed in one direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other aspects and features of embodiments of the present disclosure will become apparent by describing embodiments of the present disclosure in more detail with reference to the accompanying drawings.

[0026] Figure 1 is a perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0027] Figure 2A is an exploded perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0028] Figure 2B is a block diagram of an electronic device according to one or more embodiments of the present disclosure.

[0029] Figure 2C is a cross-sectional view of an electronic panel according to one or more embodiments of the present disclosure.

[0030] Figure 3A is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0031] Figure 3B is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0032] Figure 4A is an enlarged plan view of a portion of a first region of a display panel according to one or more embodiments of the present disclosure.

[0033] Figure 4B is an enlarged plan view of a portion of a second region of a display panel according to one or more embodiments of the present disclosure.

[0034] Figure 5A is a cross-sectional view illustrating a first region of a display panel according to one or more embodiments of the present disclosure.

[0035] Figure 5B is a cross-sectional view illustrating a second region of a display panel according to one or more embodiments of the present disclosure.

[0036] Fig. 6A is a plan view illustrating a portion of a lower light shielding pattern disposed in a second region of a display panel according to one or more embodiments of the present disclosure.

[0037] FIG. 6B to FIG. 6H is a plan view showing one layer constituting pixel circuits each arranged in the second region of the display panel according to one or more embodiments of the present disclosure.

[0038] Fig.6I is a plan view illustrating one layer constituting a light emitting layer provided in a second region of a display panel according to one or more embodiments of the present disclosure.

[0039] Figure 7 is a cross-sectional view illustrating a second region of a display panel according to one or more embodiments of the present disclosure.

[0040] Fig. 8A is a plan view illustrating one layer constituting a pixel circuit arranged in the second area of ​​the display panel according to one or more embodiments of the present disclosure.

[0041] Figure 8B is a plan view illustrating one layer constituting a light emitting layer provided in a second region of a display panel according to one or more embodiments of the present disclosure.

[0042] Fig. 9 is a cross-sectional view illustrating a second region of a display panel according to one or more embodiments of the present disclosure.

[0043] Fig. 10A is a plan view illustrating a portion of a lower light-shielding pattern disposed in a second region according to one or more embodiments of the present disclosure.

[0044] Fig. 10B is a plan view showing one layer constituting a pixel circuit arranged in the second region according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0045] In the present disclosure, the expression that a first component (or region, layer, part, portion, etc.) is "disposed on a second component", "connected to a second component" or "bonded to a second component" means that the first component is directly disposed on the second component / directly connected to the second component / directly bonded to the second component, or that a third component is placed therebetween.

[0046] The same reference numerals represent the same components. In addition, in the drawings, in order to effectively describe the technical content, the thickness, proportion and size of the components are exaggerated. The term "and / or" includes all combinations of one or more components that can be defined by the relevant components.

[0047] Although the terms "first", "second", etc. can be used to describe one or more suitable components, the components should not be limited by the terms. The terms are only used to distinguish one component from another component. For example, without departing from the spirit and scope of the present disclosure, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component. Unless otherwise clearly indicated in the context, a singular expression includes a plural expression.

[0048] Furthermore, the terms “below,” “beneath,” “on,” “over,” etc. are used to describe the relationship of components shown in the drawings. Conceptually relative terms are described based on the directions shown in the drawings.

[0049] It will be understood that the terms "comprises," "includes," "has," etc. indicate the presence of the features, quantities, steps, operations, elements or components, or combinations thereof, described in the present disclosure, and do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements or components, or combinations thereof.

[0050] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this disclosure have the same meaning as those commonly understood by those skilled in the art to which this disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted as an overly idealized or overly formalized meaning, unless clearly defined herein.

[0051] Hereinafter, one or more embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0052] Figure 1 is a perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0053] The electronic device 1000 may be a device activated according to an electrical signal. The electronic device 1000 may include one or more embodiments. For example, the electronic device 1000 may include a tablet computer, a laptop computer, a computer, and / or a smart TV, etc. In one or more embodiments, as an example, the electronic device 1000 is shown as a smart phone.

[0054] The electronic device 1000 may display an image IM in a third direction DR3 on a display surface DS parallel to the first direction DR1 and the second direction DR2. The display surface DS on which the image IM is displayed may correspond to a front surface of the electronic device 1000. The image IM may include a still image as well as a dynamic image. Figure 1 , a watch and a plurality of icons are shown as examples of the image IM.

[0055] In one or more embodiments, the front surface (or upper surface) and the rear surface (or lower surface) of each component are defined relative to the direction along which the image IM is displayed. The front surface and the rear surface may be opposite to each other in a third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. The spacing distance between the front surface and the rear surface in the third direction DR3 may correspond to the thickness of the electronic device 1000 in the third direction DR3. In addition, in the present disclosure, the meaning of "on a plane" may be defined as the state of "when viewed in the third direction DR3".

[0056] The display surface DS may include a display area DA and a non-display area NDA around the display area DA along an edge or periphery of the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA. However, the present disclosure is not limited thereto, and the shape of the display area DA and the shape of the non-display area NDA may be modified.

[0057] The sensor area ED-SA may be defined inside the display area DA of the electronic device 1000 . Figure 1 One sensor area ED-SA is shown, but the number of sensor areas ED-SA is not limited thereto. The sensor area ED-SA may be a part of the display area DA. Therefore, the electronic device 1000 may display an image through the sensor area ED-SA.

[0058] The electronic module may be disposed in a portion overlapping the sensor area ED-SA. The electronic module may receive an external input transmitted through the sensor area ED-SA, or provide an output through the sensor area ED-SA. For example, the electronic module may be a camera module, a sensor for measuring distance (such as a proximity sensor), a sensor for recognizing a part of a user's body (e.g., a fingerprint, an iris, and / or a face), or a small lamp for outputting a light beam, but the present disclosure is not particularly limited thereto.

[0059] Figure 2A is an exploded perspective view of an electronic device according to one or more embodiments of the present disclosure. Figure 2B is a block diagram of an electronic device according to one or more embodiments of the present disclosure. Figure 2C is a cross-sectional view of an electronic panel according to one or more embodiments of the present disclosure.

[0060] Reference Figure 2A , the electronic device 1000 includes a window 100, a housing 200, a display module 300, and an electronic module 400. In one or more embodiments, the window 100 and the housing 200 are combined with each other to constitute the appearance of the electronic device 1000.

[0061] The window 100 may include an insulating panel. For example, the window 100 may be made of glass, plastic, or a combination thereof. The window 100 may provide a front surface of the electronic device 1000.

[0062] The display module 300 may include at least an electronic panel EP. The electronic panel EP may generate an image and detect an external input.

[0063] The electronic panel EP includes a display area DA (see FIG. Figure 1 ) and non-display area NDA (see Figure 1 ) corresponds to a display area DP-DA and a non-display area DP-NDA. In the present disclosure, the expression “area / portion and area / portion correspond to each other” means that the area / portion and the area / portion overlap each other, and are not limited to the same area.

[0064] In one or more embodiments, the electronic panel EP is assembled in a flat state in which the display area DP-DA and the non-display area DP-NDA face the window 100. However, this is an example, and a portion of the non-display area DP-NDA of the electronic panel EP may be bent. For example, a portion of the non-display area DP-NDA faces the rear surface of the electronic device 1000, and thus the non-display area NDA shown on the front surface of the electronic device 1000 (see FIG. 1 ) may be reduced. Figure 1 ). In some embodiments, the electronic panel EP may be assembled in a state in which a portion of the display area DP-DA is bent. In some embodiments, in the electronic panel EP according to one or more embodiments of the present disclosure, the non-display area DP-NDA may not be provided.

[0065] The display area DP-DA may be an area in which a plurality of pixels PX are arranged. The display area DP-DA may include a first area A1 and a second area A2. The second area A2 may be aligned with the sensor area ED-SA (see FIG. 1 ) of the electronic device 1000. Figure 1 ) overlap or correspond. In one or more embodiments, the second area A2 has a circular shape, but may have one or more suitable shapes (such as a polygon, an ellipse, a shape with at least one curved edge, or an atypical shape), and the present disclosure is not limited to the embodiments. The first area A1 may be referred to as a main display area or a general display area, and the second area A2 may be referred to as a component area.

[0066] The second area A2 may have a transmittance higher than that of the first area A1. In some embodiments, the resolution of the second area A2 may be lower than that of the first area A1, but the present disclosure is not limited thereto. For example, the second area A2 has a transmittance higher than that of the first area A1, but the resolution of the second area A2 may be substantially the same as that of the first area A1. The second area A2 may be defined as an area overlapping with an area where the electronic module 400 is disposed inside the housing 200 in the display area DP-DA.

[0067] The first area A1 may be adjacent to the second area A2. In one or more embodiments, the first area A1 is shown to have a shape surrounding the entire second area A2 (e.g., surrounding the entire second area A1), but this is an example. The first area A1 may be defined as being adjacent to only a portion of an edge of the second area A2, and the present disclosure is not limited to a specific embodiment.

[0068] Reference Figure 2B and Figure 2C , the electronic panel EP may include a display panel 310 and an input detection unit 320 .

[0069] The display panel 310 may be a component that generally generates an image. The display panel 310 may be a light-emitting display panel, for example, the display panel 310 may be an organic light-emitting display panel, an inorganic light-emitting display panel, a micro-light-emitting diode (LED) display panel, or a nano-LED display panel. The display panel 310 may be referred to as a display layer.

[0070] The display panel 310 may include a base layer 311 , a circuit layer 312 , a light emitting element layer 313 , and an encapsulation layer 314 .

[0071] The base layer 311 may be Figure 2A The display area DP-DA and the non-display area DP-NDA are overlapped. The base layer 311 may be a member that provides a base surface on which the circuit layer 312 is disposed. The base layer 311 may be a rigid base or a flexible base that can be bent, folded and / or curled. The base layer 311 may be a glass base, a metal base and / or a polymer base, etc. However, one or more embodiments of the present disclosure are not limited thereto, and the base layer 311 may be an inorganic layer, an organic layer and / or a composite material layer.

[0072] The base layer 311 may have a multi-layer structure. For example, the base layer 311 may include a first synthetic resin layer, a multi-layer or single-layer inorganic layer, and a second synthetic resin layer disposed on the multi-layer or single-layer inorganic layer. Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide-based resin, but the present disclosure is not particularly limited thereto.

[0073] The circuit layer 312 may be disposed on the base layer 311. The circuit layer 312 may include an insulating layer, a semiconductor pattern, a conductive pattern, and / or a signal line, and the like.

[0074] The light emitting element layer 313 may be disposed on the circuit layer 312. The light emitting element layer 313 may include a light emitting element. For example, the light emitting element may include an organic light emitting material, an inorganic light emitting material, an organic inorganic light emitting material, a quantum dot, a quantum rod, a micro-LED and / or a nano-LED.

[0075] The encapsulation layer 314 may be disposed on the light emitting element layer 313. The encapsulation layer 314 may protect the light emitting element layer 313 from foreign matter such as moisture, oxygen and / or dust particles. The encapsulation layer 314 may include at least one inorganic layer. The encapsulation layer 314 may include a stacked structure of inorganic layer / organic layer / inorganic layer.

[0076] The input detection unit 320 may be provided on the display panel 310. The input detection unit 320 may detect an external input applied from an external unit. The external input may be an input of a user. The user's input may include one or more suitable types (kinds) of external input (such as a part of the user's body, light, heat, a pen, and / or pressure).

[0077] The input detection unit 320 may be formed on the display panel 310 through a simultaneous or continuous process. In this case, the input detection unit 320 may be directly disposed on the display panel 310. Here, “directly disposed” may mean that a third component is not disposed between the input detection unit 320 and the display panel 310. For example, a separate adhesive member may not be disposed between the input detection unit 320 and the display panel 310.

[0078] Return to reference Figure 2A The display module 300 may further include a driving chip DIC disposed in the non-display area DP-NDA. The display module 300 may further include a flexible circuit film FCB coupled to the non-display area DP-NDA.

[0079] The driving chip DIC may include a chip for driving the display panel 310 (see Figure 2B ) of the pixel PXij (for example, see Figure 3B ) of the driving element (e.g., data driving circuit). Figure 2A , a structure in which the driving chip DIC is mounted on the electronic panel EP is shown, but the present disclosure is not limited thereto. For example, the driving chip DIC may be mounted on a flexible circuit film FCB.

[0080] The electronic module 400 is disposed below the display module 300. The electronic module 400 may receive an external input transmitted through the second area A2, or output a signal through the second area A2. According to the present disclosure, the second area A2 having a relatively high transmittance is disposed inside the display area DP-DA, and thus the electronic module 400 may be disposed to overlap the display area DP-DA.

[0081] Reference Figure 2B , the electronic device 1000 may include a display module 300 (see 2A) including at least an electronic panel EP, a power module PM, a first electronic module EM1, and a second electronic module EM2. The electronic panel EP, the power module PM, the first electronic module EM1, and the second electronic module EM2 may be electrically connected to each other.

[0082] The power module PM supplies power required for overall operations of the electronic device 1000. The power module PM may include a general battery module.

[0083] The first and second electronic modules EM1 and EM2 may include one or more suitable functional modules for operating the electronic device 1000. The first electronic module EM1 may be directly mounted on a motherboard electrically connected to the electronic panel EP, or mounted on a separate substrate and thus may be electrically connected to the motherboard through a connector.

[0084] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM, and an external interface IF. Some of the modules are not mounted on the motherboard and may be electrically connected to the motherboard through a flexible circuit board.

[0085] The control module CM controls the overall operation of the electronic device 1000. The control module CM may be a microprocessor. For example, the control module CM activates or deactivates the electronic panel EP. The control module CM may control other modules such as the image input module IIM and the audio input module AIM based on a touch signal received from the electronic panel EP.

[0086] The wireless communication module TM can be used to send wireless signals to / receive wireless signals from another terminal using a Bluetooth line and / or a Wi-Fi line. The wireless communication module TM can be used to send and / or receive audio signals using a general communication line. The wireless communication module TM includes a sending unit TM1 for modulating and sending a signal to be sent and a receiving unit TM2 for demodulating a received signal.

[0087] The image input module IIM processes the image signal and converts it into image data that can be displayed on the electronic panel EP. The audio input module AIM receives an external audio signal through a microphone in a recording mode and / or a voice recognition mode, etc., and converts the received external audio signal into electrical voice data.

[0088] The external interface IF serves as an interface for connecting to an external charger, a wired / wireless data port, and / or a card (eg, a memory card and a Subscriber Identity Module (SIM) / User Identity Module (UIM) card) socket, etc.

[0089] The second electronic module EM2 may include an audio output module AOM, a light emitting module LM, a light receiving module LRM and / or a camera module CMM, etc. The components may be mounted directly on the motherboard or on a separate substrate and electrically connected to the electronic panel EP or to the first electronic module EM1 through a connector.

[0090] The audio output module AOM converts audio data received from the wireless communication module TM or audio data stored in the memory MM into voice, and outputs the converted voice to the outside.

[0091] The light emitting module LM generates and outputs a light beam. The light emitting module LM may output an infrared light beam. The light emitting module LM may include a light emitting diode (LED) element. The light receiving module LRM may detect the infrared light beam. When an infrared light beam having a suitable level (e.g., a set level or a predetermined level) or higher is detected, the light receiving module LRM may be activated. The light receiving module LRM may include a complementary metal oxide semiconductor (CMOS) sensor. The infrared light beam generated by the light emitting module LM may be output and then reflected by an external object (e.g., a finger or face of a user), and the reflected infrared light beam may be input to the light receiving module LRM. The camera module CMM captures external images.

[0092] According to one or more embodiments of the present disclosure, Figure 2A The electronic module 400 shown in the figure may include at least one of the components of the second electronic module EM2. For example, the electronic module 400 may include at least one of a camera, a speaker, a light detection sensor, and a heat detection sensor. The electronic module 400 may detect an external input received through the second area A2, or provide a sound signal such as a voice to the outside through the second area A2. In addition, the electronic module 400 may include a plurality of components, and the present disclosure is not limited to a specific embodiment. In some embodiments, although not shown, the electronic module 400 may be attached to the electronic panel EP by a separate adhesive.

[0093] Return to reference Figure 2A, the housing 200 is coupled to the window 100. The housing 200 is coupled to the window 100 to provide a suitable internal space (eg, a set or predetermined internal space). The display module 300 and the electronic module 400 may be accommodated in the internal space.

[0094] The housing 200 may include a material having relatively high rigidity. For example, the housing 200 may include a plurality of frames and / or plates made of glass, plastic, and / or metal and / or a combination thereof. The housing 200 may stably protect the components of the electronic device 1000 contained in the internal space from external impacts.

[0095] Figure 3A is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0096] Reference Figure 3A , a display area DP-DA and a non-display area DP-NDA around the display area DP-DA may be defined in the display panel 310. The display area DP-DA and the non-display area DP-NDA may be distinguished from each other according to whether the pixel PX is disposed in the area. The pixel PX is disposed in the display area DP-DA. The scanning driving unit SDV, the data driving unit, and the light emitting driving unit EDV may be disposed in the non-display area DP-NDA. The data driving unit may be a part of a circuit included in the driving chip DIC.

[0097] The display area DP-DA may include a first area A1 and a second area A2. The display area DP-DA may include a first area A1 and a second area A2. Figure 4B ) to distinguish the first area A1 and the second area A2 from each other. The first area A1 and the second area A2 will be described in more detail.

[0098] The display panel 310 may include a first panel area AA1, a bending area BA, and a second panel area AA2 defined in the second direction DR2. The second panel area AA2 and the bending area BA may be partial areas of the non-display area DP-NDA. The bending area BA is disposed between the first panel area AA1 and the second panel area AA2. The first panel area AA1 is Figure 1 The area corresponding to the display surface DS.

[0099] The width of the bending area BA parallel to the first direction DR1 and the width (or length) of the second panel area AA2 parallel to the first direction DR1 may be smaller than the width (or length) of the first panel area AA1 parallel to the first direction DR1. An area with a shorter length in the bending axis direction may bend more easily.

[0100] The display panel 310 may include pixels PX, write scan lines GWL1 to GWLm, compensation scan lines GCL1 to GCLm, initialization scan lines GIL1 to GILm, black scan lines GBL1 to GBLm, light emission control lines ECL1 to ECLm, data lines DL1 to DLn, first control lines CSL1 and second control lines CSL2, driving voltage lines PL, and a plurality of pads (also called "pads" or "pads") PD. In this case, "m" and "n" are natural numbers greater than or equal to 2.

[0101] The pixels PX may be connected to write scan lines GWL1 to GWLm, compensation scan lines GCL1 to GCLm, initialization scan lines GIL1 to GILm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, and data lines DL1 to DLn.

[0102] The write scan lines GWL1 to GWLm, the compensation scan lines GCL1 to GCLm, the initialization scan lines GIL1 to GILm, and the black scan lines GBL1 to GBLm may extend in the first direction DR1 and may be electrically connected to the scan driving unit SDV. The data lines DL1 to DLn may extend in the second direction DR2 and may be electrically connected to the driving chip DIC via the bending area BA. The light emission control lines ECL1 to ECLm may extend in the first direction DR1 and may be electrically connected to the light emission driving unit EDV.

[0103] The driving voltage line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be arranged in different layers. The portion of the driving voltage line PL extending in the second direction DR2 may extend to the second panel area AA2 via the bending area BA. The driving voltage line PL may provide a driving voltage to the pixel PX.

[0104] The first control line CSL1 may be connected to the scan driving unit SDV and may extend toward the lower end of the second panel area AA2 via the bending area BA. The second control line CSL2 may be connected to the light emitting driving unit EDV and may extend toward the lower end of the second panel area AA2 via the bending area BA.

[0105] When viewed on a plane, the pad PD may be arranged adjacent to the lower end of the second panel area AA2. The driving chip DIC, the driving voltage line PL, the first control line CSL1, and the second control line CSL2 may be electrically connected to the pad PD. The flexible circuit film FCB may be electrically connected to the pad PD through an anisotropic conductive adhesive layer.

[0106] Figure 3Bis an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure. Figure 3B A plurality of pixels PX are shown (see Figure 3A ) is an example equivalent circuit diagram of a pixel PXij among multiple pixels PX (see Figure 3A ) have the same circuit structure, so the description of the circuit structure of the pixel PXij will not be provided for other pixels PX (see Figure 3A ) in detail.

[0107] Reference Figure 3B , the pixels PXij are connected to the data lines DL1 to DLn (see Figure 3A ) among the i-th data line DLi, the write scan lines GWL1 to GWLm (see Figure 3A ) among the j-th write scan line GWLj, the compensation scan lines GCL1 to GCLm (see Figure 3A ) among the j-th compensation scanning line GCLj, the initialization scanning lines GIL1 to GILm (see Figure 3A ) among the j-th initialization scanning line GILj, the black scanning lines GBL1 to GBLm (see Figure 3A ) among the j-th black scanning line GBLj, the light emitting control lines ECL1 to ECLm (see Figure 3A ), the j-th light emitting control line ECLj, the first driving voltage line VL1 and the second driving voltage line VL2, the first initialization voltage line VL3 and the second initialization voltage line VL4, and the bias voltage line VL5. In this case, "i" is an integer greater than or equal to 1 and less than or equal to n, and "j" is an integer greater than or equal to 1 and less than or equal to m.

[0108] The pixel PXij may include a pixel circuit PC and a light emitting element LD connected to the pixel circuit PC. The light emitting element LD may be a light emitting diode. As an example of the present disclosure, the light emitting element LD may be an organic light emitting diode including an organic light emitting layer, but the present disclosure is not particularly limited thereto. The pixel circuit PC may drive the light emitting element LD. The pixel circuit PC may be referred to as a pixel driving circuit. The pixel circuit PC may control the amount of current flowing in the light emitting element LD in response to the i-th data signal Di. The light emitting element LD may emit a light beam having a suitable brightness (e.g., a set or predetermined brightness) corresponding to the amount of current provided from the pixel circuit PC. In the present disclosure, the amount of current of the pixel PXij may be the amount of current provided to the light emitting element LD.

[0109] The pixel circuit PC may include a plurality of transistors T1 to T8 and a capacitor Cst. According to the present disclosure, the configuration of the pixel circuit PC is not limited to Figure 3B The embodiment shown in . Figure 3BThe pixel circuit PC shown in FIG. 1 is merely an example, and the configuration of the pixel circuit PC may be modified and implemented.

[0110] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be LTPS transistors.

[0111] In detail, the first transistor (or driving transistor) T1 that directly affects the brightness of the light-emitting element LD includes a highly reliable polycrystalline silicon semiconductor layer, and therefore, a high-resolution display device can be realized. In one or more embodiments, because the oxide semiconductor has high carrier mobility and low leakage current, the voltage drop is not large even if the driving time is long. For example, because the color change of the image caused by the voltage drop is not large even during low-frequency driving, low-frequency driving can be performed. In this way, because the oxide semiconductor has a low leakage current, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 can adopt an oxide transistor, and therefore the leakage current that may flow to the gate electrode can be prevented or reduced, and power consumption can be reduced at the same time.

[0112] Some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may be P-type (or P-type) transistors, and the others may be N-type (or N-type) transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may be P-type (or P-type) transistors, and the third transistor T3 and the fourth transistor T4 may be N-type (or N-type) transistors.

[0113] The configuration of the pixel circuit PC according to the present disclosure is not limited to Figure 3B The embodiment shown in . Figure 3BThe pixel circuit PC shown in is only an example, and the configuration of the pixel circuit PC may be modified and implemented. For example, all of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type (or P-class) transistors or N-type (or N-class) transistors.

[0114] The jth write scan line GWLj, the jth compensation scan line GCLj, the jth initialization scan line GILj, the jth black scan line GBLj, and the jth emission control line ECLj can transmit the jth write scan signal GWj, the jth compensation scan signal GCj, the jth initialization scan signal GIj, the jth black scan signal GBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have the same value as that input to the electronic panel EP (see Figure 2A )’s image signal corresponding to the voltage level.

[0115] The first driving voltage line VL1 and the second driving voltage line VL2 can transmit the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PXij, respectively. In addition, the first initialization voltage line VL3 and the second initialization voltage line VL4 can transmit the first initialization voltage VINT and the second initialization voltage VAINT to the pixel PXij, respectively. The bias voltage line VL5 can transmit the bias voltage VOBS to the pixel PXij.

[0116] The first transistor T1 is connected between the first driving voltage line VL1 receiving the first driving voltage ELVDD and the light emitting element LD. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to a pixel electrode (or referred to as an anode) of the light emitting element LD via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the capacitor Cst. The first transistor T1 can receive the i-th data signal Di transmitted by the i-th data line DLi according to the switching operation of the second transistor T2, and supply a driving current to the light emitting element LD.

[0117] The second transistor T2 is connected between the data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 can be turned on according to the j-th write scan signal GWj transmitted through the j-th write scan line GWLj, and can transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0118] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line GCLj. The third transistor T3 may be turned on according to the j-th compensation scan signal GCj transmitted through the j-th compensation scan line GCLj, may connect the third electrode of the first transistor T1 and the second electrode of the first transistor T1 to each other, and thus may diode-connect the first transistor T1.

[0119] The fourth transistor T4 is connected between the first initialization voltage line VL3 to which the first initialization voltage VINT is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 to which the first initialization voltage VINT is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the jth initialization scan line GILj. The fourth transistor T4 is turned on according to the jth initialization scan signal GIj transmitted through the jth initialization scan line GILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT to the first node N1, and initializes the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0120] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th light emission control line ECLj. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode of the light emitting element LD, and a third electrode (e.g., a gate electrode) connected to the j-th light emission control line ECLj.

[0121] The fifth transistor T5 and the sixth transistor T6 are turned on simultaneously (e.g., in parallel) according to the jth light emitting control signal EMj transmitted through the jth light emitting control line ECLj. The first driving voltage ELVDD applied by the turned-on fifth transistor T5 can be compensated by the diode-connected first transistor T1 and then transmitted to the light emitting element LD through the sixth transistor T6.

[0122] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VL4 to which a second initialization voltage VAINT is applied, a second electrode connected to a second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to the jth black scan line GBLj. The second initialization voltage VAINT may have a voltage level lower than or equal to the first initialization voltage VINT. The seventh transistor T7 may improve the black performance of the pixel PXij. When the seventh transistor T7 is turned on, the parasitic capacitor of the light emitting element LD may be discharged. Therefore, when black brightness is achieved, the light emitting element LD does not emit a light beam due to the leakage current of the first transistor T1, and therefore, the black performance may be improved.

[0123] One end of the capacitor Cst is connected to the third electrode of the first transistor T1, and the other end of the capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element LD can be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The second driving voltage ELVSS can have a voltage level lower than the voltage level of the first driving voltage ELVDD. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 can be determined according to the voltage stored in the capacitor Cst.

[0124] The eighth transistor T8 may include a first electrode connected to the bias voltage line VL5, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the j-th black scan line GBLj. The eighth transistor T8 is turned on by the j-th black scan signal GBj and may provide a bias voltage VOBS to the first electrode of the first transistor T1. When the bias voltage VOBS is applied to the first transistor T1, the movement of the hysteresis curve of the first transistor T1 may be suppressed or reduced.

[0125] Figure 4A is an enlarged plan view of a portion of a display area according to one or more embodiments of the present disclosure. Figure 4A The display area DP-DA is shown in an enlarged manner (see Figure 2A ) and illustrates a portion of the first area A1 and a pixel PX in the first area A1 (see Figure 2A ) arrangement.

[0126] Figure 4A The four first pixel rows PXL1 in the first area A1 are shown in an enlarged manner. k 、PXL1 k-1 、PXL1 k-2 and PXL1 k-3 . Reference Figure 4A , in the kth first pixel row PXL1 kIn one first pixel group PXU1, one 1-1 color pixel PX1r, two 2-1 color pixels PX1g, and one 3-1 color pixel PX1b may constitute one first pixel group PXU1. In one first pixel group PXU1, the 1-1 color pixel PX1r, the 2-1 color pixel PX1g, the 3-1 color pixel PX1b, and the 2-1 color pixel PX1g may be arranged along the first direction DR1.

[0127] The 1-1st color pixel PX1r, the 2-1st color pixel PX1g, and the 3-1st color pixel PX1b may include pixel circuits PC1r, PC1g, and PC1b and light emitting elements LD1r, LD1g, and LD1b, respectively. Figure 4A In FIG. 1 , the pixel circuits PC1r, PC1g, and PC1b are shown by dotted lines. Figure 4A A region of the anode of each of the light emitting elements LD1r, LD1g, and LD1b exposed by a light emitting opening to be described is shown. Portions of the anodes of the light emitting elements LD1r, LD1g, and LD1b exposed by a light emitting opening to be described may be defined as a light emitting region, and the light emitting region may correspond to a region in which light beams provided from the light emitting elements LD1r, LD1g, and LD1b are emitted.

[0128] The 1-1 color pixel PX1r may include a 1-1 pixel circuit PC1r and a 1-1 light emitting element LD1r, and the 1-1 light emitting element LD1r may be configured to emit a light beam having a first color to a first light emitting area. The 2-1 color pixel PX1g may include a 2-1 pixel circuit PC1g and a 2-1 light emitting element LD1g, and the 2-1 light emitting element LD1g may be configured to emit a light beam having a second color different from the first color to a second light emitting area. The 3-1 color pixel PX1b may include a 3-1 pixel circuit PC1b and a 3-1 light emitting element LD1b, and the 3-1 light emitting element LD1b may be configured to emit a light beam having a third color different from the first color and the second color to a third light emitting area. In one or more embodiments, the light beam having the first color may be a red light beam, the light beam having the second color may be a green light beam, and the light beam having the third color may be a blue light beam.

[0129] In one first pixel group PXU1 , a 1-1th pixel circuit PC1 r , a 2-1th pixel circuit PC1 g , a 3-1th pixel circuit PC1 b , and a 2-1th pixel circuit PC1 g may be arranged side by side along the first direction DR1 .

[0130] In one first pixel group PXU1, the 1-1st light emitting element LD1r and the 3-1st light emitting element LD1b may be spaced apart from each other in the first direction DR1, and the two 2-1st light emitting elements LD1g may be spaced apart from each other in the first direction DR1. In one first pixel group PXU1, the two 2-1st light emitting elements LD1g may be spaced apart from the 1-1st light emitting element LD1r and the 3-1st light emitting element LD1b in the fourth direction DR4. The fourth direction DR4 (e.g., an oblique line direction) may be a direction crossing the first direction DR1 and the second direction DR2 on a plane defined by the first direction DR1 and the second direction DR2.

[0131] In the kth first pixel row PXL1 k In the embodiment, the first pixel groups PXU1 may be repeatedly arranged along the first direction DR1. k-1 , k-2 first pixel row PXL1 k-2 and the k-3 first pixel row PXL1 k-3 In the embodiment, the first pixel groups PXU1 may also be repeatedly arranged along the first direction DR1.

[0132] kth first pixel row PXL1 k The first pixel group PXU1 and the k-2 first pixel row PXL1 k-2 The first pixel groups PXU1 may be repeatedly arranged along the second direction DR2. In one or more embodiments, in the k-1th first pixel row PXL1 k-1 and the k-3 first pixel row PXL1 k-3 In the k-th pixel row PXL1 k and the k-2 first pixel row PXL1 k-2 In contrast, the first pixel group PXU1 may be partially shifted in the first direction DR1. Therefore, the 1-1th light emitting element LD1r and the 3-1th light emitting element LD1b may be alternately arranged along the second direction DR2.

[0133] Figure 4B is an enlarged plan view of a portion of a display area according to one or more embodiments of the present disclosure. Figure 4B The display area DP-DA is shown in an enlarged manner (see Figure 2A ) and shows a portion of the second area A2, and a pixel PX in the second area A2 (see Figure 2A ) arrangement.

[0134] Reference Figure 4BThe second area A2 may include an element area EA and a transmission area TA. In the second area A2, the element area EA and the transmission area TA may extend in the first direction DR1, and the element area EA and the transmission area TA may be alternately arranged along the second direction DR2.

[0135] The element area EA may be a region in which pixels PX (see Figure 2A ) is a region where the conductive material is patterned. The transmittance of the transmission area TA may be higher than the transmittance of the element area EA. In one or more embodiments, the element area EA may be formed by the lower light shielding pattern BLBP (see Figure 5B ) covers the entire ground.

[0136] As an example, Figure 4B Two element regions EA and two transmission regions TA are shown alternately arranged. One second pixel row may be provided in each of the two element regions EA. Thus, Figure 4B The two second pixel rows PXL2 are shown in an enlarged manner. h and PXL2 h-1 .

[0137] In the hth second pixel row PXL2 h In one second pixel group PXU2, the 1-2nd color pixel PX2r, the 2-2nd color pixel PX2g, the 3-2nd color pixel PX2b and the 2-2nd color pixel PX2g may be arranged along the first direction DR1.

[0138] The 1-2nd color pixel PX2r, the 2-2nd color pixel PX2g, and the 3-2nd color pixel PX2b may include pixel circuits PC2r, PC2g, and PC2b and light emitting elements LD2r, LD2g, and LD2b, respectively. Figure 4B , the pixel circuits PC2r, PC2g, and PC2b are shown by dotted lines. Figure 4B The region of the anode of each of the light emitting elements LD2r, LD2g, and LD2b exposed by the light emitting opening to be described is shown. The region of the anode of the light emitting elements LD2r, LD2g, and LD2b exposed by the light emitting opening to be described may be defined as a light emitting region, and the light emitting region may correspond to a region in which light beams provided from the light emitting elements LD2r, LD2g, and LD2b are emitted.

[0139] The 1-2nd color pixel PX2r may include a 1-2nd pixel circuit PC2r and a 1-2nd light emitting element LD2r, and the 1-2nd light emitting element LD2r may be configured to emit a light beam having a first color to a first light emitting region. The 2-2nd color pixel PX2g may include a 2-2nd pixel circuit PC2g and a 2-2nd light emitting element LD2g, and the 2-2nd light emitting element LD2g may be configured to emit a light beam having a second color different from the first color to a second light emitting region. The 3-2nd color pixel PX2b may include a 3-2nd pixel circuit PC2b and a 3-2nd light emitting element LD2b, and the 3-2nd light emitting element LD2b may be configured to emit a light beam having a third color different from the first color and the second color to a third light emitting region.

[0140] In one second pixel group PXU2 , the 1-2 nd pixel circuit PC2 r , the 2-2 nd pixel circuit PC2 g , the 3-2 nd pixel circuit PC2 b , and the 2-2 nd pixel circuit PC2 g may be arranged side by side along the first direction DR1 .

[0141] In one second pixel group PXU2, the 1-2nd light emitting element LD2r and the 3-2nd light emitting element LD2b may be spaced apart from each other in the first direction DR1. One of the two 2-2nd light emitting elements LD2g may be spaced apart from the 1-2nd light emitting element LD2r in the fifth direction DR5 (e.g., the oblique direction). The fifth direction DR5 may be a direction intersecting the first direction DR1, the second direction DR2, and the fourth direction DR4 on a plane defined by the first direction DR1 and the second direction DR2. The other of the two 2-2nd light emitting elements LD2g may be spaced apart from the 3-2nd light emitting element LD2b in the fourth direction DR4. The two 2-2nd light emitting elements LD2g may be spaced apart (e.g., separated) from each other in the fourth direction DR4, with the 3-2nd light emitting element LD2b disposed therebetween.

[0142] In the hth second pixel row PXL2 h In the h-1th second pixel row PXL2, the second pixel groups PXU2 may be arranged repeatedly with each other along the first direction DR1. h-1 In the embodiment, the second pixel groups PXU2 may be repeatedly arranged with each other along the first direction DR1.

[0143] Refer to Figure 4A and Figure 4B, the pixel arrangement in the second area A2 may be formed by removing some pixels from the pixel arrangement in the first area A1. Therefore, the second area A2 may have a transmittance higher than the transmittance of the first area A1. In one or more embodiments of the present disclosure, the pixel arrangement in the second area A2 may be formed by removing some pixels from first pixel rows adjacent to each other in the first area A1 (hereinafter, based on the kth first pixel row PXL1 k and the k-1th first pixel row PXL1 k-1 for description).

[0144] The arrangement of the pixel circuits in the second area A2 may be selected as the kth first pixel row PXL1 k In other words, the pixel circuit in the k-1 first pixel row PXL1 can be k-1 The arrangement of the pixel circuits in the second area A2 is obtained by removing the pixel circuits. The second pixel row PXL2 is arranged in the hth pixel row. h The arrangement of the 1-2nd pixel circuit PC2r, the 2-2nd pixel circuit PC2g and the 2-3rd pixel circuit PC2b in the k-th first pixel row PXL1k may be the same as the arrangement of the 1-1st pixel circuit PC1r, the 2-1st pixel circuit PC1g and the 3-1st pixel circuit PC1b arranged in the k-th first pixel row PXL1k.

[0145] The arrangement of the light emitting elements in the second area A2 may be selected as the kth first pixel row PXL1 k Some of the light emitting elements in the k-1 first pixel row PXL1 k-1 For example, in the hth second pixel row PXL2 h In the arrangement of the light emitting elements, the kth first pixel row PXL1 may be selected k Some of the 1-1th light emitting element LD1r, the 3-1th light emitting element LD1b, and the 2-1th light emitting element LD1g, and the k-1th first pixel row PXL1 may be selected. k-1 In other words, some of the 2-1st light emitting elements LD1g are removed. k Some of the 2-1st light emitting elements LD1g are removed, and the k-1th first pixel row PXL1 is removed. k-1 Some of the 2-1st light emitting element LD1g, the 1-1st light emitting element LD1r, and the 3-1st light emitting element LD1b.

[0146] The hth second pixel row PXL2 h The 2-2 luminescent element LD2g in the k-th first pixel row PXL1 can be connected to the k-th first pixel row PXL1. k The selected 2-1st light emitting element LD1g and the first pixel row PXL1 from the k-1th pixel rowk-1 The k-th first pixel row PXL1 may be repeated in units of one pixel group. k The selection and removal of the 2-1st light emitting element LD1g in the k-1th first pixel row PXL1 may also be repeated in units of one pixel group. k-1 Selection and removal of the 2-1st light emitting element LD1g.

[0147] In one or more embodiments, the side light-shielding pattern SLBP may be disposed in the second area A2. The side light-shielding pattern SLBP may be disposed inside the element area EA.

[0148] The side light shielding pattern SLBP may include a first side pattern SLBP1 and a second side pattern SLBP2. Each of the first side pattern SLBP1 and the second side pattern SLBP2 may extend in the first direction DR1. The first side pattern SLBP1 and the second side pattern SLBP2 may be spaced apart from each other in the second direction DR2 and arranged in the h-th second pixel row PXL2. h Each of the first side pattern SLBP1 and the second side pattern SLBP2 may be arranged along the h-th second pixel row PXL2. h The pixel circuits PC2r, PC2g and PC2b in the embodiment extend continuously.

[0149] A plurality of side light shielding patterns SLBP may be provided and arranged in each of the element areas EA. Figure 4B As shown in FIG. 1 , the side light shielding pattern SLBP may also be provided in which the h-1 second pixel row PXL2 is provided. h-1 Inside the component area EA.

[0150] From the electronic module 400 (see Figure 2A ) may be provided to the transmission area TA and reflected and / or transmitted toward the element area EA. However, according to the present disclosure, the side light shielding pattern SLBP may be used to limit, prevent or reduce the transmission of the light beam LT (eg, infrared light beam) emitted from the electronic module 400 (see Figure 2A ) is introduced into the pixel circuits PC2r, PC2g and PC2b in the second pixel row. This will be described in detail.

[0151] In one or more embodiments, Figure 4A and Figure 4B 2 shows an example arrangement form of the pixel circuit and the light emitting area, but the present disclosure is not limited thereto, and the pixel circuit and the light emitting area may be arranged in one or more suitable forms. Figure 4AThe pixel circuit and the light emitting area are arranged in a form part to obtain Figure 4B The arrangement of the pixel circuit and the light emitting area is described in detail, but the present disclosure is not limited thereto. For example, the pixel circuit and the light emitting area may be arranged independently of each other. Figure 4A The arrangement of the pixel circuit and the light emitting area and Figure 4B The arrangement of pixel circuits and light-emitting areas.

[0152] Figure 5A is a cross-sectional view illustrating a first region of a display panel according to one or more embodiments of the present disclosure. Figure 5B is a cross-sectional view showing a second region of a display panel according to one or more embodiments of the present disclosure. Figures 1 to 4B The same / similar components described in the accompanying drawings will be described below, and repeated descriptions thereof will not be provided.

[0153] Reference Figure 5A and Figure 5B , the display panel 310 according to one or more embodiments may include a base layer 311 , a barrier layer BRL, a lower light blocking pattern BLBP, a buffer layer BFL, a circuit layer 312 , a light emitting element layer 313 , and an encapsulation layer 314 .

[0154] In one or more embodiments of the present disclosure, it can be seen that the first area A1 and the element area EA and the transmission area TA included in the second area A2 are defined in the base layer 311, and in this case, it can be seen that the components arranged on the base layer 311 are arranged to overlap with the first area A1, the element area EA and / or the transmission area TA.

[0155] The barrier layer BRL may be disposed on the base layer 311. The barrier layer BRL may include an inorganic material. For example, the barrier layer BRL may include at least one of silicon oxide, aluminum oxide, titanium oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0156] In one or more embodiments, Figure 5B As shown in , the lower light shielding pattern BLBP may be disposed in the element area EA of the second area A2. The lower light shielding pattern BLBP may overlap with the element area EA of the second area A2, and may not overlap with at least a portion of the transmission area TA. In one or more embodiments, the lower light shielding pattern BLBP may be disposed to entirely overlap with the element area EA.

[0157] The lower light shielding pattern BLBP may be disposed on the barrier layer BRL so that the problem of visually recognizing the conductive material disposed on the base layer 311 and the barrier layer BRL in the element area EA by an external light beam may be solved. Figure 2A ) is set in the display area DA (see Figure 1 ) inside, since the interference with the conductive material arranged on the base layer 311 and the barrier layer BRL is reduced or minimized, the electronic module 400 (see Figure 2A ) has improved performance of the electronic device 1000 (see Figure 1 ).

[0158] In addition, the lower light blocking pattern BLBP can prevent or reduce the light from entering the electronic module 400 (see FIG. Figure 2A ) emits a light beam (eg, an infrared light beam) reaching the transistors arranged on the base layer 311 and the blocking layer BRL.

[0159] Figure 5A is an example showing that the lower light blocking pattern BLBP is not disposed in the first area A1, but the lower light blocking pattern BLBP may be disposed inside the first area A1. In one or more embodiments, the lower light blocking pattern BLBP may entirely overlap the first area A1 and / or may overlap at least some transistors.

[0160] The buffer layer BFL may be disposed on the barrier layer BRL and the lower light shielding pattern BLBP. The buffer layer BFL may prevent or reduce diffusion of metal atoms or impurities from the base layer 311 to the semiconductor pattern. In addition, the buffer layer BFL may adjust a heat supply rate during a crystallization process for forming a semiconductor pattern so that the semiconductor pattern may be uniformly formed.

[0161] The buffer layer BFL may include a plurality of inorganic layers. For example, the buffer layer BFL may include a first sub-buffer layer including silicon nitride and a second sub-buffer layer disposed on the first sub-buffer layer and including silicon oxide. The buffer layer BFL may be referred to as a lower insulating layer.

[0162] The circuit layer 312 may be disposed on the buffer layer BFL, and the light emitting element layer 313 may be disposed on the circuit layer 312 .

[0163] Figure 5A 1 is a cross-sectional view of a portion of a light emitting element (hereinafter, referred to as a first light emitting element LD- 1 ) and a pixel circuit (hereinafter, referred to as a first pixel circuit PC- 1 ) arranged in the first area A1 . Figure 5A The first light emitting element LD-1 and the first pixel circuit PC-1 can be connected with Figure 4A The light emitting element and the pixel circuit of any one of the 1-1st color pixel PX1r, the 2-1st color pixel PX1g, and the 3-1st color pixel PX1b correspond.

[0164] Figure 5B 1 is a cross-sectional view of part of a light emitting element (hereinafter, referred to as a second light emitting element LD- 2 ) and a pixel circuit (hereinafter, referred to as a second pixel circuit PC- 2 ) arranged in the second area A2 . Figure 5B The second light emitting element LD-2 and the second pixel circuit PC-2 can be connected with Figure 4B The light emitting element and the pixel circuit of any one of the 1-2nd color pixel PX2r, the 2-2nd color pixel PX2g, and the 3-2nd color pixel PX2b correspond.

[0165] As an example, Figure 5A A first type (or first class) transistor TFT1a and a second type (or second class) transistor TFT2a of the first pixel circuit PC-1 are shown. Figure 5B The first type (or first class) transistor TFT1b and the second type (or second class) transistor TFT2b of the second pixel circuit PC-2 are shown. In one or more embodiments, the first type (or first class) transistors TFT1a and TFT1b may be silicon thin film transistors, and the second type (or second class) transistors TFT2a and TFT2b may be oxide thin film transistors. The first type (or first class) thin film transistors TFT1a and TFT1b may be Figure 3B In one or more embodiments, the first type (or first type) transistors TFT1a and TFT1b and the second type (or second type) transistors TFT2a and TFT2b may be arranged in different layers.

[0166] A semiconductor pattern of first type (or first class) transistors TFT1a and TFT1b (hereinafter, referred to as a first semiconductor pattern ACT1) may be arranged on the buffer layer BFL. The first semiconductor pattern ACT1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon and / or polycrystalline silicon, etc. For example, the first semiconductor pattern ACT1 may include low temperature polycrystalline silicon.

[0167] Figure 5A and Figure 5B Only a portion of the first semiconductor pattern ACT1 disposed on the buffer layer BFL is shown, and the first semiconductor pattern ACT1 may be further disposed in another region. The first semiconductor pattern ACT1 may span across the pixel PX (see FIG. Figure 2A) are arranged in a specific arrangement (e.g., a rule). Depending on whether the first semiconductor pattern ACT1 is doped, the first semiconductor pattern ACT1 may have different electrical characteristics. The first semiconductor pattern ACT1 may include a first region having a higher conductivity and a second region having a lower conductivity. The first region may be doped with an N-type (or N-type) dopant or a P-type (or P-type) dopant. A P-type (or P-type) transistor may include a doped region doped with a P-type (or P-type) dopant, and an N-type (or N-type) transistor may include a doped region doped with an N-type (or N-type) dopant. The second region may be a non-doped region, or may be a region doped with a concentration lower than that of the first region.

[0168] The conductivity of the first region is greater than that of the second region, and the first region can be basically used as an electrode or a signal line. The second region can basically correspond to the active region (or channel) of the first type (or first class) transistors TFT1a and TFT1b. In other words, a portion of the first semiconductor pattern ACT1 can be the active region of the first type (or first class) transistors TFT1a and TFT1b, another portion thereof can be the source region or drain region of the first type (or first class) transistors TFT1a and TFT1b, and yet another portion thereof can be a connection electrode or a connection signal line.

[0169] The source region S1, active region AC1, and drain region D1 of the first type (or first class) transistors TFT1a and TFT1b may be formed by the first semiconductor pattern ACT1. The source region S1 and the drain region D1 may extend in opposite directions from the active region AC1 in cross section.

[0170] The connection signal line SCL may be disposed on the buffer layer BFL. The connection signal line SCL may be connected to the sixth transistor T6 (see FIG. Figure 3B ) of the drain area.

[0171] The circuit layer 312 may include a plurality of inorganic layers and a plurality of organic layers. In one or more embodiments, the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 sequentially stacked on the buffer layer BFL may be inorganic layers, and the sixth insulating layer 60 and the seventh insulating layer 70 may be organic layers.

[0172] The first insulating layer 10 may be disposed on the buffer layer BFL and the first semiconductor pattern ACT1. The first insulating layer 10 may cover the first semiconductor pattern ACT1. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In one or more embodiments, the first insulating layer 10 may be a single-layer silicon oxide layer. The insulating layer to be described of the circuit layer 312 and the first insulating layer 10 may have a single-layer structure or a multi-layer structure.

[0173] The gate electrodes of the first type (or first class) transistors TFT1a and TFT1b (hereinafter, referred to as the first gate electrode GE1) may be arranged on the first insulating layer 10. The first gate electrode GE1 may be a part of the metal pattern. The first gate electrode GE1 overlaps the active region AC1 in the third direction DR3. In the process of doping the first semiconductor pattern ACT1, the first gate electrode GE1 may be used as a mask. The first gate electrode GE1 may include titanium, silver, an alloy containing silver, molybdenum, an alloy containing molybdenum, aluminum, an alloy containing aluminum, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide, and / or indium zinc oxide, but the present disclosure is not particularly limited thereto.

[0174] In one or more embodiments, the first semiconductor pattern ACT1 and the first gate electrode GE1 of the first type (or first class) transistor TFT1b in the second area A2 may be arranged to overlap with the lower light shielding pattern BLBP on a plane. Therefore, the light from the electronic module 400 (see Figure 2A ) introduced into the lower side of the second pixel circuit PC-2 reaches the first type (or first class) transistor TFT1b.

[0175] The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the first gate electrode GE1. The second insulating layer 20 may be an inorganic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In one or more embodiments, the second insulating layer 20 may have a single-layer structure including a silicon nitride layer.

[0176] The upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap the first gate electrode GE1 in the third direction DR3 (eg, in a plan view). The upper electrode UE may be a portion of a metal pattern, or may be a portion of a doped semiconductor pattern. A portion of the first gate electrode GE1 and the upper electrode UE overlapping the portion of the first gate electrode GE1 may define a capacitor Cst (see Figure 3B ).

[0177] The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the upper electrode UE. The third insulating layer 30 may be an inorganic layer and may have a single layer structure or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0178] The semiconductor pattern (hereinafter referred to as the second semiconductor pattern ACT2) of the second type (or second class) transistor TFT2a and TFT2b may be arranged on the third insulating layer 30. The second semiconductor pattern ACT2 may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions classified according to whether the metal oxide is reduced. The region in which the metal oxide is reduced (hereinafter referred to as the reduction region) has a higher conductivity than the region in which the metal oxide is not reduced (hereinafter referred to as the non-reduction region). The reduction region is basically used as the source / drain region or signal line of the second type (or second class) transistor TFT2a and TFT2b. The non-reduction region basically corresponds to the active region (or semiconductor region or channel) of the second type (or second class) transistor TFT2a and TFT2b. In other words, a portion of the second semiconductor pattern ACT2 may be the active region of the second type (or second class) transistor TFT2a and TFT2b, another portion thereof may be the source / drain region of the second type (or second class) transistor TFT2a and TFT2b, and another portion thereof may be the signal transmission region.

[0179] The source region S2, active region AC2, and drain region D2 of the second type (or second class) transistors TFT2a and TFT2b may be formed by the second semiconductor pattern ACT2. The source region S2 and the drain region D2 may extend in opposite directions from the active region AC2 in cross section.

[0180] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may cover the second semiconductor pattern ACT2. The fourth insulating layer 40 may be an inorganic layer and may have a single-layer structure or a multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In one or more embodiments, the fourth insulating layer 40 may have a single-layer structure including silicon oxide.

[0181] The gate electrodes of the second type (or second class) transistors TFT2a and TFT2b (hereinafter, referred to as the second gate electrode GE2) may be arranged on the fourth insulating layer 40. The second gate electrode GE2 may be a part of the metal pattern. The second gate electrode GE2 overlaps the active region AC2 in the third direction DR3. In the process of doping the second semiconductor pattern ACT2, the second gate electrode GE2 may be used as a mask.

[0182] In one or more embodiments, the second semiconductor pattern ACT2 and the second gate electrode GE2 of the second type (or second class) transistor TFT2b in the second region A2 may be arranged to overlap with the lower light shielding pattern BLBP on a plane. Therefore, the light from the electronic module 400 (see Figure 2A ) emitted and introduced into the lower side of the second pixel circuit PC-2 reaches the second type (or second class) transistor TFT2b.

[0183] In one or more embodiments, the second type (or second class) transistor TFT2b may be referred to as an additional transistor, the second semiconductor pattern ACT2 may be referred to as an additional semiconductor pattern, and the second gate electrode GE2 may be referred to as an additional gate electrode.

[0184] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second gate electrode GE2. The fifth insulating layer 50 may be an inorganic layer and / or an organic layer and may have a single layer structure or a multilayer structure. For example, the fifth insulating layer 50 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer.

[0185] The first connection electrode CNE1 and the second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CH1 passing through the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the second semiconductor pattern ACT2 through a contact hole CH2 passing through the fourth insulating layer 40 and the fifth insulating layer 50.

[0186] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover the first and second connection electrodes CNE1 and CNE2. The sixth insulating layer 60 may be an organic material.

[0187] The third connection electrode (or upper connection electrode) CNE3 may be disposed on the sixth insulating layer 60. The third connection electrode CNE3 may be connected to the first connection electrode CNE1 through a contact hole CH3 passing through the sixth insulating layer 60.

[0188] The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 to cover the third connection electrode CNE3. The seventh insulating layer 70 may be an organic material. For example, each of the sixth insulating layer 60 and the seventh insulating layer 70 may include a general polymer (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), and polystyrene (PS)), a polymer derivative having a phenol group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a paraxylene-based polymer, a vinyl alcohol-based polymer, and / or a blend thereof.

[0189] A light emitting element layer 313 including a first light emitting element LD-1 and a second light emitting element LD-2 may be disposed on the circuit layer 312. Each of the first light emitting element LD-1 and the second light emitting element LD-2 may include a pixel electrode (or anode) AE, a first functional layer HFL, a light emitting layer EL, a second functional layer EFL, and a common electrode (or cathode) CE. Figure 2A ) A first functional layer HFL, a second functional layer EFL and a common electrode CE are provided together.

[0190] The pixel electrode AE ​​may be disposed on the seventh insulating layer 70. The pixel electrode AE ​​may be connected to the third connection electrode CNE3 through the contact hole CH4 passing through the seventh insulating layer 70. The pixel electrode AE ​​may be a transmissive (semi-transmissive) electrode or a reflective electrode. In one or more embodiments, the pixel electrode AE ​​may include a reflective layer formed of silver, magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, chromium and / or a compound or mixture thereof and / or a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxide, indium oxide and aluminum-doped zinc oxide. For example, the pixel electrode AE ​​may include a multilayer structure in which indium tin oxide, silver and / or indium tin oxide are sequentially stacked.

[0191] The pixel defining film PDL may be disposed on the seventh insulating layer 70. Light emitting openings P1-OP and P2-OP that expose portions of the pixel electrode AE ​​may be defined in the pixel defining film PDL. The pixel defining film PDL may cover edges of the pixel electrode AE. Light emitting regions PXA1 and PXA2 may be defined by the light emitting openings P1-OP and P2-OP defined in the pixel defining film PDL. For example, the first light emitting region PXA1 may be defined relative to the first light emitting element LD-1, and the second light emitting region PXA2 may be defined relative to the second light emitting element LD-2.

[0192] The pixel defining film PDL may have a characteristic of absorbing light beams, for example, the pixel defining film PDL may have a black color. The pixel defining film PDL may include a black colorant. The black colorant may include a black dye and / or a black pigment. The black colorant may include carbon black, a metal such as chromium, and / or an oxide thereof.

[0193] The first functional layer HFL may be disposed on the pixel electrode AE ​​and the pixel definition layer PDL. The first functional layer HFL may include a hole transport layer, a hole injection layer, or both a hole transport layer and a hole injection layer (e.g., a hole transport layer and a hole injection layer at the same time). The first functional layer HFL may be disposed throughout the first area A1 and the second area A2.

[0194] The light emitting layer EL may be disposed on the first functional layer HFL and may be disposed in an area corresponding to the light emitting openings P1-OP and P2-OP of the pixel defining film PDL. The light emitting layer EL may include an organic material, an inorganic material, and / or an organic / inorganic material configured to emit a light beam having a suitable color (e.g., a set or predetermined color). The light emitting layer EL may be disposed in the first area A1 and the second area A2. The light emitting layer EL disposed in the second area A2 may be disposed in an area spaced apart from the transmission area TA (i.e., in the element area EA).

[0195] The second functional layer EFL may be disposed on the light emitting layer EL and cover the light emitting layer EL. The second functional layer EFL may include an electron transport layer, an electron injection layer, or both the electron transport layer and the electron injection layer (e.g., including both the electron transport layer and the electron injection layer). The second functional layer EFL may be disposed throughout the first region A1 and the second region A2.

[0196] The common electrode CE may be disposed on the second functional layer EFL. The common electrode CE may be commonly disposed in a plurality of pixels PX (see Figure 2A )middle.

[0197] The encapsulation layer 314 may be disposed on the light emitting element layer 313. The encapsulation layer 314 may include an inorganic layer 81, an organic layer 82, and an inorganic layer 83 sequentially stacked, and the layers constituting the encapsulation layer 314 are not limited thereto.

[0198] The inorganic layers 81 and 83 may protect the light emitting element layer 313 from moisture and oxygen, and the organic layer 82 may protect the light emitting element layer 313 from foreign matter such as dust particles. The inorganic layers 81 and 83 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer, etc. The organic layer 82 may include an acrylic organic layer, but the present disclosure is not limited thereto.

[0199] The transmission area TA of the second region A2 may be defined as a region in which a conductive material or an insulating layer is patterned or not deposited to improve light transmittance.

[0200] In one or more embodiments, among the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, the sixth insulating layer 60, and the seventh insulating layer 70, the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the seventh insulating layer 70 may be arranged not to be deposited in the transmission area TA or to be patterned and removed after deposition. Therefore, the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the seventh insulating layer 70 arranged inside the second area A2 may not overlap with the transmission area TA.

[0201] The lower light blocking pattern BLBP may not overlap at least a portion of the transmission area TA. Figure 5B A cross section of a portion of the lower light-shielding pattern BLBP in which the opening B-OP overlapping the transmission area TA is defined is shown, but in one or more embodiments of the present disclosure, the portion of the lower light-shielding pattern BLBP may extend across the transmission area TA. In this case, the lower light-shielding pattern BLBP may have an entire integrated pattern within the second area A2.

[0202] A side surface of the lower light-shielding pattern BLBP defining the opening B-OP may be covered by the unpatterned buffer layer BFL. The barrier layer BRL exposed through the opening B-OP of the lower light-shielding pattern BLBP may also be covered by the buffer layer BFL.

[0203] In addition, in the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50, the transmission opening IL-OP may be defined by a side surface formed by patterning, and the side surface defining the transmission opening IL-OP may be covered by an unpatterned sixth insulating layer 60 among the organic insulating layers.

[0204] In addition, the common electrode CE among the components of the second light-emitting element LD-2 may also be arranged not to be deposited in the transmission area TA or to be patterned and removed after deposition. In one or more embodiments, when forming the opening CE-OP of the common electrode CE, the lower light-shielding pattern BLBP may be used as a mask. For example, a light beam irradiated toward the common electrode CE from the rear surface of the base layer 311 may pass through the opening B-OP of the lower light-shielding pattern BLBP and reach a portion of the common electrode CE. For example, the portion of the common electrode CE may be removed by the light beam passing through the opening B-OP of the lower light-shielding pattern BLBP. The light beam may be a laser beam. In this case, the lower light-shielding pattern BLBP may prevent or protect the components arranged on the lower light-shielding pattern BLBP from being damaged by the laser beam.

[0205] According to one or more embodiments, the first functional layer HFL and the second functional layer EFL may not be patterned and may be disposed to overlap the transmission area TA In this case, a side surface of the opening CE-OP defining the common electrode CE may be covered by the second functional layer EFL.

[0206] In one or more embodiments, the base layer portion 311-P, the blocking layer portion BRL-P, the buffer layer portion BFL-P, the sixth insulating layer portion 60-P, the first functional portion HFL-P, the second functional portion EFL-P, the first inorganic portion 81-P, the organic portion 82-P and the second inorganic portion 83-P may be arranged in the transmission area TA.

[0207] In order to compensate for the step difference between the insulating layers that are not deposited in the transmission area TA or are patterned after deposition, the regions of the organic layer 82 of the encapsulation layer 314 may have different thicknesses. For example, the thickness of the organic layer 82 overlapping the transmission area TA among the organic layers 82 may be greater than the maximum thickness of the organic layer 82 overlapping the first area A1 and the element area EA among the organic layers 82.

[0208] According to one or more embodiments of the present disclosure, the second region A2 may be a region having a higher light transmittance than that of the first region A1, and the transmissive area TA in the second region A2 may have the highest light transmittance.

[0209] In one or more embodiments, the side light shielding pattern SLBP may be disposed in the second area A2. The side light shielding pattern SLBP may be disposed on the fifth insulating layer 50 and covered by the sixth insulating layer 60. The side light shielding pattern SLBP may be disposed in the same layer (e.g., at the same layer) as the first connection electrode CNE1. In one or more embodiments, the side light shielding pattern SLBP may include the same material as that of the first connection electrode CNE1. The side light shielding pattern SLBP may be formed simultaneously (e.g., in parallel) in the process of forming the first connection electrode CNE1.

[0210] The side light-shielding pattern SLBP may be connected to the lower light-shielding pattern BLBP through a contact hole passing through the buffer layer BFL and an insulating layer disposed between the first semiconductor pattern ACT1 and the first connection electrode CNE1. In one or more embodiments, the side light-shielding pattern SLBP may contact the lower light-shielding pattern BLBP through a contact hole CH5 passing through the buffer layer BFL and the first, second, third, fourth, and fifth insulating layers 10, 20, 30, 40, and 50.

[0211] The side light-shielding pattern SLBP may include a first side pattern SLBP1 and a second side pattern SLBP2. The first side pattern SLBP1 and the second side pattern SLBP2 may be spaced apart (or face) from each other with the second pixel circuit PC-2 interposed therebetween.

[0212] The first side pattern SLBP1 and the second side pattern SLBP2 may include first portions P1-1 and P1-2 and second portions P2-1 and P2-2. The first portions P1-1 and P1-2 may be portions arranged on the fifth insulating layer 50, and the second portions P2-1 and P2-2 may be portions extending through the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 in the thickness direction (i.e., the third direction DR3). The first portions P1-1 and P1-2 may extend in one direction, and the second portions P2-1 and P2-2 may also extend in the one direction along the first portions P1-1 and P1-2. It will be described in detail.

[0213] In one or more embodiments, the side portions of the first semiconductor pattern ACT1 and the first gate electrode GE1 of the first type (or first class) transistor TFT1b in the second area A2 may be covered by the side shielding pattern SLBP. In addition, the side portions of the second semiconductor pattern ACT2 and the second gate electrode GE2 of the second type (or second class) transistor TFT2b in the second area A2 may be covered by the side shielding pattern SLBP. Therefore, the light from the electronic module 400 (see FIG. 4 ) may be prevented, reduced or limited. Figure 2A ) emitted by the first pixel circuit PC-2 and introduced into the lateral side thereof, reaches the first type (or first class) transistor TFT1b and the second type (or second class) transistor TFT2b.

[0214] In addition, from the electronic module 400 (see Figure 2A) may be transmitted along the buffer layer BFL including the inorganic layer and the first, second, third, fourth, and fifth insulating layers 10, 20, 30, 40, and 50. However, according to one or more embodiments, the light beam may be prevented, reduced, or limited from being transmitted to a portion in which the second pixel circuit PC-2 is disposed by the side light shielding pattern SLBP.

[0215] In one or more embodiments, the upper light shielding pattern ULBP may be disposed in the second area A2. The upper light shielding pattern ULBP may be disposed on the seventh insulating layer 70 and covered by the pixel defining film PDL. The upper light shielding pattern ULBP may be disposed on the same layer (e.g., at the same layer) as the pixel electrode AE. In one or more embodiments, the upper light shielding pattern ULBP may include the same material as the material of the pixel electrode AE. The upper light shielding pattern ULBP may be formed simultaneously (e.g., in parallel) in the process of forming the pixel electrode AE.

[0216] The opening U-OP may be defined in the upper light-shielding pattern ULBP. The pixel electrode AE ​​may be disposed inside the opening U-OP of the upper light-shielding pattern ULBP. For example, the pixel electrode AE ​​may be at least partially surrounded by the upper light-shielding pattern ULBP.

[0217] like Figure 5B As shown in , the upper portion of the second type (or second class) transistor TFT2b in the second region A2 (eg, the second semiconductor pattern ACT2 and the second gate electrode GE2) may be at least partially covered by the upper light shielding pattern ULBP. In addition, as an example, Figure 5B The first type (or first class) transistor TFT1b is shown to be arranged to overlap the pixel electrode AE ​​(for example, in the third direction DR3 or in a plan view), but a portion of the first type (or first class) transistor TFT1b may not overlap the pixel electrode AE. The upper portion of the first type (or first class) transistor TFT1b that does not overlap the pixel electrode AE ​​(for example, the first semiconductor pattern ACT1 and the first gate electrode GE1) may also be at least partially covered by the upper light shielding pattern ULBP.

[0218] From the electronic module 400 (see Figure 2A ) may be reflected by the common electrode CE and introduced into the upper side of the second pixel circuit PC-2. However, according to one or more embodiments, due to the upper light shielding pattern ULBP, the light beam reflected by the common electrode CE and introduced into the upper side of the second pixel circuit PC-2 may be prevented, reduced or restricted from reaching the first type (or first class) transistor TFT1b and the second type (or second class) transistor TFT2b.

[0219] Therefore, according to one or more embodiments of the present disclosure, the electronic module 400 (see Figure 2A ) can be set to match the display area DA (see Figure 1 ), and even when the transmission area TA is disposed adjacent to the element area EA, the transmission area TA can prevent, reduce or limit the transmission area from the electronic module 400 (see Figure 2A ) is introduced into the lower side, lateral side and upper side of the second pixel circuit PC-2. Therefore, damage to the transistor due to the infrared beam can be prevented or reduced, and changes in the characteristics of the transistor can be prevented or reduced. Therefore, leakage current (for example, off-leakage current flowing in a case where the transistor is turned off) can be prevented from being generated in the transistor, and thus the occurrence of abnormal light emission in the light-emitting element can be prevented, reduced or suppressed. Therefore, an electronic device 1000 with improved display quality can be provided (see Figure 1 ).

[0220] Fig. 6A is a plan view illustrating a portion of a lower light shielding pattern according to one or more embodiments of the present disclosure. Fig. 6A The second area A2 (see Figure 5B ) is a part of the lower light blocking pattern BLBP.

[0221] Reference Figure 5B and Fig. 6A , the lower light blocking pattern BLBP may be disposed between the barrier layer BRL and the buffer layer BFL. Fig. 6A In a second pixel group PXU2 (see Figure 4B ) The 1-2 pixel circuit PC2r, the 2-2 pixel circuit PC2g and the 3-2 pixel circuit PC2b are shown by dotted lines. All of the 1-2 pixel circuit PC2r, the 2-2 pixel circuit PC2g and the 3-2 pixel circuit PC2b may be arranged to overlap with the lower light shielding pattern BLBP on a plane.

[0222] For ease of description, Fig. 6A A portion of the lower light-shielding pattern BLBP in contact with the side light-shielding pattern SLBP is shown. The side light-shielding pattern SLBP may include a first side pattern SLBP1 and a second side pattern SLBP2. Second portions P2-1 and P2-2 of the first side pattern SLBP1 and the second side pattern SLBP2 may be in contact with the lower light-shielding pattern BLBP. Second portions P2-1 and P2-2 of the first side pattern SLBP1 and the second side pattern SLBP2 may extend in the first direction DR1.

[0223] On a plane (for example, in a second direction DR2 in a plan view), the second portion P2-1 of the first side pattern SLBP1 may be disposed on the upper side of the 1-2 pixel circuit PC2r, the 2-2 pixel circuit PC2g, and the 3-2 pixel circuit PC2b, and may be in contact with the lower light-shielding pattern BLBP on the upper side of the 1-2 pixel circuit PC2r, the 2-2 pixel circuit PC2g, and the 3-2 pixel circuit PC2b. On a plane (for example, in a plan view), the second portion P2-2 of the second side pattern SLBP2 may be disposed on the lower side of the 1-2 pixel circuit PC2r, the 2-2 pixel circuit PC2g, and the 3-2 pixel circuit PC2b, and may be in contact with the lower light-shielding pattern BLBP on the lower side of the 1-2 pixel circuit PC2r, the 2-2 pixel circuit PC2g, and the 3-2 pixel circuit PC2b. The first side pattern SLBP1 and the second side pattern SLBP2 may be used to prevent or reduce a light beam (for example, an infrared light beam) from being directed toward the element area EA (see Figure 4B ) adjacent to the transmissive region TA (see Figure 4B ) is introduced into the 2-1st pixel circuit PC2r, the 2-2nd pixel circuit PC2g and the 3-2nd pixel circuit PC2b.

[0224] FIG. 6B to FIG. 6H is a plan view showing one layer constituting a pixel circuit arranged in the second region according to one or more embodiments of the present disclosure. FIG. 6B to FIG. 6H The second area A2 (see Figure 5B ) of the circuit layer 312 (see Figure 5B ) is a plan view of the arrangement order of the conductive pattern and the semiconductor pattern included in the embodiment. The same / similar reference numerals are used for Figures 1 to 5B The same / similar components described in the accompanying drawings will be described below, and repeated descriptions thereof will not be provided.

[0225] FIG. 6B to FIG. 6H The second pixel group PXU2 (see FIG. Figure 4B ) The 1st-2nd pixel circuit PC2r (see Fig. 6A ), 2-2 pixel circuit PC2g (see Fig. 6A ), the 3-2 pixel circuit PC2b (see Fig. 6A ) and the 2-2 pixel circuit PC2g (see Fig. 6A ) are included in the components. For ease of description, FIG. 6B to FIG. 6G Each shows a circuit layer 312 (see Figure 5B ) of the side light shielding pattern SLBP of the insulating layer. The second portions P2-1 and P2-2 of the side light shielding pattern SLBP may pass through the circuit layer 312 (see Figure 5B ) insulation layer.

[0226] Reference Figure 5B and Figure 6B , the first semiconductor layer ACL1 may be disposed between the buffer layer BFL and the first insulating layer 10. The first semiconductor layer ACL1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon and / or polycrystalline silicon, etc. For example, the first semiconductor layer ACL1 may include low-temperature polycrystalline silicon. The first semiconductor layer ACL1 may include a 1-2 pixel circuit PC2r, a 2-2 pixel circuit PC2g, and a 3-2 pixel circuit PC2b (see Fig. 6A ) in the first semiconductor pattern ACT1.

[0227] On a plane (eg, in a plan view), the entire first semiconductor pattern ACT1 may overlap the lower light blocking pattern BLBP. Therefore, the light from the electronic module 400 (see FIG. 4 ) may be prevented, reduced, or limited. Figure 2A ) is introduced into the second pixel circuit PC-2 (see Figure 5B ) reaches the first semiconductor pattern ACT1.

[0228] Figure 6B The side light-shielding pattern SLBP shown in FIG. 4 may be a portion passing through the first insulating layer 10. In a cross section viewed in a direction perpendicular to an extending direction of the side light-shielding pattern SLBP, the entire first semiconductor pattern ACT1 may overlap the side light-shielding pattern SLBP.

[0229] In more detail, when viewed in the second direction DR2, the entire first semiconductor pattern ACT1 may overlap the first side pattern SLBP1 (e.g., the second portion P2-1). When viewed in a direction opposite to the second direction DR2, the entire first semiconductor pattern ACT1 may overlap the second side pattern SLBP2 (e.g., the second portion P2-2).

[0230] Therefore, it is possible to prevent, reduce or limit the electronic module 400 (see Figure 2A ) is introduced into the second pixel circuit PC-2 (see Figure 5B ) reaches the first semiconductor pattern ACT1.

[0231] Reference Figure 5B and Figure 6C , the first conductive layer CDL1 may be disposed between the first insulating layer 10 and the second insulating layer 20. The first conductive layer CDL1 may include a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material, etc. For example, the first conductive layer CDL1 may include silver, an alloy including silver, molybdenum, an alloy including molybdenum, aluminum, an alloy including aluminum, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide, and / or indium zinc oxide, etc., but the present disclosure is not particularly limited thereto.

[0232] The first conductive layer CDL1 may include a first conductive pattern C11, a second conductive pattern C12, a third conductive pattern C13, a fourth conductive pattern C14, and a fifth conductive pattern C15.

[0233] The first conductive pattern C11 may be Figure 5B The first gate electrode GE1 shown in FIG. 11 may be provided in an island shape. The first conductive pattern C11 is provided with the first semiconductor pattern ACT1 (see FIG. 11 ). Figure 6B ) together can constitute the first transistor T1.

[0234] The second conductive pattern C12 may be Figure 3B The second conductive pattern C12 is connected to the first semiconductor pattern ACT1 (see Figure 6B ) together can constitute the second transistor T2.

[0235] The third conductive pattern C13 may be Figure 3B The third conductive pattern C13 is connected to the first semiconductor pattern ACT1 (see Figure 6B ) together can constitute the fifth transistor T5 and the sixth transistor T6.

[0236] The fourth conductive pattern C14 may be Figure 3B The fourth conductive pattern C14 corresponds to the j-th black scanning line GBLj. Figure 6B ) together can constitute the seventh transistor T7 and the eighth transistor T8.

[0237] The fifth conductive pattern C15 may be a first initialization voltage VINT (see Figure 3B ) is supplied to its first initialization voltage line VL3 (see Figure 3B ) part.

[0238] Figure 6CThe side light shielding pattern SLBP shown in the figure may be a portion passing through the second insulating layer 20. In a cross section viewed in a direction perpendicular or orthogonal to the extending direction of the side light shielding pattern SLBP, all of the first transistor T1, the second transistor T2, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may overlap with the side light shielding pattern SLBP. In more detail, when viewed in the second direction DR2, each of the first transistor T1, the second transistor T2, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may overlap with the first side pattern SLBP1 (e.g., the second portion P2-1). When viewed in a direction opposite to the second direction DR2, each of the first transistor T1, the second transistor T2, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may overlap with the second side pattern SLBP2 (e.g., the second portion P2-2).

[0239] Therefore, it is possible to prevent, reduce or limit the electronic module 400 (see Figure 2A ) is introduced into the second pixel circuit PC-2 (see Figure 5B ) reaches the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. Therefore, the characteristic variation of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be prevented or reduced.

[0240] Reference Figure 5B and Fig.6D , the second conductive layer CDL2 may be disposed between the second insulating layer 20 and the third insulating layer 30. The second conductive layer CDL2 may include metal, alloy, conductive metal oxide and / or transparent conductive material, etc. For example, the second conductive layer CDL2 may have a single layer structure including molybdenum.

[0241] The second conductive layer CDL2 may include a first conductive pattern C21 , a second conductive pattern C22 , and a third conductive pattern C23 .

[0242] The first conductive pattern C21 may be connected to the first conductive layer CDL1 (see Figure 6C ) of the first conductive pattern C11 (see Figure 6C The first conductive pattern C21 overlaps with the first conductive pattern C11 (see Figure 6C ) together can form a capacitor Cst (see Figure 3B The first driving voltage ELVDD (see Figure 3B ) may be provided to the first conductive pattern C21.

[0243] The second conductive pattern C22 may be Figure 3B The third conductive pattern C23 may correspond to the j-th compensation scanning line GCLj. Figure 3B Corresponding to the j-th initialization scan line GILj.

[0244] Fig.6D The side light blocking pattern SLBP shown in illustrative figures may be a portion passing through the third insulating layer 30 .

[0245] Reference Figure 5B and Fig. 6E , the second semiconductor layer ACL2 may be disposed between the third insulating layer 30 and the fourth insulating layer 40. The second semiconductor layer ACL2 may include an oxide semiconductor. The second semiconductor layer ACL2 may include a second semiconductor pattern ACT2 included in the 1-2 pixel circuit PC2r, the 2-2 pixel circuit PC2g, and the 3-2 pixel circuit PC2b. The second semiconductor pattern ACT2 may be arranged at a different layer from the first semiconductor pattern ACT1, and the second semiconductor pattern ACT2 may not overlap the first semiconductor pattern ACT1.

[0246] In a plane, the entire second semiconductor pattern ACT2 may overlap the lower light blocking pattern BLBP (eg, in the third direction DR3 or in a plan view). Therefore, the light from the electronic module 400 (see FIG. 4 ) may be prevented, reduced, or limited. Figure 2A ) is introduced into the second pixel circuit PC-2 (see Figure 5B ) reaches the second semiconductor pattern ACT2.

[0247] Fig. 6E The side light-shielding pattern SLBP shown in FIG. 4 may be a portion passing through the fourth insulating layer 40. In a cross section viewed in a direction perpendicular to the extending direction of the side light-shielding pattern SLBP, the entire second semiconductor pattern ACT2 may overlap the side light-shielding pattern SLBP.

[0248] In more detail, when viewed in the second direction DR2, the entire second semiconductor pattern ACT2 may overlap the first side pattern SLBP1 (e.g., the second portion P2-1). When viewed in a direction opposite to the second direction DR2, the entire second semiconductor pattern ACT2 may overlap the second side pattern SLBP2 (e.g., the second portion P2-2).

[0249] Therefore, it is possible to prevent, reduce or limit the electronic module 400 (see Figure 2A ) is introduced into the second pixel circuit PC-2 (see Figure 5B ) reaches the second semiconductor pattern ACT2.

[0250] Reference Figure 5B and Fig. 6F , the third conductive layer CDL3 may be disposed between the fourth insulating layer 40 and the fifth insulating layer 50. The third conductive layer CDL3 may include a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material, etc. The third conductive layer CDL3 may have a multilayer structure in which titanium and molybdenum are sequentially stacked, but the present disclosure is not particularly limited thereto.

[0251] The third conductive layer CDL3 may include a first conductive pattern C31 , a second conductive pattern C32 , a third conductive pattern C33 , and a fourth conductive pattern C34 .

[0252] The first conductive pattern C31 may be Figure 3B The first conductive pattern C31 corresponds to the j-th compensation scanning line GCLj. Fig. 6E ) together can constitute a third transistor T3.

[0253] The second conductive pattern C32 may be Figure 3B The second conductive pattern C32 corresponds to the j-th initialization scan line GILj. Fig. 6E ) together can constitute the fourth transistor T4.

[0254] The third conductive pattern C33 may be a second initialization voltage VAINT (see Figure 3B ) is supplied to its second initialization voltage line VL4 (see Figure 3B According to one or more embodiments, the third conductive pattern C33 may be electrically connected to the 2-2 pixel circuit PC2g and the 3-2 pixel circuit PC2b (see Fig. 6A ), and to the 2-2 pixel circuit PC2g and the 3-2 pixel circuit PC2b (see Fig. 6A ) provides a second initialization voltage VAINT (see Figure 3B ).

[0255] The fourth conductive pattern C34 may be a bias voltage VOBS (see Figure 3B ) is supplied to its bias voltage line VL5 (see Figure 3B ) part.

[0256] Fig. 6FThe side light-shielding pattern SLBP shown in the figure may be a portion passing through the fifth insulating layer 50. In a cross section viewed in a direction perpendicular to the extending direction of the side light-shielding pattern SLBP, both the third transistor T3 and the fourth transistor T4 may overlap with the side light-shielding pattern SLBP. When viewed in the second direction DR2, both the third transistor T3 and the fourth transistor T4 (e.g., simultaneously) may overlap with the first side pattern SLBP1 (e.g., the second portion P2-1). When viewed in a direction opposite to the second direction DR2, both the third transistor T3 and the fourth transistor T4 (e.g., simultaneously) may overlap with the second side pattern SLBP2 (e.g., the second portion P2-2).

[0257] Therefore, it is possible to prevent, reduce or limit the electronic module 400 (see Figure 2A ) is introduced into the second pixel circuit PC-2 (see Figure 5B ) reaches the third transistor T3 and the fourth transistor T4. Therefore, the characteristic variation of the third transistor T3 and the fourth transistor T4 can be prevented or reduced.

[0258] Reference Figure 5B and Figure 6G , the fourth conductive layer CDL4 may be disposed between the fifth insulating layer 50 and the sixth insulating layer 60. The fourth conductive layer CDL4 may include a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material, etc. The fourth conductive layer CDL4 may have a multilayer structure in which titanium, aluminum, and titanium are sequentially stacked, but the present disclosure is not particularly limited thereto.

[0259] The fourth conductive layer CDL4 may include first conductive patterns C41, second conductive patterns C42, third conductive patterns C43, fourth conductive patterns C44, fifth conductive patterns C45, sixth conductive patterns C46, ​​seventh conductive patterns C47, eighth conductive patterns C48, ninth conductive patterns C49, and tenth conductive patterns C410, and first and second side patterns SLBP1 and SLBP2. The first conductive patterns C41, second conductive patterns C42, third conductive patterns C43, fourth conductive patterns C44, fifth conductive patterns C45, sixth conductive patterns C46, ​​seventh conductive patterns C47, eighth conductive patterns C48, ninth conductive patterns C49, and tenth conductive patterns C410 may be connection electrodes connected to one pattern or a plurality of patterns.

[0260] The first conductive pattern C41 may be connected to the second semiconductor pattern ACT2 (see Fig. 6E ) and the first conductive layer CDL1 (see Figure 6C ) of the fifth conductive pattern C15 (see Figure 6C The second conductive pattern C42 may be connected to the first semiconductor pattern ACT1 (see Figure 6BThe third conductive pattern C43 may be connected to the second semiconductor pattern ACT2 (see Fig. 6E ) and the first conductive layer CDL1 (see Figure 6C ) of the first conductive pattern C11 (see Figure 6C In one or more embodiments, the first conductive pattern C41 and the third conductive pattern C43 may be Figure 5B The fourth conductive pattern C44 may be connected to the first semiconductor pattern ACT1 (see Figure 6B ) and the second semiconductor pattern ACT2 (see Fig. 6E ).

[0261] The fifth conductive pattern C45 may be connected to the first semiconductor pattern ACT1 (see Figure 6B ) and the second conductive layer CDL2 (see Fig.6D ) of the first conductive pattern C21 (see Fig.6D The fifth conductive pattern C45 may be a first driving voltage ELVDD (see Figure 3B ) is supplied to its first driving voltage line VL1 (see Figure 3B ) part. The first driving voltage ELVDD (see Figure 3B ) can be provided to the first conductive pattern C21 through the fifth conductive pattern C45 (see Fig.6D ). The sixth conductive pattern C46 may be connected to the first semiconductor pattern ACT1 (see Figure 6B ).

[0262] The seventh conductive pattern C47 may be connected to the first semiconductor pattern ACT1 (see Figure 6B The seventh conductive pattern C47 may be a second initialization voltage VAINT (see Figure 3B ) is supplied to its second initialization voltage line VL4 (see Figure 3B ) part.

[0263] According to one or more embodiments, the seventh conductive pattern C47 may be electrically connected to the 2-2 th pixel circuit PC2g and provide the second initialization voltage VAINT (see FIG. 2 ) to the 2-2 th pixel circuit PC2g. Figure 3B ). The seventh conductive pattern C47 is connected to the first semiconductor pattern ACT1 thereof (see Figure 6B ) can be connected to the first semiconductor pattern ACT1 (see Figure 6B The second initialization voltage VAINT (see FIG. 1 ) is provided to the 1-2 pixel circuit PC2r and the 3-2 pixel circuit PC2b. Figure 3B ) and the second initialization voltage VAINT (see Figure 3B ) can be different from each other.

[0264] As an example, Fig. 6F and Figure 6G The first initialization voltage line VL3 (see FIG. 1 ) connected to the 1-2 pixel circuit PC2r and the 3-2 pixel circuit PC2b is shown. Figure 3B ) and the first initialization voltage line VL3 (see Figure 3B ) are separated from each other to provide first initialization voltages VINT with different levels (see Figure 3B ), but the present disclosure is not limited thereto. For example, the 1-2 pixel circuit PC2r, the 2-2 pixel circuit PC2g, and the 3-2 pixel circuit PC2b may be connected to the same first initialization voltage line VL3 (see Figure 3B ), and a first initialization voltage VINT having the same level may be applied (see Figure 3B ).

[0265] The eighth conductive pattern C48 may be connected to the first semiconductor pattern ACT1 (see Figure 6B In one or more embodiments, the eighth conductive pattern C48 may be Figure 5B Corresponding to the first connection electrode CNE1 in.

[0266] The ninth conductive pattern C49 may be connected to the first semiconductor pattern ACT1 (see Figure 6B ) and the third conductive layer CDL3 (see Fig. 6F ) of the fourth conductive pattern C34 (see Fig. 6F ). The ninth conductive pattern C49 may connect the first semiconductor pattern ACT1 (see Figure 6B ) and the bias voltage VOBS (see Figure 3B ) is supplied to its bias voltage line VL5 (see Figure 3B )Electrical connection.

[0267] The tenth conductive pattern C410 may be connected to the first semiconductor pattern ACT1 (see Figure 6B ) and the third conductive layer CDL3 (see Fig. 6F ) of the fourth conductive pattern C34 (see Fig. 6F ). The tenth conductive pattern C410 may connect the first semiconductor pattern ACT1 (see Figure 6B ) and the second initialization voltage VAINT (see Figure 3B ) is supplied to its second initialization voltage line VL4 (see Figure 3B )Electrical connection.

[0268] Figure 6GThe side light shielding pattern SLBP shown in the figure may be the first portions P1-1 and P1-2. The first portions P1-1 and P1-2 of the first side pattern SLBP1 and the second side pattern SLBP2 may extend in the first direction DR1. On a plane, the first portion P1-1 of the first side pattern SLBP1 and the first portion P1-2 of the second side pattern SLBP2 may be spaced apart from each other in the second direction DR2, with the first conductive pattern C41 to the tenth conductive pattern C410 arranged in one second pixel row interposed therebetween.

[0269] Figure 6G A portion where the side light-shielding pattern SLBP contacts the lower light-shielding pattern BLBP is shown together. The portion of the side light-shielding pattern SLBP that contacts the lower light-shielding pattern BLBP may correspond to the second portions P2-1 and P2-2. The second portion P2-1 of the first side pattern SLBP1 may extend in the first direction DR1 along the first portion P1-1 of the first side pattern SLBP1. The second portion P2-2 of the second side pattern SLBP2 may extend in the first direction DR1 along the first portion P1-2 of the second side pattern SLBP2.

[0270] Reference Figure 5B and Figure 6H , the fifth conductive layer CDL5 may be disposed between the sixth insulating layer 60 and the seventh insulating layer 70. The fifth conductive layer CDL5 may include a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material, etc. The fifth conductive layer CDL5 may have a multilayer structure in which titanium, aluminum, and / or titanium are sequentially stacked, but the present disclosure is not particularly limited thereto.

[0271] The fifth conductive layer CDL5 may include first, second, third, and fourth conductive patterns C51, C52, C53, and C54. The first, second, third, and fourth conductive patterns C51, C52, C53, and C54 may be connection electrodes connected to one pattern or a plurality of patterns.

[0272] The first conductive pattern C51 may be connected to the fourth conductive layer CDL4 (see Figure 6G ) of the second conductive pattern C42 (see Figure 6G ). The first conductive pattern C51 may be Figure 3B Corresponding to the i-th data line DLi.

[0273] The second conductive pattern C52 may be connected to the fourth conductive layer CDL4 (see Figure 6G ) of the fifth conductive pattern C45 (see Figure 6G The second conductive pattern C52 may be a first driving voltage ELVDD (see Figure 3B ) is supplied to its first driving voltage line VL1 (see Figure 3BThe third conductive pattern C53 may be connected to the fourth conductive layer CDL4 (see Figure 6G ) of the fifth conductive pattern C45 (see Figure 6G ).

[0274] One end of the fourth conductive pattern C54 may be connected to the fourth conductive layer CDL4 (see Figure 6G ) of the eighth conductive pattern C48 (see Figure 6G ). The fourth conductive pattern C54 may be Figure 5B The other end of the fourth conductive pattern C54 may be connected to the 1-2nd light emitting element LD2r, the 2-2nd light emitting element LD2g and the 3-2nd light emitting element LD2b (see Figure 4B ) of the corresponding light emitting element pixel electrode AE ​​(see Figure 5B ).

[0275] Fig.6I is a plan view illustrating one layer constituting a light emitting layer provided in the second region according to one or more embodiments of the present disclosure.

[0276] Reference Figure 4B , Figure 5B and Fig.6I , the sixth conductive layer CDL6 may be disposed between the seventh insulating layer 70 and the pixel defining layer PDL. The sixth conductive layer CDL6 may include a pixel electrode AE ​​and an upper light blocking pattern ULBP. Fig.6I The pixel electrodes AEr, AEg, and AEb of the 1-2nd light emitting element LD2r, the 2-2nd light emitting element LD2g, the 3-2nd light emitting element LD2b, and the 2-2nd light emitting element LD2g are shown.

[0277] In one or more embodiments, the pixel electrode AEr, AEg or AEb of each light emitting element LD2r, LD2g or LD2b may be connected to the fourth conductive pattern C54 (see FIG. 5A ) through a contact hole passing through the seventh insulating layer 70. Figure 6H ).

[0278] The upper light blocking pattern ULBP may be disposed to surround at least a portion of the pixel electrode AE ​​in plane. An inner edge of the opening U-OP defining the upper light blocking pattern ULBP may have a shape extending along an edge of the pixel electrode AE ​​in plane.

[0279] According to one or more embodiments, even when the electronic module 400 (see Figure 2A ) when a light beam (for example, an infrared light beam) emitted by the common electrode CE is reflected by the common electrode CE, the upper light shielding pattern ULBP can also prevent, reduce or limit the light beam reflected by the common electrode CE from reaching the transistor.

[0280] In one or more embodiments, the configuration is shown as an example. FIG. 6A to FIG. 6I The shape of the pattern of pixels shown in , and the present disclosure is not necessarily limited thereto. In addition, as an example, Fig.6I The shapes of the pixel electrodes AE are shown in FIG. 1 , and the present disclosure is not necessarily limited thereto.

[0281] Figure 7 is a cross-sectional view illustrating a second region of a display panel according to one or more embodiments of the present disclosure. Fig. 8A is a plan view showing one layer constituting a pixel circuit arranged in the second region according to one or more embodiments of the present disclosure. Figure 8B is a plan view illustrating one layer constituting a light emitting layer provided in the second region according to one or more embodiments of the present disclosure. Fig. 8A The fifth conductive layer CDL5a is shown disposed between the sixth insulating layer 60 and the seventh insulating layer 70. Figure 8B The sixth conductive layer CDL6a disposed between the seventh insulating layer 70 and the pixel definition layer PDL is shown. Figures 1 to 6I The same / similar components described in the accompanying drawings are not disclosed herein, and their repeated descriptions will not be provided or repeated.

[0282] Reference Figures 7 to 8B , the upper light shielding pattern ULBPa may be disposed in the second area A2. In one or more embodiments, the upper light shielding pattern ULBPa may be disposed on the sixth insulating layer 60 and covered by the seventh insulating layer 70. For example, the upper light shielding pattern ULBPa may be a component included in the fifth conductive layer CDL5a.

[0283] like Fig. 8A and Figure 8B As shown in FIG. , the fifth conductive layer CDL5a according to one or more embodiments may include first, second, third, and fourth conductive patterns C51, C52, C53, and C54 and an upper light blocking pattern ULBPa, and the sixth conductive layer CDL6a may include a pixel electrode AE. Figure 6H The above description may be equally applied to the first conductive pattern C51, the second conductive pattern C52, the third conductive pattern C53, and the fourth conductive pattern C54. Fig.6I The description of can be equally applied to the pixel electrode AE. Figure 7 The third connection electrode CNE3 can be connected to Fig. 8A Corresponding to the fourth conductive pattern C54.

[0284] The upper light-shielding pattern ULBPa may be disposed on the same layer (e.g., at the same layer) as the first conductive pattern C51, the second conductive pattern C52, the third conductive pattern C53, and the fourth conductive pattern C54, and may include the same material as the first conductive pattern C51, the second conductive pattern C52, the third conductive pattern C53, and the fourth conductive pattern C54. The upper light-shielding pattern ULBPa may be formed simultaneously (e.g., in parallel) in the process of forming the first conductive pattern C51, the second conductive pattern C52, the third conductive pattern C53, and the fourth conductive pattern C54. In other words, the upper light-shielding pattern ULBPa may be disposed on the same layer (e.g., at the same layer) as the third connection electrode CNE3, and may include the same material as the third connection electrode CNE3. In addition, the upper light-shielding pattern ULBPa may be disposed on the same layer (e.g., at the same layer) as the third connection electrode CNE3, and may include the same material as the third connection electrode CNE3. Figure 3B ) and the first driving voltage line VL1 (see Figure 3B ) is disposed in the same layer (eg, at the same layer), and may include an i-th data line DLi (see Figure 3B ) and the first driving voltage line VL1 (see Figure 3B ) of the same material.

[0285] The upper light shielding pattern ULBPa may be spaced apart from the first conductive pattern C51, the second conductive pattern C52, the third conductive pattern C53, and the fourth conductive pattern C54, and may be disposed in a portion in which the first conductive pattern C51, the second conductive pattern C52, the third conductive pattern C53, and the fourth conductive pattern C54 are not disposed. In other words, the upper light shielding pattern ULBPa may be spaced apart from the third connection electrode CNE3, and may be disposed in a portion in which the third connection electrode CNE3 is not disposed. The upper light shielding pattern ULBPa may be spaced apart from the i-th data line DLi (see Figure 3B ) and the first driving voltage line VL1 (see Figure 3B ) and may be disposed in a region where the i-th data line DLi (see Figure 3B ) and the first driving voltage line VL1 (see Figure 3B ) section.

[0286] The edge of the upper light-shielding pattern ULBPa may have a shape extending along some of the edges of the first conductive pattern C51, the second conductive pattern C52, the third conductive pattern C53, and the fourth conductive pattern C54. As an example, Fig. 8A The shape of the upper light shielding pattern ULBPa is shown, and the upper light shielding pattern ULBPa may be disposed in one or more suitable shapes inside a portion where the first to fourth conductive patterns C51 to C52 to C53 and C54 are not arranged.

[0287] According to one or more embodiments, even when the electronic module 400 (see Figure 2A ) when a light beam (for example, an infrared light beam) emitted by the common electrode CE is reflected by the common electrode CE, the upper light shielding pattern ULBPa can also prevent, reduce or limit the light beam reflected by the common electrode CE from reaching the transistor.

[0288] In one or more embodiments, the configuration is shown as an example. Fig. 8A The shape of the pattern of pixels shown in , and the present disclosure is not necessarily limited thereto. In addition, as an example, Figure 8B The shapes of the pixel electrodes AE are shown in FIG. 1 , and the present disclosure is not necessarily limited thereto.

[0289] Fig. 9 is a cross-sectional view illustrating a second region of a display panel according to one or more embodiments of the present disclosure. Fig. 10A is a plan view illustrating a portion of a lower light shielding pattern according to one or more embodiments of the present disclosure. Fig. 10B 1 is a plan view showing a layer constituting a pixel circuit arranged in the second region according to one or more embodiments of the present disclosure. Figures 1 to 6I The same / similar components described in the accompanying drawings will be described below, and repeated descriptions thereof will not be provided.

[0290] Fig. 10A The second area A2 (see Fig. 9 ) in a portion of the lower light shielding pattern BLBPb. Fig. 10A In a second pixel group PXU2 (see Figure 4B ) The 1-2 pixel circuit PC2r, the 2-2 pixel circuit PC2g and the 3-2 pixel circuit PC2b are indicated by dotted lines.

[0291] Fig. 10B The first semiconductor layer ACL1 b disposed between the buffer layer BFL and the first insulating layer 10 is shown. Fig. 10B The second pixel group PXU2 (see FIG. Figure 4B ) The 1st-2nd pixel circuit PC2r (see Fig. 10A ), 2-2 pixel circuit PC2g (see Fig. 10A ), the 3-2 pixel circuit PC2b (see Fig. 10A ) and the 2-2 pixel circuit PC2g (see Fig. 10A ) components included in the .

[0292] Reference Figures 9 to 10B, the lower light shielding pattern BLBPb may be disposed between the barrier layer BRL and the buffer layer BFL. All of the 1-2 nd pixel circuit PC2r, the 2-2 nd pixel circuit PC2g, and the 3-2 nd pixel circuit PC2b may be arranged to overlap the lower light shielding pattern BLBPb on a plane.

[0293] In one or more embodiments, a light absorption pattern ABP may be further disposed in the second area A2. The light absorption pattern ABP may be disposed on the buffer layer BFL and may be covered by the first insulating layer 10. For example, the light absorption pattern ABP may be a component included in the first semiconductor layer ACL1b.

[0294] The light absorption pattern ABP may be disposed in the same layer (e.g., at the same layer) as the first semiconductor pattern ACT1. The light absorption pattern ABP may include the same material as that of the first semiconductor pattern ACT1. The light absorption pattern ABP may be formed simultaneously (e.g., in parallel) in the process of forming the first semiconductor pattern ACT1. In this case, the light absorption pattern ABP may be referred to as an additional semiconductor pattern. However, the present disclosure is not limited thereto, and the light absorption pattern ABP may include a material different from that of the first semiconductor pattern ACT1, and may be formed separately from the first semiconductor pattern ACT1.

[0295] The light absorption pattern ABP may include a first light absorption pattern ABP1 and a second light absorption pattern ABP2. Each of the first light absorption pattern ABP1 and the second light absorption pattern ABP2 may extend in the first direction DR1. On a plane (e.g., in the second direction DR2), the first light absorption pattern ABP1 may be disposed above the 1-2 pixel circuit PC2r, the 2-2 pixel circuit PC2g, and the 3-2 pixel circuit PC2b, and the second light absorption pattern ABP2 may be disposed below the 1-2 pixel circuit PC2r, the 2-2 pixel circuit PC2g, and the 3-2 pixel circuit PC2b in the second direction DR2.

[0296] From the electronic module 400 (see Figure 2A ) may be transmitted along the first insulating layer 10 including the inorganic layer. However, according to one or more embodiments, the light beam transmitted along the first insulating layer 10 may be absorbed by the light absorption pattern ABP. Therefore, the light beam transmitted from the electronic module 400 (see Figure 2A ) is transmitted to a portion in which the first semiconductor pattern ACT1 is disposed.

[0297] In one or more embodiments, the side light-shielding pattern SLBPb may contact the light absorption pattern ABP through a contact hole passing through the first insulating layer 10 to the fifth insulating layer 50. The first side pattern SLBP1b may contact the first light absorption pattern ABP1, and the second side pattern SLBP2b may contact the second light absorption pattern ABP2. On a plane, the first side pattern SLBP1b may overlap at least a portion of the first light absorption pattern ABP1, and the second side pattern SLBP2b may overlap at least a portion of the second light absorption pattern ABP2. In one or more embodiments, the side light-shielding pattern SLBPb and the lower light-shielding pattern BLBPb may not contact each other.

[0298] For ease of description, Fig. 10B , a portion of the light absorption pattern ABP that contacts the side light shielding pattern SLBPb is shown by a dotted line. The second portions P2-1b and P2-2b of the side light shielding pattern SLBPb may contact the lower light shielding pattern BLBPb. The first light absorption pattern ABP1 may extend in the first direction DR1 in the direction along which the second portion P2-1b of the first side pattern SLBP1b extends. The second light absorption pattern ABP2 may extend in the first direction DR1 in the direction along which the second portion P2-2b of the second side pattern SLBP2b extends.

[0299] In one or more embodiments, the transistors TFT1b and TFT2b in the second region A2 may be covered by the side light shielding pattern SLBPb. Therefore, the light from the electronic module 400 (see FIG. 4 ) may be prevented, reduced or limited. Figure 2A ) introduced into the lateral side of the second pixel circuit PC-2 reaches the transistors TFT1b and TFT2b.

[0300] In one or more embodiments, the configuration is shown as an example. Fig. 10A and Fig. 10B The shape of the pattern of pixels shown in FIG. 1 is shown in FIG. 4 , and the present disclosure is not necessarily limited thereto.

[0301] According to the present disclosure, the display panel may include an element region and a transmission region adjacent to each other in an area of ​​the display area overlapping the sensor area, and a shading pattern may be arranged in the element region. The shading pattern may include a lower shading pattern, a side shading pattern, and an upper shading pattern. Therefore, it is possible to prevent or reduce a light beam (e.g., an infrared light beam) provided to the sensor area from being reflected and / or transmitted into the element region. It is possible to prevent, reduce, or inhibit the infrared light beam from reaching the transistor in the element region, and thus it is possible to inhibit, prevent, or reduce the characteristic change of the transistor. Therefore, an electronic device with improved display quality can be provided.

[0302] Although the above description has been made with reference to one or more embodiments of the present disclosure, it is to be understood that a person skilled in the art or a person of ordinary skill in the art may modify and change the present disclosure in various ways without departing from the spirit and technical scope of the present disclosure described in the appended claims. Therefore, the technical scope of the present disclosure is not limited to the detailed description of the specification, but should be defined by the appended claims and their equivalents.

Claims

1. An electronic device, the electronic device include: Base layer; at least one transistor including a semiconductor pattern on the base layer and a gate electrode on the semiconductor pattern; connecting an electrode on the at least one transistor; at least one insulating layer between the semiconductor pattern and the connecting electrode; A side light shielding pattern, which is on the same layer as the connecting electrode; as well as a light emitting element on the connection electrode and electrically connected to the at least one transistor, wherein the connection electrode passes through the at least one insulating layer and is electrically connected to the semiconductor pattern, and Wherein, the side light shielding pattern passes through the at least one insulating layer.

2. The electronic device according to claim 1, in, The side light shielding pattern extends in one direction on a plane, and Wherein, when viewed in a direction that defines a plane together with the one direction and intersects the one direction, the semiconductor pattern overlaps the side light shielding pattern.

3. The electronic device according to claim 1, further comprising: include: A lower light shielding pattern is located between the base layer and the semiconductor pattern, The at least one transistor overlaps with the lower light-shielding pattern on a plane.

4. The electronic device according to claim 3, wherein the electronic device further comprises: include: a lower insulating layer, between the lower light shielding pattern and the semiconductor pattern, The side light-shielding pattern overlaps the lower light-shielding pattern on a plane, and further passes through the lower insulating layer to contact the lower light-shielding pattern.

5. The electronic device according to claim 1, wherein the electronic device further comprises: include: a light absorption pattern, which is in the same layer as the semiconductor pattern and includes the same material as that of the semiconductor pattern, Wherein, the side light shielding pattern is in contact with the light absorbing pattern.

6. The electronic device according to claim 1, in, The side light shielding pattern includes: a first side pattern and a second side pattern extending in a first direction on a plane and spaced apart from each other in a second direction crossing the first direction on a plane, and the at least one transistor is interposed between the first side pattern and the second side pattern.

7. The electronic device according to claim 6, in, When viewed in the second direction, the at least one transistor overlaps the first side pattern and the second side pattern.

8. The electronic device according to claim 6, further comprising: include: a first light absorption pattern and a second light absorption pattern, which are spaced apart from each other in the second direction, and the at least one transistor is disposed between the first light absorption pattern and the second light absorption pattern, each of the first light absorption pattern and the second light absorption pattern extending in the first direction and arranged at the same layer as the semiconductor pattern, The first side pattern overlaps with the first light absorption pattern and contacts with the first light absorption pattern, and the second side pattern overlaps with the second light absorption pattern and contacts with the second light absorption pattern.

9. The electronic device according to claim 6, in, The light emitting element comprises a plurality of light emitting elements, The plurality of light emitting elements include: first light emitting elements, each first light emitting element being configured to emit a light beam having a first color toward a first light emitting area; second light emitting elements, each second light emitting element being configured to emit a light beam having a second color different from the first color to a second light emitting area; and third light emitting elements, each of the third light emitting elements being configured to emit a light beam having a third color different from the first color and the second color to a third light emitting area, wherein one first pixel element in the first light-emitting element, two second pixel elements in the second light-emitting element, and one third pixel element in the third light-emitting element are arranged in one pixel group, and The pixel group is repeatedly arranged in a pixel row along the first direction.

10. The electronic device as claimed in claim 9, in, In the one pixel group, the first light-emitting region of the one first pixel element and the third light-emitting region of the one third pixel element are spaced apart from each other in the first direction, and the second light-emitting regions of the two second pixel elements are spaced apart from each other in a direction intersecting the first direction and the second direction, and the third light-emitting region of the one third pixel element is placed between the second light-emitting regions of the two second pixel elements.

11. The electronic device according to claim 9, in, The substrate layer comprises: a component area, including a transmission area and a component area; and a main display area, adjacent to the component area, and The light emitting element overlaps with the element area and the main display area, and does not overlap with the transmission area.

12. The electronic device according to claim 11, in, A plurality of transmission regions including the transmission region and a plurality of element regions including the element region are arranged in the base layer, and the transmission regions and the element regions are arranged to alternate with each other in the second direction inside the element region, and Wherein, the one pixel row overlaps with the component area.

13. The electronic device according to claim 12, in, The first side pattern and the second side pattern are arranged to overlap each of the element regions.

14. The electronic device according to claim 11, further comprising: include: a first pixel circuit electrically connected to a corresponding first light emitting element of the first light emitting elements; a second pixel circuit electrically connected to a corresponding second light emitting element of the second light emitting elements; as well as a third pixel circuit electrically connected to a corresponding third light emitting element among the third light emitting elements, wherein each of the first to third pixel circuits comprises the at least one transistor and the connecting electrode, and Among them, in the one pixel group, one of the first pixel circuits, one of the two of the second pixel circuits, one of the third pixel circuits, and the other of the two of the second pixel circuits are arranged along the first direction.

15. The electronic device according to claim 1, further comprising: include: an upper light shielding pattern, overlapping at least a portion of the semiconductor pattern on a plane, The light emitting element includes a first electrode on the connecting electrode and electrically connected to the connecting electrode, a light emitting layer on the first electrode, and a second electrode on the light emitting layer, and Wherein, the upper light shielding pattern and the first electrode are in the same layer.

16. The electronic device according to claim 1, further comprising: include: an upper connecting electrode, located between the connecting electrode and the light emitting element, and electrically connected between the connecting electrode and the light emitting element; as well as The upper light shielding pattern overlaps with at least a portion of the semiconductor pattern in a plane and is located in the same layer as the upper connecting electrode.

17. The electronic device according to claim 1, in, The at least one insulating layer comprises: a first insulating layer located between the semiconductor pattern and the gate electrode; and a second insulating layer, located between the gate electrode and the connecting electrode, and The side light shielding pattern continuously passes through the first insulating layer and the second insulating layer.

18. The electronic device according to claim 17, wherein the electronic device further comprises: include: at least one additional transistor including an additional semiconductor pattern located between the gate electrode and the connection electrode and an additional gate electrode located between the additional semiconductor pattern and the connection electrode, Wherein, the at least one insulating layer further comprises: a third insulating layer, located between the gate electrode and the additional semiconductor pattern; a fourth insulating layer located between the additional semiconductor pattern and the additional gate electrode; and a fifth insulating layer located between the additional gate electrode and the connecting electrode, and The side light shielding pattern continuously passes through the first insulating layer to the fifth insulating layer.

19. The electronic device according to claim 1, in, The side light shielding pattern includes the same material as that of the connection electrode.

20. An electronic device, the electronic device include: A pixel circuit comprising at least one transistor, wherein the at least one transistor comprises a semiconductor pattern and a gate electrode on the semiconductor pattern; a light emitting element, electrically connected to the pixel circuit; as well as a side light shielding pattern, comprising a first side pattern and a second side pattern, wherein the first side pattern and the second side pattern are spaced apart from each other in one direction on a plane, and the pixel circuit is disposed between the first side pattern and the second side pattern, Wherein, when viewed in the one direction, the semiconductor pattern overlaps each of the first side pattern and the second side pattern.

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