Hall sensor and manufacturing method thereof

Abstract

The present invention relates to a Hall sensor and a method of manufacturing the same, the Hall sensor comprising: a substrate having a second conductivity type; the buried region is located in the substrate and has a first conduction type; the first conductive type and the second conductive type are opposite; and the plurality of first conductive type well regions are located on the buried region, the bottom of each first conductive type well region is in direct contact with the buried region, and the adjacent first conductive type well regions are separated by the substrate. According to the invention, carriers can be promoted to flow through the interior of the device through the buried region, so that a current path is optimized, the influence of the surface effect and noise of the device on the performance of the Hall device is reduced, and the sensitivity of the Hall device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to a Hall sensor, and also to a manufacturing method of the Hall sensor. Background Art

[0002] The Hall sensor is a sensor that uses the Hall effect to measure magnetic fields. A semiconductor device is set in the Hall sensor. When the current passes through the semiconductor perpendicular to the external magnetic field, the carriers are deflected, generating an additional electric field in the direction perpendicular to the current and the magnetic field, and generating a potential difference at both ends of the semiconductor. This potential difference is also called the Hall potential difference.

[0003] In recent years, various types of vertical Hall devices have been proposed, including five-electrode, four-electrode, six-electrode and double three-electrode structures. Some electrodes are used to apply voltage or current, and some electrodes are used to detect Hall voltage or Hall current. In traditional five-electrode Hall devices, some carriers flow on the surface of the device, resulting in short-circuit effect and surface effect, which limits the performance of the five-electrode Hall device. Summary of the invention

[0004] Based on this, it is necessary to provide a Hall sensor with higher sensitivity.

[0005] A Hall sensor comprises: a substrate having a second conductivity type; a buried region located in the substrate and having a first conductivity type; the first conductivity type and the second conductivity type are opposite conductivity types; and a plurality of first conductivity type well regions located on the buried region, wherein the bottom of each first conductivity type well region is in direct contact with the buried region, and adjacent first conductivity type well regions are separated by the substrate.

[0006] In the above-mentioned Hall sensor, adjacent first conductive type well regions are separated by a second conductive type substrate, which can prevent carriers from flowing on the surface of the substrate and promote carriers to flow from the inside of the device through the buried region, thereby optimizing the current path, thereby increasing the effective thickness of the active area, reducing the impact of the device's surface effect and noise on the performance of the Hall device, and improving the sensitivity of the Hall device.

[0007] In one embodiment, the Hall sensor further includes a plurality of first conductivity type doped regions, each of the first conductivity type well regions is provided with at least one first conductivity type doped region, and the doping concentration of each first conductivity type doped region is greater than the doping concentration of the first conductivity type well region in which it is located.

[0008] In one embodiment, the Hall sensor is a five-electrode sensor, the number of the first conductive type well region and the first conductive type doped region is 5, the 5 first conductive type doped regions are respectively a first Hall sensing port, a second Hall sensing port, a second bias port and two first bias ports, the first Hall sensing port and the second Hall sensing port are used to detect Hall voltage or Hall current, the second bias port is used to input electrical energy, and the first bias port is used to output electrical energy.

[0009] In one embodiment, the doping concentration of each of the first conductivity type doping regions is greater than the doping concentration of the buried region.

[0010] In one embodiment, the lengths of the two first bias ports in the first direction are smaller than the lengths of the first Hall sensing port, the second Hall sensing port and the second bias port in the first direction, and the spacing direction between the first Hall sensing port and the second bias port is perpendicular to the first direction.

[0011] In one embodiment, the length of the two first offset ports in the first direction is half of the length of the second offset port in the first direction.

[0012] In one embodiment, the lengths of the first Hall sensing port and the second Hall sensing port in the first direction are equal to the length of the second bias port in the first direction.

[0013] In one embodiment, in each of the first conductivity type well regions, a distance between adjacent first conductivity type well regions is greater than 0.3 micrometers.

[0014] In one embodiment, the width of each first conductivity type well region in the second direction is greater than 1.6 micrometers, and the second direction is the spacing direction between adjacent first conductivity type well regions.

[0015] In one embodiment, the width of the Hall sensor is 18 micrometers, and the width direction is the spacing direction between adjacent first conductivity type well regions.

[0016] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0017] A method for manufacturing a Hall sensor, comprising: obtaining a substrate formed with a buried region; the buried region has a first conductivity type, the substrate has a second conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types; forming a doping window exposed by a photoresist through photolithography; doping the substrate through the doping window to form a plurality of first conductivity type well regions located on the buried region; the bottom of each first conductivity type well region is in direct contact with the buried region, and adjacent first conductivity type well regions are separated by the substrate; doping the deposit again through the doping window to form a first conductivity type doping region in each first conductivity type well region; the doping concentration of each first conductivity type doping region is greater than the doping concentration of the first conductivity type well region in which it is located.

[0018] In the manufacturing method of the Hall sensor, the doping of the first conductive type well region and the doping of the first conductive type doping region use the same doping window, which does not increase the photolithography level and can save manufacturing costs. In addition, the adjacent first conductive type well regions in the manufactured Hall sensor are separated by the second conductive type substrate, which can prevent carriers from flowing on the surface of the substrate and promote carriers to flow through the device through the buried region, thereby optimizing the current path, thereby increasing the effective thickness of the active region, reducing the impact of the device's surface effect and noise on the performance of the Hall device, and improving the sensitivity of the Hall device.

[0019] In one embodiment, the step of forming a plurality of first conductivity type well regions located on the buried region includes: performing first conductivity type ion implantation using the photoresist as an implantation mask, and then performing heat treatment to form the first conductivity type well region.

[0020] In one embodiment, the step of forming a first conductivity type doped region in each of the first conductivity type well regions includes: performing first conductivity type ion implantation using the photoresist as an implantation mask, and then performing heat treatment to form the first conductivity type doped region.

[0021] In one of the embodiments, the method further includes: forming an insulating dielectric layer on the substrate; patterning the insulating dielectric layer to form contact holes on each of the first conductive type doped regions; and forming a conductive structure in each of the contact holes that is electrically connected to the corresponding first conductive type doped region.

[0022] In one embodiment, the Hall sensor is a five-electrode sensor, the number of the first conductive type well region and the first conductive type doped region is 5, the 5 first conductive type doped regions are respectively a first Hall sensing port, a second Hall sensing port, a second bias port and two first bias ports, the first Hall sensing port and the second Hall sensing port are used to detect Hall voltage or Hall current, the second bias port is used to input electrical energy, and the first bias port is used to output electrical energy.

[0023] In one embodiment, the doping concentration of each of the first conductivity type doping regions is greater than the doping concentration of the buried region.

[0024] In one embodiment, the lengths of the two first bias ports in the first direction are smaller than the lengths of the first Hall sensing port, the second Hall sensing port and the second bias port in the first direction, and the spacing direction between the first Hall sensing port and the second bias port is perpendicular to the first direction.

[0025] In one embodiment, the length of the two first offset ports in the first direction is half of the length of the second offset port in the first direction.

[0026] In one embodiment, the lengths of the first Hall sensing port and the second Hall sensing port in the first direction are equal to the length of the second bias port in the first direction.

[0027] In one embodiment, in each of the first conductivity type well regions, a distance between adjacent first conductivity type well regions is greater than 0.3 micrometers.

[0028] In one embodiment, the width of each first conductivity type well region in the second direction is greater than 1.6 micrometers, and the second direction is the spacing direction between adjacent first conductivity type well regions.

[0029] In one embodiment, the width of the Hall sensor is 18 micrometers, and the width direction is the spacing direction between adjacent first conductivity type well regions.

[0030] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0032] Figure 1 This is a schematic diagram of the structure of a Hall sensor in one embodiment of the present application;

[0033] Figure 2 This is a working principle diagram of a Hall sensor in one embodiment of the present application;

[0034] Figure 3 is a schematic cross-sectional structure diagram of a Hall sensor in one embodiment of the present application;

[0035] Figure 4 is along Figure 3 The top view of the AA' section;

[0036] Figure 5 is a comparison of the current density distribution of the Hall sensor of an embodiment of the present application and the Hall sensor of a comparative example;

[0037] Figure 6 A Hall voltage diagram of a Hall sensor of an embodiment of the present application and a comparative example under magnetic induction intensity in the same direction;

[0038] Figure 7 is a flow chart of a method for manufacturing a Hall sensor in one embodiment of the present application;

[0039] Figures 8a to 8d is based on Figure 7 A schematic cross-sectional view of a device structure during the process of manufacturing a Hall sensor by the method shown;

[0040] Fig. 9 is a flow chart of a method for manufacturing a Hall sensor in another embodiment. DETAILED DESCRIPTION

[0041] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0043] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. "Connection" in this specification should be understood as "electrical connection", "communication connection" and the like if the connected circuits, modules, units, etc. have transmission of electrical signals or data to each other. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0044] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0045] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" refers to one or more, and "multiple" refers to two or more. "At least part of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0047] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0048] Figure 1 1 is a schematic diagram of the structure of a Hall sensor in an embodiment of the present application, which shows the surface (including profile and cross-section) structure of the device, but does not show the structure inside the device (i.e., not on the device surface). The Hall sensor includes a substrate 110, a buried region 120, and a plurality of first conductive type well regions. Each first conductive type well region is located on the buried region 120, and the bottom of each first conductive type well region is in direct contact with the buried region 120, and adjacent first conductive type well regions are separated by the substrate 110.

[0049] In the above-mentioned Hall sensor, adjacent first conductive type well regions are separated by a second conductive type substrate 110, which can prevent carriers from flowing on the surface of the substrate 110 and promote carriers to flow from the inside of the device through the buried region 120. This optimizes the current path, thereby increasing the effective thickness of the active area, reducing the impact of the device's surface effect and noise on the performance of the Hall device, and improving the sensitivity of the Hall device.

[0050] In one embodiment of the present application, the Hall sensor further includes a plurality of first conductivity type doped regions, each first conductivity type well region is provided with at least one first conductivity type doped region, and the doping concentration of each first conductivity type doped region is greater than the doping concentration of the first conductivity type well region in which it is located. Providing the first conductivity type doped region can achieve good ohmic contact, which can reduce the contact resistance of the device and improve the efficiency of current transmission.

[0051] Figure 1The Hall sensor shown is a five-electrode sensor having five first conductivity type doping regions (doping region 141, doping region 143, doping region 145, doping region 147 and doping region 149) and corresponding five first conductivity type well regions (well region 131, well region 133, well region 135, well region 137 and well region 139). The doping region 143 is the first Hall sensing port V sense1 , the doped region 147 is the second Hall sensing port V sense2 , the doped region 145 is the second bias port V bias2 , the doping region 143 and the doping region 149 are both the first bias port V bias1 , and through the metal wiring layer ( Figure 1 The second bias port V bias2 The first bias port is used to input electrical energy (such as input voltage or current), and the first bias port is used to output electrical energy (such as output voltage or current). The input and output will cause the first Hall sensing port V sense1 and the second Hall sensing port V sense2 A potential difference is formed between them, so it can be sensed through the first Hall effect port V sense1 and the second Hall sensing port V sense2 Detect the Hall voltage (or Hall current). Figure 1 In the illustrated embodiment, the first conductivity type is N-type, and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type, and the second conductivity type may be N-type.

[0052] Figure 2 This is a working principle diagram of a Hall sensor in an embodiment of the present application. The device structure can be referred to Figure 1 The Hall sensor shown in FIG. 1 is not described in detail here. The external current is input from the doped region 145, then flows through the well region 135 in the buried region 120, and finally flows through the well region 131 and the well region 139 to the doped region 141 and the doped region 149, respectively. The corresponding current path is as follows: Figure 2 As shown by the thick arrow in . Since the adjacent first conductivity type well regions are separated by the substrate 110, this current flows through the inside of the device and does not flow through the surface of the device, thereby optimizing the surface effect of the vertical device structure, increasing the effective thickness of the active region, reducing the surface effect and noise performance of the device, and improving the sensitivity of the device. Further, when the Hall sensor is in the state as Figure 2 When in the magnetic field shown (refer to Figure 2 In the figure, there are magnetic flux lines B pointing from the north pole N to the south pole S. Under the action of the magnetic field, the carriers are deflected by the Lorentz force, making the current distribution on both sides uneven, such as Figure 2As shown by the thin arrows in FIG. 1 , a potential difference is generated between the Hall electrodes on both sides (ie, the doped region 147 and the doped region 143 ), and finally a Hall voltage is formed.

[0053] Figure 3 is a schematic diagram of the cross-sectional structure of a Hall sensor in an embodiment of the present application. The device structure can be referred to Figure 1 The Hall sensor shown in the figure will not be described in detail here. Figure 3 , the Hall sensor also includes an insulating dielectric layer 150 located on the substrate 110. A contact hole 151 is formed on each first conductive type doped region, which penetrates the insulating dielectric layer 150. The contact hole 151 is filled with a conductive material (such as metal and / or alloy) to lead each first conductive type doped region out as an electrode. In one embodiment of the present application, the insulating dielectric layer 150 is an oxide layer, and its material is silicon oxide, such as silicon dioxide. When the Hall sensor is working, due to the obstruction of the substrate 110, the carriers cannot flow along the surface of the Hall device (i.e., the surface of the substrate 110), but are driven to flow inside the deep well (first conductive type well region), thereby avoiding the "short circuit effect" caused by the current being more inclined to flow directly from the electrode when the bias current is applied to the device. In addition, since the charge carried in the oxide layer on the surface of the device will attract the carriers in the active area, it will bring about a "surface effect", which will affect the sensitivity of the Hall sensor. The first conductive type well region in the Hall device of the present application will greatly reduce the impact of the surface effect on the current, thereby maintaining the proper sensitivity of the device.

[0054] In one embodiment of the present application, the lengths of the two first bias ports (i.e., the doping region 141 and the doping region 149) in the first direction are smaller than the lengths of the first Hall sensing port (i.e., the doping region 143), the second Hall sensing port (i.e., the doping region 147), and the second bias port (i.e., the doping region 145) in the first direction, and the first direction is perpendicular to the spacing direction between the Hall sensing port and the second bias port, referring to Figure 4 , the first direction is Figure 4 In the z-axis direction, Figure 4 is along Figure 3 The top view of the AA' section of the structure. The two first bias ports V bias1 The length of the device can be shortened to improve the sensitivity of the device when the contact electrodes at both ends of the device are unbalanced. sense1 , the second bias port V bias2 The second Hall sensing port V sense2 The length of the three contact electrodes is lengthened, which can reduce the mismatch error on the active area during the process, thereby reducing the offset voltage and achieving a better compromise between sensitivity and offset.

[0055] In one embodiment of the present application, the length a of the two first bias ports (i.e., the doping region 141 and the doping region 149) in the first direction is half of the length b of the second bias port (i.e., the doping region 145) in the first direction. In one embodiment of the present application, the length b of the first Hall sensing port (i.e., the doping region 143) and the second Hall sensing port (i.e., the doping region 147) in the first direction is also.

[0056] In summary, the lengths of doping region 141, doping region 143, doping region 145, doping region 147, and doping region 149 in the first direction (i.e., the lengths of the five electrodes of the five-electrode Hall sensor) are designed in a ratio of 1:2:2:2:1, which can achieve a better compromise between sensitivity and offset of the device.

[0057] The inventors have found that if the spacing width between the first conductivity type well regions is too small, the device will generate too little charge during operation and the sensitivity will be too low. In one embodiment of the present application, the spacing between adjacent first conductivity type well regions is greater than 0.3 microns, that is, the spacing between each pair of adjacent first conductivity type well regions is greater than 0.3 microns. Figure 4 , the interval e between the well region 131 and the well region 133, and the interval d between the well region 133 and the well region 135 are both greater than 0.3 microns. In one embodiment of the present application, the width of each first conductivity type well region in the second direction is greater than 1.6 microns, which can obtain better device performance. The second direction is the spacing direction between adjacent first conductivity type well regions, that is, Figure 4 In the x-axis direction of the image sensor. In one embodiment of the present application, the width of the Hall sensor in the second direction is 18 microns. The inventor believes that if the interval between adjacent first conductive type well regions is too wide, the resistance between electrodes will increase, and the increased input resistance will reduce the Hall current, which will also reduce the sensitivity. Therefore, the interval between adjacent first conductive type well regions cannot be too large. The specific upper limit of the interval width varies with the width of the Hall sensor.

[0058] Figure 5 : is a comparison of the current density distribution of the Hall sensor of an embodiment of the present application and the Hall sensor of the comparative example, wherein Figure 5 The two figures on the left are embodiments of the present application, and the two figures on the right are comparative examples; Figure 5 The two figures in the middle and lower sides outline the equipotential line contours of the current density distribution. It can be seen that the high current density area of ​​the embodiment of the present application is obviously lower than the corresponding position of the comparative example, that is, the current of the device is transferred from the surface to the inside, which optimizes the current path of the device and improves the sensitivity of the device.

[0059] Figure 6This is a Hall voltage diagram of the Hall sensor of an embodiment of the present application and a comparative example under the same direction of magnetic induction intensity. It can be seen that under the same magnetic induction intensity, the sensitivity of the Hall sensor of the embodiment of the present application can be improved by about 17%.

[0060] The present application accordingly provides a method for manufacturing a Hall sensor, which can be used to manufacture the Hall sensor described in any of the aforementioned embodiments. Figure 7 : is a flow chart of a method for manufacturing a Hall sensor in an embodiment of the present application, comprising the following steps:

[0061] S710, obtaining a substrate having a buried region formed thereon.

[0062] A semiconductor wafer is obtained, and the wafer includes a substrate 110. The substrate 110 is a semiconductor substrate, and its material can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). Figure 8a In the embodiment shown, the substrate 110 is made of single crystal silicon. The buried region 120 has a first conductivity type, and the substrate 110 has a second conductivity type. Figure 8a In the embodiment shown, the first conductivity type is N type and the second conductivity type is P type; in other embodiments, the first conductivity type may be P type and the second conductivity type may be N type. Figure 8a In the embodiment shown, N-type ions are implanted into the substrate 110 by using an ion implantation process to form an N-type buried layer as the buried region 120. In other embodiments, other methods may be used to form the buried region 120. For example, after N-type ions are implanted into a shallow layer of the substrate to form a buried layer, a P-type epitaxial layer is formed on the buried layer by epitaxy.

[0063] S720, forming a doping window exposed by the photoresist by photolithography.

[0064] In one embodiment of the present application, a layer of photoresist is coated on the front side of the substrate 110, and then the photoresist is exposed using a deep well photomask. After development, the photoresist at a portion of the position is removed to expose the doping window 181, and the photoresist 191 remaining on the front side of the substrate 110 serves as a doping barrier layer. Figure 8b .

[0065] S730 , performing doping through the doping window to form a first conductivity type well region located on the buried region.

[0066] In one embodiment of the present application, a deep well implantation is performed on the substrate 110 using the photoresist 191 as an ion implantation mask (implantation barrier layer) to form a plurality of first conductivity type well regions in the substrate 110, and the implantation depth is deep enough so that the bottom of each first conductivity type well region can reach the buried region 120. In one embodiment of the present application, the wafer is heat treated (e.g., thermal annealing) after the implantation, and the implanted first conductivity type ions diffuse to form each first conductivity type well region. Adjacent first conductivity type well regions are separated by the substrate 110, see Figure 8c .exist Figure 8c In the illustrated embodiment, the Hall sensor is a five-electrode sensor, and the number of first conductivity type well regions is 5, namely well region 131 , well region 133 , well region 135 , well region 137 , and well region 139 .

[0067] S740, performing doping again through the doping window to form a first conductive type doping region.

[0068] In one embodiment of the present application, the photoresist 191 formed in step S720 is retained as an implantation mask, and the substrate 110 is doped again, thereby forming a first conductive type doped region in each first conductive type well region. After doping, the wafer is heat treated (for example, thermal annealing). Step S740 is heavy doping, and the dose of the first conductive type ions injected is greater than the dose of the first conductive type ions injected in the ion implantation of step S730, so that the doping concentration of each first conductive type doped region is greater than the doping concentration of the first conductive type well region in which it is located. Figure 8d In the illustrated embodiment, the number of first conductivity type doping regions is 5, corresponding one to one with the first conductivity type well regions, including doping region 141, doping region 143, doping region 145, doping region 147 and doping region 149. In one embodiment of the present application, the doping concentration of each first conductivity type doping region is greater than the doping concentration of the buried region 120.

[0069] As an alternative solution, shallow trenches / deep trenches can be set to prevent current from flowing through the device surface; or P+ doping can be performed next to the electrode to prevent current from flowing through the device surface through P+ isolation. However, these solutions all require the addition of additional photolithography layers, and the added photolithography layers will inevitably introduce new asymmetry problems and cause greater device misalignment. The solution of the present application can solve the problems of the above-mentioned surface effect and short-circuit effect without adding photolithography layers, thereby reducing the mismatch caused by the manufacturing process.

[0070] The manufacturing method of the Hall sensor described above prepares a plurality of discrete deep wells (i.e., first conductivity type well regions) by segmented doping technology. The doping of the first conductivity type well region and the doping of the first conductivity type doping region use the same doping window, which does not increase the photolithography level and can save manufacturing costs. In addition, the adjacent first conductivity type well regions in the manufactured Hall sensor are separated by a second conductivity type substrate. The carriers on the device surface will be hindered by the substrate and flow into the deep well. At the same time, due to the presence of the buried region 120, a connecting path between the discrete deep wells is established, so that the carriers can flow in the area connected to the buried region 120 at the bottom of the deep well, thereby optimizing the current path, thereby increasing the effective thickness of the active region, reducing the influence of the surface effect and noise of the device on the performance of the Hall device, and improving the sensitivity of the Hall device.

[0071] Fig. 9 is a flow chart of a method for manufacturing a Hall sensor in another embodiment, which is Figure 7 The difference between the illustrated embodiments is that the following steps are further included after step S740:

[0072] S750, forming an insulating dielectric layer on the substrate.

[0073] Oxide is deposited on the front surface of the substrate 110 as an insulating dielectric layer 150. In one embodiment of the present application, the insulating dielectric layer 150 is made of silicon oxide, such as silicon dioxide.

[0074] S760, patterning the insulating dielectric layer to form contact holes on each first conductivity type doped region.

[0075] In one embodiment of the present application, a contact hole photomask is used to photolithograph and etch the insulating dielectric layer 150 , thereby forming a contact hole 151 on each first conductive type doping region.

[0076] S770 , forming a conductive structure in each contact hole that is electrically connected to the corresponding first conductive type doping region.

[0077] Fill each contact hole with a conductive material, and lead each first conductive type doped region out as an electrode of the Hall sensor. The conductive material may be a metal and / or alloy. The device structure after step S770 is completed may refer to Figure 3 A metal wiring layer ( Figure 3 (not shown).

[0078] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0079] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0080] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A Hall sensor, characterized in that: include: a substrate having a second conductivity type; a buried region, located in the substrate and having a first conductivity type; The first conductivity type and the second conductivity type are opposite conductivity types; A plurality of first conductivity type well regions are located on the buried region, the bottom of each of the first conductivity type well regions is in direct contact with the buried region, and adjacent first conductivity type well regions are separated by the substrate.

2. The Hall sensor according to claim 1, characterized in that: It also includes a plurality of first conductivity type doping regions, each of which is provided with at least one first conductivity type doping region, and the doping concentration of each first conductivity type doping region is greater than the doping concentration of the first conductivity type well region in which it is located.

3. The Hall sensor according to claim 2, characterized in that: The Hall sensor is a five-electrode sensor, the number of the first conductive type well region and the first conductive type doped region is 5, the 5 first conductive type doped regions are respectively a first Hall sensing port, a second Hall sensing port, a second bias port and two first bias ports, the first Hall sensing port and the second Hall sensing port are used to detect Hall voltage or Hall current, the second bias port is used to input electrical energy, and the first bias port is used to output electrical energy.

4. The Hall sensor according to claim 3, characterized in that: The lengths of the two first bias ports in the first direction are smaller than the lengths of the first Hall sensing port, the second Hall sensing port and the second bias port in the first direction, and the spacing direction between the first Hall sensing port and the second bias port is perpendicular to the first direction.

5. The Hall sensor according to claim 4, characterized in that: The length of the two first offset ports in the first direction is half of the length of the second offset port in the first direction.

6. The Hall sensor according to claim 4 or 5, characterized in that: The lengths of the first Hall sensing port and the second Hall sensing port in the first direction are equal to the length of the second bias port in the first direction.

7. The Hall sensor according to claim 1, characterized in that: In each of the first conductivity type well regions, the interval between adjacent first conductivity type well regions is greater than 0.3 micrometers; and / or The width of each of the first conductivity type well regions in the second direction is greater than 1.6 micrometers, and the second direction is the spacing direction between adjacent first conductivity type well regions.

8. A method for manufacturing a Hall sensor, comprising: Obtaining a substrate having a buried region formed thereon; the buried region having a first conductivity type, the substrate having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; forming a doping window exposed by the photoresist by photolithography; doping the substrate through the doping window to form a plurality of first conductivity type well regions located on the buried region; the bottom of each of the first conductivity type well regions is in direct contact with the buried region, and adjacent first conductivity type well regions are separated by the substrate; The deposit is doped again through the doping window to form a first conductivity type doping region in each first conductivity type well region; the doping concentration of each first conductivity type doping region is greater than the doping concentration of the first conductivity type well region in which it is located.

9. The method for manufacturing a Hall sensor according to claim 8, characterized in that: The step of forming a plurality of first conductivity type well regions located on the buried region comprises: performing first conductivity type ion implantation using the photoresist as an implantation mask, and then performing heat treatment to form the first conductivity type well region; and / or The step of forming a first conductivity type doped region in each of the first conductivity type well regions comprises: performing first conductivity type ion implantation using the photoresist as an implantation mask, and then performing heat treatment to form the first conductivity type doped region.

10. The method for manufacturing a Hall sensor according to claim 8, characterized in that: Also includes: forming an insulating dielectric layer on the substrate; Patterning the insulating dielectric layer to form contact holes on each of the first conductive type doped regions; A conductive structure electrically connected to the corresponding first conductive type doping region is formed in each of the contact holes.

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