Semiconductor device and method for manufacturing the same

Abstract

The present application provides a semiconductor device and a preparation method thereof, which relates to the field of semiconductor technology and is used to solve the technical problem that increasing the coercivity of a magnetic tunnel junction will cause the power consumption of a SOT-MRAM to increase exponentially. The semiconductor device at least includes a substrate, and a first heavy metal layer, a second heavy metal layer, and a magnetic tunnel junction stacked in sequence on the substrate; wherein the first heavy metal layer and the second heavy metal layer are made of the same material and have different crystal phases, and the first heavy metal layer and the second heavy metal layer are bonded by a bonding process; the free layer in the magnetic tunnel junction is arranged adjacent to the second heavy metal layer, and after being treated by an annealing process, the free layer and the second heavy metal layer are lattice mismatched, so that the free layer generates lattice stress. The present application is used to increase the coercivity of a magnetic tunnel junction and, at the same time, reduce the power consumption of a semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Spin-orbit Torque Magnetic Random Access Memory (SOT-MRAM) has the characteristics of low power consumption, high density, non-volatility, high read and write speed and long service life, and has attracted special attention in the industry.

[0003] In the related art, SOT-MRAM includes a stacked magnetic tunnel junction (MTJ) and a heavy metal layer. The MTJ is the basic storage unit of SOT-MRAM. The coercive force (Hc) is one of the main parameters affecting the antimagnetic properties of the MTJ, which will affect the stability of SOT-MRAM data storage. Therefore, improving the coercive force of the MTJ in SOT-MRAM is one of the main means to improve the stability of SOT-MRAM data storage.

[0004] However, in the related art, the coercive force of the magnetic tunnel junction is improved by changing the crystal phase inside the metal layer material, which will lead to a very low spin conversion efficiency of the SOT-MRAM, thereby causing the power consumption to increase exponentially; methods such as adding IrMn / PtMn intercalation under the free layer, artificial antiferromagnetic coupling of the free layer, and increasing the ratio of the major and minor axes of the elliptical device to change the shape anisotropy of the device through stress can also improve the coercive force, but will also damage the key performance of the device. Summary of the invention

[0005] In view of the above problems, an embodiment of the present application provides a semiconductor device and a method for manufacturing the same, which are used to improve the coercivity of a magnetic tunnel junction and, at the same time, reduce the power consumption of the semiconductor device.

[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] A first aspect of an embodiment of the present application provides a semiconductor device, comprising at least: a substrate, and a first heavy metal layer, a second heavy metal layer, and a magnetic tunnel junction sequentially stacked on the substrate;

[0008] Wherein, the first heavy metal layer and the second heavy metal layer are made of the same material but have different crystal phases, and the first heavy metal layer and the second heavy metal layer are bonded by a bonding process;

[0009] The free layer in the magnetic tunnel junction is arranged adjacent to the second heavy metal layer. After annealing, the free layer and the second heavy metal layer have lattice mismatch, so that lattice stress is generated in the free layer.

[0010] In some optional embodiments, the spin conversion efficiency of the first heavy metal layer is greater than the spin conversion efficiency of the second heavy metal layer; and the resistivity of the first heavy metal layer is greater than the resistivity of the second heavy metal layer.

[0011] In some optional embodiments, under the annealing process, the crystal phase stability of the first heavy metal layer is less than the crystal phase stability of the second heavy metal layer;

[0012] And / or, the thickness of the first heavy metal layer is greater than the thickness of the second heavy metal layer.

[0013] In some optional embodiments, the second heavy metal layer is partially or completely bonded to the first heavy metal layer after the bonding process.

[0014] A second aspect of an embodiment of the present application provides a method for preparing a semiconductor device, comprising:

[0015] forming a first heavy metal layer on a first substrate;

[0016] forming a stacked magnetic tunnel junction and a second heavy metal layer on a second substrate;

[0017] Wherein, the first heavy metal layer and the second heavy metal layer are made of the same material but have different crystal phases;

[0018] The free layer in the magnetic tunnel junction is arranged adjacent to the second heavy metal layer, and after annealing, the free layer and the second heavy metal layer have a lattice mismatch, so that the free layer generates lattice stress;

[0019] performing bonding treatment on the first heavy metal layer and the second heavy metal layer so that the first heavy metal layer and the second heavy metal layer are partially or completely bonded;

[0020] The second substrate is removed.

[0021] In some optional implementations, after forming the magnetic tunnel junction on the second substrate, the method further comprises:

[0022] depositing a heavy metal material on the magnetic tunnel junction to form an initial second heavy metal layer;

[0023] Annealing the magnetic tunnel junction and the initial second heavy metal layer;

[0024] performing a thinning process on the initial second heavy metal layer to form a second heavy metal layer;

[0025] wherein the thickness of the initial second heavy metal layer is greater than the thickness of the first heavy metal layer;

[0026] After the thinning process, the thickness of the second heavy metal layer is less than or equal to half of the thickness of the first heavy metal layer.

[0027] In some optional implementations, after forming the magnetic tunnel junction on the second substrate, the method further comprises:

[0028] Depositing a heavy metal material on the magnetic tunnel junction to form an initial first heavy metal layer; wherein the initial first heavy metal layer and the second heavy metal layer are made of the same material but have different crystal phases;

[0029] The magnetic tunnel junction and the initial first heavy metal layer are annealed, and the initial first heavy metal layer is phase-changed into the second heavy metal layer.

[0030] In some optional implementations, a bonding process is used to bond the first heavy metal layer and the second heavy metal layer, and then the method further includes:

[0031] Etching the magnetic tunnel junction, the second heavy metal layer and the first heavy metal layer;

[0032] forming a protective layer on the sidewalls of the etched magnetic tunnel junction, the second heavy metal layer and the first heavy metal layer;

[0033] An interconnection structure is formed in the protection layer to electrically connect the first substrate to the outside.

[0034] In some optional implementations, before bonding the first heavy metal layer and the second heavy metal layer, the method further includes:

[0035] Using the second substrate as an etching stop layer, etching the magnetic tunnel junction and the second heavy metal layer;

[0036] forming a first protective layer on the sidewalls of the retained magnetic tunnel junction and the second heavy metal layer;

[0037] forming a first interconnect structure in the first protective layer to electrically connect the second substrate to the outside;

[0038] Etching the first heavy metal layer on the first substrate;

[0039] forming a second protective layer on the sidewalls of the retained first heavy metal layer;

[0040] A second interconnect structure is formed in the second protection layer to electrically connect the first substrate to the outside.

[0041] In some optional implementations, the first heavy metal layer and the second heavy metal layer are bonded using a bonding process, and the first interconnect structure is electrically connected to the second interconnect structure.

[0042] In the semiconductor device provided by the embodiment of the present application, a first heavy metal layer and a second heavy metal layer are stacked in sequence between a substrate and a magnetic tunnel junction, the materials of the first heavy metal layer and the second heavy metal layer are the same and the crystal phases are different, and the first heavy metal layer and the second heavy metal layer are bonded by a bonding process, and the free layer in the magnetic tunnel junction is arranged adjacent to the second heavy metal layer. After the annealing process, the lattice mismatch between the free layer and the second heavy metal layer can cause lattice stress in the free layer to induce a large coercive force and improve the stability of data storage in the device. The first heavy metal layer and the second heavy metal layer are separately manufactured and have different crystal phases, thereby avoiding the change of the crystal phase of the first heavy metal layer caused by high-temperature annealing, so that the semiconductor device can have both high-temperature annealing and a large spin conversion efficiency, thereby reducing the power consumption of the semiconductor device.

[0043] The method for preparing the semiconductor device provided in the embodiment of the present application has the same beneficial effects as the semiconductor device provided in the above embodiment, which will not be described in detail here.

[0044] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor device and the preparation method thereof provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 A schematic diagram of a structure in which a free layer of a semiconductor device provided in Embodiment 1 of the present application is a single-layer structure;

[0047] Figure 2 A schematic diagram of a structure in which a free layer of a semiconductor device provided in Embodiment 1 of the present application is a multi-layer composite structure;

[0048] Figure 3A schematic diagram of a structure in which a first heavy metal layer and a second heavy metal layer are partially combined in a semiconductor device provided in Embodiment 1 of the present application;

[0049] Figure 4 A schematic flow chart of a method for preparing a semiconductor device provided in Embodiment 2 of the present application;

[0050] Figure 5 This is a schematic diagram of the structure of forming a first heavy metal layer on a first substrate in Embodiment 2 of the present application;

[0051] Figure 6 This is a schematic diagram of the structure of forming an initial second heavy metal layer in Example 2 of the present application;

[0052] Figure 7 A schematic diagram of the structure of thinning the initial second heavy metal layer to form a second heavy metal layer in the second embodiment of the present application;

[0053] Figure 8 This is a schematic diagram of the structure of forming an initial first heavy metal layer in Example 2 of the present application;

[0054] Fig. 9 This is a schematic diagram of the structure after the first heavy metal layer and the second heavy metal layer are bonded in Example 2 of the present application;

[0055] Fig.10 for Fig. 9 A schematic diagram of a structure in which the second substrate is removed;

[0056] Fig.11 For Fig.10 A schematic diagram of the structure after etching the magnetic tunnel junction, the first heavy metal layer and the second heavy metal layer on the basis of FIG.

[0057] Fig.12 A schematic diagram of a structure in which a protective layer is formed on the side walls of the etched magnetic tunnel junction, the first heavy metal layer, and the second heavy metal layer;

[0058] Fig.13 This is a schematic diagram of a structure of a free layer of a multi-layer composite structure formed on a second substrate in Embodiment 3 of the present application;

[0059] Fig.14 This is a schematic diagram of the structure in which the second substrate is used as an etching stop layer in the fourth embodiment of the present application;

[0060] Fig.15 This is a schematic diagram of the structure of etching the first heavy metal layer in Embodiment 4 of the present application;

[0061] Fig.16 This is a schematic diagram of the structure after the first heavy metal layer and the second heavy metal layer are bonded in the fourth embodiment of the present application;

[0062] Fig.17This is a schematic diagram of the structure of the first heavy metal layer and the second heavy metal layer partially combined after bonding in the fourth embodiment of the present application;

[0063] Fig.18 for Fig.16 Schematic diagram of the structure after removing the substrate.

[0064] Reference numerals:

[0065] 10-Semiconductor devices;

[0066] 100 - substrate; 110 - first substrate; 120 - second substrate;

[0067] 200 - first heavy metal layer; 210 - initial first heavy metal layer;

[0068] 300 - second heavy metal layer; 310 - initial second heavy metal layer;

[0069] 400-magnetic tunnel junction;

[0070] 410 - free layer; 411 - first ferromagnetic layer; 412 - antiferromagnetic coupling layer; 413 - second ferromagnetic layer;

[0071] 420- tunneling layer;

[0072] 430-reference layer;

[0073] 440-pinning layer;

[0074] 450- oxide layer;

[0075] 500-protective layer; 510-first protective layer; 520-second protective layer;

[0076] 600 - interconnection structure; 610 - first interconnection structure; 620 - second interconnection structure. DETAILED DESCRIPTION

[0077] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of this application. Example

[0078] Please refer to Figures 1 to 3 As shown, an embodiment of the present application provides a semiconductor device 10, which may be a spin-orbit torque magnetic memory. The semiconductor device 10 is described below by taking the spin-orbit torque magnetic memory as an example.

[0079] The semiconductor device 10 provided in the embodiment of the present application may include a plurality of memory cells, and the plurality of memory cells may be arranged along a row and column array, or in other words, the plurality of memory cells may be arranged in a matrix form. Among them, the memory cells in the same row (or the same column) may be coupled to the same word line (word line, WL for short), and the memory cells in the same column (or the same row) may be coupled to the same group of bit lines (bit line, BL for short) and source lines (source line, SL for short). In other words, the memory cell may be a three-terminal device, and the memory cell may include a first end coupled to the word line, a second end coupled to the bit line, and a third end coupled to the source line.

[0080] In the embodiment of the present application, the storage unit at least includes a substrate 100, a heavy metal layer disposed on the substrate 100, and a magnetic tunnel junction 400 disposed on the heavy metal layer; the magnetic tunnel junction 400 at least includes a free layer 410, a tunnel layer 420 and a reference layer 430 stacked in sequence in a direction perpendicular to the substrate 100, the free layer 410 has a variable magnetic moment, the tunnel layer 420 allows spin electrons to tunnel through the insulating barrier, and the reference layer 430 has a fixed magnetic moment. When the magnetic moments of the free layer 410 and the reference layer 430 are parallel, the junction resistance of the magnetic tunnel junction 400 is low resistance, which can be represented by the binary number "0 ” indicates; when the magnetic moments of the free layer 410 and the reference layer 430 are antiparallel, the junction resistance of the magnetic tunnel junction 400 is high resistance, which can be represented by the binary number “1”; due to the spin-orbit moment effect, when current flows through the heavy metal layer, a spin-orbit moment is generated, and under the influence of the spin Hall effect and the Rashba effect, the charge flow is converted into a spin current, and the spin current then diffuses to the free layer 410. The magnetic moment of the free layer 410 is directional-reversed under the action of the spin current to realize data reading and writing. Since the write current does not pass through the tunnel layer 420, the SOT-MRAM has a longer service life.

[0081] The substrate 100 may be used as a basic support structure of the storage unit, and the substrate 100 may provide support for the structural layers stacked thereon. Exemplarily, the substrate 100 may be a silicon substrate 100, a germanium substrate 100, a silicon carbide substrate 100, a silicon germanium substrate 100, a germanium on insulator (GOI) substrate 100, or a silicon on insulator (SOI) substrate 100, etc.

[0082] In some embodiments, the magnetic tunnel junction 400 further includes a pinning layer 440 , which is disposed on a side of the reference layer 430 away from the tunneling layer 420 , and the pinning layer 440 is used to pin the magnetization direction of the reference layer 430 in a fixed direction.

[0083] As the process of the semiconductor device 10 is miniaturized, the coercive force (Hc) of the free layer 410 in the magnetic tunnel junction 400 will be affected, and the anti-magnetic properties of the magnetic tunnel junction 400 will deteriorate, causing the semiconductor device 10 to fail under the influence of a small magnetic field. It will also cause the thermal stability of the semiconductor device 10 to deteriorate, reducing the stability of data storage in the semiconductor device 10.

[0084] In order to improve the coercivity of the free layer 410 in the magnetic tunnel junction 400, the research found that by changing the crystal phase inside the heavy metal layer material, for example, when the heavy metal layer is made of a heavy metal material with an α crystal phase, the heavy metal layer is in contact with the free layer 410, the coercivity of the free layer 410 can be improved. Due to the lattice mismatch between the α crystal phase heavy metal layer and the free layer 410, strain is generated. The strain can affect the nucleation characteristics and magnetic domain structure of the material, and will introduce lattice stress, which can induce an increase in the coercivity of the free layer 410.

[0085] It should be noted that the crystal phase of a metal refers to the properties such as the grain composition and relative proportion of the metal. Grains are the basic structural units of metals, and different grain compositions will exhibit different mechanical and chemical properties.

[0086] Lattice mismatch, or lattice mismatch, refers to the different lattice constants of two substances, which will generate stress near the interface where the two substances contact, and then produce a crystal defect called lattice mismatch dislocation between the two substances.

[0087] Although the contact between the α-crystalline heavy metal layer and the free layer 410 can improve the coercive force of the free layer 410, the power consumption of the semiconductor device 10 is increased exponentially. For example, the spin-rotation efficiency of the α-crystalline heavy metal layer is more than five times lower than the spin-rotation rate of the β-crystalline heavy metal layer, which leads to an exponential increase in power consumption. If a β-crystalline heavy metal material is used as the heavy metal layer, due to the poor stability of the β-crystalline heavy metal layer, if it is grown together with the α-crystalline heavy metal layer, the α-crystalline heavy metal layer will induce the β-crystalline heavy metal layer to phase transform into the α-crystalline heavy metal layer. In addition, the crystal phase of the heavy metal layer is also related to the deposition thickness of the heavy metal layer. The thicker the heavy metal layer is, the more α-crystalline components there are, and the greater the power consumption of the semiconductor device 10.

[0088] For the above questions, please refer to Figure 1As shown, in an embodiment of the present application, a first heavy metal layer 200 and a second heavy metal layer 300 are arranged between a substrate 100 and a magnetic tunnel junction 400, and the first heavy metal layer 200, the second heavy metal layer 300 and the magnetic tunnel junction 400 are stacked in sequence on the substrate 100 along a direction perpendicular to the substrate 100, wherein the materials of the first heavy metal layer 200 and the second heavy metal layer 300 are the same and have different crystal phases, for example, the first heavy metal layer 200 is a heavy metal layer of β crystal phase, and the second heavy metal layer 300 is a heavy metal layer of α crystal phase, so that the first heavy metal layer 200 has a higher spin conversion efficiency; the materials of the first heavy metal layer 200 and the second heavy metal layer 300 include: tungsten, tantalum, tungsten-tantalum compounds and tungsten-tantalum alloys, etc.; and the spin conversion efficiency of the first heavy metal layer 200 is greater than the conversion efficiency of the second heavy metal layer 300; in addition, the resistivity of the first heavy metal layer 200 is greater than the resistivity of the second heavy metal layer 300.

[0089] Since the magnetic tunnel junction 400 needs to undergo high-temperature annealing to change the crystallization of the reference layer 430, when the magnetic tunnel junction 400 is subjected to high-temperature annealing, the lattice mismatch between the second heavy metal layer 300 and the reference layer 430 causes the free layer 410 to generate lattice stress, which can induce the free layer 410 to generate a large coercive force. The high-temperature annealing causes the first heavy metal layer 200 with a high spin conversion efficiency to undergo a phase change, so that the crystal phase of the first heavy metal layer 200 is the same as the crystal phase of the second heavy metal layer 300. Therefore, in order to avoid high-temperature annealing inducing changes in the crystal phase of the first heavy metal layer 200, in the embodiment of the present application, The first heavy metal layer 200 and the second heavy metal layer 300 are bonded by a bonding process instead of growing the first heavy metal layer 200 and the second heavy metal layer 300 together. In this way, the first heavy metal layer 200 and the second heavy metal layer 300 can be prevented from growing together, so that the second heavy metal layer 300 contacts the free layer 410 and induces the free layer 410 to generate a larger coercive force, thereby improving the anti-magnetic properties of the magnetic tunnel junction 400, so as to improve the stability of data storage in the semiconductor device 10. At the same time, the first heavy metal layer 200 maintains a relatively high spin polarization efficiency, thereby reducing the power consumption of the semiconductor device 10.

[0090] That is to say, under the high temperature annealing process, the crystal phase stability of the first heavy metal layer 200 is less than the crystal phase stability of the second heavy metal layer 300. Crystal phase stability refers to the ability of a crystal to maintain its crystal structure and composition unchanged under certain conditions. The crystal phase stability of the first heavy metal layer 200 is less than that of the second heavy metal layer 300, that is, under the same external influence, the ability of the first heavy metal layer 200 to maintain its existing crystal structure is weaker than the ability of the second heavy metal layer 300 to maintain its existing crystal structure. The crystal phase of the second heavy metal layer 300 remains unchanged during high temperature annealing, but the crystal phase of the first heavy metal layer 200 may be phase-changed to the same crystal phase as the first heavy metal layer 200. Therefore, the first heavy metal layer 200 needs to be annealed before the first heavy metal layer 200 and the second heavy metal layer 300 are bonded through a bonding process to avoid inducing a phase change in the crystal phase of the second heavy metal layer 300.

[0091] It can be seen that in the embodiment of the present application, the first heavy metal layer 200 and the second heavy metal layer 300 are bonded to each other through a bonding process. In this way, the problem of phase change of the crystal phase of the first heavy metal layer 200 at the high temperature annealing temperature is solved, thereby avoiding affecting the spin conversion efficiency of the first heavy metal layer 200. In addition, the overall annealing temperature of the magnetic tunnel junction 400 can be increased, thereby increasing the tunneling magnetic resistance and improving the performance of the semiconductor device 10.

[0092] In some embodiments, the thickness of the first heavy metal layer 200 is greater than the thickness of the second heavy metal layer 300. Since the thickness of the heavy metal layer and the process conditions will control the phase change of the heavy metal layer, the thickness of the first heavy metal layer 200 and the second metal layer can be controlled respectively so that the crystal phases of the first heavy metal layer 200 and the second heavy metal layer 300 are different, thereby ensuring the data storage stability of the semiconductor device 10 while reducing the power consumption of the semiconductor device 10.

[0093] Since the thickness of the heavy metal layer needs to be greater than or equal to 5nm to form a heavy metal layer of α crystal phase, the initial thickness of the second heavy metal layer needs to be greater than or equal to 5nm, and the thickness of the second heavy metal layer 300 after thinning is less than or equal to 2nm. In this way, the influence of the second heavy metal layer 300 on the spin efficiency can be reduced, so that the spin current of the first heavy metal layer 200 can be better transferred to the free layer 410, thereby improving the spin efficiency of the semiconductor device 10.

[0094] In addition, the first heavy metal layer 200 and the second heavy metal layer 300 are bonded to each other through a bonding process, and the second heavy metal layer 300 after the bonding process is partially or fully bonded to the first heavy metal layer 200, that is, along the direction perpendicular to the substrate 100, the projection of the first heavy metal layer 200 on the substrate 100 partially overlaps or fully overlaps with the projection of the second heavy metal layer 300 on the substrate 100.

[0095] An exemplary example is Figure 1 As shown in FIG. 1 , the first heavy metal layer 200 and the second heavy metal layer 300 are completely combined, that is, the sidewall of the first heavy metal layer 200 is flush with the sidewall of the second heavy metal layer 300 , so as to meet the performance requirements of the semiconductor device 10 .

[0096] Another exemplary example is Figure 2 As shown in the figure, the first heavy metal layer 200 and the second heavy metal layer 300 are partially combined, that is, in the direction perpendicular to the substrate 100, the projection of the first heavy metal layer 200 on the substrate 100 partially overlaps with the projection of the second heavy metal layer 300 on the substrate 100, and the first heavy metal layer 200 and the second heavy metal layer 300 are misaligned in the direction parallel to the substrate 100, so that the side walls of the first heavy metal layer 200 and the second heavy metal layer 300 are not flush, so that the first heavy metal layer 200 and the second heavy metal layer 300 are not flush. The metal layer 300 together forms a heavy metal layer with an asymmetric structure. In this way, when the charge flow passes through the heavy metal layer with an asymmetric structure, a non-uniform spin current will be generated due to the symmetry breaking. The non-uniform spin current helps to break the stability of the magnetic moment of the free layer 410 and realize fast field-free reversal. The spin current usually generated is perpendicular to the magnetic moment of the free layer 410, and it is difficult to realize the out-of-plane magnetic moment directional field-free reversal. The angle between the asymmetric spin current and the magnetic moment of the free layer 410 is an obtuse angle, which can realize the out-of-plane magnetic moment directional field-free reversal, thereby improving the reading and writing efficiency.

[0097] In some embodiments, please refer to Figure 2 and Figure 3 As shown in the figure, the free layer 410 is a composite layer. Exemplarily, the free layer 410 includes a first ferromagnetic layer 411, an antiferromagnetic coupling layer 412 and a second ferromagnetic layer 413, wherein the thickness of the first ferromagnetic layer 411 is less than the thickness of the second ferromagnetic layer 413, and the first ferromagnetic layer 411 is arranged between the second heavy metal layer 300 and the antiferromagnetic coupling layer 412. After the magnetic tunnel junction 400 is subjected to high-temperature annealing, due to the lattice mismatch between the second heavy metal layer 300 and the first ferromagnetic layer 411, the lattice distortion causes lattice stress, which can induce a large coercive force. Due to the blocking of the antiferromagnetic coupling layer 412, the second ferromagnetic layer 413 does not produce lattice distortion and can be better crystallized, thereby improving the tunneling magnetoresistance.

[0098] Among them, the materials of the first ferromagnetic layer 411 and the second ferromagnetic layer 413 include but are not limited to one or more ferromagnetic metal materials and alloy materials such as Co, Fe, Ni, CoFe, NiFe, CoFeB, etc.; the material of the antiferromagnetic coupling layer 412 is one or more non-magnetic metals and their alloys with antiferromagnetic coupling effect such as Ru, Ir, W, Ta, etc.

[0099] The thickness of the first ferromagnetic layer 411 can be greater than, less than or equal to the thickness of the second ferromagnetic layer 413, which will not affect the second heavy metal layer 300 inducing the first ferromagnetic layer 411 to generate a large coercive force, and no specific restrictions are made on the thickness relationship between the first ferromagnetic layer 411 and the second ferromagnetic layer 413. The preferred solution is that the thickness of the first ferromagnetic layer 411 is less than the thickness of the second ferromagnetic layer 413. At this time, the first ferromagnetic layer 411 is thin and the overall magnetic moment is small, which makes it easier to flip, and can further reduce the flip current and reduce the power consumption of the device.

[0100] It should be noted that the “first ferromagnetic layer 411 ” and the “second ferromagnetic layer 413 ” are merely exemplary expressions, and the number of ferromagnetic layers in the storage unit includes but is not limited to two. In actual use, the number of ferromagnetic layers can be adjusted according to actual needs, which will not be elaborated here.

[0101] In some embodiments, Figures 1 to 3 As shown in the figure, a protective layer 500 covering the surface of the magnetic tunnel junction 400 is provided on the outer wall surface of the magnetic tunnel junction 400, that is, the protective layer 500 covers the side surface of the magnetic tunnel junction 400 facing away from the substrate 100 and the side wall of the magnetic tunnel junction 400 to protect the outline of the magnetic tunnel junction 400.

[0102] In addition, if Figures 1 to 3 As shown in , the semiconductor device 10 further includes an interconnection structure 600, and the interconnection structure 600 penetrates the protective layer 500 and is electrically connected to the substrate 100, so that the substrate 100 is electrically connected to the outside through the interconnection structure 600. Among them, the interconnection structure 600 can be a structure such as an interconnection conductive column formed by a conductive material such as metal copper, gold, silver, etc., as long as it can realize the electrical connection between the substrate 100 and the external circuit, and is not limited here. Example

[0103] Please refer to Figure 4 As shown, an embodiment of the present application provides a method for preparing a semiconductor device, which can be used to prepare the semiconductor structure provided in the above embodiment, and the preparation method specifically includes:

[0104] Step S101: forming a first heavy metal layer on a first substrate.

[0105] When implementing it, please combine Figure 5As shown, first, a first substrate 110 is provided. The first substrate 110 may be a logic substrate or other substrate containing internal circuits, and a first heavy metal layer 200 is grown on the first substrate 110 .

[0106] Exemplarily, heavy metal material can be deposited on the first substrate 110 by magnetron sputtering to form a first heavy metal layer 200 having a β-crystalline phase; wherein the thickness of the first heavy metal layer 200 is preferably greater than or equal to 5 nm, so that the first heavy metal layer 200 has a higher spin-on efficiency.

[0107] Step S102: forming a stacked magnetic tunnel junction and a second heavy metal layer on a second substrate, wherein the first heavy metal layer and the second heavy metal layer are made of the same material but have different crystal phases; a free layer in the magnetic tunnel junction is arranged adjacent to the second heavy metal layer, and after annealing, the free layer and the second heavy metal layer are lattice mismatched so that lattice stress is generated in the free layer.

[0108] Specifically, after the first heavy metal layer 200 is formed on the first substrate 110, a second substrate 120 independent of the first substrate 110 is provided again. The second substrate 120 can be used as a temporary growth substrate. The material of the second substrate can be a semiconductor material, such as silicon, silicon carbide, gallium nitride, aluminum nitride, etc., or an insulating material, such as germanium.

[0109] In some embodiments, please refer to Figure 6 As shown, an oxide layer 450, a pinned layer 440, a reference layer 430, a tunneling layer 420 and a free layer 410 are sequentially grown on the second substrate 120, wherein the pinned layer 440, the reference layer 430, the tunneling layer 420 and the free layer 410 together form a magnetic tunnel junction 400 of a bottom pinned structure, and then a second heavy metal layer 300 is formed on the magnetic tunnel junction 400 of the bottom pinned structure.

[0110] In some embodiments, Figure 6 As shown in , the material of the free layer 410 includes but is not limited to at least one of cobalt (Co), iron (Fe), boron (B), nickel (Ni), ruthenium (Ru), iridium (Ir), and platinum (Pt).

[0111] There are many ways to form the second heavy metal layer 300 on the magnetic tunnel junction 400 of the bottom pinned structure. The following will illustrate the formation of the second heavy metal layer 300 through different embodiments with reference to the accompanying drawings.

[0112] In some embodiments, a heavy metal material is deposited on the magnetic tunnel junction 400 of the bottom pinned structure to form an initial second heavy metal layer 310, wherein the crystal phase of the initial second heavy metal layer 310 is an α crystal phase, and the thickness of the initial second heavy metal layer 310 is greater than or equal to 5 nm. Thereafter, the initial second heavy metal layer 310 and the magnetic tunnel junction 400 are subjected to a high-temperature annealing treatment, wherein the annealing temperature can be increased, thereby increasing the tunneling magnetic resistance of the magnetic tunnel junction 400 and also changing the crystallization of the reference layer 430, so that the free layer 410 is lattice mismatched with the second heavy metal layer 300, so that the free layer 410 generates lattice stress to induce the free layer 410 to generate a large coercive force, thereby improving the anti-magnetic properties of the magnetic tunnel junction 400.

[0113] Exemplarily, the thickness of the initial second heavy metal layer 310 is greater than the thickness of the first heavy metal layer 200 , so that during the annealing process, a larger coercive force is induced in the free layer 410 .

[0114] Since the initial second heavy metal layer 310 after annealing has induced the free layer 410 to generate a large coercive force, please combine Figure 7 As shown, the initial second heavy metal layer 310 after annealing is thinned by a thinning process to reduce the thickness of the initial second heavy metal layer 310 from greater than or equal to 5 nm to less than or equal to 2 nm (eg, Figure 7 As shown in ), the thinned initial second heavy metal layer 310 is formed into a second heavy metal layer 300, wherein, after the thinning process, the thickness of the formed second heavy metal layer 300 is less than the thickness of the first heavy metal layer 200, so as to reduce the influence of the second heavy metal layer 300 on the spin-to-polarization efficiency, so that the spin current of the first heavy metal layer 200 can be better transferred to the free layer 410, thereby improving the spin-to-polarization efficiency of the semiconductor device 10.

[0115] The thinning process includes but is not limited to a chemical mechanical polishing process. Of course, an etching process may also be used, as long as the initial second heavy metal layer 310 can be thinned, and no limitation is made here.

[0116] In other embodiments, please combine Figure 8As shown, a heavy metal material is deposited on the magnetic tunnel junction 400 to form an initial first heavy metal layer 210; wherein the initial first heavy metal layer 210 is made of the same material as the second heavy metal layer 300 and has a different crystal phase, and the thickness of the initial first heavy metal layer 210 is less than the thickness of the first heavy metal layer 200. For example, the thickness of the initial first heavy metal layer 210 is less than or equal to 2 nm. After the initial first heavy metal layer 210 is formed, the magnetic tunnel junction 400 and the initial first heavy metal layer 210 are annealed, and the initial first heavy metal layer 210 is phase-changed into the second heavy metal layer 300. It can be seen that in the embodiment of the present application, by forming a thin initial first heavy metal layer 210 on the magnetic tunnel junction 400 and performing an annealing process, the initial first heavy metal layer 210 undergoes a crystal phase change during the annealing process to form the second heavy metal layer 300, thereby forming a second heavy metal layer 300 having the same thickness as the first heavy metal layer 210. Figure 7 The same structure shown in FIG. 1 does not require a thinning process, but directly prepares the thickness of the initial first heavy metal layer 210 to be formed as the thickness of the second heavy metal layer 300 to be formed subsequently, thereby reducing the thinning process and reducing the process cost.

[0117] Step S103: performing bonding treatment on the first heavy metal layer and the second heavy metal layer so that the first heavy metal layer and the second heavy metal layer are partially or completely bonded.

[0118] Please combine Fig. 9 As shown, after the second heavy metal layer 300 is formed on the magnetic tunnel junction 400, a bonding process is used to bond the second heavy metal layer 300 to the first heavy metal layer 200, and the second heavy metal layer 300 is arranged on the first heavy metal layer 200. In this way, after the bonding process, the magnetic tunnel junction 400 of the bottom pinned structure is formed into a top pinned magnetic tunnel junction 400, that is, the second heavy metal layer 300 is arranged on the first heavy metal layer 200, the magnetic tunnel junction 400 is arranged above the second heavy metal layer 300, and the second substrate 120 is arranged above the magnetic tunnel junction 400.

[0119] Step S104: removing the second substrate.

[0120] Please combine Fig.10 As shown, after the second heavy metal layer 300 and the first heavy metal layer 200 are bonded by a bonding process, a debonding process or a chemical mechanical polishing process is used to remove the second substrate 120 to facilitate subsequent processing.

[0121] After removing the second substrate 120, the first substrate 110 has a first heavy metal layer 200 with high self-spin efficiency, the first heavy metal layer 200 has a second heavy metal layer 300 that can induce the free layer 410 to generate a large coercive force, and the magnetic tunnel junction 400 with a top pinning structure is arranged on the second heavy metal layer 300. Since the first heavy metal layer 200 and the second heavy metal layer 300 are bonded to each other through a bonding process, the problem of phase change of the crystal phase of the first heavy metal layer 200 at a high temperature annealing temperature is solved, thereby avoiding affecting the self-spin efficiency of the first heavy metal layer 200. In addition, the second heavy metal layer 300 can induce the free layer 410 to generate a large coercive force. At the same time, the overall annealing temperature of the magnetic tunnel junction 400 can also be increased, thereby increasing the tunneling magnetoresistance and improving the performance of the semiconductor device 10.

[0122] Please combine Fig.11 As shown, after the first heavy metal layer 200 and the second heavy metal layer 300 are bonded by a bonding process, the magnetic tunnel junction 400, the second heavy metal layer 300 and the first heavy metal layer 200 can be etched by an etching process to shrink the size of the magnetic tunnel junction 400, the second heavy metal layer 300 and the first heavy metal layer 200 so that the size of the magnetic tunnel junction 400, the second heavy metal layer 300 and the first heavy metal layer 200 reaches the target size to meet the size requirements of the semiconductor device 10.

[0123] Please combine Fig.12 As shown, after the magnetic tunnel junction 400, the second heavy metal layer 300 and the first heavy metal layer 200 are etched, an atomic layer deposition process, a chemical deposition process or a physical deposition process can be used to form a protective layer 500 on the side walls of the etched magnetic tunnel junction 400, the second heavy metal layer 300 and the first heavy metal layer 200, so as to protect the surface profile of the magnetic tunnel junction 400, the second heavy metal layer 300 and the first heavy metal layer 200 through the protective layer 500, wherein the material of the protective layer 500 includes but is not limited to dielectric materials such as SiO, SiN, SiON, etc.

[0124] Please combine Figure 1 As shown, after a protective layer 500 is formed on the side walls of the etched magnetic tunnel junction 400, the second heavy metal layer 300 and the first heavy metal layer 200, an etching process can be used to etch an interconnection hole on the protective layer 500, and the interconnection hole penetrates the protective layer 500 in a direction perpendicular to the first substrate 110 to expose the first substrate 110, and a conductive material such as metal tungsten is deposited in the interconnection hole to form an interconnection structure 600, so that the first substrate 110 is electrically connected to an external circuit through the interconnection structure 600, thereby controlling the current to pass through the first heavy metal layer 200, realizing the directional flipping of the free layer 410, and realizing the reading and writing of data. Example

[0125] The only difference from the above-mentioned embodiment 2 is the structure of the free layer 410. The free layer 410 in the above-mentioned embodiment 2 is a single-layer structure, while the structure of the free layer 410 in the embodiment of the present application is a multi-layer composite structure. Other structures and preparation methods can refer to the above-mentioned embodiment 2 and will not be repeated here.

[0126] When the free layer 410 is a multi-layer composite structure, for example, Fig.13 As shown in the figure, the free layer 410 includes a first ferromagnetic layer 411, an antiferromagnetic coupling layer 412 and a second ferromagnetic layer 413, that is, the second ferromagnetic layer 413, the antiferromagnetic coupling layer 412 and the first ferromagnetic layer 411 are sequentially formed on the second substrate 120, and then the second heavy metal layer 300 is formed on the first ferromagnetic layer 411, wherein the thickness of the first ferromagnetic layer 411 is less than the thickness of the second ferromagnetic layer 413, and the first ferromagnetic layer 411 is arranged between the second heavy metal layer 300 and the antiferromagnetic coupling layer 412. Between the magnetic coupling layers 412, after the magnetic tunnel junction 400 is subjected to high-temperature annealing, due to the lattice mismatch between the second heavy metal layer 300 and the first ferromagnetic layer 411, the lattice distortion causes lattice stress, which can induce a large coercive force. Due to the blocking of the antiferromagnetic coupling layer 412, the lattice transmission of the first ferromagnetic layer 411 through the tunneling layer 420 can be avoided, and the second ferromagnetic layer 413 does not produce lattice distortion, so that the second ferromagnetic layer 413 can be better crystallized, thereby improving the tunneling magnetic resistance.

[0127] Among them, the materials of the first ferromagnetic layer 411 and the second ferromagnetic layer 413 include but are not limited to one or more ferromagnetic metal materials and alloy materials such as Co, Fe, Ni, CoFe, NiFe, CoFeB, etc.; the material of the antiferromagnetic coupling layer 412 is one or more non-magnetic metals and their alloys with antiferromagnetic coupling effect such as Ru, Ir, W, Ta, etc.

[0128] It should be noted that the thickness of the first ferromagnetic layer 411 can be greater than or less than or equal to the thickness of the second ferromagnetic layer 413, which will not affect the second heavy metal layer 300 inducing the first ferromagnetic layer 411 to generate a large coercive force, and no specific restrictions are made on the thickness relationship between the first ferromagnetic layer 411 and the second ferromagnetic layer 413. A preferred solution is that the thickness of the first ferromagnetic layer 411 is less than the thickness of the second ferromagnetic layer 413. At this time, the first ferromagnetic layer 411 is thin and the overall magnetic moment is small, which makes it easier to flip, and can further reduce the flip current and reduce the power consumption of the device. Example

[0129] The present embodiment only describes the preparation steps that are different from the above-mentioned embodiment 2, and the same preparation steps are not repeated here.

[0130] It should be noted that the free layer 410 in the magnetic tunnel junction 400 in the embodiment of the present application can be a single-layer structure as in the first embodiment, or a multi-layer composite structure as in the second embodiment. The free layer 410 as a multi-layer composite structure will be introduced as an example below.

[0131] Please combine Figures 14 to 18 As shown, in the embodiment of the present application, after forming the first heavy metal layer 200 on the first substrate 110, and forming the stacked magnetic tunnel junction 400 and the second heavy metal layer 300 on the second substrate 120, before the first heavy metal layer 200 and the second heavy metal layer 300 are bonded by a bonding process, as shown in FIG. Fig.14 As shown in , an etching process is adopted, and the second substrate 120 is used as an etching stop layer to etch the magnetic tunnel junction 400 and the second heavy metal layer 300 on the second substrate 120 so that the magnetic tunnel junction 400 and the second heavy metal layer 300 reach the target size, and there is no need to worry about over-etching causing a short circuit in the heavy metal layer, so that the etching process window can be enlarged and the process difficulty can be reduced; then, an oxide layer 450 is deposited on the sidewalls of the retained magnetic tunnel junction 400 and the second heavy metal layer 300 to form a first protective layer 510, and a first interconnection hole penetrating the first protective layer 510 is formed on the first protective layer 510 in a direction perpendicular to the second substrate 120, and a conductive material such as metal tungsten is deposited in the first interconnection hole to form a first interconnection structure 610 in the first protective layer 510; as shown in Fig.15 As shown in , the first heavy metal layer 200 on the first substrate 110 is etched by an etching process to etch the size of the first heavy metal layer 200 to the target size of the magnetic tunnel junction 400, and an oxide material is deposited on the surface of the etched first heavy metal layer 200 to form a second protective layer 520. Then, an etching process is used on the second protective layer 520 to form a second interconnection hole penetrating the second protective layer 520 in a direction perpendicular to the first substrate 110. Then, a conductive material such as metal tungsten is deposited in the second interconnection hole to form a second interconnection structure 620. Then, as shown in Fig.16 and Fig.17 As shown in , a bonding process is used to bond the first heavy metal layer 200 and the second heavy metal layer 300, and the first interconnect structure 610 is electrically connected to the second interconnect structure 620. During bonding, the first heavy metal layer 200 and the second heavy metal layer 300 may be partially or fully bonded, as shown in FIG. Fig.16 In the embodiment, the first heavy metal layer 200 and the second heavy metal layer 300 are all combined; Fig.17 In the embodiment, the first heavy metal layer 200 and the second heavy metal layer 300 are partially combined; after the bonding process, please refer to Fig.18 and Figure 3As shown, the second substrate 120 is removed so that the first substrate 110 is electrically connected to the outside through the first interconnect structure 610 and the second interconnect structure 620, thereby controlling the current to pass through the first heavy metal layer 200, achieving directional flipping of the free layer 410, and realizing data reading and writing.

[0132] It should be noted that the first heavy metal layer 200 and the second heavy metal layer 300 are partially combined, that is, the first heavy metal layer 200 and the second heavy metal layer 300 are misaligned in a direction parallel to the substrate 100, so that the side walls of the first heavy metal layer 200 and the second heavy metal layer 300 are not flush, so that the first heavy metal layer 200 and the second heavy metal layer 300 together form a heavy metal layer with an asymmetric structure. In this way, when the charge flow passes through the heavy metal layer with an asymmetric structure, a non-uniform spin current will be generated due to the symmetry breaking. The non-uniform spin current helps to break the magnetic moment stability of the free layer 410 to achieve rapid field-free reversal, thereby improving the reading and writing efficiency.

[0133] In summary, in the semiconductor device provided by the embodiment of the present application, a first heavy metal layer and a second heavy metal layer are stacked in sequence between a substrate and a magnetic tunnel junction, the materials of the first heavy metal layer and the second heavy metal layer are the same and the crystal phases are different, and the first heavy metal layer and the second heavy metal layer are bonded by a bonding process, and the free layer in the magnetic tunnel junction is arranged adjacent to the second heavy metal layer. After the annealing process, the lattice mismatch between the free layer and the second heavy metal layer can cause lattice stress in the free layer to induce a large coercive force and improve the stability of data storage in the device. The first heavy metal layer and the second heavy metal layer are separately manufactured and have different crystal phases, which avoids the change of the crystal phase of the first heavy metal layer caused by high-temperature annealing, so that the semiconductor device can have both high-temperature annealing and a large spin conversion efficiency, thereby reducing the power consumption of the semiconductor device.

[0134] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0135] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: At least: A substrate, and a first heavy metal layer, a second heavy metal layer and a magnetic tunnel junction sequentially stacked on the substrate; Wherein, the first heavy metal layer and the second heavy metal layer are made of the same material but have different crystal phases, and the first heavy metal layer and the second heavy metal layer are bonded by a bonding process; The free layer in the magnetic tunnel junction is arranged adjacent to the second heavy metal layer, and after annealing, the free layer and the second heavy metal layer have a lattice mismatch, so that the free layer generates lattice stress; The spin conversion efficiency of the first heavy metal layer is greater than the spin conversion efficiency of the second heavy metal layer; and under the annealing process, the crystal phase stability of the first heavy metal layer is less than the crystal phase stability of the second heavy metal layer.

2. The semiconductor device according to claim 1, wherein: The resistivity of the first heavy metal layer is greater than the resistivity of the second heavy metal layer.

3. The semiconductor device according to claim 1, wherein: The thickness of the first heavy metal layer is greater than the thickness of the second heavy metal layer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: After the bonding process, the second heavy metal layer is partially or completely bonded to the first heavy metal layer.

5. A method for preparing a semiconductor device, characterized in that: include: forming a first heavy metal layer on a first substrate; forming a stacked magnetic tunnel junction and a second heavy metal layer on a second substrate; Wherein, the first heavy metal layer and the second heavy metal layer are made of the same material but have different crystal phases; The free layer in the magnetic tunnel junction is arranged adjacent to the second heavy metal layer, and after annealing, the free layer and the second heavy metal layer are lattice mismatched, so that the free layer generates lattice stress, and the spin conversion efficiency of the first heavy metal layer is greater than the spin conversion efficiency of the second heavy metal layer; under the annealing process, the crystal phase stability of the first heavy metal layer is less than the crystal phase stability of the second heavy metal layer; performing bonding treatment on the first heavy metal layer and the second heavy metal layer so that the first heavy metal layer and the second heavy metal layer are partially or completely bonded; The second substrate is removed.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: After forming the magnetic tunnel junction on the second substrate, the method comprises: depositing a heavy metal material on the magnetic tunnel junction to form an initial second heavy metal layer; Annealing the magnetic tunnel junction and the initial second heavy metal layer; performing a thinning process on the initial second heavy metal layer to form a second heavy metal layer; wherein the thickness of the initial second heavy metal layer is greater than the thickness of the first heavy metal layer; After the thinning process, the thickness of the second heavy metal layer is less than or equal to half of the thickness of the first heavy metal layer.

7. The method for preparing a semiconductor device according to claim 5, characterized in that: After forming the magnetic tunnel junction on the second substrate, the method comprises: Depositing a heavy metal material on the magnetic tunnel junction to form an initial first heavy metal layer; wherein the initial first heavy metal layer and the second heavy metal layer are made of the same material but have different crystal phases; The magnetic tunnel junction and the initial first heavy metal layer are annealed, and the initial first heavy metal layer is phase-changed into the second heavy metal layer.

8. The method for preparing a semiconductor device according to claim 5, characterized in that: The first heavy metal layer and the second heavy metal layer are bonded by a bonding process, and then the method further includes: Etching the magnetic tunnel junction, the second heavy metal layer and the first heavy metal layer; forming a protective layer on the sidewalls of the etched magnetic tunnel junction, the second heavy metal layer and the first heavy metal layer; An interconnection structure is formed in the protection layer to electrically connect the first substrate to the outside.

9. The method for preparing a semiconductor device according to claim 5, characterized in that: Before bonding the first heavy metal layer and the second heavy metal layer, the method further includes: Using the second substrate as an etching stop layer, etching the magnetic tunnel junction and the second heavy metal layer; forming a first protective layer on the sidewalls of the retained magnetic tunnel junction and the second heavy metal layer; forming a first interconnect structure in the first protective layer to electrically connect the second substrate to the outside; Etching the first heavy metal layer on the first substrate; forming a second protective layer on the sidewalls of the retained first heavy metal layer; A second interconnect structure is formed in the second protection layer to electrically connect the first substrate to the outside.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The first heavy metal layer and the second heavy metal layer are bonded by a bonding process, and the first interconnection structure is electrically connected to the second interconnection structure.

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