Semiconductor device and stack structure

Abstract

A semiconductor device according to one embodiment of the present disclosure includes: a semiconductor chip provided with a first pad, a first wiring, and a first insulating film; a second insulating film disposed on the semiconductor chip and having a flat surface; and a second pad disposed on the second insulating film and made of a metal material. The second pad is electrically connected to the first pad or the first wiring, and is provided up to the surface of the second insulating film.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and stacked structures. Background Art

[0002] There has been proposed a unit having a semiconductor substrate and a memory chip connected through a first redistribution portion, a first connection pad, a bump, a second connection pad, and a second redistribution portion.

[0003] Citation list

[0004] Patent Literature

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2019-68049 Summary of the invention

[0006] What is required of semiconductor devices is to allow bonding between metal electrodes.

[0007] It is desirable to provide a semiconductor device suitable for bonding between metal electrodes.

[0008] A semiconductor device according to an embodiment of the present disclosure includes: a semiconductor chip including a first pad, a first wiring and a first insulating film; a second insulating film provided on the semiconductor chip and having a flat surface; and a second pad provided on the second insulating film and including a metal material. The second pad is electrically connected to the first pad or the first wiring and is provided up to the surface of the second insulating film.

[0009] A stacked structure according to an embodiment of the present disclosure includes: a semiconductor substrate; a wiring layer stacked on the semiconductor substrate; and a semiconductor device stacked on the wiring layer. The semiconductor device includes: a semiconductor chip including a first pad, a first wiring and a first insulating film; a second insulating film disposed on the semiconductor chip and having a flat surface; and a second pad disposed on the second insulating film and containing a metal material. The second pad is electrically connected to the first pad or the first wiring and is disposed up to the surface of the second insulating film. The wiring layer has a third pad bonded to the second pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram showing a schematic configuration example of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram for explaining a configuration example of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 3is a diagram for explaining a configuration example of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 4A is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 4B is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 4C is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 4D is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 4E is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 5A is a diagram showing a configuration example of a semiconductor device according to a first modification example of the present disclosure.

[0019] Figure 5B is a diagram showing another configuration example of the semiconductor device according to the first modification example of the present disclosure.

[0020] Figure 5C is a diagram showing another configuration example of the semiconductor device according to the first modification example of the present disclosure.

[0021] Fig. 6A is a diagram showing a configuration example of a semiconductor device according to a second modification example of the present disclosure.

[0022] Figure 6B is a diagram showing another configuration example of the semiconductor device according to the second modification example of the present disclosure.

[0023] Figure 6C is a diagram showing another configuration example of the semiconductor device according to the second modification example of the present disclosure.

[0024] Fig.6D is a diagram showing another configuration example of the semiconductor device according to the second modification example of the present disclosure.

[0025] Fig. 7A is a diagram showing a configuration example of a semiconductor device according to a third modification example of the present disclosure.

[0026] Figure 7B is a diagram showing another configuration example of a semiconductor device according to a third modification example of the present disclosure.

[0027] Fig. 8A is a diagram showing a configuration example of a semiconductor device according to a fourth modification example of the present disclosure.

[0028] Figure 8B is a diagram showing another configuration example of a semiconductor device according to a fourth modification example of the present disclosure.

[0029] Fig. 9 is a diagram showing a configuration example of a semiconductor device according to a fifth modification example of the present disclosure.

[0030] Fig.10 is a diagram showing another configuration example of a semiconductor device according to a fifth modification example of the present disclosure.

[0031] Fig.11A 1 is a diagram for explaining a layout example of redistribution wiring of a semiconductor device according to a fifth modification example of the present disclosure.

[0032] Fig. 11B 1 is a diagram for explaining a layout example of redistribution wiring of a semiconductor device according to a fifth modification example of the present disclosure.

[0033] Fig. 11C 1 is a diagram for explaining a layout example of redistribution wiring of a semiconductor device according to a fifth modification example of the present disclosure. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The description will be made in the following order.

[0035] 1. Implementation Plan

[0036] 2. Modifications

[0037] 2-1. First Modification

[0038] 2-2. Second Modification

[0039] 2-3. Third Modification

[0040] 2-4. Fourth Modification

[0041] 2-5. Fifth Modification

[0042] <1. Implementation Plan>

[0043] Figure 1 is a diagram showing a schematic configuration example of a semiconductor device according to an embodiment of the present disclosure. Figure 1 FIG. 2 shows an example of a cross-sectional structure of the semiconductor device 1. Figure 1As shown, the semiconductor device 1 includes a semiconductor chip 10 and a redistribution layer 40. Examples of the semiconductor chip 10 include processors, memories, sensors, and other integrated circuits. As examples, the semiconductor chip 10 may be a general purpose memory, general purpose logic, or custom designed chip.

[0044] For example, the semiconductor chip 10 may be a general-purpose memory such as DRAM (dynamic random access memory), SRAM (static random access memory), or MRAM (magnetic random access memory). In addition, the semiconductor chip 10 may be a general-purpose logic such as DSP (digital signal processor) or FPGA (field programmable gate array).

[0045] As an example, the rewiring layer 40 may be formed on a semiconductor chip 10 of a finished product such as a general-purpose memory or a general-purpose logic. Figure 1 The semiconductor device 1 shown in FIG. The pads of the semiconductor chip 10 and the pads of the redistribution layer 40 are electrically connected to each other.

[0046] The semiconductor device 1 has a configuration in which the semiconductor chip 10 and the redistribution layer 40 are stacked in the Z-axis direction. Figure 1 As shown, the left-right direction of the paper plane perpendicular to the Z-axis direction is defined as the X-axis direction, and the direction perpendicular to the Z-axis and the X-axis is defined as the Y-axis direction. Figure 1 The direction of the arrow indicates the direction.

[0047] The semiconductor chip 10 includes a first substrate 101, a wiring layer 111, and a protective film 80. The first substrate 101 is composed of a semiconductor substrate (e.g., a silicon substrate). Various circuit elements constituting the semiconductor chip 10, such as transistors, diodes, resistors, and capacitors, may be formed on the first substrate 101. The first substrate 101 may include a compound semiconductor material.

[0048] The wiring layer 111 is provided on the upper surface of the first substrate 101. The wiring layer 111 includes, for example, a conductive film and an insulating film, and includes a plurality of wirings, vias (VIA), etc. The wiring layer 111 includes, for example, two or more layers of wirings. The wiring layer 111 has, for example, a configuration in which a plurality of wirings are stacked and an insulating film is interposed therebetween.

[0049] The wiring layer 111 includes aluminum (Al), copper (Cu), tungsten (W), polysilicon (Poly-Si), etc. The insulating film includes, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc. The insulating film may also be referred to as an interlayer insulating film (interlayer insulating layer). The first substrate 101 and the wiring layer 111 may be collectively referred to as the first substrate 101 (or the first circuit layer).

[0050] like Figure 1As shown, the protective film 80 is provided on the wiring layer 111. The protective film 80 is a passivation film (protective layer), and is formed to cover the entire surface of the wiring layer 111. It should be noted that the semiconductor chip 10 may not have the protective film 80.

[0051] exist Figure 1 In the example shown, the semiconductor chip 10 includes an insulating film 91 and an insulating film 92. For example, the insulating film 91 and the insulating film 92 are respectively composed of a single-layer film including one of an oxide film (e.g., a silicon oxide film), a nitride film (e.g., a silicon nitride film), and a nitride oxide film, or a stacked film composed of two or more of these films. The insulating film 92 is stacked on the insulating film 91. The protective film 80 is formed on the insulating film 92.

[0052] Figure 1 The wiring 17 shown is, for example, a wiring containing aluminum (Al). It should be noted that the wiring 17 may contain other metal materials. A plurality of wirings 17 are formed in the insulating film 92 and on the insulating film 91. The respective wirings 17 are spaced apart from each other in the X-axis direction. Figure 1 In the example shown, the plurality of wirings 17 are constituted by the uppermost wiring in the wiring layer 111 .

[0053] The wiring 17 is a power wiring, a GND (ground) wiring, a signal transmission wiring, etc. It should be noted that a plurality of wirings 17 may be arranged side by side with air gaps interposed therebetween. Providing air gaps between adjacent wirings 17 makes it possible to reduce parasitic capacitance added to the wirings 17.

[0054] In the semiconductor chip 10, a pad 15 (PAD) is provided. The pad 15 is, for example, an electrode containing aluminum. It should be noted that the pad 15 may contain other metal materials. In the semiconductor chip 10, a plurality of pads 15 electrically connected to circuit elements in the semiconductor chip 10 are provided. Figure 1 The pad 15 shown is located on the insulating film 91 and is formed inside the insulating film 92 .

[0055] In the semiconductor chip 10, an opening 25 is formed on the pad 15, and the pad 15 is partially exposed through the opening 25. The opening 25 is defined by the end surface of each of the protective film 80 and the insulating film 92. The opening 25 is a hole (through hole) that penetrates the protective film 80 and the insulating film 92. It should be noted that the pad 15 can be referred to as a pad electrode, and the opening 25 can also be referred to as a pad opening. The pad 15 can also be referred to as a terminal (connection terminal) of the semiconductor chip 10.

[0056] A plurality of pads 15 may be provided on the semiconductor chip 10. For example, the plurality of pads 15 may include a power pad and a GND pad, and may supply a power voltage and a GND voltage (ground voltage) to each circuit of the semiconductor chip 10.

[0057] In addition, for example, the plurality of pads 15 of the semiconductor chip 10 may include pads for transmitting signals to the outside. For example, the plurality of pads 15 include input / output pads for inputting and outputting signals, input pads for inputting signals from the outside of the semiconductor chip 10, output pads for outputting signals to the outside of the semiconductor chip 10, etc.

[0058] The rewiring layer 40 includes, for example, a conductor film and an insulating film, and includes a plurality of rewirings, vias, etc. The rewiring layer 40 includes one or more layers of rewiring. The rewiring layer 40 may have a structure in which wiring is stacked and an insulating film is interposed therebetween. The rewiring as the wiring of the rewiring layer 40 contains aluminum, copper, etc. The rewiring is, for example, a wiring for electrical connection between the circuit of the semiconductor chip 10 and an external circuit.

[0059] exist Figure 1 In the example shown, the rewiring layer 40 includes the via hole 21, the via hole 22, the rewiring 31, the pad (referred to as the connection pad 35), and the insulating film 95. It should be noted that the number and arrangement of the pad 15, the connection pad 35, the via hole 21, the via hole 22, the rewiring 31, etc. are not limited to the example shown. Figure 1 Only one pad 15 and one connection pad 35 are shown in FIG. 1 , but a plurality of pads 15 and a plurality of connection pads 35 may be provided in the semiconductor device 1 .

[0060] The via 21 electrically connects the pad 15 and the redistribution line 31. The via 21 contains, for example, tungsten (W), aluminum (Al), cobalt (Co), etc. The via 21 is formed between the pad 15 of the semiconductor chip 10 and the redistribution line 31. Figure 1 As shown, vias 21 are arranged around opening 25 .

[0061] The via hole 21 extends in the Z-axis direction around the opening 25, and is provided to penetrate a portion of the protective film 80 and a portion of the insulating film 92. The via hole 21 penetrates a portion of the protective film 80 and a portion of the insulating film 92, and connects the pad 15 and the redistribution wiring 31. The via hole 21 is formed from the redistribution wiring 31 to the pad 15, and a portion of the via hole 21 is provided in the wiring layer 111.

[0062] The via 22 electrically connects the connection pad 35 and the redistribution line 31. The via 22 contains, for example, tungsten, aluminum, cobalt, etc. The via 22 is formed between the connection pad 35 and the redistribution line 31, and connects the connection pad 35 and the redistribution line 31.

[0063] In the semiconductor device 1, as Figure 1As shown, the size of via 21 is larger than that of via 22. The width of via 21 in the X-axis direction is larger than that of via 22 in the X-axis direction. The diameter of via 21 is, for example, 1 μm or more. By connecting relatively large via 21 to pad 15, the contact characteristics with pad 15 can be ensured.

[0064] For example, the connection pad 35 is an electrode containing copper (Cu). In the redistribution layer 40 of the semiconductor device 1, for example, a plurality of connection pads 35 are provided corresponding to the number of pads 15 of the semiconductor chip 10. The connection pad 35 may contain a metal material other than copper, such as nickel (Ni), cobalt (Co), tin (Sn), gold (Au), etc.

[0065] like Figure 1 As shown, the connection pad 35 is electrically connected to the pad 15 of the semiconductor chip 10 and is provided up to the surface S1 (end surface) of the insulating film 95. The connection pad 35 is provided in the insulating film 95 and reaches the surface S1 of the insulating film 95. That is, the connection pad 35 is located up to the surface S1 of the insulating film 95. Figure 1 In the illustrated example, the connection pad 35 is electrically connected to the pad 15 via the redistribution wiring 31. The connection pad 35 is an electrode for bonding between metal electrodes, and functions as a bonding electrode.

[0066] like Figure 1 As shown, the insulating film 95 is provided on the semiconductor chip 10 and has a flat surface S1. The insulating film 95 is composed of, for example, a single-layer film including one of an oxide film, a nitride film, an oxynitride film, etc., or a stacked film including two or more of these films. The via 22, the redistribution 31, and a portion of the via 21 are provided in the insulating film 95.

[0067] The connection pad 35 is arranged so that the surface (end face) of the connection pad 35 is exposed from the insulating film 95. The connection pad 35 is arranged up to the surface S1 (end face) of the insulating film 95, and serves as a pad exposed to the outside from the insulating film 95. As described above, the surface S1 of the insulating film 95 has a flat shape. Therefore, bonding between metal electrodes can be performed by using the connection pad 35 as a metal electrode.

[0068] For example, the semiconductor chip 10 and other semiconductor chips are bonded to each other by bonding between metal electrodes containing Cu, that is, by Cu-Cu bonding. The other semiconductor chips include processors, memories, sensors, any other integrated circuits, etc. For example, the other semiconductor chips are general-purpose memories, general-purpose logic, or custom-designed chips.

[0069] Figure 2 is a diagram for explaining a configuration example of a semiconductor device according to the embodiment. Figure 2The example in which the semiconductor chip 10 and the semiconductor chip 20 having the light receiving element 51 are bonded by bonding between metal electrodes is schematically shown. The semiconductor device 1 has a configuration in which the semiconductor chip 10 including the first substrate 101 and the semiconductor chip 20 including the second substrate 102 are stacked in the Z-axis direction. The first substrate 101 and the second substrate 102 are each composed of a semiconductor substrate (e.g., a silicon substrate).

[0070] like Figure 2 As shown, the first substrate 101 has a first surface 11S1 and a second surface 11S2, and the second substrate 102 has a first surface 12S1 and a second surface 12S2. For example, each of the first surfaces 11S1 and 12S1 is a component formation surface on which components such as transistors are formed. Gate electrodes, gate oxide films, etc. are provided on each of the first surfaces 11S1 and 12S1. As described above, the wiring layer 111 is provided on the first surface 11S1 of the first substrate 101.

[0071] The second substrate 102 is provided with a plurality of pixels P, each of which has a light receiving element 51. The light receiving element 51 (light receiving portion) of each pixel P is, for example, a photodiode, and can receive light and generate charge by photoelectric conversion. The light receiving element 51 is a photoelectric conversion portion, and is configured to allow photoelectric conversion of light.

[0072] On the second surface 11S2 side of the second substrate 102, for example, a lens 56 for converging light, a filter 55, etc. are provided for each pixel P. The filter 55 is configured to selectively transmit light of a specific wavelength range in the incident light. The filter 55 is, for example, an RGB color filter, a filter that transmits infrared light, etc.

[0073] like Figure 2 As shown, the wiring layer 121 is provided on the first surface 12S1 of the second substrate 102. The wiring layer 121 includes, for example, a conductor film and an insulating film, and includes a plurality of wirings, vias, etc. The wiring layer 121 includes, for example, two or more layers of wirings. The wiring layer 121 has, for example, a configuration in which a plurality of wirings are stacked and an insulating film is interposed therebetween.

[0074] The wiring layer 121 includes aluminum, copper, tungsten, polysilicon, etc. The insulating film includes, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. It should be noted that the second substrate 102 and the wiring layer 121 may be collectively referred to as the second substrate 102 (or second circuit layer).

[0075] exist Figure 2In the example shown, the wiring layer 121 includes a via 62, a pad (referred to as a connection pad 65), and an insulating film 97. It should be noted that the number and arrangement of the connection pad 65 and the via 62 are not limited to the example shown. The via 62 electrically connects the connection pad 65 and the wiring of the wiring layer 121. The via 62 contains, for example, tungsten, aluminum, cobalt, etc.

[0076] The connection pad 65 is an electrode including, for example, copper (Cu). The connection pad 65 may include a metal material other than copper, such as nickel, cobalt, tin, gold, etc. Figure 2 As shown, the connection pads 65 are electrically connected to the internal circuit of the semiconductor chip 20 , and are provided up to the surface S2 of the insulating film 97 .

[0077] exist Figure 2 In the example shown, the connection pad 65 is electrically connected to the internal circuit of the semiconductor chip 20 via the via 62. The connection pad 65 is an electrode for bonding between metal electrodes, and functions as a bonding electrode.

[0078] Insulating film 97 has a flat surface S2 similar to surface S1 of insulating film 95 of semiconductor chip 10. Insulating film 97 is composed of, for example, a single layer film including one of oxide film, nitride film, oxynitride film, etc., or a stacked film including two or more of these films.

[0079] The connection pad 65 is arranged so that the surface (end face) of the connection pad 65 is exposed from the insulating film 97. The connection pad 65 is arranged up to the surface S2 (end face) of the insulating film 97, and serves as a pad exposed to the outside from the insulating film 97. The connection pad 65 is arranged in the insulating film 97 and reaches the surface S2 of the insulating film 97. That is, the connection pad 65 is located up to the surface S2 of the insulating film 97. As described above, the surface S2 of the insulating film 97 has a flat shape.

[0080] The semiconductor chips 10 and 20 are stacked so that the first surface 11S1 of the first substrate 101 and the first surface 12S1 of the second substrate 102 are opposite to each other through the bonding between the metal electrodes. The first substrate 101 and the second substrate 102 are connected to each other by bonding the plurality of connection pads 35 in the insulating film 95 and the plurality of connection pads 65 in the insulating film 97.

[0081] As described above, in the present embodiment, the semiconductor chip is provided with an insulating film having a flat surface and a connection pad. In this way, a plurality of semiconductor chips can be stacked by bonding (e.g., Cu-Cu bonding) between metal electrodes. Compared with the case of stacking semiconductor chips using bumps, stacking semiconductor chips by Cu-Cu bonding makes it possible to promote miniaturization.

[0082] Furthermore, in this embodiment, various semiconductor chips including general-purpose products can be bonded. Figure 2 In the present invention, for example, a semiconductor chip 20 having a light receiving element and a semiconductor chip 10 such as a general-purpose memory or a general-purpose logic may be stacked to realize a high-performance semiconductor device 1 .

[0083] It should be noted that if Figure 3 As schematically shown, there is a case where the needle trace 16 is generated in the pad 15 of the semiconductor chip 10. For example, during the inspection process of the semiconductor chip 10, the probe (needle) P1 indicated by the dotted line contacts the pad 15 in the opening 25, causing the pad 15 to rise and fall and forming the needle trace 16. The needle trace 16 of the pad 15 has a shape including, for example, concavities and convexities. Therefore, it is difficult to set the via 21 in the opening 25.

[0084] Therefore, in the present embodiment, as described above, the via hole 21 is formed in the area around the opening 25, and is connected to the pad 15. Therefore, the via hole 21 can be formed with high precision, and insufficient contact with the pad 15 can be prevented.

[0085] FIG. 4A to FIG. 4E is a diagram showing an exemplary manufacturing process of a semiconductor device according to an embodiment. Figure 4A As shown in FIG. 1 , a semiconductor chip 10 such as a general-purpose memory is prepared. Next, as shown in FIG. Figure 4B As shown in FIG. 1 , an insulating film 95 is formed on the semiconductor chip 10. Thereafter, as shown in FIG. Figure 4C As shown, unnecessary portions of the insulating film 95 are removed by CMP (Chemical Mechanical Polishing).

[0086] Next, if Figure 4D As shown, a groove (hole) is formed by photolithography and etching, and metal plating is performed to form a via hole 21. Figure 4D As shown in FIG. 2 , a redistribution line 31 is formed on the via hole 21. Thereafter, as shown in FIG. Figure 4E As shown, the insulating film 95 is formed, and the via hole 22 and the connection pad 35 are formed. The connection pad 35 is exposed on the flat surface S1 of the insulating film 95.

[0087] It can be manufactured by the above manufacturing method Figure 1 The semiconductor device 1 is shown. It should be noted that the above-mentioned manufacturing method is merely an example, and any other manufacturing method may be adopted.

[0088] [Function and Effect]

[0089] The semiconductor device (semiconductor device 1) according to the present embodiment includes: a semiconductor chip (semiconductor chip 10) including a first pad (pad 15), a first wiring (wiring 17) and a first insulating film (insulating film 92 and insulating film 91); a second insulating film (insulating film 95) provided on the semiconductor chip and having a flat surface; and a second pad (connecting pad 35) provided on the second insulating film and containing a metal material. The second pad is electrically connected to the first pad or the first wiring and is provided up to the surface of the second insulating film.

[0090] In the semiconductor device 1 according to the present embodiment, the insulating film 95 having a flat surface and the connection pad 35 are provided on the semiconductor chip 10. Therefore, it is possible to perform bonding between metal electrodes, such as Cu-Cu bonding, using various semiconductor chips such as general-purpose memories, etc. A semiconductor device suitable for bonding between metal electrodes can be provided.

[0091] Next, a modification of the present disclosure will be described. Hereinafter, the same components as those in the above-described embodiment are denoted by the same reference numerals, and description thereof will be appropriately omitted.

[0092] [2. Modifications]

[0093] (2-1. First Modification)

[0094] In the above-described embodiments, the configuration example of the semiconductor device has been described, but the configuration of the semiconductor device is not limited thereto. Figure 5A 1 is a diagram showing a configuration example of a semiconductor device according to a first modification example of the present disclosure. Figure 5A As shown, the via hole 21 may be disposed in the opening 25 . The via hole 21 extends in the Z-axis direction in the opening 25 and is connected to the pad 15 .

[0095] In the above-described embodiment, an example has been described in which the connection pad 35 is electrically connected to the pad 15 , but the connection pad 35 may be electrically connected to the wiring of the wiring layer 111 . Figure 5B and Figure 5C 1 is a diagram showing another configuration example of a semiconductor device according to the first modification. Figure 5B As shown, the connection pad 35 can be electrically connected to the wiring 17 of the wiring layer 111. Figure 5B In the illustrated embodiment, the connection pad 35 is electrically connected to the wiring 17 in the insulating film 92 through the via 22 , the redistribution wiring 31 , and the via 21 .

[0096] In addition, if Figure 5C As shown, the connection pad 35 can be electrically connected to the wiring 18 of the wiring layer 111. The wiring 18 is located within the insulating film 91 and is provided in a layer different from the pad 15 and the wiring 17. Figure 5C In the illustrated embodiment, the connection pad 35 is electrically connected to the wiring 18 in the insulating film 91 through the via 22, the redistribution wiring 31, and the via 21. Also in the case of this modification, effects similar to those of the above-described embodiment can be obtained.

[0097] (2-2. Second Modification)

[0098] FIG. 6A to FIG. 6D 1 is a diagram showing a configuration example of a semiconductor device according to a second modification. The connection pad 35 may be directly connected to the pad 15 or the wiring of the wiring layer 111. For example, Fig. 6A As shown, the connection pad 35 can be directly connected to the pad 15. Fig. 6A In the illustrated embodiment, the connection pad 35 is provided around the opening 25. The connection pad 35 extends in the Z-axis direction around the opening 25 and is connected to the pad 15. The connection pad 35 is also a via connected to the pad 15 and is also a pad suitable for bonding.

[0099] like Figure 6B As shown, the connection pad 35 may be disposed in the opening 25. The connection pad 35 extends in the Z-axis direction in the opening 25 and is connected to the pad 15. In addition, for example, Figure 6C As shown, the connection pad 35 can be directly connected to the wiring 17 in the insulating film 92 of the wiring layer 111. Fig.6D As shown, the connection pad 35 can be directly connected to the wiring 18 in the insulating film 91 of the wiring layer 111. Also in the case of this modification, effects similar to those of the above-described embodiment can be obtained.

[0100] (2-3. Third Modification)

[0101] The redistribution layer 40 of the semiconductor device 1 may have a structure in which insulating films are stacked. Fig. 7A 1 is a diagram showing a configuration example of a semiconductor device according to a third modification example. Fig. 7A As shown in FIG. 1 , the rewiring layer 40 includes an insulating film 95a, an insulating film 96, and an insulating film 95b having a flat surface S1. A portion of the connection pad 35 is disposed within the insulating film 96. Figure 7B As shown in the example of , the connection pad 35 may be directly connected to the pad 15. In addition, the connection pad 35 may be directly connected to the wiring of the wiring layer 111.

[0102] (2-4. Fourth Modification)

[0103] Fig. 8A and Figure 8B 1 is a diagram showing a configuration example of a semiconductor device according to a fourth modification. Fig. 8A and Figure 8B As shown in FIG. 1 , the protective film 80 may not be provided in the semiconductor device 1. It should be noted that, for example, the connection pad 35 may be formed as shown in FIG. Fig. 8A As in the example shown, the pad 15 may be connected by a redistribution wiring 31, or may be connected by a redistribution wiring 31 as in the example shown. Figure 8B The connection is made directly to pad 15 as in the example shown.

[0104] (2-5. Fifth Modification)

[0105] The redistribution layer 40 of the semiconductor device 1 may have multiple layers of redistribution. Fig. 9 4 is a diagram showing a configuration example of a semiconductor device according to a fifth modification. The redistribution layer 40 has two layers of redistribution (in Fig. 9 The redistribution lines 31 and 32 are provided in different layers from each other. Fig. 9 The via 23 shown electrically connects the redistribution line 31 and the redistribution line 32. The connection pad 35 is electrically connected to the pad 15 through the via 22, the redistribution line 32, the via 23, the redistribution line 31, and the via 21.

[0106] It should be noted that the semiconductor device 1 may include a capacitive element formed by a plurality of redistributions of the redistribution layer 40 . Fig.10 is a diagram showing another configuration example of a semiconductor device according to a fifth modification. Fig.10 In the example shown, the redistribution layer 40 includes redistribution lines 31, 32a, and 32b. Fig.10 As shown, the rewiring 31 and the rewiring 32b are arranged to face each other, and the semiconductor device 1 includes a capacitive element composed of the rewiring 31 and the rewiring 32b facing each other. Therefore, for example, a capacitor between the rewiring 31 and the rewiring 32b can be added between the power pad and the GND pad.

[0107] FIG. 11A to FIG. 11C 1 is a diagram for explaining a layout example of redistribution wiring of a semiconductor device according to a fifth modification. Fig.11A As shown, the common pads (terminals) can be electrically connected through the redistribution wiring. For example, the common pads 15a and 15c used as power supply pads (or GND pads) can be electrically connected through the redistribution wiring 31a.

[0108] In addition, as described above, the capacitor element may be formed by a plurality of redistribution lines. Fig. 11B As shown in the example of , the redistribution wiring 31a and the redistribution wiring 31c may be arranged in a comb shape to provide a capacitive element. Fig. 11B In the illustrated example, for example, a capacitor composed of the redistribution wiring 31 a and the redistribution wiring 31 c may be connected between the pad 15 a as a power supply pad and the pad 15 c as a GND pad.

[0109] It should be noted that multiple redistributions can be used to form an inductor. Fig. 11C In the example shown, the redistribution wirings 31a, 31b, 31c are formed in a spiral shape, and the semiconductor device 1 includes an inductor constituted by the redistribution wirings formed in a spiral shape. The inductor can be formed for any pad.

[0110] Although the present disclosure has been described with reference to the embodiments and the modified examples, the present technology is not limited to the above-described embodiments, etc., and various modifications are possible. For example, as a modified example of the above-described embodiment, the above modified example has been described, but the configurations of the modified examples can be appropriately combined.

[0111] A semiconductor device according to an embodiment of the present disclosure includes: a semiconductor chip including a first pad, a first wiring and a first insulating film; a second insulating film, which is arranged on the semiconductor chip and has a flat surface; and a second pad, which is arranged on the second insulating film and contains a metal material. The second pad is electrically connected to the first pad or the first wiring and is arranged all the way to the surface of the second insulating film. Therefore, various semiconductor chips such as general-purpose memories can be used to perform bonding between metal electrodes (e.g., Cu-Cu bonding). A semiconductor device suitable for bonding between metal electrodes can be provided.

[0112] It should be noted that the effects described in this specification are only examples, and the description thereof is not restrictive. Other effects may also be provided. In addition, the present disclosure may have the following configurations. (1)

[0114] A semiconductor device comprising:

[0115] a semiconductor chip including a first pad, a first wiring, and a first insulating film;

[0116] a second insulating film provided on the semiconductor chip and having a flat surface; and

[0117] A second pad is provided on the second insulating film and comprises a metal material, wherein

[0118] The second pad is electrically connected to the first pad or the first wiring, and is provided up to the surface of the second insulating film. (2)

[0120] The semiconductor device according to (1), further comprising a redistribution line provided in the second insulating film, wherein

[0121] The second pad is electrically connected to the first pad via the redistribution line. (3)

[0123] The semiconductor device according to (2), further comprising:

[0124] a first via electrically connecting the first pad and the redistribution line; and

[0125] A second via electrically connecting the second pad and the redistribution line, wherein

[0126] A size of the first via hole is greater than a size of the second via hole. (4)

[0128] The semiconductor device according to any one of (1) to (3), wherein the first insulating film is provided to cover at least a portion of each of the first pad and the first wiring. (5)

[0130] The semiconductor device according to any one of (1) to (4), wherein

[0131] The first insulating film has an opening disposed on the first pad, and

[0132] The first via hole is disposed around the opening. (6)

[0134] The semiconductor device according to (5), wherein the first pad has a stitch within the opening. (7)

[0136] The semiconductor device according to any one of (1) to (6), wherein

[0137] The first insulating film has an opening disposed on the first pad, and

[0138] The first via hole is disposed in the opening. (8)

[0140] The semiconductor device according to any one of (1) to (7), wherein

[0141] The first pad and the first wiring are provided in different layers from each other, and

[0142] The second pad is electrically connected to the first wiring. (9)

[0144] The semiconductor device according to any one of (1) to (8), further comprising a third insulating film provided between the semiconductor chip and the second insulating film, wherein

[0145] At least a portion of the second pad is disposed within the third insulating film. (10)

[0147] The semiconductor device according to any one of (1) to (9), further comprising first redistribution wiring and second redistribution wiring provided in layers different from each other, wherein

[0148] The second pad is electrically connected to the first pad via the first redistribution line and the second redistribution line. (11)

[0150] The semiconductor device according to any one of (1) to (10), further comprising a capacitance element constituted by a first redistribution wiring and a second redistribution wiring opposed to each other, wherein

[0151] The first redistribution line and the second redistribution line are electrically connected to pads different from each other. (12)

[0153] The semiconductor device according to any one of (1) to (11), further comprising an inductor composed of redistribution wiring formed in a spiral shape, wherein

[0154] The second pad is electrically connected to the first pad via the redistribution line. (13)

[0156] The semiconductor device according to any one of (1) to (12), wherein

[0157] The first insulating film has an opening disposed on the first pad, and

[0158] The second pad is directly connected to the first pad around the opening. (14)

[0160] The semiconductor device according to any one of (1) to (13), wherein

[0161] The first insulating film has an opening disposed on the first pad, and

[0162] The second pad is directly connected to the first pad within the opening. (15)

[0164] The semiconductor device according to any one of (1) to (14), wherein the second pad is directly connected to the first wiring. (16)

[0166] The semiconductor device according to any one of (1) to (15), wherein the second pad includes copper. (17)

[0168] The semiconductor device according to any one of (1) to (16), wherein the semiconductor chip includes a plurality of the first wirings, and air gaps are provided between the plurality of first wirings. (18)

[0170] The semiconductor device according to any one of (1) to (17), wherein the second insulating film includes at least one of an oxide film and a nitride film. (19)

[0172] The semiconductor device according to any one of (1) to (18) further includes a protective film provided between the first insulating film and the second insulating film. (20)

[0174] The semiconductor device according to any one of (1) to (19), wherein the semiconductor chip includes a general-purpose memory, a general-purpose logic, or a custom-designed chip. (twenty one)

[0176] A stacking structure, comprising:

[0177] Semiconductor substrates;

[0178] a wiring layer stacked on the semiconductor substrate; and

[0179] a semiconductor device stacked on the wiring layer,

[0180] The semiconductor device comprises:

[0181] a semiconductor chip including a first pad, a first wiring, and a first insulating film;

[0182] a second insulating film provided on the semiconductor chip and having a flat surface; and

[0183] A second pad is provided on the second insulating film and comprises a metal material, wherein

[0184] The second pad is electrically connected to the first pad or the first wiring and is provided up to the surface of the second insulating film, and

[0185] The wiring layer has a third pad bonded to the second pad. (twenty two)

[0187] The stacked structure according to (21), wherein the semiconductor substrate includes a photoelectric conversion portion.

[0188] This application claims priority from Japanese Priority Patent Application JP2022-106529 filed with the Japan Patent Office on June 30, 2022, the entire contents of which are incorporated herein by reference.

[0189] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may be made according to design requirements and other factors within the scope of the appended claims or the equivalents thereof.

Claims

1. A semiconductor device comprising: a semiconductor chip including a first pad, a first wiring, and a first insulating film; a second insulating film disposed on the semiconductor chip and having a flat surface; as well as A second pad is provided on the second insulating film and comprises a metal material, wherein The second pad is electrically connected to the first pad or the first wiring, and is provided up to the surface of the second insulating film.

2. The semiconductor device according to claim 1, further comprising a redistribution line provided in the second insulating film, wherein The second pad is electrically connected to the first pad via the redistribution line.

3. The semiconductor device according to claim 2, further comprising: a first via electrically connecting the first pad and the redistribution line; as well as A second via electrically connecting the second pad and the redistribution line, wherein A size of the first via hole is greater than a size of the second via hole. 4 . The semiconductor device according to claim 3 , wherein the first insulating film is provided to cover at least a portion of each of the first pad and the first wiring.

5. The semiconductor device according to claim 3, wherein The first insulating film has an opening disposed on the first pad, and The first via hole is disposed around the opening. The semiconductor device according to claim 5 , wherein the first pad has a stitch within the opening.

7. The semiconductor device according to claim 3, wherein The first insulating film has an opening disposed on the first pad, and The first via hole is disposed in the opening.

8. The semiconductor device according to claim 1, wherein The first pad and the first wiring are provided in different layers from each other, and The second pad is electrically connected to the first wiring.

9. The semiconductor device according to claim 1, further comprising a third insulating film provided between the semiconductor chip and the second insulating film, wherein At least a portion of the second pad is disposed within the third insulating film.

10. The semiconductor device according to claim 1, further comprising first redistribution wiring and second redistribution wiring provided in layers different from each other, wherein The second pad is electrically connected to the first pad via the first redistribution line and the second redistribution line.

11. The semiconductor device according to claim 1, further comprising a capacitance element constituted by a first redistribution wiring and a second redistribution wiring opposed to each other, wherein The first redistribution line and the second redistribution line are electrically connected to pads different from each other.

12. The semiconductor device according to claim 1, further comprising an inductor composed of redistribution wiring formed in a spiral shape, wherein The second pad is electrically connected to the first pad via the redistribution line.

13. The semiconductor device according to claim 1, wherein The first insulating film has an opening disposed on the first pad, and The second pad is directly connected to the first pad around the opening.

14. The semiconductor device according to claim 1, wherein The first insulating film has an opening disposed on the first pad, and The second pad is directly connected to the first pad within the opening. 15 . The semiconductor device according to claim 1 , wherein the second pad is directly connected to the first wiring. The semiconductor device according to claim 1 , wherein the second pad comprises copper. 17 . The semiconductor device according to claim 1 , wherein the semiconductor chip includes a plurality of the first wirings, and air gaps are provided between the plurality of first wirings.

18. The semiconductor device according to claim 1, wherein the second insulating film includes at least one of an oxide film and a nitride film. 19 . The semiconductor device according to claim 1 , further comprising a protective film provided between the first insulating film and the second insulating film.

20. The semiconductor device according to claim 1, wherein the semiconductor chip comprises a general-purpose memory, a general-purpose logic, or a custom-designed chip.

21. A stacking structure comprising: Semiconductor substrates; a wiring layer stacked on the semiconductor substrate; as well as a semiconductor device stacked on the wiring layer, The semiconductor device comprises: a semiconductor chip including a first pad, a first wiring, and a first insulating film; a second insulating film provided on the semiconductor chip and having a flat surface; and A second pad is provided on the second insulating film and comprises a metal material, wherein The second pad is electrically connected to the first pad or the first wiring and is provided up to the surface of the second insulating film, and The wiring layer has a third pad bonded to the second pad. 22 . The stacked structure according to claim 21 , wherein the semiconductor substrate includes a photoelectric conversion portion.

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