Drive circuit and drive method for power semiconductor element, and power module

Abstract

In a drive circuit (1000) for a power semiconductor element (8), a first gate voltage control circuit (10) controls a gate voltage (Vg) of the power semiconductor element (8) in a different manner in the order of a first time region (RG1), a second time region (RG2), and a third time region (RG3) in response to an ON command, thereby causing the gate voltage (Vg) to reach a Miller voltage (Vm). The gate voltage (Vg) reaches the Miller voltage (Vm) in the second time region (RG2) or the third time region (RG3) in accordance with the magnitude of the main current flowing through the power semiconductor element (8). A second gate voltage control circuit (4) controls a gate voltage (Vg) that is equal to or greater than the Miller voltage (Vm).

Description

Technical Field

[0001] The present disclosure relates to a driving circuit and a driving method for a power semiconductor element, and a power module. Background Art

[0002] Power semiconductor devices that control large amounts of power are used, for example, in power supply circuits that generate alternating current (AC) of varying frequencies from DC and AC, and in power conversion devices including these circuits. When power semiconductor devices are used in power conversion devices such as inverters, suppressing power consumption is important from the perspectives of energy conservation and greenhouse gas reduction.

[0003] Japanese Patent Application Publication No. 2008-519529 (Patent Document 1) discloses a method for reducing energy consumed in a power semiconductor element by controlling the switching operation of the power semiconductor element.

[0004] Specifically, the document discloses the following method: "A method for driving a power transistor switch, comprising: a stage of receiving a drive input signal; a stage of converting the drive input signal into a converted drive input signal; and a stage of providing the converted drive input signal to a control electrode of the switch to turn on the switch, wherein the converted drive input signal has three time-related regions, each of which has a slope, a first region being a time period during which a first slope exists until a Miller Plateau of the switch, a second region being a time period during which a second slope smaller than the first slope exists, and a third region being a time period during which a third slope larger than the second slope exists, thereby causing the control electrode voltage to rapidly reach the Miller Plateau voltage, then to reach the threshold voltage of the switch at a lower speed, and then to rapidly increase when the switch is almost completely turned on. By adjusting the precharge voltage of the transistor control electrode, the switch delay time is maintained substantially constant" (refer to the abstract of Japanese Patent Application Publication No. 2008-519529).

[0005] Patent Document 1: Japanese Patent Application No. 2008-519529 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] The control method for a power semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2008-519529 (Patent Document 1) reduces EMI (electromagnetic interference) by reducing the current change rate (dI / dt) during switching. However, when the current I flowing through the power semiconductor device is large, controlling the current change rate to reduce the current change rate leads to a problem in which switching losses are increased due to increased switching time. This patent document does not address this issue.

[0008] The present disclosure has been made in consideration of the above-mentioned problems, and one of its objects is to provide a drive circuit for a power semiconductor element that can suppress switching loss even when a relatively large current flows through the power semiconductor element.

[0009] Solutions for solving problems

[0010] A drive circuit for a power semiconductor device according to one embodiment includes a first gate voltage control circuit and a second gate voltage control circuit. The first gate voltage control circuit, in response to a power semiconductor device turn-on command, controls the gate voltage of the power semiconductor device in different ways, sequentially in a first time period, a second time period, and a third time period, thereby causing the gate voltage to reach the Miller voltage. The gate voltage reaches the Miller voltage in the second time period or the third time period, depending on the magnitude of the main current flowing through the power semiconductor device. The second gate voltage control circuit controls the gate voltage to be greater than the Miller voltage.

[0011] Effects of the Invention

[0012] According to the above-described embodiment, the drive circuit controls the gate voltage of the power semiconductor element in a different manner in the order of the first time period, the second time period, and the third time period in response to a turn-on command for the power semiconductor element, thereby causing the gate voltage to reach the Miller voltage. This reduces switching losses even when a relatively large current flows through the power semiconductor element. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a block diagram showing the configuration of a drive circuit for a power semiconductor element according to the first embodiment.

[0014] Figure 2 This is a diagram showing an example of the configuration of a voltage limiting circuit.

[0015] Figure 3 This is a diagram showing an example of the configuration of the first variable voltage generating circuit.

[0016] Figure 4 This is a diagram showing an example of the configuration of the first variable voltage generating circuit.

[0017] Figure 5 1 is a diagram showing an example of the configuration of the second variable voltage generating circuit.

[0018] Figure 6 1 is a diagram showing an example of the configuration of the second variable voltage generating circuit.

[0019] Figure 7 This is a diagram showing an example of the configuration of a comparison circuit.

[0020] Figure 8 This is a diagram showing an example of the configuration of an adding circuit.

[0021] Figure 9 This is a diagram showing an example of the configuration of a buffer circuit.

[0022] Figure 10 This is a diagram showing an example of the configuration of a buffer circuit.

[0023] Figure 11 This is a diagram showing an example of the configuration of a buffer circuit.

[0024] Figure 12 This is a diagram showing an example of the structure of a power semiconductor element.

[0025] Figure 13 This is a timing chart for explaining a first operation example of the driving circuit of the power semiconductor element according to the first embodiment.

[0026] Figure 14 This is a timing chart for explaining a second operation example of the driving circuit of the power semiconductor element according to the first embodiment.

[0027] Figure 15 This is a flowchart showing a control procedure when the power semiconductor element is turned on by the drive circuit of the first embodiment.

[0028] Figure 16 This is a diagram showing an example of how the drive circuit according to the first embodiment is mounted.

[0029] Figure 17 Yes Figure 16 FIG. 1 is a diagram showing a modified example of the installation method.

[0030] Figure 18 This is a diagram showing another example of how the drive circuit of the first embodiment is mounted.

[0031] Figure 19 Yes Figure 18 FIG. 1 is a diagram showing a modified example of the installation method.

[0032] Figure 20 This is a diagram showing a configuration of a drive circuit for a power semiconductor element according to a second embodiment.

[0033] Figure 21 1 is a diagram showing an example of the configuration of a Miller voltage detection circuit.

[0034] Figure 22 This is a diagram showing an example of the configuration of a differentiating circuit.

[0035] Figure 23 This is a diagram showing an example of the configuration of a differentiating circuit.

[0036] Figure 24 This is a diagram showing an example of the configuration of a binarization circuit.

[0037] Figure 25 This is a diagram showing an example of the configuration of an edge detection circuit.

[0038] Figure 26 This is a diagram showing an example of the structure of a flip-flop circuit.

[0039] Figure 27 This is an example of the structure of an inverting circuit.

[0040] Figure 28 This is a timing chart for explaining an operation example of the power semiconductor driving circuit according to the second embodiment.

[0041] Figure 29 This is a flowchart showing a control procedure when the power semiconductor element is turned on by the drive circuit of the second embodiment.

[0042] (Explanation of Reference Numerals)

[0043] 1: Voltage limiting circuit; 2: First variable voltage generating circuit; 3: Second variable voltage generating circuit; 4: Comparator circuit (second gate voltage control circuit); 5: Adder circuit; 6: Buffer circuit; 7: UN, UP control input terminals; 8: Power semiconductor element; 9: Miller voltage detection circuit; 10: First gate voltage control circuit; 11: Zener diode; 41: Comparator; 42: Comparison voltage source; 61, 63: Bipolar transistors; 65, 916: Operational amplifier; 82: Freewheeling diode; 91: Differentiator circuit; 92: Binarization circuit; 93: Edge detection circuit; 94: trigger circuit; 95, 931: inversion circuit; 921: inversion-type Schmitt trigger circuit; 932: delay circuit; 1000, 2000: drive circuit; 10000, 10000a, 10000b, 10000c: power module; RG1~RG4: first time zone to fourth time zone; SL1~SL4: first slope to fourth slope; VL: limit voltage; V1: first change voltage; V2: second change voltage; VC: comparison voltage; Vg: gate voltage; Vm: Miller voltage; Vref: reference potential; Vth: threshold voltage. DETAILED DESCRIPTION

[0044] Hereinafter, each embodiment will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and their description will not be repeated.

[0045] Implementation method 1.

[0046] [Structure of a drive circuit for a power semiconductor device]

[0047] Figure 1 1 is a block diagram showing the configuration of a drive circuit 1000 for a power semiconductor element according to Embodiment 1. The drive circuit 1000 generates a gate voltage Vg for controlling the switching operation of the power semiconductor element 8 in accordance with a control signal input to the control input terminal 7. More specifically, the drive circuit 1000 sequentially adjusts the voltage change of the gate voltage Vg during the on-operation of the power semiconductor element 8 in the first time region ( Figure 13 、 Figure 14 RG1) to the fourth time zone ( Figure 13 、 Figure 14 In the following description, the first to fourth time zones are also simply referred to as the first to fourth zones.

[0048] like Figure 1 As shown, the drive circuit 1000 includes a voltage limiting circuit 1, a first variable voltage generating circuit 2, a second variable voltage generating circuit 3, a comparison circuit 4, an adder circuit 5, and a buffer circuit 6. The voltage limiting circuit 1, the first variable voltage generating circuit 2, the second variable voltage generating circuit 3, the adder circuit 5, and the buffer circuit 6 are collectively referred to as a first gate voltage control circuit 10. In response to an on-command, the first gate voltage control circuit 10 controls the gate voltage Vg of the power semiconductor device 8 in a different manner in the order of the first time region RG1, the second time region RG2, and the third time region RG3, thereby causing the gate voltage Vg to reach the Miller voltage Vm. The gate voltage Vg reaches the Miller voltage Vm in the second region RG2 or the third region RG3. The comparison circuit 4, serving as the second gate voltage control circuit, controls the gate voltage Vg after the Miller period. The functions of each circuit are briefly described below.

[0049] The voltage limiting circuit 1 controls the voltage variation of the gate voltage Vg in the first region RG1. Specifically, the voltage limiting circuit 1 outputs a limit voltage VL (also referred to as a first voltage) in response to an on instruction, thereby causing the gate voltage Vg to change with a first slope ( Figure 13 、 Figure 14 SL1) rapidly increases to the limit voltage VL. Specifically, the voltage limiting circuit 1 limits the gate voltage Vg to the limit voltage VL when the power semiconductor element 8 is activated. Preferably, the limit voltage VL corresponds to the threshold voltage Vth of the power semiconductor element 8 and has a value approximately equal to the threshold voltage Vth.

[0050] The first variable voltage generating circuit 2 controls the voltage variation of the gate voltage Vg in the second region RG2. Specifically, the first variable voltage generating circuit 2 generates a second slope ( SL1 ) which is gentler than the first slope SL1. Figure 13 、 Figure 14 The first variable voltage generating circuit 2 supplies the generated first variable voltage V1 to the gate of the power semiconductor element 8 via the buffer circuit 6, thereby increasing the gate voltage Vg from the limit voltage VL at the second slope SL2.

[0051] The second variable voltage generating circuit 3 controls the voltage variation of the gate voltage Vg in the third region RG3. Specifically, the second variable voltage generating circuit 3 generates a second variable voltage V2 that varies more rapidly than the first variable voltage V1 output from the first variable voltage generating circuit 2. Thus, after the first period ( Figure 13 From time t0 to t3, Figure 14 When the gate voltage Vg does not reach the Miller voltage at the time point (time t0 to t2), the gate voltage Vg increases to the Miller voltage with a third slope SL3 that is gentler than the first slope SL1 but steeper than the second slope SL2.

[0052] The comparison circuit 4 controls the voltage change of the gate voltage Vg in the fourth region RG4. Specifically, the ... Figure 13 、 Figure 14 From the time point (time t0 to t4), the gate voltage Vg is increased from the Miller voltage at a fourth slope SL4 that is steeper than the third slope SL3 described above. Finally, the gate voltage Vg reaches the power supply voltage supplied to the driving circuit 1000.

[0053] Before the first period elapses after receiving the on-command, the adding circuit 5 outputs a voltage obtained by adding the first variable voltage V1 to the limit voltage VL. Starting at the point in time when the first period elapses after receiving the on-command, the adding circuit 5 outputs a current obtained by adding the output current of the voltage limiting circuit 1, the output current of the first variable voltage generating circuit 2, and the output current of the second variable voltage generating circuit 3, thereby outputting a third variable voltage V3 based on the limit voltage VL, the first variable voltage V1, and the second variable voltage V2. The buffer circuit 6 transmits the output voltage of the adding circuit 5 to the gate of the power semiconductor element 8, thereby generating a gate voltage Vg for the power semiconductor element 8.

[0054] The four time regions described above are summarized as follows: The first region RG1 corresponds to the time period immediately after the gate voltage Vg is received and rising. The second region RG2 covers the time period from the time the gate voltage Vg rises until the first period has elapsed. The third region RG3 covers the time period from the time the first period has elapsed to the time the second period has elapsed. The fourth region RG4 covers the time period from the time the second period has elapsed until the gate voltage Vg reaches the power supply voltage of the driver circuit 1000.

[0055] Figure 2 1 is a diagram showing an example of the configuration of the voltage limiting circuit 1. The voltage limiting circuit 1 is configured by a Zener diode 11 as an example.

[0056] like Figure 2 As shown, an input node (Node) IN1 of the voltage limiting circuit 1 is connected to a control input terminal 7 for externally controlling a power semiconductor device 8. An output node OUT1 of the voltage limiting circuit 1 is connected to an adder circuit 5. Within the voltage limiting circuit 1, the cathode of a Zener diode 11 is connected to the input node IN1, and the anode of the Zener diode 11 is connected to the output node OUT1.

[0057] According to the configuration of the voltage limiting circuit 1 described above, when the control signal input to the control input terminal 7, which serves as a command for the on-state operation, changes from low to high, the voltage limiting circuit 1 limits the voltage change at the output node OUT1. Specifically, the voltage at the output node OUT1 of the voltage limiting circuit 1 does not change until the voltage at the input node IN1 of the voltage limiting circuit 1 reaches the Zener voltage of the Zener diode 11 (hereinafter also referred to as the limit voltage VL). Thereafter, the voltage limiting circuit 1 is limited to the Zener voltage. Thus, the voltage limiting circuit 1 generates a rapidly changing voltage to control the voltage change of the gate voltage Vg in the first region RG1.

[0058] Figure 3 and Figure 4This diagram shows an example of the configuration of the first variable voltage generating circuit 2. The input node IN2 of the first variable voltage generating circuit 2 is connected to the control input terminal 7, and the output node OUT2 of the first variable voltage generating circuit 2 is connected to the output node OUT1 of the voltage limiting circuit 1. When the control signal input to the control input terminal 7, which serves as an on-state instruction, changes from Low to High, the first variable voltage generating circuit 2 generates a first variable voltage V1 that increases relatively gently at a first time rate of change dV1 / dt, based on the limit voltage VL, the voltage value limited by the voltage limiting circuit 1, and outputs the generated first variable voltage V1 to the adding circuit 5. This controls the time variation of the gate voltage Vg in the second region RG2 (corresponding to the first slope SL1) before the gate voltage Vg reaches the Miller voltage.

[0059] Specifically, in Figure 3 In the configuration example, the first variable voltage generating circuit 2 is configured as a first-order lag circuit including a resistor element 21 and a capacitor element 22. The resistor element 21 is connected between the input node IN2 and the output node OUT2. The capacitor element 22 is connected between the output node OUT2 and a reference node 23 that provides a reference potential Vref. With this configuration, the voltage at the output node OUT2 increases relatively gradually from the limit voltage VL at a substantially constant rate of increase over time, according to a time constant CR determined by the resistance value R of the resistor element 21 and the capacitance value C of the capacitor element 22.

[0060] exist Figure 4 In the configuration example, the first variable voltage generating circuit 2 includes a constant current source 24 and a capacitor element 22. The constant current source 24 is connected between a power supply node 25, to which a power supply voltage is supplied, and the output node OUT2. The capacitor element 22 is connected between the output node OUT2 and a reference node 23. When the control signal input to the control input terminal 7, which serves as an on-state instruction, changes from low (Low) to high (High), the constant current source 24 begins to flow a constant current to the capacitor element 22. As a result, the voltage of the capacitor element 22 increases at a constant rate of change over time from the limit voltage VL.

[0061] Figure 5 and Figure 6This diagram shows an example of the configuration of the second variable voltage generating circuit 3. The input node IN3 of the second variable voltage generating circuit 3 is connected to the control input terminal 7, and the output node OUT3 of the second variable voltage generating circuit 3 is connected to the comparison circuit 4 and the adder circuit 5. When the control signal input to the control input terminal 7, which serves as an instruction for the on-state operation, changes from low (Low) to high (High), the second variable voltage generating circuit 3 generates and outputs a second variable voltage V2 that increases relatively gently at a second time rate of change dV2 / dt based on the reference potential Vref of the drive circuit 1000. The second time rate of change dV2 / dt is greater than the first time rate of change dV1 / dt described above. The time change of the gate voltage Vg in the third region RG3 before the gate voltage Vg reaches the Miller voltage (corresponding to the third slope SL3) is based on the time rate of change dV2 / dt of the second variable voltage V2 output from the second variable voltage generating circuit 3.

[0062] Specifically, in Figure 5 In the structural example of Figure 3 Similarly, the second variable voltage generating circuit 3 is configured as a first-order lag circuit including a resistor element 31 and a capacitor element 32. The resistor element 31 is connected between the input node IN3 and the output node OUT3. The capacitor element 33 is connected between the output node OUT3 and a reference node 33 for providing a reference potential Vref. With this configuration, the voltage at the output node OUT3 increases relatively gradually from the reference potential Vref at a substantially constant rate of increase, according to a time constant CR determined by the resistance value R of the resistor element 31 and the capacitance value C of the capacitor element 33.

[0063] exist Figure 6 In the structural example of Figure 4 Similarly, the second variable voltage generating circuit 3 includes a constant current source 34 and a capacitor element 32. The constant current source 34 is connected between a power supply node 35, to which a power supply voltage is supplied, and the output node OUT3. The capacitor element 33 is connected between the output node OUT3 and a reference node 33. When the control signal input to the control input terminal 7, which serves as an on-state instruction, changes from low (Low) to high (High), the constant current source 34 begins to flow a constant current to the capacitor element 33. As a result, the voltage of the capacitor element 33 increases at a constant rate of increase from the reference potential Vref.

[0064] Figure 7 FIG. 4 is a diagram showing an example of the structure of the comparison circuit 4. Figure 7As shown, the comparison circuit 4 includes a comparator 41 and a comparison voltage source 42. The input node IN4 of the comparison circuit 4 is connected to the output node OUT3 of the second variable voltage generating circuit 3, and the output node OUT4 of the comparison circuit 4 is connected to the gate terminal of the power semiconductor element 8. Within the comparison circuit 4, the non-inverting input terminal of the comparator 41 is connected to the input node IN4, the inverting input terminal of the comparator 41 is connected to the comparison voltage source 42, and the output terminal of the comparator 41 is connected to the output node OUT4.

[0065] According to the aforementioned configuration of the comparison circuit 4, the comparison circuit 4 outputs a low level (i.e., the reference potential Vref of the driver circuit 1000) until the second variable voltage V2 output from the second variable voltage generating circuit 3 reaches the voltage value of the comparison voltage source 42 (i.e., the comparison voltage VC). Thereafter, the comparison circuit 4 outputs a high level (i.e., the power supply voltage of the driver circuit 1000). Thus, the comparison circuit 4 generates a voltage that increases sharply at a fourth slope SL4, thereby controlling the change in the gate voltage Vg in the fourth region where the gate voltage Vg is above the Miller voltage. Alternatively, the comparison circuit 4 may be configured to compare the first variable voltage V1 output from the first variable voltage generating circuit 2 with the comparison voltage VC. The value of the comparison voltage VC is adjusted based on the voltage change rate dV1 / dt of the first variable voltage V1.

[0066] Figure 8 1 is a diagram showing an example of the structure of the adding circuit 5. Figure 8 As shown, the adding circuit 5 includes a diode 51. An input node IN5A of the adding circuit 5 is connected to the output node OUT1 of the voltage limiting circuit 1 and the output node OUT2 of the first variable voltage generating circuit 2. An input node IN5B of the adding circuit 5 is connected to the output node OUT3 of the second variable voltage generating circuit 3. An output node OUT5B of the adding circuit 5 is connected to an input node IN6 of the buffer circuit 6. Within the adding circuit 5, the input node IN5A and the output node OUT5 are directly connected via wiring. The diode 51 is connected between the input node IN5B and the output node OUT5, with the direction from the input node IN5B to the output node OUT5 being the forward direction.

[0067] According to the configuration of the adding circuit 5 described above, until the second variable voltage V2 outputted from the second variable voltage generating circuit 3, which increases at the second rate of change, reaches the combined voltage (VL+V1) of the limit voltage VL outputted from the voltage limiting circuit 1 and the first variable voltage V1 outputted from the first variable voltage generating circuit 2, which increases at the first rate of change, the adding circuit 5 outputs the combined voltage (VL+V1) from the output node OUT5. Thereafter, the adding circuit 5 outputs a current resulting from the sum of the output currents of the voltage limiting circuit 1, the first variable voltage generating circuit 2, and the second variable voltage generating circuit 3, thereby outputting a third variable voltage V3 based on the combined voltage (VL+V1) and the second variable voltage V2. The value of the third variable voltage V3 is determined by factors such as the characteristics and parasitic capacitance of the diode 51. The time rate of change dV3 / dt of the third variable voltage V3 is greater than the time rate of change dV1 / dt of the first variable voltage V1. The aforementioned first period corresponds to the period until the second variable voltage V2 reaches the sum of the limit voltage VL and the first variable voltage V1.

[0068] Figure 9 、 Figure 10 as well as Figure 11 1 is a diagram showing an example of the configuration of the buffer circuit 6. The buffer circuit 6 transmits the output voltage of the adder circuit 5 inputted via the input node IN6 to the gate of the power semiconductor element 8 via the output node OUT6, thereby generating a gate voltage Vg of the power semiconductor element 8.

[0069] Specifically, in Figure 9 In the configuration example, buffer circuit 6 is formed of an emitter-follower NPN bipolar transistor 61. The voltage amplification factor of the emitter-follower is 1. More specifically, the collector of bipolar transistor 61 is connected to power supply node 62 to which the power supply voltage is supplied, the emitter of bipolar transistor 61 is connected to output node OUT6, and the base of bipolar transistor 61 is connected to input node IN6.

[0070] exist Figure 10 In the configuration example, buffer circuit 6 is composed of a push-pull emitter-follower circuit consisting of an NPN bipolar transistor 61 and a PNP bipolar transistor 63. The voltage gain of the emitter-follower circuit is 1. More specifically, the collector of bipolar transistor 61 is connected to a power supply node 62 to which a power supply potential is supplied, and the collector of bipolar transistor 63 is connected to a reference node 64 to which a reference potential Vref is supplied. The emitters of bipolar transistors 61 and 63 are connected to output node OUT6. The bases of bipolar transistors 61 and 63 are connected to input node IN6.

[0071] exist Figure 11In the configuration example, the buffer circuit 6 is formed of a unity gain buffer using an operational amplifier 65. More specifically, the output terminal of the operational amplifier 65 is connected to the output node OUT6 and is also connected to the inverting input terminal of the operational amplifier 65. The non-inverting input terminal of the operational amplifier 65 is connected to the input node IN6.

[0072] Figure 12 1 is a diagram showing an example of the structure of the power semiconductor element 8. Figure 12 In the example shown, power semiconductor element 8 is composed of an IGBT (Insulated Gate Bipolar Transistor) 81 and a freewheeling diode 82. FETs (Field Effect Transistors) can be used instead of IGBTs, or bipolar transistors can be used. The type of semiconductor element is not particularly limited. In this disclosure, the control electrode of power semiconductor element 8 is also referred to as the gate, and the voltage of the control electrode is also referred to as the gate voltage.

[0073] [Operation of the Drive Circuit for Power Semiconductor Devices]

[0074] Next, the operation of the drive circuit 1000 according to the first embodiment when the power semiconductor element 8 is turned on will be described. Figure 13 The operation when the collector current Ic, which is the main current of the power semiconductor element 8, is relatively small will be described. Figure 14 The operation when the collector current Ic of the power semiconductor element 8 is relatively large will be described. The power semiconductor element drive circuit 1000 according to the first embodiment is characterized in that the control method of the gate voltage Vg of the power semiconductor element 8 differs between when the collector current Ic is small and when the collector current Ic is large.

[0075] Figure 13 1 is a timing chart for explaining a first operation example of the driving circuit 1000 of the power semiconductor element according to the first embodiment. Figure 13 , a timing chart is shown when the collector current Ic is relatively small during the on-state operation of the power semiconductor element 8. Figure 13The waveforms of the control signal input to the control input terminal 7, the sum (VL + V1) of the limit voltage VL output from the voltage limiter circuit 1 and the first variable voltage V1 output from the first variable voltage generator circuit 2, the second variable voltage V2 output from the second variable voltage generator circuit 3, the output voltage V3 of the adder circuit 5, the determination result of the comparison circuit 4, and the gate voltage Vg, collector current Ic, and collector-emitter voltage Vce of the power semiconductor device 8 are shown in order from the top. The waveforms of the gate voltage Vg, collector current Ic, and collector-emitter voltage Vce are shown in solid lines for the present embodiment, and in dashed lines for the comparative example. The comparative example shows a constant voltage drive type or constant current drive type drive circuit that does not control the gate voltage Vg of the power semiconductor device 8 in multiple time zones.

[0076] The following is a chronological order of description. Figure 13 The operation of the driving circuit 1000 at time t0.

[0077] At time t0, when the control signal input to control input terminal 7 changes from low to high as a command for an on-state operation, the voltage limiting circuit 1, the first variable voltage generating circuit 2, and the second variable voltage generating circuit 3 begin operating. The voltage limiting circuit 1 controls the voltage change of the gate voltage Vg in the first region RG1 around time t0.

[0078] Specifically, the output voltage V1 of the voltage limiting circuit 1 rises sharply to the limit voltage VL at a first slope SL1. Here, the limit voltage VL of the voltage limiting circuit 1 is set to approximately the threshold voltage Vth of the power semiconductor element 8. As a result, the gate voltage Vg reaches the threshold voltage Vth of the power semiconductor element 8, causing the collector current Ic to begin flowing through the power semiconductor element 8. On the other hand, in the case of the comparative example drive circuit, the gate voltage Vg begins to rise, but it takes time to reach the threshold voltage Vth, so the collector current Ic does not rise immediately. Thus, according to the drive circuit 1000 of Embodiment 1, compared to the comparative example drive circuit, by causing the gate voltage Vg in the first region RG1 to rise sharply to approximately the threshold voltage at the first slope SL1, it is possible to shorten the dead time and reduce losses.

[0079] At time t0, the output voltage V1 of the first variable voltage generating circuit 2 begins to rise at a first time rate of change dV1 / dt relative to the limit voltage VL of the voltage limiter circuit 1. Furthermore, the output voltage V2 of the second variable voltage generating circuit 3 begins to rise at a second time rate of change dV2 / dt relative to the reference potential Vref of the driver circuit 1000. In the driver circuit 1000 of Embodiment 1, the rate of change dV2 / dt of the second variable voltage V2 generated by the second variable voltage generating circuit 3 is greater than the rate of change dV1 / dt of the first variable voltage V1 generated by the first variable voltage generating circuit 2.

[0080] Around time t0, the sum of the limit voltage VL output by the voltage limiter circuit 1 and the first variable voltage generator circuit 2 and the first variable voltage V1 is greater than the second variable voltage V2 output by the second variable voltage generator circuit 3. Therefore, the output voltage V3 of the adder circuit 5 is equal to the sum of the limit voltage VL and the first variable voltage V1. The determination result of the comparator circuit 4 is a low (L) level because the output voltage V2 of the second variable voltage generator circuit 3 is lower than the output voltage of the comparison voltage source 42 (i.e., the comparison voltage VC).

[0081] The following describes the changes in gate voltage Vg, collector current Ic, and collector-emitter voltage Vce of power semiconductor device 8 around time t0, comparing the present embodiment with the comparative example. In the present embodiment, when the control signal, which serves as the on-state instruction, changes from low to high, gate voltage Vg rapidly increases at a first slope SL1 in the first region RG1 due to the operation of voltage limiting circuit 1, reaching threshold voltage Vth. In contrast, in the comparative example drive circuit, gate voltage Vg begins to rise gradually when the control signal, which serves as the on-state instruction, changes from low to high, but does not immediately reach threshold voltage Vth.

[0082] In this embodiment, collector current Ic starts flowing as soon as gate voltage Vg reaches threshold voltage Vth based on limit voltage VL set in voltage limit circuit 1. In the comparative example, collector current Ic remains at 0 and does not change because gate voltage Vg does not reach threshold voltage Vth.

[0083] The collector-emitter voltage Vce of the power semiconductor element 8 starts to drop due to the influence of the change rate dIc / dt of the collector current Ic as the collector current Ic starts to flow. In the comparative example, the collector-emitter voltage Vce does not change because the collector current Ic does not flow.

[0084] Next, explain Figure 13 The operation of the driver circuit 1000 from time t0 to t1 is shown in FIG. The voltage limiting circuit 1 outputs the limit voltage VL, and the first variable voltage generating circuit 2 outputs the first variable voltage V1, which increases at a first rate of change dV1 / dt. Therefore, the combined voltage (VL + V1), obtained by adding these voltages, increases at the first rate of change dV1 / dt relative to the limit voltage VL. The output voltage V2 of the second variable voltage generating circuit 3 increases at a second rate of change dV2 / dt relative to the reference potential Vref of the driver circuit 1000.

[0085] Since the combined voltage (VL + V1) of the adder circuit 5 is greater than the second variable voltage V2, the output voltage V3 of the adder circuit 5 increases at the first rate of change dV1 / dt relative to the limit voltage VL. The comparison circuit 4 determines that the output voltage V2 of the second variable voltage generating circuit 3 is still low because it is smaller than the comparison voltage VC.

[0086] In the present embodiment, the gate voltage Vg rises sharply to the threshold voltage Vth at a first slope SL1 in the first region RG1 around time t0. Thereafter, the gate voltage Vg rises at a relatively gradual rate at a second slope SL2 in the second region RG2 based on the rate of change dV1 / dt of the output voltage of the first variable voltage generating circuit 2. In the comparative example drive circuit, the gate voltage Vg reaches the threshold voltage Vth of the power semiconductor device 8 at time t1.

[0087] In the present embodiment, the collector current Ic of the power semiconductor element 8 increases in the second region RG2 at a current change rate based on the gate voltage Vg that changes with the second slope SL2. In the comparative example drive circuit, the collector current Ic begins to flow at time t1 when the gate voltage Vg reaches the threshold voltage Vth.

[0088] The collector-emitter voltage Vce in this embodiment decreases due to the change rate of the collector current Ic. In the comparative example drive circuit, the collector-emitter voltage Vce does not change while the collector current Ic is not flowing, but begins to decrease after the collector current Ic starts flowing at time t1.

[0089] Next, explain Figure 13 The operation of the driving circuit 1000 from time t1 to t2 is shown. The output voltage V1 of the voltage limiting circuit 1 and the first variable voltage generating circuit 2, the output voltage V2 of the second variable voltage generating circuit 3, the output voltage V3 of the adding circuit 5, and the output of the comparator circuit 4 are the same as those from time t0 to t1, and therefore, description thereof will not be repeated.

[0090] In the present embodiment, similar to the case from time t0 to time t1, the gate voltage Vg increases relatively gently with the second slope in the second region RG2, based on the voltage change rate dV1 / dt of the output voltage of the first variable voltage generating circuit 2, reaching the Miller voltage at time t2. In the comparative example drive circuit, the gate voltage Vg reaches the threshold voltage at time t1. Therefore, in the comparative example drive circuit, the collector current Ic begins to flow from time t1.

[0091] Here, the rate of change of the gate voltage Vg in the comparative example is greater than the rate of change of the gate voltage Vg corresponding to the second slope SL2 in the second region RG2 in the present embodiment. Therefore, the rate of change dIc / dt of the collector current Ic in the comparative example is greater than the rate of change dIc / dt of the collector current Ic in the present embodiment. As a result, in the present embodiment, the switching loss of the power semiconductor element 8 in the second region RG2 increases compared to the case of the drive circuit of the comparative example. However, Figure 13 In the case of , the collector current Ic is relatively small, so the influence of this loss is small.

[0092] Changes in the collector-emitter voltage Vce of the power semiconductor element 8 are affected by the rate of change dIc / dt of the collector current Ic. Therefore, the rate of change dIc / dt in the drive circuit of the comparative example is greater than that in the present embodiment, and therefore the rate of change of the collector-emitter voltage Vce in the drive circuit of the comparative example is also greater than that in the present embodiment.

[0093] Next, explain Figure 13 The operation of the driving circuit 1000 from time t2 to t3 is as follows. The output voltage V1 of the voltage limiting circuit 1 and the first variable voltage generating circuit 2 and the output voltage V2 of the second variable voltage generating circuit 3 are the same as those from time t0 to t2, and therefore their description will not be repeated.

[0094] Until time t3, similar to the case from time t0 to time t2, the sum (VL + V1) of the limit voltage VL output from the voltage limiting circuit and the first variable voltage V1 output from the first variable voltage generating circuit 2 is greater than the second variable voltage V2 output from the second variable voltage generating circuit 3. Therefore, the output voltage V3 of the adding circuit 5 is equal to the sum of the limit voltage VL and the first variable voltage V1. After time t3, the second variable voltage V2 is greater than the sum (VL + V1) of the limit voltage VL and the first variable voltage V1. Therefore, the output voltage V3 of the adding circuit 5 becomes a value based on the limit voltage VL, the first variable voltage V1, and the second variable voltage V2, with a rate of change greater than dV1 / dt. Furthermore, the output current of the adding circuit 5 is equal to the sum of the output currents of the voltage limiting circuit 1, the first variable voltage generating circuit 2, and the second variable voltage generating circuit 3. Here, the second region RG2 is the period from the moment the gate voltage Vg changes abruptly at the first slope SL1 in the first region RG1 to time t3 (the aforementioned first period).

[0095] exist Figure 13 In the case of the collector current Ic of the power semiconductor element 8 being small, in the second region RG2, the gate voltage Vg reaches the Miller period. The second region RG2 includes the time for recovery after the recovery current flows (in Figure 13 The characteristic is that in the second region RG2, the driving circuit 1000 controls the gate voltage Vg based on the first variable voltage V1 having a relatively gentle voltage change rate dV1 / dt generated by the first variable voltage generating circuit 2.

[0096] In this embodiment, the gate voltage Vg in the second region RG2 changes with a second slope SL2 based on the voltage change rate dV1 / dt set in the first variable voltage generating circuit 2. Therefore, compared to the drive circuit of the comparative example, the change rate of the gate voltage Vg is smaller, and the change rate dIc / dt of the collector current Ic during recovery is also smaller. As a result, the change rate dVce / dt of the collector-emitter voltage Vce caused by the recovery current is also smaller, thereby reducing EMI.

[0097] Furthermore, the above description assumes that the rate of change dIc / dt of the collector current Ic in the second region RG2 in this embodiment is smaller than that in the comparative example drive circuit. However, depending on the setting of the rate of change dV1 / dt of the first variable voltage V1 outputted from the first variable voltage generating circuit 2, the rate of change dIc / dt of the collector current Ic in this embodiment becomes larger than that in the comparative example drive circuit. In this case, while the EMI caused by the recovery current is greater in this embodiment than in the comparative example, it also offers the advantage of further reducing switching losses in the second region RG2.

[0098] Next, explain Figure 13 The operation of the driving circuit 1000 from time t3 to t4 is shown in FIG. After time t3, the second variable voltage V2 output by the second variable voltage generating circuit 3 becomes greater than the sum of the limit voltage VL output by the voltage limiting circuit 1 and the first variable voltage V1 output by the first variable voltage generating circuit 2. Therefore, after time t3, the output voltage V3 of the adding circuit 5 changes not only based on the limit voltage VL and the first variable voltage V1, but also based on the second variable voltage V2.

[0099] The third region RG3 is a period during which the gate voltage Vg is controlled primarily based on the output voltage V2 of the second variable voltage generating circuit 3. However, since the gate voltage Vg reaches the Miller period at time t2 in the second region RG2, the gate voltage Vg remains constant in the third region RG3. Similarly, in the case of the drive circuit of the comparative example, the gate voltage Vg reaches the Miller voltage at time t2 and remains constant in the third region RG3.

[0100] The collector current Ic of the power semiconductor element 8 is constant after time t3 because the recovery current is restored at time t3. In the case of the drive circuit of the comparative example, the collector current Ic is also constant after time t3. The collector-emitter voltage Vce of the power semiconductor element 8 decreases at a voltage change rate dVce / dt corresponding to the drive capability of the buffer circuit 6. In the case of the drive circuit of the comparative example, the collector-emitter voltage Vce also decreases at a voltage change rate corresponding to the drive capability of the drive circuit.

[0101] Next, explain Figure 13The operation of the drive circuit 1000 from time t4 to time t5 is shown. At time t4, the output voltage V2 of the second variable voltage generating circuit 3 input to the comparison circuit 4 reaches the comparison voltage VC of the comparison circuit 4. As a result, the determination result of the comparison circuit 4 changes from low to high. When the determination result of the comparison circuit 4 becomes high, current is injected into the gate terminal of the power semiconductor element 8, causing the gate voltage Vg to rise sharply at the fourth slope SL4. The period from time t0 to time t4 corresponds to the second period described above.

[0102] The fourth region RG4 is the time period during which the gate voltage Vg increases at a fourth slope SL4 based on changes in the output voltage of the comparison circuit 4. Specifically, it is the period from the end of the Miller period of the gate voltage Vg (time t4) to the time when the gate voltage Vg reaches the power supply voltage of the driver circuit 1000 (time t5). On the other hand, the gate voltage Vg of the driver circuit of the comparative example is in the Miller period from time t5 onwards and before time t6, and losses due to switching operations occur during the Miller period.

[0103] Thus, according to the driver circuit 1000 of this embodiment, the gate voltage Vg in the fourth region RG4 is controlled using the comparison circuit 4, causing the gate voltage Vg to increase sharply at the fourth slope SL4. This increases the time rate of change dVce / dt of the collector-emitter voltage Vce, thereby reducing switching losses in the fourth region RG4 compared to the driver circuit of the comparative example. Furthermore, the driver circuit 1000 of the first embodiment is characterized in that the fourth slope SL4 in the fourth region RG4 is greater than the second slope SL2 in the second region RG2.

[0104] Next, explain Figure 13 Operation of the drive circuit 1000 after time t5. In the case of the drive circuit 1000 of this embodiment, the changes of the collector current Ic and the collector-emitter voltage Vce have ended at time t5, and therefore these states do not change until a shutdown command is input.

[0105] On the other hand, in the case of the driving circuit of the comparative example, after the gate voltage Vg reaches the Miller voltage at time t2, the length of the Miller period depends on the magnitude of the output current of the driving circuit. Figure 13 In this case, the Miller period continues until time t6. After the collector-emitter voltage Vce drops to a certain value until time t3, the collector-emitter voltage Vce continues to drop gently until time t6, when the Miller period ends. Therefore, the period from time t3 to t6 causes increased switching losses.

[0106] As described above, according to the drive circuit 1000 of the first embodiment, the gate voltage Vg of the power semiconductor element 8 when it is turned on is divided into four time regions: the first region RG1 to the fourth region RG4, and is controlled accordingly. Specifically, in the first region RG1, the voltage limiting circuit 1 controls the gate voltage Vg, causing the gate voltage Vg to rise sharply to approximately the threshold voltage at the first slope SL1. This shortens the dead time and reduces losses.

[0107] In the following second region RG2, the gate voltage Vg is controlled by the first variable voltage generating circuit 2. When the collector current Ic flowing through the power semiconductor device 8 is low, the gate voltage Vg reaches the Miller voltage in this second region RG2. The rate of change of the voltage generated by the first variable voltage generating circuit 2 is lower than the rate of change of the voltage generated by the second variable voltage generating circuit 3. This reduces the rate of change dVce / dt of the collector-emitter voltage Vce caused by the recovery current, resulting in reduced EMI.

[0108] In the subsequent third region RG3, the gate voltage Vg is mainly controlled by the second variable voltage generating circuit 3. When the collector current Ic flowing through the power semiconductor element 8 is small, the gate voltage Vg reaches the Miller voltage in the second region RG2, and thus the gate voltage Vg in the third region RG3 is constant.

[0109] In the subsequent fourth region RG4, the gate voltage Vg is controlled using the output voltage of the comparison circuit 4. The rate of change of the gate voltage Vg in this fourth region RG4 (corresponding to the fourth slope SL4) is made greater than the rate of change of the gate voltage Vg in the second region RG2 (corresponding to the second slope SL2) controlled by the first variable voltage generating circuit 2. As a result, the rate of change dVce / dt of the collector-emitter voltage Vce can be increased, thereby reducing switching losses.

[0110] Figure 14 1 is a timing chart for explaining a second operation example of the driving circuit 1000 for the power semiconductor element according to the first embodiment. Figure 14 , a timing chart is shown for a case where the collector current is relatively large during the on-operation of the power semiconductor element 8 . Figure 14 The waveforms shown correspond to Figure 13 The waveforms shown. Figure 13 Similarly, in the waveforms of the gate voltage Vg, collector current Ic, and collector-emitter voltage Vce, the solid line represents the case of the present embodiment, and the dotted line represents the case of the comparative example. The comparative example shows the case of a constant voltage drive type or constant current drive type drive circuit that controls the gate voltage Vg of the power semiconductor element 8 without dividing it into multiple time zones.

[0111] Figure 14 The control action of the driving circuit 1000 from time t0 to time t1 and the change of the gate voltage Vg are Figure 13 The same is true for , so the description is not repeated.

[0112] Next, explain Figure 14 The operation of the driving circuit 1000 from time t1 to t2 is the same as that from time t0 to t1. The limit voltage VL outputted from the voltage limiter circuit 1, the first variable voltage V1 outputted from the first variable voltage generator circuit 2, the second variable voltage V2 outputted from the second variable voltage generator circuit 3, the output voltage V3 of the adder circuit 5, and the output of the comparison circuit 4 are the same as those from time t0 to t1.

[0113] In the case of this embodiment, the gate voltage Vg increases at a relatively gentle second slope SL2 in the second region RG2, similarly to the case from time t0 to time t1, based on the voltage change rate dV1 / dt of the output voltage V1 of the voltage limiting circuit 1 and the first variable voltage generating circuit 2. Figure 13 When the collector current Ic is relatively small, the Miller voltage is also relatively small, so the gate voltage Vg reaches the Miller voltage Vm at time t2. Figure 14 In that case, when the collector current Ic is relatively large, the Miller voltage Vm is also relatively large, so the gate voltage Vg will not reach the Miller voltage Vm at time t2. The changes in the collector current Ic and the collector-emitter voltage Vce from time t1 to time t2 are similar to Figure 13 The same is true for , so the description is not repeated.

[0114] Next, explain Figure 14 The operation of the driver circuit 1000 from time t2 to t3 is shown in FIG. After time t2, and before the gate voltage Vg reaches the Miller voltage Vm, the second variable voltage V2 output from the second variable voltage generating circuit 3 is greater than the sum of the limit voltage VL output by the voltage limiting circuit 1 and the first variable voltage generating circuit 2, and the first variable voltage V1. As a result, the output voltage V3 of the adding circuit 5 changes from the combined voltage VL+V1 generated by the voltage limiting circuit 1 and the first variable voltage generating circuit 2 to a voltage based on the combined voltage VL+V1 and the second variable voltage V2 generated by the second variable voltage generating circuit 3. Consequently, the rate of change of the output voltage V3 of the adding circuit 5 also changes from dV1 / dt to a larger value.

[0115] The third region RG3 is a period after the voltage change rate is switched from dV1 / dt to a larger change rate corresponding to the third slope SL3 as described above. Figure 13When the collector current Ic is small, the gate voltage Vg reaches the Miller voltage Vm before the third region RG3, so the gate voltage Vg does not change in the third region RG3. Figure 14 When the collector current Ic is large as described above, the gate voltage Vg does not reach the Miller voltage Vm, and therefore the gate voltage Vg is controlled at a voltage change rate corresponding to the third slope SL3 .

[0116] From time t0 to t2, the rate of change dIc / dt of collector current Ic of power semiconductor element 8 varies based on the rate of change dV1 / dt of first variable voltage V1 generated by first variable voltage generating circuit 2. In contrast, from time t2 to t3, control is primarily based on the rate of change dV2 / dt of second variable voltage V2 generated by second variable voltage generating circuit 3. Because the rate of change dV2 / dt is greater than the rate of change dV1 / dt, the rate of change dIc / dt of collector current Ic increases after time t2 compared to before time t2. In contrast, in the comparative example drive circuit, the rate of change dIc / dt of collector current Ic remains constant from time t1, when gate voltage Vg reaches threshold voltage Vth, to time t3.

[0117] Thus, in the drive circuit 1000 of this embodiment, when the collector current Ic is relatively large, the rate of change dIc / dt of the collector current Ic is varied in two stages until time t3, when the gate voltage Vg reaches the Miller voltage Vm. Consequently, in the second region RG2, where the rate of change dIc / dt of the collector current Ic is smaller than that of the drive circuit of the comparative example, the switching losses of the power semiconductor device 8 are greater than those of the drive circuit of the comparative example. On the other hand, in the third region RG3, by maintaining the rate of change dIc / dt of the collector current Ic at the same level as that of the drive circuit of the comparative example, the switching losses of the power semiconductor device 8 can be made equivalent to those of the drive circuit of the comparative example.

[0118] Next, explain Figure 14 The operation of the driving circuit 1000 from time t3 to time t4. Figure 14 In the case of the drive circuit of the comparative example, at time t3 in the third region RG3 where the gate voltage Vg is mainly controlled by the second variable voltage generating circuit 3, the gate voltage Vg reaches the Miller voltage Vm. Similarly, in the case of the drive circuit of the comparative example, the gate voltage Vg reaches the Miller voltage Vm at time t3. When the gate voltage Vg reaches the Miller voltage Vm, a recovery current flows, and thus the collector current Ic changes. Here, Figure 14In the example shown, the rate of change of the gate voltage Vg of the driver circuit 1000 of this embodiment is made the same as the rate of change of the gate voltage Vg in the driver circuit of the comparative example. Therefore, the rate of change dIc / dt of the collector current Ic is also the same between this embodiment and the comparative example. Furthermore, the rate of change of the gate voltage Vg in the third region RG3 does not need to be the same between this embodiment and the comparative example.

[0119] Next, explain Figure 14 The operation of the drive circuit 1000 from time t4 to time t5 is shown. At time t4, the output voltage V2 of the second variable voltage generating circuit 3 input to the comparator circuit 4 reaches the comparison voltage VC of the comparator circuit 4. As a result, the determination result of the comparator circuit 4 changes from low to high. When the determination result of the comparator circuit 4 becomes high, current is injected into the gate terminal of the power semiconductor element 8, causing the gate voltage Vg to rise sharply at the fourth slope SL4.

[0120] The fourth region RG4 is a region in which the gate voltage Vg changes at a fourth slope SL based on the change in the output voltage of the comparison circuit 4. That is, it is the period from the end of the Miller period of the gate voltage Vg (time t4) to the time when the gate voltage Vg reaches the power supply voltage of the driver circuit 1000 (time t5). On the other hand, the gate voltage Vg of the driver circuit of the comparative example is in the Miller period after time t5 and before time t6, and loss due to switching operation occurs during the Miller period. The operation of such a driver circuit is similar to that of Figure 13 The same is true for the case where the collector current Ic is relatively small.

[0121] Thus, according to the driver circuit 1000 of this embodiment, the gate voltage Vg in the fourth region RG4 is controlled using the comparison circuit 4, causing the gate voltage Vg to increase sharply at the fourth slope SL4. This increases the rate of change dVce / dt of the collector-emitter voltage Vce, thereby reducing switching losses in the fourth region RG4 compared to the driver circuit of the comparative example. Furthermore, the driver circuit 1000 of the first embodiment is characterized in that the rate of change of the gate voltage Vg in the fourth region RG4 (i.e., the fourth slope SL4) is greater than the rate of change of the gate voltage Vg in the second region RG2 (i.e., the second slope SL2).

[0122] Next, explain Figure 14 Operation of the drive circuit 1000 after time t5. In the case of the drive circuit 1000 of this embodiment, the changes of the collector current Ic and the collector-emitter voltage Vce have ended at time t5, and therefore these states do not change until a shutdown command is input.

[0123] On the other hand, in the case of the driving circuit of the comparative example, after the gate voltage Vg reaches the Miller voltage at time t2, the length of the Miller period depends on the magnitude of the output current of the driving circuit 1000. Figure 13 In this case, the Miller period continues until time t6. After the collector-emitter voltage Vce drops to a certain value until time t3, the collector-emitter voltage Vce continues to drop gently until time t6, when the Miller period ends. Therefore, during the period from time t3 to t6, the switching loss of the power semiconductor element 8 controlled by the drive circuit of the comparative example is greater than that of the present embodiment.

[0124] Figure 15 This is a flowchart showing a control process when the power semiconductor element 8 is turned on by the drive circuit 1000 according to the first embodiment. Figure 15 To summarize the description so far.

[0125] exist Figure 15 In step ST110 , the drive circuit 1000 increases the gate voltage Vg of the power semiconductor element 8 at the first slope SL1 to the limit voltage VL corresponding to the threshold voltage Vth of the power semiconductor element 8 in the first time region RG1 in response to the on command of the power semiconductor element 8 .

[0126] In the next step ST120 , the driving circuit 1000 increases the gate voltage Vg from the limit voltage VL at a second slope SL2 that is gentler than the first slope SL1 in a second time region RG2 subsequent to the first time region RG1 .

[0127] In the next step ST130, at the time point ( Figure 13 At time t2, Figure 14 If gate voltage Vg has not reached Miller voltage Vm at time t3 (i.e., time t1), drive circuit 1000 increases gate voltage Vg to Miller voltage Vm in a third time period RG3 following second time period RG2 at a third slope SL3 that is gentler than first slope SL1 but steeper than second slope SL2. In the first embodiment, drive circuit 1000 increases the rate of increase of the voltage supplied to the gate terminal of power semiconductor element 8 when the first period has elapsed since receiving the on-command, regardless of whether gate voltage Vg has reached Miller voltage Vm. However, if the Miller period begins before the first period has elapsed, the effect of the increased rate of voltage increase will not manifest itself as a change in gate voltage.

[0128] In the next step ST140 , the driver circuit 1000 increases the gate voltage from the Miller voltage at a fourth slope SL4 that is steeper than the third slope SL3 in the fourth time period RG4 . Finally, the gate voltage Vg increases to the power supply voltage supplied to the driver circuit 1000 .

[0129] [Effects of Embodiment 1]

[0130] As described above, according to the drive circuit 1000 of the first embodiment, the gate voltage Vg of the power semiconductor element 8 when it is turned on is divided into four time regions: the first region RG1 to the fourth region RG4, and is controlled accordingly. Specifically, in the first region RG1, the voltage limiting circuit 1 controls the gate voltage Vg, causing the gate voltage Vg to rise sharply to approximately the threshold voltage at the first slope SL1. This shortens the dead time and reduces losses.

[0131] In the following second region RG2, the gate voltage Vg is controlled by the first variable voltage generating circuit 2. When the collector current Ic flowing through the power semiconductor device 8 is low, the gate voltage Vg reaches the Miller voltage in this second region RG2. The rate of change of the voltage generated by the first variable voltage generating circuit 2 is lower than the rate of change of the voltage generated by the second variable voltage generating circuit 3. This reduces the rate of change dVce / dt of the collector-emitter voltage Vce caused by the recovery current, resulting in reduced EMI.

[0132] In the subsequent third region RG3, when collector current Ic flowing through power semiconductor device 8 is relatively high, gate voltage Vg reaches the Miller voltage in this third region RG3. In this case, before gate voltage Vg reaches the Miller voltage, gate voltage Vg is increased at a third slope SL3, primarily using second variable voltage generating circuit 3. This third slope SL3 is greater than second slope SL2, the rate of change of gate voltage Vg in the second region RG2. This increases the rate of change dIc / dt of collector current Ic, thereby suppressing any increase in losses.

[0133] In the subsequent fourth region RG4, the gate voltage Vg is controlled using the output voltage of the comparison circuit 4. The rate of change of the gate voltage Vg at this time is made greater than the rate of change of the voltage in the second region RG2 controlled by the second variable voltage generating circuit 3. As a result, the rate of change dVce / dt of the collector-emitter voltage Vce can be increased, thereby reducing switching losses.

[0134] [Drive circuit installation method]

[0135] Hereinafter, several examples will be given to explain how to mount the driving circuit 1000 described so far.

[0136] Figure 16 FIG. 1 is a diagram showing an example of how the drive circuit 1000 according to the first embodiment is mounted. Figure 16 As shown, the drive circuit 1000 of the first embodiment can be combined with the power module 10000 including the power semiconductor element 8. In this way, the drive circuit 1000 of the first embodiment can also be configured independently of the power module 10000 including the power semiconductor element 8.

[0137] Figure 17 Yes Figure 16 The figure shows a modified example of the installation method. Figure 17 As shown, the drive circuit 1000 of the first embodiment may be included in a power module 10000a including the power semiconductor element 8. That is, the power module 10000a includes the drive circuit 1000 of the first embodiment and the power semiconductor element 8.

[0138] Figure 18 This is a diagram showing another example of how the driving circuit 1000 according to the first embodiment is mounted. Figure 18 shows a more specific example of installing a drive circuit 1000 in combination with a three-phase AC power module 10000b. Specifically, six drive circuits 1000un, 1000vn, 1000wn, 1000up, 1000vp, and 1000wp are installed to drive power module 10000b, which is composed of six power semiconductor elements. Furthermore, there is no particular limit on the number of power semiconductor elements included in a single power module. In other words, power modules can use 1-in-1, 2-in-1, 6-in-1, or multi-parallel configurations.

[0139] Figure 18 6-in-1 power module 10000b is shown. Power module 10000b includes power semiconductor elements 8up, 8vp, 8wp, 8un, 8vn, and 8wn. Each power semiconductor element 8 includes an IGBT 81 (81up, 81vp, 81wp, 81un, 81vn, 81wn) and a diode 82 (82up, 82vp, 82wp, 82un, 82vn, 82wn) connected in antiparallel therewith.

[0140] Specifically, power semiconductor elements 8up and 8un for the U phase are connected in series between the P and Q terminals. The connection node of power semiconductor elements 8up and 8un is connected to the U terminal. The gates of power semiconductor elements 8up and 8un are connected to drive circuits 1000up and 1000un, respectively. Drive circuits 1000up and 1000un are provided with control input terminals UP and UN, respectively. The same applies to the V and W phases; in the above description, u (or U) can be replaced with v and w (or V and W).

[0141] Figure 19 Yes Figure 18 The figure shows a modified example of the installation method. Figure 19 As shown, a power module 10000c composed of power semiconductor elements 8up, 8vp, 8wp, 8un, 8vn, and 8wn may include six drive circuits 1000un, 1000vn, 1000wn, 1000up, 1000vp, and 1000wp. That is, the power module 10000c includes the six drive circuits 1000un, 1000vn, 1000wn, 1000up, 1000vp, and 1000wp of the first embodiment and the corresponding power semiconductor elements 8up, 8vp, 8wp, 8un, 8vn, and 8wn.

[0142] In addition, with Figure 18 Similarly, there is no particular limit on the number of power semiconductor devices included in a single power module. Specifically, power modules can use 1-in-1, 2-in-1, 6-in-1, or multi-parallel configurations. Furthermore, a single power module contains the same number of drive circuits as power semiconductor devices.

[0143] Implementation method 2.

[0144] The power semiconductor device driving circuit 2000 of the second embodiment further includes a Miller voltage detection circuit 9 for detecting the Miller voltage, and is different from the driving circuit 1000 of the first embodiment. This will be described in detail below with reference to the drawings.

[0145] [Structure of the driving circuit]

[0146] Figure 20 This is a diagram showing a configuration of a drive circuit 2000 for a power semiconductor element according to a second embodiment. Figure 20Similar to drive circuit 1000 in Embodiment 1, drive circuit 2000 generates gate voltage Vg for controlling the switching operation of power semiconductor element 8 in accordance with the control signal input to control input terminal 7. More specifically, drive circuit 1000 sequentially controls the voltage change of gate voltage Vg during the on-state operation of power semiconductor element 8 in four time zones: first zone RG1 to fourth zone RG4. However, in Embodiment 2, the third zone RG3 may not be provided, and the control may directly transition from second zone RG2 to fourth zone RG4.

[0147] like Figure 20 As shown, the driving circuit 2000 includes a voltage limiting circuit 1, a first variable voltage generating circuit 2, a second variable voltage generating circuit 3, a comparison circuit 4, an adding circuit 5, and a buffer circuit 6, which are the same configurations as the driving circuit 1000 in the first embodiment. The functions of these circuits are the same as those in the first embodiment, except for the comparison circuit 4. Briefly, the voltage limiting circuit 1 controls the voltage variation of the gate voltage Vg in the first region.

[0148] The first variation voltage generating circuit 2 controls the voltage variation of the gate voltage Vg in the second region.

[0149] The second variable voltage generating circuit 3 controls the voltage variation of the gate voltage Vg in the third region. The comparison circuit 4 controls the voltage variation of the gate voltage Vg in the fourth region. The adding circuit 5 outputs the current and voltage output from the voltage limiting circuit 1 and the first variable voltage generating circuit 2 in the second region RG2. In the third region RG3, the adding circuit 5 adds the output current of the second variable voltage generating circuit 3 to the output currents of the voltage limiting circuit 1 and the first variable voltage generating circuit 2. The buffer circuit 6 transmits the output voltage of the adding circuit 5 to the gate terminal of the power semiconductor element 8, thereby generating a gate voltage for the power semiconductor element 8.

[0150] Drive circuit 2000 includes a novel Miller voltage detection circuit 9. Miller voltage detection circuit 9 detects when gate voltage Vg reaches the Miller voltage and outputs the detection result to comparison circuit 4. Comparison circuit 4 compares the detection result of Miller voltage detection circuit 9 with the output voltage of comparison voltage source 42 (i.e., comparison voltage VC) and outputs the comparison result. Specifically, when the output of Miller voltage detection circuit 9 is activated at a high level, the high-level output signal of Miller voltage detection circuit 9 is greater than comparison voltage VC. Therefore, in this case, comparison circuit 4 outputs the power supply voltage of drive circuit 2000 as a high-level signal to the gate terminal of power semiconductor element 8.

[0151] The driver circuit 1000 of Embodiment 1, which does not include the Miller voltage detection circuit 9, has the following problem. Specifically, in the driver circuit 1000 of Embodiment 1, the timing of transitioning to the fourth region is controlled based on the set value of the comparison voltage of the comparison circuit 4. More specifically, the comparison circuit 4 compares the comparison voltage VC (i.e., the voltage value of the comparison voltage source 42) with the output voltage V2 of the second variable voltage generation circuit 3. When the output voltage V2 is equal to or greater than the comparison voltage VC, the driver circuit 4 transitions to the fourth region, thereby varying the rate of change of the gate voltage Vg. This initiates gate voltage control in the fourth region at a timing dependent on the rate of change of the voltage V2 generated by the second variable voltage generation circuit 3. Therefore, even if the collector current Ic of the power semiconductor device changes, resulting in changes in the Miller voltage and the length of the Miller period, the timing of starting gate voltage control in the fourth region remains unchanged. Consequently, in the driver circuit 1000 of Embodiment 1, the time from when the gate voltage reaches the Miller voltage until gate voltage control in the fourth region begins increases as the collector current Ic decreases. As a result, the switching loss reduction effect achieved by increasing the rate of change dVce / dt of collector-emitter voltage Vce by controlling the rate of change of gate voltage in the fourth region decreases. In the drive circuit 2000 of the second embodiment, the above-mentioned problem is solved.

[0152] Figure 21 1 is a diagram showing an example of the structure of the Miller voltage detection circuit 9. Figure 21 As shown, the Miller voltage detection circuit 9 includes a differentiating circuit 91 , a binarizing circuit 92 , an edge detection circuit 93 , a flip-flop circuit 94 , and an inverting circuit 95 .

[0153] Differentiating circuit 91, binarizing circuit 92, and edge detection circuit 93 are connected in this order between input node IN9A and the S input of flip-flop circuit 94. Input node IN9A is connected to the gate terminal of power semiconductor element 8. Inverting circuit 95 is connected between input node IN9B and the R input of flip-flop circuit 94. Input node IN9B is connected to control input terminal 7. The Q output of flip-flop circuit 94 is connected to input node IN4 of comparison circuit 4 via output node OUT9.

[0154] In Miller voltage detection circuit 9, a differentiating circuit 91, a binarizing circuit 92, and an edge detection circuit 93 detect the Miller voltage generated in gate signal Vg of power semiconductor element 8, and a flip-flop circuit 94 holds the detected state. Furthermore, an inverting circuit 95 in Miller voltage detection circuit 9 inverts the control signal input from control input terminal 7. The inverted control signal is used to reset flip-flop circuit 94. Thus, Miller voltage detection circuit 9 detects the Miller voltage and holds the detection result when the control signal is high, and resets the held detection result when the control signal is low.

[0155] Figure 22 and Figure 23 Yes Figure 21 FIG. 9 is a diagram showing an example of a configuration of a differentiating circuit 91 . The differentiating circuit 91 differentiates the gate voltage Vg of the power semiconductor element 8 and outputs the differentiated signal to a binarization circuit 92 .

[0156] exist Figure 22 In the configuration example, the differentiating circuit 91 includes a capacitor 911 and a resistor 912. The capacitor 911 is connected between the input node IN91 and the output node OUT91. The resistor 912 is connected between the output node OUT91 and a reference node 913 to which a reference potential Vref is supplied. The input node IN91 is connected to the gate terminal of the power semiconductor element 8, and the output node OUT91 is connected to the input of the binarization circuit 92.

[0157] exist Figure 23 In the configuration example, the differentiating circuit 91 includes a resistor 914, a capacitor 915, and an operational amplifier 916. The resistor 914 is connected between the inverting input terminal of the operational amplifier 916 and its output terminal. The capacitor 915 is connected between the inverting input terminal of the operational amplifier 916 and the input node IN91A. The reference potential Vref of the driver circuit 2000 is input to the non-inverting input terminal of the operational amplifier 916 via the input node IN91B. The output terminal of the operational amplifier 916 is connected to the input of the binarization circuit 92 via the output node OUT91.

[0158] Figure 24 1 is a diagram showing an example of the structure of the binarization circuit 92. The binarization circuit 92 converts the output of the differential circuit 91 into two values, namely, a high level and a low level, and outputs the converted binarized signal to the edge detection circuit 93. Figure 24 As shown, the edge detection circuit 93 is composed of an inverting Schmitt trigger circuit 921 (also called a Schmitt trigger inverter or a hysteresis inverter).

[0159] Figure 25This diagram shows an example of the configuration of edge detection circuit 93. Edge detection circuit 93 detects the rising or falling edge of the output signal of binarization circuit 92 and outputs the detection result. Whether to detect a rising edge or a falling edge can be changed by the polarity of binarization circuit 92 or the polarity detected by flip-flop circuit 94, selecting an edge suitable for detecting when gate voltage Vg reaches the Miller voltage.

[0160] like Figure 25 As shown, the edge detection circuit 93 includes an inversion circuit (inverter) 931, a delay circuit 932, and a NOR circuit 933. For example, the delay circuit 932 includes a resistor 9321 and a capacitor 9322. The input node IN93 of the edge detection circuit 93 is connected to the first input terminal of the NOR circuit 933 and is connected to the second input terminal of the NOR circuit 933 via the inversion circuit 931 and the delay circuit 932 in sequence. The resistor 9321 of the delay circuit 932 is connected between the output terminal of the inversion circuit 931 and the second input terminal of the NOR circuit 933. The capacitor 9322 of the delay circuit 932 is connected between the second input terminal of the NOR circuit 933 and a reference node 9323 to which a reference potential Vref is supplied. The input node IN93 of the edge detection circuit 93 is connected to the output of the binarization circuit 92. The output terminal of the NOR circuit 933 is connected to the S input node of the flip-flop circuit 94 via the output node OUT93.

[0161] Figure 26 This diagram shows an example of the structure of a flip-flop circuit 94. Flip-flop circuit 94 includes two NOR circuits 941 and 942. The first input terminal of NOR circuit 941 is connected to the output node OUT93 of edge detection circuit 93 as a set terminal S. The second input terminal of NOR circuit 941 is connected to the output terminal of NOR circuit 942. The output terminal of NOR circuit 941 is connected to the first input terminal of NOR circuit 942. The second input terminal of NOR circuit 942 is connected to the output of inversion circuit 95 as a reset terminal R. The output terminal of NOR circuit 942 is connected to the input of comparison circuit 4 as output terminal Q of flip-flop circuit 94.

[0162] The flip-flop circuit 94 is activated when a signal detected by the edge detection circuit 93 is input to the set terminal S, and is deactivated when a control signal inverted by the inversion circuit 95 is input to the reset terminal R.

[0163] Figure 27This is an example of the structure of the inversion circuit 95. The inversion circuit 95 includes a NOT circuit 951. The inversion circuit 95 inverts the polarity of the control signal input from the control input terminal 7 and outputs the inverted control signal to the reset terminal R of the flip-flop circuit 94. As a result, the state held by the flip-flop circuit 94 is reset.

[0164] [Operation of the drive circuit]

[0165] Figure 28 1 is a timing chart for explaining an operation example of the power semiconductor driving circuit 2000 according to the second embodiment. Figure 28 1 shows a timing chart of a case where the collector current Ic is relatively small during the on-state operation of the power semiconductor element 8. Figure 28 The waveforms shown, starting from the top, are the control signal input to the control input terminal 7, the sum (VL + V1) of the limit voltage VL output from the voltage limiter circuit 1 and the first variable voltage V1 output from the first variable voltage generator circuit 2, the second variable voltage V2 output from the second variable voltage generator circuit 3, the output voltage V3 of the adder circuit 5, the gate voltage Vg of the power semiconductor device 8, the set signal from the flip-flop circuit 94, the output of the Miller voltage detection circuit 9 and the output of the comparison circuit 4, the collector current Ic of the power semiconductor device 8, and the collector-emitter voltage Vce. The waveforms of the gate voltage Vg, collector current Ic, and collector-emitter voltage Vce are shown in solid lines for the present embodiment, and in dashed lines for the comparative example. The comparative example shows a constant voltage drive type or constant current drive type drive circuit that does not control the gate voltage Vg of the power semiconductor device 8 in multiple time zones.

[0166] In addition, the driving circuit 2000 of the power semiconductor element according to the second embodiment is characterized in that, similar to the driving circuit 1000 according to the first embodiment, the control method of the collector current Ic and the collector-emitter voltage Vce of the power semiconductor element 8 is different between the case where the collector current Ic is relatively small and the case where the collector current Ic is relatively large. In the following description of the operation of the driving circuit 2000 according to the second embodiment, the control method of the collector current Ic and the collector-emitter voltage Vce is different between the case where the collector current Ic is relatively small and the case where the collector current Ic is relatively large. Figure 13 The difference in operation of the driving circuit 1000 in the first embodiment is shown.

[0167] The following is a chronological order of description. Figure 28 The operation of the driving circuit 2000 at time t0.

[0168] At time t0, similar to the driver circuit 1000 in Embodiment 1, when the control signal at control input terminal 7 changes from Low to High as a command for turning on, the voltage limiting circuit 1, the first variable voltage generating circuit 2, and the second variable voltage generating circuit 3 begin operation. The voltage limiting circuit 1 controls the change in gate voltage Vg in the first region RG1 around time t0. As in Embodiment 1, the voltage limiting circuit 1 rapidly increases gate voltage Vg at a first slope SL1 in the first region RG1 to approximately the threshold voltage Vth (corresponding to the limit voltage VL). This shortens dead time and reduces losses.

[0169] exist Figure 28 The operation of the driving circuit 2000 from time t0 to time t2 is the same as Figure 13 The operation of the driving circuit 1000 of the embodiment 1 shown is substantially the same. That is, the waveforms of the output combined voltage VL+V1 of the voltage limiting circuit 1 and the first variable voltage generating circuit 2, the output voltage V2 of the second variable voltage generating circuit 3, the output voltage V3 of the adding circuit 5, the collector current Ic, and the collector-emitter voltage Vce are similar to those of the embodiment 1 shown in FIG. Figure 13 The same applies to the driving circuit 1000 of the first embodiment shown.

[0170] The flip-flop circuit 94 is in an inactive state because the gate voltage Vg has not reached the Miller voltage Vm before time t2. Therefore, the output of the Miller voltage detection circuit 9 is also at a low (L) level.

[0171] Next, explain Figure 28 The operation of the driving circuit 2000 from time t2 to t5.

[0172] At time t2, gate voltage Vg reaches Miller voltage Vm. When gate voltage Vg reaches the Miller voltage, Miller voltage detection circuit 9 activates, and the timing at which gate voltage Vg reaches the Miller voltage is detected by differentiating circuit 91, binarizing circuit 92, and edge detection circuit 93. Because a delay occurs in the timing detection performed by differentiating circuit 91, binarizing circuit 92, and edge detection circuit 93, the set signal of flip-flop circuit 94 changes from Low to High at time t3, a certain period after time t2.

[0173] Furthermore, the designer can arbitrarily design the delay time generated in the timing detection by the differentiating circuit 91, the binarizing circuit 92, and the edge detection circuit 93 as a design parameter. Therefore, the designer can also arbitrarily design the interval from the time when the gate voltage Vg reaches the Miller voltage Vm to the time when the comparison circuit 4 adjusts the rate of change of the gate voltage Vg as the next operation.

[0174] When the setting signal of the trigger circuit 94 changes from low (Low) to high (High) at time t3, the output of the Miller voltage detection circuit 9 changes from low (Low) to high (High) and maintains this state. Moreover, when the output of the Miller voltage detection circuit 9 changes from low (Low) to high (High) at time t3, the determination result of the comparison circuit 4 also changes from low (Low) to high (High). When the determination result of the comparison circuit 4 becomes high (High), current is injected into the gate terminal of the power semiconductor element 8, so the gate voltage Vg increases sharply at the fourth slope SL4. That is, at Figure 28 In the example, the gate voltage Vg is directly transferred from the second region RG2 to the fourth region RG4 without passing through the third region RG3. By rapidly increasing the gate voltage Vg at the fourth slope SL4, the change rate dVce / dt of the collector-emitter voltage Vce can be increased, thereby reducing switching loss.

[0175] During the period from time t2 to time t5, the gate voltage Vg controlled by the driving circuit of the comparative example is still in the Miller period, and loss due to switching operation occurs during the Miller period. Figure 13 In the case of the driving circuit 1000 of the first embodiment shown, the timing at which the output of the comparison circuit 4 switches from Low to High is determined by the result of comparing the arbitrarily set comparison voltage of the comparison circuit 4 with the output voltage V2 of the second variable voltage generating circuit 3. Therefore, depending on the setting of the comparison voltage, the timing at which the output of the comparison circuit 4 switches from Low to High is delayed compared to the case of the driving circuit 2000 of the second embodiment.

[0176] In drive circuit 2000 of this second embodiment, even when the Miller period of gate voltage Vg varies depending on the value of collector current Ic, Miller voltage detection circuit 9 can detect the timing when gate voltage Vg reaches Miller voltage Vm, and operate comparison circuit 4 based on this detection result. In contrast, in drive circuit 1000 of the first embodiment, as Miller voltage Vm decreases, the timing of operation of comparison circuit 4 is delayed, thereby delaying the timing of controlling collector-emitter voltage Vce. Therefore, drive circuit 2000 of the second embodiment can reduce losses compared to drive circuit 1000 of the first embodiment.

[0177] After the set signal of flip-flop circuit 94 changes to High at time t3, it drops from High to Low at time t4 in response to the operation of edge detection circuit 93. The period during which edge detection circuit 93 maintains a High level can be arbitrarily set by the designer. Therefore, the period during which edge detection circuit 93 maintains a High level can be arbitrarily set based on the operable length of flip-flop circuit 94 and the frequency at which power semiconductor device 8 is operated.

[0178] At time t5, when gate voltage Vg reaches the power supply voltage of driver circuit 2000, edge detection circuit 93 of Miller voltage detection circuit 9 changes from Low to High. However, since the output of flip-flop circuit 94, i.e., the output of Miller voltage detection circuit 9, has remained High since time t3, these output states do not change.

[0179] At time t7, when the control signal changes from High to Low, the shutdown operation begins, and the output voltages V1 of the voltage limiting circuit 1 and the first variable voltage generating circuit 2, the output voltage V2 of the second variable voltage generating circuit 3, and the output voltage V3 of the adding circuit 5 all decrease to 0.

[0180] Furthermore, when the control signal in Miller voltage detection circuit 9 changes from High to Low, the reset signal of flip-flop circuit 94 changes to a High level. This resets the state held by flip-flop circuit 94. In other words, both the output of Miller voltage detection circuit 9 and the determination result of comparison circuit 4 change from High to Low. This terminates the injection of current into the gate terminal of power semiconductor element 8.

[0181] Figure 29 This is a flowchart showing a control process when the power semiconductor element 8 is turned on by the drive circuit 2000 according to the second embodiment. Figure 29 To summarize the description so far.

[0182] exist Figure 29 In step ST110 , the drive circuit 2000 increases the gate voltage Vg of the power semiconductor element 8 at the first slope SL1 to the limit voltage VL corresponding to the threshold voltage Vth of the power semiconductor element 8 in the first time region RG1 in response to the on command of the power semiconductor element 8 .

[0183] In the next step ST120 , the driving circuit 2000 increases the gate voltage Vg from the limit voltage VL at a second slope SL2 that is gentler than the first slope SL1 in a second time region RG2 subsequent to the first time region RG1 .

[0184] If Miller voltage detection circuit 9 then detects that gate voltage Vg has reached Miller voltage Vm ("YES" in step ST125), drive circuit 2000 proceeds to step ST150. In step ST150, drive circuit 2000 increases gate voltage Vg from the Miller voltage at a fourth slope SL4 that is steeper than third slope SL3. Ultimately, gate voltage Vg increases to the power supply voltage supplied to drive circuit 2000.

[0185] On the other hand, if Miller voltage detection circuit 9 has not detected that gate voltage Vg has reached Miller voltage Vm after the first period has elapsed since the on command was received (NO in step ST125 ), the process proceeds to step ST130 .

[0186] In step ST130 , the driving circuit 2000 increases the gate voltage Vg to the Miller voltage Vm at a third slope SL3 that is gentler than the first slope SL1 but steeper than the second slope SL2 in a third time region RG3 following the second time region RG2 .

[0187] [Effects of Embodiment 2]

[0188] As described above, according to the drive circuit 2000 of the second embodiment, similar to the drive circuit 1000 of the first embodiment, the gate voltage Vg of the power semiconductor element 8 when it is turned on is basically divided into four time regions: the first region RG1 to the fourth region RG4, and is controlled. Specifically, in the first region RG1, the voltage limiting circuit 1 controls the gate voltage Vg, causing the gate voltage Vg to increase sharply with the first slope SL1 to approximately the threshold voltage. This shortens the dead time and reduces losses.

[0189] In the following second region RG2, the gate voltage Vg is controlled by the first variable voltage generating circuit 2. When the collector current Ic flowing through the power semiconductor device 8 is low, the gate voltage Vg reaches the Miller voltage in this second region RG2. The rate of change of the voltage generated by the first variable voltage generating circuit 2 (corresponding to the second slope SL2) is lower than the rate of change of the voltage generated by the second variable voltage generating circuit 3. This reduces the rate of change dVce / dt of the collector-emitter voltage Vce caused by the recovery current, resulting in reduced EMI.

[0190] The control in the subsequent third region RG3 is performed when the collector current Ic flowing through the power semiconductor device 8 is relatively high. When the collector current Ic is relatively high, the gate voltage Vg reaches the Miller voltage midway through the third region RG3. In this case, control is performed such that, before the gate voltage Vg reaches the Miller voltage, the second variable voltage generating circuit 3 is used to increase the gate voltage Vg at a third slope SL3 greater than the second slope SL2. This results in a greater rate of change dIc / dt of the collector current Ic, thereby suppressing any increase in losses.

[0191] The control in the subsequent fourth region RG4 is performed based on the detection by Miller voltage detection circuit 9 of the timing at which gate voltage Vg reaches Miller voltage Vm. Comparison circuit 4 operates in response to the detection of the timing at which Miller voltage Vm is reached, thereby increasing the rate of change dVce / dt of collector-emitter voltage Vce and reducing switching losses. Because comparison circuit 4 operates based on the detection results of Miller voltage detection circuit 9, switching losses can be reduced compared to the drive circuit 1000 of Embodiment 1, in which the timing of comparison circuit 4 operation is delayed as the Miller voltage decreases.

[0192] [Mounting Method of Driving Circuit in Embodiment 2]

[0193] Reference to Implementation 1 Figures 16 to 19 The described mounting method can also be applied to the driving circuit 2000 of the second embodiment.

[0194] The embodiments disclosed herein are to be considered in all respects as illustrative and non-restrictive. The scope of the present application is indicated by the claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A driving circuit for a power semiconductor element, wherein: A first gate voltage control circuit is provided, which controls the gate voltage of the power semiconductor element in a first time zone, a second time zone, and a third time zone in a sequence of different modes in response to an on-command of the power semiconductor element, thereby making the gate voltage reach the Miller voltage. The gate voltage reaches the Miller voltage in the second time zone or the third time zone according to the magnitude of the main current flowing in the power semiconductor element. A second gate voltage control circuit is further provided, the second gate voltage control circuit controlling the gate voltage to be equal to or higher than the Miller voltage.

2. The driving circuit of the power semiconductor element according to claim 1, wherein: The first gate voltage control circuit is composed of: In the first time zone, the gate voltage is increased to a first voltage with a first slope, In the second time zone, the gate voltage is increased from the first voltage at a second slope that is gentler than the first slope, If the gate voltage does not reach the Miller voltage in the second time zone, in the third time zone, the gate voltage is increased to the Miller voltage with a third slope that is gentler than the first slope but steeper than the second slope, The second gate voltage control circuit is composed of: The gate voltage is increased from the Miller voltage at a fourth slope that is steeper than the third slope.

3. The driving circuit of the power semiconductor element according to claim 2, wherein: The first gate voltage control circuit comprises: A first voltage generating circuit, generating the first voltage; a first changing voltage generating circuit, generating a first changing voltage that increases at a first changing rate corresponding to the second slope, and superimposing the first changing voltage on the first voltage; a second changing voltage generating circuit for generating a second changing voltage which increases at a second changing rate which is greater than the first changing rate; an adding circuit that outputs the first changing voltage superimposed on the first voltage in the second time zone, and generates a third changing voltage that increases at a changing rate corresponding to the second slope based on the first voltage, the first changing voltage, and the second changing voltage in the third time zone; and The buffer circuit transmits the voltage generated by the adding circuit to the gate of the power semiconductor element.

4. The driving circuit of the power semiconductor element according to claim 3, wherein: The first variable voltage generating circuit and the second variable voltage generating circuit start generating the first variable voltage and the second variable voltage, respectively, upon receiving the on instruction. When the sum of the first voltage and the first changed voltage is equal to the second changed voltage, the second time zone is switched to the third time zone.

5. The driving circuit of the power semiconductor element according to claim 3 or 4, wherein: The first voltage generating circuit includes a Zener diode that limits the gate voltage of the power semiconductor element to the first voltage when the gate voltage increases.

6. The driving circuit of the power semiconductor element according to any one of claims 3 to 5, wherein: The adding circuit includes a diode, a cathode of the diode is applied with the first voltage and the first changed voltage, and an anode of the diode is applied with the second changed voltage. A voltage at a cathode of the diode is input to the buffer circuit.

7. The driving circuit of a power semiconductor element according to any one of claims 3 to 6, wherein: The first variation voltage generating circuit and the second variation voltage generating circuit each include a first-order lag circuit using a resistance element and a capacitance element, A step input corresponding to the switch-on command is input to the first-order lag circuit, An output of the first-order lag circuit corresponds to the first changing voltage or the second changing voltage.

8. The driving circuit of a power semiconductor element according to any one of claims 3 to 6, wherein: The first variation voltage generating circuit and the second variation voltage generating circuit each include a capacitance element and a current source that inputs a current to the capacitance element in response to the on instruction, and outputs a voltage of the capacitance element as the first variation voltage or the second variation voltage.

9. The driving circuit of a power semiconductor element according to any one of claims 3 to 8, wherein: The second gate voltage control circuit includes a comparator, which compares the first change voltage or the second change voltage with a certain comparison voltage. The comparator outputs the power supply voltage of the drive circuit to the gate of the power semiconductor element as a high-level output when the first variable voltage or the second variable voltage becomes larger than the comparison voltage.

10. The driving circuit of a power semiconductor element according to any one of claims 2 to 9, wherein: The driving circuit further includes a Miller voltage detection circuit, the Miller voltage detection circuit detecting a timing when the gate voltage reaches the Miller voltage. The second gate voltage control circuit outputs the power supply voltage supplied to the drive circuit to the gate of the power semiconductor element based on the timing detected by the Miller voltage detection circuit.

11. The driving circuit of the power semiconductor element according to claim 10, wherein: The Miller voltage detection circuit comprises: A differential circuit, outputting a time differential of the gate voltage; A binarization circuit converts the output of the differential circuit into two values, a high level and a low level, and outputs the converted value; and The edge detection circuit detects the edge of the output waveform of the binarization circuit.

12. A power module comprising: Semiconductor components for power use; and A drive circuit as claimed in any one of claims 1 to 11.

13. A method for driving a power semiconductor element, comprising: In a first time period after receiving a command to turn on the power semiconductor element, increasing the gate voltage of the power semiconductor element to a first voltage at a first slope; In a second time zone subsequent to the first time zone, the gate voltage is increased from the first voltage at a second slope gentler than the first slope; If the gate voltage does not reach the Miller voltage in the second time zone, in a third time zone following the second time zone, increase the gate voltage to the Miller voltage with a third slope that is gentler than the first slope but steeper than the second slope; as well as The step of increasing the gate voltage from the Miller voltage at a fourth slope that is steeper than the third slope.

14. The method for driving a power semiconductor element according to claim 13, wherein: The step of increasing the gate voltage from the Miller voltage at the fourth slope is performed when a predetermined period has elapsed since the on command was received.

15. The method for driving a power semiconductor element according to claim 13, wherein: The driving method further comprises a step of detecting a timing at which the gate voltage reaches the Miller voltage. The step of increasing the gate voltage from the Miller voltage at the fourth slope is performed based on the detected timing.

16. The method for driving a power semiconductor element according to claim 15, wherein: The step of detecting the timing at which the gate voltage reaches the Miller voltage comprises: a step of detecting a time differential of the gate voltage; The step of converting the detected time differential into two values ​​of a high level and a low level; and The step of detecting the edge of the time differential converted into said binary value.

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