A semiconductor power entity and method for producing such entity by hybrid bonding

Abstract

The invention relates to a semiconductor power entity comprising: a first laminate layer; a second laminate layer; the isolation layer is arranged between the first lamination layer and the second lamination layer; a first metal layer disposed at a first lamination upper main surface of the first lamination layer; a second metal layer disposed at a first lamination undermain surface of the first lamination layer; a third metal layer disposed at a second laminate upper main surface of the second laminate layer; a fourth metal layer disposed at a second lamination lower main surface of the second lamination layer; and the connecting metal layer is embedded in the isolation layer between the first lamination layer and the second lamination layer, and the connecting metal layer is electrically connected with the second metal layer and the third metal layer. The invention further describes a method for producing such a semiconductor power entity. The method provides for simultaneous formation of electrical connections and isolation layer bonds in one lamination or bonding step.

Description

Technical Field

[0001] The present invention relates to the field of power products and methods for producing the same. In particular, the present invention relates to a semiconductor power entity and a method for producing such an entity by hybrid bonding. Specifically, a hybrid bonding method and a corresponding structure are disclosed. Background Art

[0002] To increase power density and efficiency in next generation power packages, short, current capable, low parasitic interconnect paths, very good thermal management, and electrical isolation are essential. Current targets are wire traces with current capabilities of tens to hundreds of amperes and power modules with internal stray inductances below 10nH.

[0003] In today’s chip embedding technology, only limited interconnect capabilities are available. In order to establish a connection between two vertically arranged power semiconductors on 2 different core layers, only microvia interconnects can be produced outside the projected physical outline of the two components, i.e. outside the die area. In order to take into account the via process tolerances, the vias must be placed at a minimum distance of about 400μm to 500μm from the edge of the embedded component. This results in long wiring distances and leads to high commutation loop inductances. Another serious disadvantage of this setup is the thermal decoupling caused by the laminate layer between the two dies, which usually has a low thermal conductivity. Depending on the cooling on either side of the component, the dies can reach different operating temperatures and produce a decentralized switching behavior. Summary of the invention

[0004] The present invention provides a solution for semiconductor power products and for manufacturing such power products without the above mentioned disadvantages.

[0005] In particular, the present invention proposes a solution for a semiconductor power entity having improved thermal characteristics and providing low parasitic interconnection paths.

[0006] The above and other objects are achieved by the features of the independent claims. Other implementations are apparent from the dependent claims, the description and the drawings.

[0007] The solution proposed by the present invention achieves these goals at a feasible cost through a combination of vertical system integration (3rd dimension), panel-level packaging and low-temperature metal connection (e.g., diffusion welding or sintering). Through the combination of these technologies, the following advantages can be achieved:

[0008] Vertical system integration (3D integration) greatly shortens the interconnection length and significantly improves the power density. According to the present invention, the technology can be used for chip embedding or other panel level packaging technology and power device packaging on an industrial scale.

[0009] Hybrid bonding according to the present invention is a process that can bond metal contacts and dielectric areas simultaneously in one bonding process. Hybrid bonding can be used for wafer-level 3D integration. Typically, a direct surface activated bonding (SAB) process is used, which requires specialized high vacuum equipment and strict control of surface quality, for example, roughness in the range of about 1 nm. This makes hybrid bonding in its current form unsuitable for power electronic packaging. The present invention proposes a mechanism that enables this technology to be used in a panel-level hybrid bonding process for power electronic device packaging.

[0010] Chip embedding according to the present invention uses printed circuit board (PCB) materials directly connected to the semiconductor die. In addition to excellent electrical and thermal performance, chip embedding also has the advantage of panel-level mass production. At present, CE, which is still a new technology, has not been used for 3D stacking. Chip embedding can be used, but due to limitations such as direct vertical connection, chip embedding (only one core layer, i.e., laminate layer) has not been used yet.

[0011] According to the present invention, vertical connections can be made between pre-fabricated PCB layers, thereby forming a connection layer that embeds a large connection metal area into the isolation material, thereby achieving sufficient current carrying capacity and thermal conductivity for power electronic devices.

[0012] The present invention is based on the concept that a direct vertical connection can be made between two or more laminated core layers (also referred to as laminate layers or core layers), the vertical connection having the following characteristics: the vertical connection can be made within the projected physical outline of the embedded component; the vertical connection is not limited to a certain shape (e.g., circular) or size (e.g., 100 μm in diameter); the vertical connection does not require an outer layer electroplating process to form an electrical connection; the vertical connection is suitable for power electronic devices (with low inductance and high current capability); the vertical connection is reliable and will not remelt at bonding temperatures; the vertical connection can be formed by diffusion welding or sintering.

[0013] The method or process of forming these vertical connections has the following characteristics: using standard PCB lamination processes (bonding temperature, pressure, format); using hybrid bonding to bond metal to metal and dielectric to dielectric in one step; several prefabricated layers can be connected to each other in one lamination step or in several consecutive lamination steps; the bonding material can be attached or applied to the surface of the laminate layer or placed between the laminate layers before bonding.

[0014] In the case of diffusion welding, vertical metal-to-metal connections can be based on the formation of an intermetallic phase in a selected bimetallic or multimetallic system. The structure can have at least three layers, including at least one metal or metal alloy layer with a low melting point, which is located between two separate metal layers with a high melting point.

[0015] Typical low melting point metals that can be used are, for example, tin (Sn) and indium (In), and high melting point metals or top metal layers are, for example, copper (Cu), gold (Au) and silver (Ag). In diffusion welding, the two high melting point metal layers can be bonded together by at least one low temperature melting metal layer. During the bonding process, the layers can be pressed against each other and the temperature can be raised to above the eutectic point of the selected metal system. Since the temperature is higher than the eutectic point of the selected metal system, a liquid phase will appear, and the metals will begin to diffuse into each other and produce intermetallic compounds (IMC). Since the intermetallic compounds formed have a higher melting point, these intermetallic compounds will gradually solidify. If the bonding time is long enough, all low melting point metals will react with the high melting point metal to form intermetallic compounds, and the joint will be completely solidified. The melting point of the intermetallic compound formed is significantly higher than that of the low melting point metal, and the joint will no longer melt at the bonding temperature.

[0016] The diffusion soldering process can be divided into five stages: wetting, alloying, liquid diffusion, gradual solidification, and solid diffusion. Suitable metals, metal alloys, or pastes can be applied to one or two laminated layers or between laminated layers (with metal) by electroplating, printing, dispensing, or other suitable methods. For example, diffusion soldering or sintering can be used to form metal interconnects.

[0017] The disclosed semiconductor power entity can be described by the following main features, namely: two or more laminated layers, which are i) laminated together with an isolation polymer layer; ii) have Cu metal wiring on at least the top and bottom sides; iii) are electrically connected with non-remeltable metal joints embedded in the isolation polymer layer.

[0018] Other features are as follows: All laminate layers are panel-level PCB core layers (up to normal PCB production size); power components are embedded inside at least one laminate layer; the first power die in the first laminate layer and the second power die in the second laminate layer can face different directions, but not limited to this, in some other applications, the first power die and the second power die can also face the same direction. In one example, the first power die in the first laminate layer and the second power die in the second laminate layer can be set in a half-bridge configuration. It is understood that many other configurations of the two power die are also possible.

[0019] To describe the present invention in detail, the following terms, abbreviations and symbols will be used:

[0020] PCB Printed Circuit Board

[0021] SAB Surface Activated Bonding

[0022] HDI High Density Interconnect

[0023] SLID solid-liquid interdiffusion

[0024] TLP Transient Liquid Phase

[0025] TLPB Transient Liquid Phase Bonding

[0026] IMC Intermetallic Compound

[0027] The invention relates to a semiconductor power entity according to a first aspect, a method for producing such a semiconductor power entity according to a second aspect, a computer program product according to a third aspect and a computer readable medium according to a fourth aspect, as described below.

[0028] According to a first aspect, the present invention relates to a semiconductor power entity, comprising: a first laminate layer, the first laminate layer having a first laminate upper main surface and a first laminate lower main surface opposite to the first laminate upper main surface; a second laminate layer, the second laminate layer having a second laminate upper main surface and a second laminate lower main surface opposite to the second laminate upper main surface; an isolation layer, the isolation layer is arranged between the first laminate layer and the second laminate layer; a first metal layer, the first metal layer is arranged at the first laminate upper main surface of the first laminate layer; a second metal layer, the second metal layer is arranged at the first laminate lower main surface of the first laminate layer; a third metal layer, the third metal layer is arranged at the second laminate upper main surface of the second laminate layer; a fourth metal layer, the fourth metal layer is arranged at the second laminate lower main surface of the second laminate layer; a connecting metal layer, the connecting metal layer is embedded in the isolation layer between the first laminate layer and the second laminate layer, and the connecting metal layer forms an electrical connection with the second metal layer and the third metal layer.

[0029] Such semiconductor power entities provide the advantage of having direct vertical connections between two or more laminated core layers. If the laminated layer has such embedded components, these vertical connections can be made within the projected physical outline of the embedded components; these vertical connections are not limited to a specific shape or size, that is, these vertical connections can be flexibly designed in shape and size; these vertical connections do not require an outer layer plating process to form an electrical connection; these vertical connections are suitable for power electronic devices because these vertical connections have low inductance and high current capability; these vertical connections are reliable and will not remelt at bonding temperatures. These vertical connections can be formed by, for example, solid-liquid interdiffusion (SLID), transient liquid phase (TLP) bonding or sintering.

[0030] As a result, semiconductor power entities offer higher power density and efficiency, short, low parasitic interconnect paths with current capability, very good thermal management, and improved electrical isolation. Conductor traces with current capability of tens to hundreds of amperes or even higher and power modules with internal stray inductances below about 10nH or even lower can be realized.

[0031] The first metal layer, the second metal layer, the third metal layer, and the fourth metal layer may be redistribution or routing metal layers for redistributing or routing current paths. It is understood that the semiconductor power entity is not limited to these four metal layers and two laminated layers, as exemplarily shown in the figure. The semiconductor power entity may also have more layers. The laminated layers may also be layers of a multilayer board, for example, four or six layers, instead of the two-layer board shown in the figure here, which is only an example of such a multilayer board.

[0032] A semiconductor power entity can also be called a semiconductor power product. This product can also be a module or a larger size product (PCB), for example, the power components can be embedded inside the PCB and the rest of the components can be placed on top. Depending on the passive components, for example, some or all of the passive components can also be embedded in the PCB, depending on the type of passive components.

[0033] In an exemplary implementation of a semiconductor power entity, the connection metal layer forms a non-reflowable electrical and mechanical connection.

[0034] This "non-reflow" connection is different from the ordinary solder connection formed during the traditional TC / NCP process (thermocompression bonding with solder and pre-applied non-conductive polymer). The advantage of a non-reflow connection is that it is a connection that will not remelt or decompose at a temperature much higher than the process temperature that forms the connection.

[0035] In an exemplary implementation of the semiconductor power entity, the connection metal layer forms one of a diffusion solder connection or a sintered connection.

[0036] Diffusion welding or diffusion bonding is a metal joining technique that can be advantageously applied in electronic packaging. Its operating principle is the mutual diffusion of two different metals, wherein the liquid phase is completely transformed into a solid state by metallic phase reaction and the formation of intermetallic compounds. Similar terms for this technique are transient liquid phase bonding, solid-liquid interdiffusion, isothermal solidification. The advantage of this technique is that the resulting solid phase has a higher melting point than the temperature of the formation process.

[0037] Sintering is the process of compacting and forming a solid block of material by heat or pressure without melting it to the liquid point. Sintering is part of the manufacturing process of metals, ceramics, plastics and other materials. The atoms in the material diffuse through the boundaries of the particles, fusing the particles together and forming a solid block. The advantages of sintering are as follows: Since the sintering temperature does not have to reach the melting point of the material, sintering is often chosen as the forming process for materials with very high melting points.

[0038] For example, the metals may be connected to form a composite metal layer. Such a composite metal layer may include a compound of two or more metals, such as an intermetallic layer, or a connection of metal layers composed of a single metal, or a connection of a metal and a polymer or a polymer mixture.

[0039] For such an intermetallic layer, the melting point of the intermetallic layer is higher than the lamination / processing temperature when the intermetallic layer is formed.

[0040] For example, the connecting metal layer may be composed of more than 80% metal and less than 20% pores or polymer.

[0041] The connecting metal layer is designed for high current loads.

[0042] In one embodiment, the intermetallic layer may have a minimum lateral dimension of typically >1 mm but not less than 0.1 mm in each dimension.

[0043] The intermetallic layer can be a good conductor with a large cross-section and a short length, and is therefore suitable for high current loads.

[0044] In one embodiment, a typical thickness of the connection metal layer is 5 μm to 50 μm, but does not exceed 0.2 mm (in the case of a single-layer structure).

[0045] In an exemplary implementation of the semiconductor power entity, the first laminate layer embeds the first power semiconductor; and / or the second laminate layer embeds the second power semiconductor.

[0046] The advantages of such semiconductor power entities are higher power density and efficiency, short, low parasitic interconnection paths with current capability, very good thermal management and improved electrical isolation. Power modules with conductor traces with current capability of, for example, tens of amperes to hundreds of amperes and internal stray inductances of, for example, less than about 10 nH can be realized.

[0047] When defining a first power semiconductor and a second power semiconductor, this does not exclude that more than one first power semiconductor may be embedded in the first laminate layer and more than one second power semiconductor may be embedded in the second laminate layer.

[0048] In an exemplary implementation of the semiconductor power entity, the connection metal layer vertically connects the second metal layer and the third metal layer to provide a vertical electrical connection between the first power semiconductor and the second power semiconductor.

[0049] The benefit of this is that the shortest path electrical connection can be achieved, thereby reducing the stray inductance of the power entity and the impedance between the two metal layers.

[0050] In an exemplary implementation of a semiconductor power entity, the connecting metal layer forms a direct electrical connection path between the first power semiconductor and the second power semiconductor without detouring via a via disposed laterally to the two power semiconductors.

[0051] As described above, this direct electrical connection path provides the advantage of a shortest path large area electrical connection between two metal layers, thereby reducing impedance and stray inductance.

[0052] In an exemplary implementation of a semiconductor power entity, the second metal layer and / or the third metal layer includes at least one of copper, gold, silver, palladium or nickel, or a combination thereof; in the case of a diffusion soldering connection, the connecting metal layer includes any suitable low-temperature melting metal, for example, tin and indium and any one of the metals of the second metal layer or the third metal layer, or an alloy thereof; in the case of a sintering connection, the connecting metal layer includes a porous layer of silver or copper or other suitable sintered metal with an optional polymer filler.

[0053] The advantage of this is that many metals and metal alloys or combinations thereof with different properties can be applied.

[0054] Note that such a connection metal layer also includes the following combination: (tin or indium or (tin and indium)) and any one of the metals of the second metal layer or the third metal layer or an alloy thereof.

[0055] In an exemplary implementation of the semiconductor power entity, the first power semiconductor and the second power semiconductor are used to form a half-bridge configuration. It is understood that many other configurations of the two power semiconductors are also achievable.

[0056] The benefit of this is that semiconductor power entities can be efficiently used in automotive power conversion systems and other applications of semiconductor power entities. The half-bridge configuration is a key topological element that appears repeatedly in power electronics conversion circuits.

[0057] In an exemplary implementation of a semiconductor power entity, the first power semiconductor is a vertical device, which includes at least one first terminal opposite to the first laminated upper main surface and a second terminal opposite to the first laminated lower main surface; the second power semiconductor is a vertical device, which includes at least one first terminal opposite to the second laminated upper main surface and a second terminal opposite to the second laminated lower main surface.

[0058] The benefit of this is that the semiconductor power entity can provide high current density, high power dissipation and high reverse breakdown voltage.

[0059] In an alternative exemplary implementation of the semiconductor power entity, the first power semiconductor may be a lateral device and the second power semiconductor may also be a lateral device.

[0060] In an exemplary implementation of a semiconductor power entity, as described below with reference to Figure 2a The semiconductor power entity comprises: at least one first through hole and at least one second through hole, wherein the at least one first through hole and the at least one second through hole extend through the first laminate layer, wherein the at least one first through hole forms an electrical connection between the at least one first terminal of the first power semiconductor and the first metal layer, and the at least one second through hole forms an electrical connection between the second terminal of the first power semiconductor and the second metal layer; at least one third through hole and at least one fourth through hole, wherein the at least one third through hole and the at least one fourth through hole extend through the second laminate layer, wherein the at least one third through hole forms an electrical connection between the at least one first terminal of the second power semiconductor and the third metal layer, and the at least one fourth through hole forms an electrical connection between the second terminal of the second power semiconductor and the fourth metal layer.

[0061] The advantage of this design is that the shortest path between two opposite internal terminals of the power semiconductor can be used for electrical connection. Due to the large area, this makes the parasitic impedance of this buried connection low and the current capability high. The buried connection can even be made larger than the die itself. Without the disclosed technology, this connection can only be achieved by providing through holes at the periphery outside the projected die area.

[0062] With such a design, both power semiconductors can be fully embedded in the corresponding laminate layers, resulting in excellent electrical performance.

[0063] In an alternative embodiment, as described below with reference to Figure 2c to Figure 2e As shown, these vias can be replaced by large-area connections so that the front side of the die or the back side of the die can be directly connected to the metal layer without any distance. Note that large-area connections are usually made on one side of each chip. With development and process improvements, large-area connections can be made on both sides, but in this case, it is most likely to be one large-area connection / via rather than multiple small vias.

[0064] The advantage of these large area connections is that they can be configured to a) further optimize parasitic impedance by shortening the electrical path, or b) further optimize the thermal path by directly extracting heat without the need for micro vias on the external surface of the solid body.

[0065] In an exemplary implementation of a semiconductor power entity, as described below with reference to Figures 4a to 4d and Figure 5 The first power semiconductor has a first semiconductor upper main surface and a first semiconductor lower main surface opposite to the first semiconductor upper main surface; the first semiconductor upper main surface is coplanarly arranged with the first laminate upper main surface to form an electrical connection between the at least one first terminal of the first power semiconductor and the first metal layer at the first laminate upper main surface; the second terminal of the first power semiconductor is electrically connected to the second metal layer at the first laminate lower main surface through one or more micro-vias extending through the first laminate layer. Alternatively, the first semiconductor lower main surface is coplanarly arranged with the first laminate lower main surface to form an electrical connection between the second terminal of the first power semiconductor and the second metal layer at the first laminate lower main surface; the at least one first terminal of the first power semiconductor is electrically connected to the first metal layer at the first laminate upper main surface through one or more micro-vias extending through the first laminate layer.

[0066] The advantage of this design is that one side of the chip is connected to the chip with a large area of ​​the corresponding metal layer, which improves heat dissipation and electrical performance.

[0067] In an exemplary implementation of a semiconductor power entity, the second power semiconductor has a second semiconductor upper main surface and a second semiconductor lower main surface opposite to the second semiconductor upper main surface; the second semiconductor upper main surface is arranged coplanar with the second laminate upper main surface to form an electrical connection between the at least one first terminal of the second power semiconductor and the third metal layer at the second laminate upper main surface; the second terminal of the second power semiconductor is electrically connected to the fourth metal layer at the second laminate lower main surface through one or more micro-vias extending through the second laminate layer. Alternatively, the second semiconductor lower main surface is arranged coplanar with the second laminate lower main surface to form an electrical connection between the second terminal of the second power semiconductor and the fourth metal layer at the second laminate lower main surface; the at least one first terminal of the second power semiconductor is electrically connected to the third metal layer at the second laminate upper main surface through one or more micro-vias extending through the second laminate layer.

[0068] The advantage of this design is that the chip side is connected to the large area of ​​the corresponding metal layer, as described above. This large area chip connection can improve heat dissipation and electrical performance.

[0069] According to a second aspect, the invention relates to a method for producing a semiconductor power entity, as hereinafter referred to Figures 4a to 4d and Figure 5 The method comprises: providing a first laminated layer embedded with a first power semiconductor, the first laminated layer having a first laminated upper main surface and a first laminated lower main surface opposite to the first laminated upper main surface; wherein a first metal layer is arranged at the first laminated upper main surface of the first laminated layer, and a second metal layer is arranged at the first laminated lower main surface of the first laminated layer; providing a second laminated layer embedded with a second power semiconductor, the second laminated layer having a second laminated upper main surface and a second laminated lower main surface opposite to the second laminated upper main surface; wherein a third metal layer is arranged at the second laminated upper main surface of the second laminated layer, and a fourth metal layer is arranged at the second laminated lower main surface of the second laminated layer ; Applying bonding metal at the second metal layer of the first laminate layer and / or the third metal layer of the second laminate layer, wherein the bonding metal is placed between the first power semiconductor and the second power semiconductor and / or between corresponding electrical contact pairs in the first laminate layer and the second laminate layer, and an isolation layer is arranged between the second metal layer of the first laminate layer and the third metal layer of the second laminate layer; Stacking and laminating the first laminate layer, the second laminate layer and the isolation layer to a semiconductor power entity, wherein the lamination transforms the bonding metal into a connecting metal layer, and the connecting metal layer forms an electrical connection with the second metal layer and the third metal layer.

[0070] This method or process provides the advantages of forming the above-mentioned vertical connection. The method or process provides the following advantageous features: using standard PCB lamination processes with respect to bonding temperature, pressure, format; using hybrid bonding to bond metal to metal and dielectric to dielectric in one step; several prefabricated layers can be connected to each other in one lamination step or in several consecutive lamination steps; bonding materials can be attached or applied to the surface of the lamination layer or placed between the lamination layers before bonding.

[0071] In an exemplary implementation of the method, the connection metal layer is formed simultaneously with the lamination of the first lamination layer, the second lamination layer and the isolation layer.

[0072] This has the advantage that the manufacturing method can be simplified due to the simultaneous execution of two production steps.

[0073] In an exemplary implementation of the method, as described below with reference to Figure 4a The method comprises: applying the bonding metal to the second metal layer of the first laminate layer before the stacking and lamination; applying the isolation layer to the third metal layer of the second laminate layer before the stacking and lamination, wherein the isolation layer is constructed to form an opening for embedding the bonding metal.

[0074] The benefit here is flexibility in the order of the different production steps. For example, it doesn’t matter to which laminate layer the bonding metal or the isolation layer is applied. They just have to be complementary.

[0075] In an exemplary implementation of the method, applying the bonding metal includes electroplating of metal, printing or dispensing of paste, and placement of a preform; wherein applying the isolation layer includes printing, coating, laminating or dispensing of a dielectric material.

[0076] This has the benefit of providing an alternative to applying a bonding metal and applying an isolation layer.

[0077] In an exemplary implementation of the method, as described below with reference to Figure 4d The method comprises: applying the isolation layer at the third metal layer of the second lamination layer before the stacking and lamination, wherein the isolation layer is constructed to form an opening for embedding the bonding metal; and placing the bonding metal in the opening of the isolation layer on the third metal layer.

[0078] The benefit of this is flexibility in the sequence of the different production steps.

[0079] In an exemplary implementation of the method, as described below with reference to Figure 4bThe method comprises placing the isolation layer between the second metal layer of the first laminate layer and the third metal layer of the second laminate layer during the lay-up and lamination process, wherein the isolation layer is unstructured.

[0080] The benefit of this is flexibility in the sequence of the different production steps.

[0081] In an exemplary implementation of the method, as described below with reference to Figure 4c The method includes placing the isolation layer between the second metal layer of the first laminate layer and the third metal layer of the second laminate layer during the stacking and lamination process, wherein the isolation layer is configured to form an opening for embedding the bonding metal.

[0082] This has the benefit of providing an alternative to placing an isolation layer.

[0083] The following process steps of the above method are optional: drilling holes extending from the first metal layer to the fourth metal layer in the semiconductor power entity, wherein the holes are drilled laterally into the first power semiconductor and the second power semiconductor; performing metal electroplating on the holes to form metal-plated through-holes electrically connecting the first metal layer and optionally the second metal layer, the third metal layer and the fourth metal layer; constructing the first metal layer and the fourth metal layer.

[0084] According to a third aspect, the present invention relates to a computer program product comprising computer executable code or computer executable instructions, which, when executed, cause at least one computer to perform the method according to the above second aspect.

[0085] The computer program product may be run on a controller or a processor to implement the above method to produce a semiconductor power entity according to the above first aspect.

[0086] According to a fourth aspect, the present invention relates to a computer-readable medium storing instructions, which, when executed by a computer, cause the computer to perform the method according to the second aspect. Such a computer-readable medium may be a non-transitory readable storage medium. The instructions stored on the computer-readable medium may be executed by a controller or a processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] Other embodiments of the present invention will be described in conjunction with the following drawings, in which:

[0088] Figure 1a A schematic diagram showing the production 10 of a semiconductor power product 13 without hybrid bonding provided by the present invention;

[0089] Figure 1b A schematic diagram showing the production 20 of a semiconductor power product 23 using hybrid bonding provided by the present invention is shown;

[0090] Figure 2a shows a schematic cross section of a semiconductor power entity 100 provided by a first embodiment;

[0091] Figure 2b shows a schematic cross section of a semiconductor power entity 100b provided by a second embodiment;

[0092] Figure 2c shows a schematic cross section of a semiconductor power entity 100c provided by a third embodiment;

[0093] Figure 2d shows a schematic cross section of a semiconductor power entity 100d provided by a fourth embodiment;

[0094] Figure 2e shows a schematic cross section of a semiconductor power entity 100e provided by a fifth embodiment;

[0095] Figure 3 Different options of metal stacks for producing panel-level hybrid bonding provided by the present invention are shown; wherein,

[0096] Figure 3 a shows a single layer single surface as a first option;

[0097] Figure 3 b shows a single-layer double-sided as a second option;

[0098] Figure 3 c shows multi-layer, single-sided or double-sided as a third option;

[0099] Figure 3 d shows a preform as a fourth option;

[0100] Figure 4a shows a process flow chart of a method for producing a semiconductor power entity according to a first embodiment with reference to resin printing;

[0101] Figure 4b shows a process flow chart of a method for producing a semiconductor power entity according to a second embodiment with reference to an unstructured resin sheet;

[0102] Figure 4c shows a process flow chart of a method for producing a semiconductor power entity according to a third embodiment with reference to a structured prepreg or resin sheet;

[0103] Figure 4dshows a process flow diagram of a method for producing a semiconductor power entity according to a fourth embodiment with reference to preform placement;

[0104] Figure 5 A schematic diagram of a method 500 for producing a semiconductor power entity provided by the present invention is shown. DETAILED DESCRIPTION

[0105] In the following detailed description, reference is made to the accompanying drawings which form a part of this specification, wherein specific aspects of the present invention may be practiced by way of illustration. It will be appreciated that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not intended to be limiting, and the scope of the present invention is defined by the appended claims.

[0106] It should be understood that comments related to the described method are also applicable to the corresponding device or system for performing the method, and vice versa. For example, if a specific method step is described, the corresponding device may include a unit for performing the described method step, even if such a unit is not elaborated or illustrated in detail in the figure. In addition, it should be understood that the features of the various exemplary aspects described herein can be combined with each other unless otherwise explicitly stated.

[0107] In the present invention, diffusion welding is described. The principle of diffusion welding has been applied to microelectronics since the 1960s. The principle is also called SLID, transient liquid phase bonding (TLPB) or isothermal curing. Thereafter, the principle is applied to 3D integration / chip stacking and MEMS wafer-level packaging. Diffusion welding is an irreversible process, and the connection will not be remelted at the same temperature when the connection is formed, but at a higher temperature, because all low-temperature melting point welding will be converted into intermetallic compounds with a higher melting point temperature.

[0108] In the present invention, sintering is described. Sintering is another low-temperature metal joining technology that enables stable and reliable connections that cannot be remelted at relatively low bonding temperatures. Sintering is based on the high self-diffusion and surface diffusion properties of certain metals (the most well-known and applied at present are silver and copper), especially when the initial surface is very large. Typically, the paste is printed and dried on the surface of the precious metal. The paste contains silver particles of different sizes and has a special coating to prevent premature agglomeration and unnecessary sintering. Under temperature and pressure, the dried paste densifies into a porous metal layer, forming a metallurgical bond with a compatible contact metal surface. Another method to provide a large sinterable metal surface is to grow a metal wire or metal wire on the contact surface, whose diameter ranges from less than μm to more than nm and a length of tens of μm.

[0109] Figure 1a A schematic diagram of the production 10 of a semiconductor power product 13 without hybrid bonding provided by the present invention is shown; and Figure 1b A schematic diagram of the production 20 of a semiconductor power product 23 using hybrid bonding provided by the present invention is shown.

[0110] exist Figure 1a In the embodiment, two laminated layer embedded power die panels 11 are provided with a prepreg sheet 12 in between. After lamination, a semiconductor power product 13 with a stacked die half bridge is produced. No direct vertical connection between the stacked dies is possible.

[0111] The semiconductor power product 13 is characterized by an indirect electrical path 14 with high parasitic effects (R, L) and an interrupted thermal path.

[0112] exist Figure 1b In the embodiment, two laminated layer embedded power die panels 11 and a hybrid bonding material 22 in between are provided. After lamination, a semiconductor power product 23 with a stacked die half bridge is produced. The hybrid bonding method enables direct vertical connection 24 of high current.

[0113] and Figure 1a Compared with 13 semiconductor power products, Figure 1b The semiconductor power product 23 shown is characterized by a direct electrical path 24 , low parasitics (R, L) and a continuous thermal path.

[0114] The present invention provides a method for combining two or more laminate layers (with or without embedded die) (e.g. Figure 1b A method for vertically connecting two or more laminated embedded power die panels 11) relative to each other as shown in FIG. This method combines chip embedding and PCB lamination with low temperature metal connection technology. Low temperature metal connection technology can be based on diffusion welding (e.g., SLID solid-liquid interdiffusion, TLPB transient liquid phase bonding) or sintering (e.g., Ag sintering, Cu sintering, nanowire assisted sintering).

[0115] A basic idea of ​​the invention is that during a single process step, metal areas can be electrically and thermally connected using SLID bonding, diffusion bonding, sintering or nanowires, while other areas can be bonded, laminated or glued together with a non-conductive polymer material. The bonding process can be performed at relatively low temperatures. The metal and polymer bonding materials can be selected in such a way that bonding can be achieved at a temperature that is approximately the same as or lower than the curing of the polymer bonding material. The method is able to irreversibly connect two layers with embedded components vertically together, using a non-reflowable connection that has excellent electrical and thermal properties and high reliability.

[0116] The hybrid bonding method according to the present invention comprises the following steps: providing a redistribution layer (RDL) for the laminate; applying a bonding material to the bonding surface of the laminate or panel to be connected, for example, metallization for SLID, TLPS, polymer / glue; stacking step; lamination / bonding step; separation step. It is understood that additional PCB processes can be performed between these steps.

[0117] Several possible options for applying the material to the bonding surface, the structure of the bonding material, and the interaction of the bonding material with the bonding surface are described below.

[0118] The present invention provides a basic building block for panel-level power packaging, especially for large-scale packaging based on laminates. The basic building block can provide greater freedom in designing intra-package electrical and thermal connections with current capabilities in the vertical dimension. Depending on the design, the vertical connections can have different areas and shapes. The vertical connections can be used to effectively shorten critical conductor lengths or enhance thermal paths.

[0119] use Figure 1b The hybrid bonding shown has the following advantages: a) Simultaneous metal / metal and polymer / polymer bonding reduces process steps and eliminates the need for an underfill process; b) High reliability and non-melting, low parasitic electrical interconnects between laminate layers; c) 3D integration of power devices; vertically stacked packages with up to 2x higher power density; d) Panel-level packaging of vertically stacked devices; reduced tooling and tooling costs; e) Direct vertical connections inside the package with reduced package parasitics; note that traditional PCB processes cannot achieve this embedded connection between laminate layers; f) Thermal connection to heat sink using panel-level lamination processes.

[0120] Figure 2a A schematic cross section of a semiconductor power entity 100 provided by a first embodiment is shown.

[0121] The semiconductor power entity 100, also known as a semiconductor power product, includes: a first laminate layer 110, which has a first laminate upper main surface 111 and a first laminate lower main surface 112 opposite to the first laminate upper main surface 111; a second laminate layer 120, which has a second laminate upper main surface 121 and a second laminate lower main surface 122 opposite to the second laminate upper main surface 121.

[0122] The semiconductor power entity 100 includes an isolation layer 130 disposed between a first laminate layer 110 and a second laminate layer 120 .

[0123] The semiconductor power entity 100 comprises a first metal layer 113 disposed at a first laminated upper main surface 111 of a first laminated layer 110 , and a second metal layer 114 disposed at a first laminated lower main surface 112 of the first laminated layer 110 .

[0124] The semiconductor power entity 100 comprises a third metal layer 123 disposed at the second laminated upper main surface 121 of the second laminated layer 120 ; and a fourth metal layer 124 disposed at the second laminated lower main surface 122 of the second laminated layer 120 .

[0125] The semiconductor power entity 100 includes a connection metal layer 160 embedded in the isolation layer 130 between the first laminate layer 110 and the second laminate layer 120. The connection metal layer 160 forms an electrical connection with the second metal layer 114 and the third metal layer 123.

[0126] The first metal layer 113 , the second metal layer 114 , the third metal layer 123 , and the fourth metal layer 124 may be redistribution or routing metal layers for redistributing or routing current paths.

[0127] As mentioned above, a semiconductor power entity can also be called a semiconductor power product. This product can also be a module or a larger product (PCB), for example, the power components are embedded inside the PCB and the rest of the components are on top. As mentioned above, some passive devices can also be embedded inside the PCB.

[0128] The connection metal layer 160 can form non-reflow electrical and mechanical connections.

[0129] This "non-reflow" connection is different from a normal solder connection, such as that formed during a conventional TC / NCP process (thermocompression bonding with solder and a pre-applied non-conductive polymer). A non-reflow connection is one that does not reflow at the same temperature at which the connection was formed.

[0130] The connection metal layer 160 may form a diffusion welding connection or a sintering connection as described in the “Detailed Description” section above.

[0131] For example, the connection metal 160 may form a composite metal layer. Such a composite metal layer may include a compound of two or more metals, for example, an intermetallic layer, or a connection of metal layers composed of a single metal, or a connection of a metal and a polymer or a polymer mixture.

[0132] For such an intermetallic layer, the melting point of the intermetallic layer is higher than the lamination / processing temperature when the intermetallic layer is formed.

[0133] For example, the connecting metal layer may be composed of more than 80% metal and less than 20% pores or polymer.

[0134] The connecting metal layer is designed for high current loads.

[0135] In one embodiment, the intermetallic layer may have a minimum lateral dimension greater than 1 mm but not less than about 0.1 mm in each dimension.

[0136] The intermetallic layer can be a good conductor with a large cross-section and a short length, and is therefore suitable for high current loads.

[0137] In one embodiment, the typical thickness of the intermetallic layer is about 5 μm to 50 μm, but does not exceed about 0.2 mm (in the case of a single layer structure).

[0138] As mentioned above, the laminate layer may or may not be embedded in the power module.

[0139] The first laminate layer 110 may embed a first power semiconductor 140, such as Figure 2a As shown, and / or the second laminate layer 120 may embed a second power semiconductor 150, such as Figure 2a In one example, only one of the laminate layers 110 and 120 may embed a semiconductor element.

[0140] When defining the first power semiconductor and the second power semiconductor, this does not exclude that more than one first power semiconductor may be embedded in the first laminate layer 110 and more than one second power semiconductor may be embedded in the second laminate layer 120 .

[0141] The connection metal layer 160 may vertically connect the second metal layer 114 and the third metal layer 123 , and provide a vertical electrical connection between the first power semiconductor 140 and the second power semiconductor 150 .

[0142] The connection metal layer 160 can form a direct electrical connection path between the first power semiconductor 140 and the second power semiconductor 150 without detouring via a through hole arranged laterally to the two power semiconductors 140, 150, for example Figure 1b The direct connection path 24 in is shown as an example.

[0143] The second metal layer 114 and / or the third metal layer 123 may include at least one of copper, gold, silver, palladium or nickel or a combination thereof. In the case of a diffusion solder connection, the connection metal layer 160 may include any suitable low temperature melting metal, for example, metallic tin and indium and any one of the metals of the second metal layer 114 or the third metal layer 123 or an alloy thereof. In the case of a sintered connection, the connection metal layer 160 may include a porous layer of silver or copper or other suitable sintered metals with optional polymer fillers.

[0144] Note that such a connection metal layer may also include the following combination: (tin or indium or (tin and indium)) and any one of the metals of the second metal layer (114) or the third metal layer (123) or an alloy thereof.

[0145] The first power semiconductor 140 and the second power semiconductor 150 may be used to form a half-bridge configuration.

[0146] The first power semiconductor 140 may be a vertical device comprising at least one first terminal 141 , 143 (eg, Figure 2a ) and a second terminal 142 (eg, Figure 2a Drain 142 shown in FIG.

[0147] The second power semiconductor 150 may be a vertical device including at least one first terminal 151 , 153 (eg, Figure 2a ) and a second terminal 152 (eg, Figure 2a Drain 152 shown in FIG.

[0148] The semiconductor power entity 100 may include at least one first through-hole 115 and at least one second through-hole 116 extending through the first laminate layer 110. The at least one first through-hole 115 may form an electrical connection between at least one first terminal 141, 143 of the first power semiconductor 140 and the first metal layer 113. The at least one second through-hole 116 may form an electrical connection between the second terminal 142 of the first power semiconductor 140 and the second metal layer 114.

[0149] The semiconductor power entity 100 may include at least one third through-hole 125 and at least one fourth through-hole 126 extending through the second laminate layer 120. The at least one third through-hole 115 may form an electrical connection between at least one first terminal 151, 153 of the second power semiconductor 150 and the third metal layer 123. The at least one fourth through-hole 126 may form an electrical connection between the second terminal 152 of the second power semiconductor 150 and the fourth metal layer 124.

[0150] In an alternative embodiment, as described below with reference to Figure 2b to Figure 2e As described above, vias 115, 116 can be replaced by large area connections so that the front or back side of the die can be directly connected to metal layers 113, 123 without any distance. Figures 2b to 2e As shown, large area connections are usually made on one side of each chip. Through development and process improvements, large area connections can be made on both sides (but in this case, it is most likely to be one large area connection / via rather than multiple small vias).

[0151] Figure 2b A schematic cross section of a semiconductor power entity 100b according to a second embodiment is shown. In this second embodiment, a direct electrical and thermal path from the lower power semiconductor to the outer surface of the power entity can be achieved. This corresponds to a scenario where the high-side switch of the half-bridge configuration has a direct electrical and thermal path to the outer surface of the power entity.

[0152] The second embodiment is similar to the first embodiment, but the first power semiconductor 140 is directly connected to the second metal layer 114 without applying a via. Similarly, the second power semiconductor 150 is directly connected to the fourth metal layer 124 without applying a via therebetween.

[0153] Specifically, in the second embodiment, the first power semiconductor 140 has a first semiconductor upper main surface and a first semiconductor lower main surface opposite to the first semiconductor upper main surface. The second power semiconductor 150 has a second semiconductor upper main surface and a second semiconductor lower main surface opposite to the second semiconductor upper main surface.

[0154] The first semiconductor lower main surface is arranged coplanar with the first laminate lower main surface 112 to form an electrical connection between the second terminal 142 of the first power semiconductor 140 and the second metal layer 114 at the first laminate lower main surface 112. At least one first terminal 141, 143 (e.g., source and gate) of the first power semiconductor 140 is electrically connected to the first metal layer 113 at the first laminate upper main surface 111 through one or more micro-vias 115 extending through the first laminate layer 110.

[0155] Similarly, the second semiconductor lower main surface is arranged coplanar with the fourth laminate lower main surface 122 to form an electrical connection between the second terminal 152 (e.g., drain) of the second power semiconductor 150 and the fourth metal layer 124 at the second laminate lower main surface 122. At least one first terminal 151, 153 (e.g., source and gate) of the second power semiconductor 150 is electrically connected to the third metal layer 123 at the second laminate upper main surface 121 through one or more micro-vias 125 extending through the second laminate layer 120.

[0156] Figure 2c A schematic cross section of a semiconductor power entity 100 c provided by the third embodiment is shown.

[0157] This third embodiment is similar to the first embodiment, but the first power semiconductor 140 is placed directly below the first metal layer 113 and connected to the first metal layer without applying a via therebetween. Similarly, the second power semiconductor 150 is placed directly on the fourth metal layer 124 and connected to the fourth metal layer without applying a via therebetween. In this third embodiment, a direct electrical and thermal path to the outer surface of the power entity is achieved. The third embodiment facilitates heat extraction to an external heat sink because the main thermal path is free of microvias. The third embodiment also facilitates the lowest stray inductance for a half-bridge configuration, where MOSFET 1 (140) is the low-side switch and MOSFET 2 (150) is the high-side switch.

[0158] Specifically, in the third embodiment, the first power semiconductor 140 has a first semiconductor upper main surface and a first semiconductor lower main surface opposite to the first semiconductor upper main surface. The second power semiconductor 150 has a second semiconductor upper main surface and a second semiconductor lower main surface opposite to the second semiconductor upper main surface.

[0159] The first semiconductor upper main surface is arranged coplanar with the first laminate upper main surface 111 to form an electrical connection between at least one first terminal 141, 143 (e.g., source and gate) of the first power semiconductor 140 and the first metal layer 113 at the first laminate upper main surface 111. The second terminal 142 (e.g., drain) of the first power semiconductor 140 is electrically connected to the second metal layer 114 at the first laminate lower main surface 112 through one or more micro-vias 116 extending through the first laminate layer 110.

[0160] Similarly, the second semiconductor lower main surface is arranged coplanar with the fourth laminate lower main surface 122 to form an electrical connection between the second terminal 152 (e.g., drain) of the second power semiconductor 150 and the fourth metal layer 124 at the second laminate lower main surface 122. At least one first terminal 151, 153 (e.g., source and gate) of the second power semiconductor 150 is electrically connected to the third metal layer 123 at the second laminate upper main surface 121 through one or more micro-vias 125 extending through the second laminate layer 120.

[0161] Figure 2d A schematic cross section of a semiconductor power entity 100d provided by a fourth embodiment is shown. In this fourth embodiment, the shortest possible direct chip-to-chip connection can be achieved. This fourth embodiment facilitates the lowest chip-to-chip connection impedance.

[0162] The fourth embodiment is similar to the first embodiment, but the first power semiconductor 140 is placed directly on the second metal layer 114 without applying a via. Similarly, the second power semiconductor 150 is placed directly below the third metal layer 123 without applying a via.

[0163] Specifically, in the fourth embodiment, the first power semiconductor 140 has a first semiconductor upper main surface and a first semiconductor lower main surface opposite to the first semiconductor upper main surface. The second power semiconductor 150 has a second semiconductor upper main surface and a second semiconductor lower main surface opposite to the second semiconductor upper main surface.

[0164] The first semiconductor lower main surface is arranged coplanar with the first laminate lower main surface 112 to form an electrical connection between the second terminal 142 of the first power semiconductor 140 and the second metal layer 114 at the first laminate lower main surface 112. At least one first terminal 141, 143 (e.g., source and gate) of the first power semiconductor 140 is electrically connected to the first metal layer 113 at the first laminate upper main surface 111 through one or more micro-vias 115 extending through the first laminate layer 110.

[0165] Similarly, the second semiconductor upper main surface is arranged coplanar with the second laminate upper main surface 121 to form an electrical connection between at least one first terminal 151, 153 (e.g., source and gate) of the second power semiconductor 150 and the third metal layer 123 at the second laminate upper main surface 121. The second terminal 152 (e.g., drain) of the second power semiconductor 150 is electrically connected to the fourth metal layer 124 at the second laminate lower main surface 122 through one or more micro-vias 125 extending through the second laminate layer 120.

[0166] Figure 2eA schematic cross section of a semiconductor power entity 100e provided by a fifth embodiment is shown. In this fifth embodiment, a direct electrical and thermal path from the upper power semiconductor 140 to the outer surface of the power entity can be achieved. This fifth embodiment can be used to implement a low-side switch of a half-bridge configuration having a direct electrical and thermal path to the outer surface of the power entity.

[0167] The fifth embodiment is similar to the first embodiment, but the first power semiconductor 140 is placed directly under the first metal layer 113 without applying a via. Similarly, the second power semiconductor 150 is placed directly under the third metal layer 123 without applying a via.

[0168] Specifically, in the fifth embodiment, the first power semiconductor 140 has a first semiconductor upper main surface and a first semiconductor lower main surface opposite to the first semiconductor upper main surface. The second power semiconductor 150 has a second semiconductor upper main surface and a second semiconductor lower main surface opposite to the second semiconductor upper main surface.

[0169] The first semiconductor upper main surface is arranged coplanar with the first laminate upper main surface 111 to form an electrical connection between at least one first terminal 141, 143 (e.g., source and gate) of the first power semiconductor 140 and the first metal layer 113 at the first laminate upper main surface 111. The second terminal 142 (e.g., drain) of the first power semiconductor 140 is electrically connected to the second metal layer 114 at the first laminate lower main surface 112 through one or more micro-vias 116 extending through the first laminate layer 110.

[0170] Similarly, the second semiconductor upper main surface is arranged coplanar with the second laminate upper main surface 121 to form an electrical connection between at least one first terminal 151, 153 (e.g., source and gate) of the second power semiconductor 150 and the third metal layer 123 at the second laminate upper main surface 121. The second terminal 152 (e.g., drain) of the second power semiconductor 150 is electrically connected to the fourth metal layer 124 at the second laminate lower main surface 122 through one or more micro-vias 125 extending through the second laminate layer 120.

[0171] Figure 3 Different options for metal stacks for producing panel-level hybrid bonding provided by the present invention are shown. Figure 3 a shows a single layer single surface as a first option. Figure 3 b shows a single-layer double-sided as a second option. Figure 3 c shows multi-layer, single-sided or double-sided as a third option. Figure 3 d shows a preform as a fourth alternative. Although the picture is initially for slide bonding, it can also be applied to sintering and hybrid bonding according to the invention.

[0172] In all Figure 3 a to Figure 3 d, for example, Figure 2a to Figure 2e As shown in , the semiconductor power entity includes: a first laminate layer 110, which is also called a first substrate, having a first laminate upper main surface 111 and a first laminate lower main surface 112 opposite to the first laminate upper main surface 111; a second laminate layer 120, which has a second laminate upper main surface 121 and a second laminate lower main surface 122 opposite to the second laminate upper main surface 121, for example, as Figure 2a to Figure 2e as shown in .

[0173] The semiconductor power entity comprises an isolation layer 130, which is made of a polymer material, for example, and is arranged between a first laminate layer 110 and a second laminate layer 120, wherein the isolation layer 130 can be arranged between the laminate layers 110, 120 during lamination, or attached / applied to either one of the laminate layers 110, 120 facing the main surface but not both laminate layers before lamination.

[0174] The semiconductor power entity may include: a first metal layer 113 ( Figure 3 a to Figure 3 d), the third metal layer is arranged on the first laminated upper main surface 111 of the first laminated layer 110; the fourth metal layer 124 ( Figure 3 a to Figure 3 d), the fourth metal layer is arranged at the second laminated lower main surface 122 of the second laminated layer 120.

[0175] Figure 3 The semiconductor power entity of a comprises: a second metal layer 114, which is arranged at the first laminated lower main surface 112 of the first laminated layer 110; and a third metal layer 123, which is arranged at the second laminated upper main surface 121 of the second laminated layer 120. Figure 3 As shown in FIG. 1 a , these metal layers may be single metal layers 114 , 123 made of high melting point materials.

[0176] Figure 3 The semiconductor power entity of a includes a connection metal layer 160 embedded in the isolation layer 130 between the first lamination layer 110 and the second lamination layer 120, and the connection metal layer 160 forms an electrical connection with the second metal layer 114 and the third metal layer 123 after lamination. The connection metal layer 160 can be a single layer made of a bonding metal attached to the second metal layer 114 of a high melting point material, such as Figure 3 As shown in a.

[0177] Figure 3 The semiconductor power entity of b is similar to Figure 3a, however, the connecting metal layer 160 is made of two portions 160a and 160b of bonding metal, which are attached to the respective second metal layer 114 and third metal layer 123 made of high melting point materials.

[0178] Figure 3 The semiconductor power entity of c is similar to Figure 3 a, however, the second metal layer 114, the third metal layer 123 and the connecting metal layer 160 are implemented as: a first multilayer, which is formed by the corresponding parts 114a, 114b of the second metal layer arranged alternately with the corresponding parts 160a, 160b of the connecting metal layer; and a second multilayer, which is formed by the corresponding parts 123a, 123b of the third metal layer arranged alternately with the corresponding parts 160c, 160d of the connecting metal layer.

[0179] Figure 3 d's semiconductor power entity is similar to Figure 3 a, however, the connection metal layer 160 is made of a preform of a bonding metal applied between the second metal layer 114 and the third metal layer 123 made of a high melting point material.

[0180] exist Figure 3 a to Figure 3 In the semiconductor power entity shown in Figure d, different metal stack options for panel-level hybrid bonding are shown. The bonding metal can also be applied as a paste for sintering or diffusion soldering. The polymer material can be printed, dispensed or pre-laminated or any other suitable form of sheet material.

[0181] Figure 3 a to Figure 3 The embodiment shown in d can be realized by different bonding material combinations, metal stack selections and process selections shown in Table 1. The most important combinations are specifically described as embodiments, namely Figure 3 a. Figure 3 b. Figure 3 c and Figure 3 The embodiment shown in d, wherein the low melting point material is represented as bonding metal.

[0182]

[0183] Table 1: Examples of possible metal systems for low temperature joining. Columns: high temperature molten metals; Rows: low temperature molten metals and sintered materials. The cell content indicates the type of non-remelting metal joint that can be formed from this combination: "Diff.sold." = diffusion soldered (SLID, TLPB) or "Sinter" = sintered.

[0184] Table 1 is not exhaustive. This table lists the most practical and best available metal combinations. It is understood that this table 1 is only an example and does not limit the present invention to these combinations. All other suitable low temperature diffusion solder metal combinations and all other low temperature sintering metals and particle shapes can also be applied.

[0185] Among others, the following metal and bonding layer options are possible (see Table 1):

[0186] 1) The high-temperature molten metal can be a one-layer structure (e.g., Cu, Ni) or a multi-layer structure (e.g., Cu+Au, Cu+Ni, Ni+Au, Cu+Ni+Au).

[0187] 2) The low temperature molten metal can be Sn, In or some other suitable metal, metal alloy or combination of several metals, for example, SnAg,

[0188] InSn.

[0189] 3) The bonding layer can be a liquid or film type polymer material, for example, epoxy resin, epoxy resin mixture, BT epoxy, PI or other types of polymers compatible with the laminating material.

[0190] 4) The bonding material can be uncured, pre-cured or semi-cured.

[0191] Figure 3 a to Figure 3 d shows the following metal stack selections:

[0192] a) Low melting point and high melting point metals on laminate can be a simple single layer structure or printed paste (high melting point metal + low temperature metal / metal alloy stack) on only one laminate layer, see Figure 3 a.

[0193] b) Low and high melting point metals on laminate can be a simple single layer structure or printed paste (high melting point metal + low temperature metal / metal alloy stack) on two laminate layers, see Figure 3 b.

[0194] c) Low melting point and high melting point metals on laminates can be multi-layer sandwich or other types of structures on one or two laminate layers (high +

[0195] low+high+low…), see Figure 3 c.

[0196] d) The low temperature molten metal or metal alloy or metal paste may be in a separate preform placed between the laminate sheets, see Figure 3 d.

[0197] The following process / step selections can be applied:

[0198] 1) Low temperature metal or metal alloy or metal paste layer and / or polymer bonding layer is located on one or both sides of the laminate.

[0199] 2) A low temperature metal or metal alloy or metal compound layer is placed on one or both sides of the laminate and a polymer bonding layer is placed in between in a separate step.

[0200] 3) A polymer bonding layer is placed on one or both sides of the laminate and a low temperature metal or metal alloy or metal paste preform is placed in between in a separate step.

[0201] 4) During the lay-up process, the polymer bonding layer and the low temperature metal or metal alloy or metal paste preform are placed between the laminate sheets.

[0202] Combine the following Figure 4a , Figure 4b , Figure 4c and Figure 4d Describe different process flow options. In addition to the process flow described, modified combinations from the described options can also be used.

[0203] Figure 4a A process flow chart of a method for producing a semiconductor power entity according to a first embodiment with reference to resin printing is shown.

[0204] This process option 1 - resin printing - describes a process in which a polymer bonding material is printed, coated, laminated, dispensed, etc. on one (or two) laminate layers, and a bonding metal is plated, printed, dispensed, etc. on one (or two) laminate layers prior to bonding.

[0205] In a first step, two pre-fabricated laminate layers, also referred to as core layers or laminate core layers, are provided 401, which are printed with a polymer bonding material. The two pre-fabricated laminate layers may correspond to the above reference Figure 2a to Figure 2e A first laminate layer 110 and a second laminate layer 120 are depicted.

[0206] In a second step, the first pre-fabricated laminate layer 110 is coated 402a with a polymer bonding material and the second pre-fabricated laminate layer 120 is coated 402b with a low melting point metal or metal alloy or paste.

[0207] In a third step, the second pre-manufactured laminate layer 120 is turned over and positioned over the first pre-manufactured laminate layer 110 to provide a layup 403 .

[0208] In a fourth step, the lay-up 403 is laminated 404 to provide a semiconductor power product.

[0209] In a fifth step, one or more holes are drilled 405 in the semiconductor power product.

[0210] In a sixth step, one or more holes are plated 406 with a conductive metal layer.

[0211] In a seventh step, a semiconductor power product is constructed 407 , for example, by constructing first metal layer 113 and fourth metal layer 124 .

[0212] If the holes 170 are not used at this stage, the metal layer can also be structured at an earlier stage and this seventh step is not needed. This also applies to all other process options 2 to 4 described below.

[0213] The fifth, sixth and seventh steps described above are optional depending on the design and application, and may also be applied to all other process options 2 to 4 described below.

[0214] Figure 4b A process flow chart of a method for producing a semiconductor power entity according to a second embodiment with reference to an unstructured resin sheet is shown.

[0215] This process option 2 – unstructured resin sheet – describes a process where the bonding metal is plated, printed, or dispensed onto one (or both) laminate layers prior to bonding, and an unstructured polymer material is placed between the laminate layers during layup and lamination.

[0216] In a first step, two prefabricated laminate layers 411 are provided, which may correspond to the laminate layers 411 described above with reference to Figure 2a to Figure 2e A first laminate layer 110 and a second laminate layer 120 are depicted.

[0217] In a second step, a prefabricated laminate layer is printed or plated 412 with a low melting point metal or metal alloy.

[0218] In a third step, a layup 413 of a first pre-manufactured laminate layer and a second pre-manufactured laminate layer with a polymer layer located therebetween is provided.

[0219] In a fourth step, the lay-up 403 is laminated 414 to provide a semiconductor power product.

[0220] In a fifth step, one or more holes are drilled 415 in the semiconductor power product.

[0221] In a sixth step, the one or more holes are plated 416 with a conductive metal layer.

[0222] In a seventh step, a semiconductor power product is constructed 417 , for example, by constructing first metal layer 113 and fourth metal layer 124 .

[0223] If the hole 170 is not used at this stage, the metal layer can also be constructed at an earlier stage and this seventh step is not needed. The fifth step, the sixth step and the seventh step described above are optional depending on the design and application.

[0224] Figure 4c A process flow diagram of a method for producing a semiconductor power entity according to a third embodiment with reference to a structured prepreg or resin sheet is shown.

[0225] This process option 3 – structured prepreg or resin sheet – describes a process where the bonding metal is plated, printed, or dispensed onto one (or both) laminate layers prior to bonding, and a structured polymer material is placed between the laminate layers during layup and lamination.

[0226] In a first step, two prefabricated laminate layers 421 are provided, which may correspond to the laminate layers 421 described above with reference to Figure 2a to Figure 2e A first laminate layer 110 and a second laminate layer 120 are depicted.

[0227] In a second step, an activator material is printed, sprayed, etc. 422a on a first pre-fabricated laminate layer, and a pre-fabricated second laminate layer is printed or plated 422b with a low melting point metal or metal alloy.

[0228] In a third step 423 , a layup 423 of a first pre-manufactured laminate layer and a second pre-manufactured laminate layer and a structured polymer layer located therebetween is provided.

[0229] In a fourth step, the lay-up 423 is laminated 424 to provide a semiconductor power product.

[0230] In a fifth step, one or more holes are drilled 425 in the semiconductor power product.

[0231] In a sixth step, the one or more holes are plated 426 with a conductive metal layer.

[0232] In a seventh step, a semiconductor power product is constructed 427 , for example, by constructing first metal layer 113 and fourth metal layer 124 .

[0233] If the hole 170 is not used at this stage, the metal layer can also be constructed at an earlier stage and this seventh step is not needed. The fifth step, the sixth step and the seventh step described above are optional depending on the design and application.

[0234] Figure 4d A process flow diagram of a method for producing a semiconductor power entity according to a fourth embodiment with reference to preform placement is shown.

[0235] This process option 4—preform placement—describes a process in which a polymer bonding material is printed, coated, laminated, dispensed, etc., on one (or both) laminate layers and a bonding metal preform is placed on copper pads on the lower laminate layer prior to bonding (e.g., a pick and place process).

[0236] In a first step, two prefabricated laminate layers 431 are provided, which may correspond to the laminate layers 431 described above with reference to Figure 2a to Figure 2e A first laminate layer 110 and a second laminate layer 120 are depicted.

[0237] In a second step, one of the two pre-manufactured laminate layers 431 is printed with resin and the resin is dried 432 .

[0238] In a third step, the low melting point metal preform is placed on the resin printed pre-manufactured laminate layer and together with another pre-manufactured laminate layer provides a layup 433 .

[0239] In a fourth step, the lay-up 423 is laminated 434 to provide a semiconductor power product.

[0240] In a fifth step, one or more holes are drilled 435 in the semiconductor power product.

[0241] In a sixth step, the one or more holes are plated 436 with a conductive metal layer.

[0242] In a seventh step, a semiconductor power product is constructed 437 , for example, by constructing first metal layer 113 and fourth metal layer 124 .

[0243] If the hole 170 is not used at this stage, the metal layer can also be constructed at an earlier stage and this seventh step is not needed. The fifth step, the sixth step and the seventh step described above are optional depending on the design and application.

[0244] Figure 5 A schematic diagram of a method 500 for producing a semiconductor power entity provided by the present invention is shown.

[0245] The semiconductor power entity may be the semiconductor power entity 100, 100b, 100c, 100d, 100e, as described above with reference to Figure 2a to Figure 2e described.

[0246] The method 500 includes providing 501 a first laminate layer 110 embedding a first power semiconductor 140, the first laminate layer 110 having a first laminate upper main surface 111 and a first laminate lower main surface 112 opposite to the first laminate upper main surface 111, wherein a first metal layer 113 is arranged at the first laminate upper main surface 111 of the first laminate layer 110, and a second metal layer 114 is arranged at the first laminate lower main surface 112 of the first laminate layer 110, for example, as described above with reference to Figure 2a to Figure 2e described.

[0247] The method 500 includes providing 502 a second laminate layer 120 embedding a second power semiconductor 150, the second laminate layer 120 having a second laminate upper main surface 121 and a second laminate lower main surface 122 opposite to the second laminate upper main surface 121, wherein a third metal layer 123 is disposed at the second laminate upper main surface 121 of the second laminate layer 120, and a fourth metal layer 124 is disposed at the second laminate lower main surface 122 of the second laminate layer 120, for example, as described above with reference to Figure 2a to Figure 2e described.

[0248] The method 500 includes applying 503 a bonding metal at the second metal layer 114 of the first laminate layer 110 and / or the third metal layer 123 of the second laminate layer 120, placing the bonding metal between the first power semiconductor 140 and the second power semiconductor 150 and / or between corresponding electrical contact pairs in the first laminate layer and the second laminate layer, for example, as described above with reference to Figure 2a to Figure 2e described.

[0249] The method 500 includes providing 504 an isolation layer 130 between the second metal layer 114 of the first laminate layer 110 and the third metal layer 123 of the second laminate layer 120, for example, as described above with reference to Figure 2a to Figure 2e described.

[0250] The method 500 includes laying up and laminating 505 the first lamination layer 110, the second lamination layer 120 and the isolation layer 130 to the semiconductor power entity 100, wherein the lamination converts the bonding metal into the connecting metal layer 160 to form an electrical connection with the second metal layer 114 and the third metal layer 123, for example, as described above with reference to Figure 2a to Figure 2e or reference Figures 4a to 4d described.

[0251] The connection metal layer 160 may be formed simultaneously with the lamination layers of the first lamination layer 110 , the second lamination layer 120 , and the isolation layer 130 .

[0252] The method 500 may further include: applying 503 a bonding metal at the second metal layer 114 of the first laminate layer 110 before stacking and laminating 505; applying an isolation layer 130 at the third metal layer 123 of the second laminate layer 120 before stacking and laminating 505, wherein the isolation layer 130 is configured to form an opening for embedding the bonding metal, for example, Figure 4a shown.

[0253] Applying 503 the bonding metal may include electroplating, printing or dispensing; applying the isolation layer 130 may include printing, coating, laminating or dispensing, for example, Figure 4a shown.

[0254] The method 500 may further include: applying an isolation layer 130 at the third metal layer 123 of the second lamination layer 120 before stacking and laminating 505, wherein the isolation layer 130 is configured to form an opening for embedding a bonding metal; placing the bonding metal in the opening of the isolation layer 130 on the third metal layer 123, for example, Figure 4d shown.

[0255] The method 500 may further include placing a spacer layer 130 between the second metal layer 114 of the first laminate layer 110 and the third metal layer 123 of the second laminate layer 120 during the lay-up and lamination 505, wherein the spacer layer 130 is unstructured, for example, Figure 4b shown.

[0256] The method 500 may further include placing an isolation layer 130 between the second metal layer 114 of the first laminate layer 110 and the third metal layer 123 of the second laminate layer 120 during the lay-up and lamination process, wherein the isolation layer 130 is configured to form an opening for embedding the bonding metal, for example, Figure 4c shown.

[0257] The following process steps of method 500 are optional: drilling holes extending from the first metal layer 113 to the fourth metal layer 124 in the semiconductor power entity 100, wherein the holes are drilled laterally into the first power semiconductor 140 and the second power semiconductor 150; performing metal electroplating on the holes to form metal-plated through-holes electrically connecting the first metal layer 113 with the fourth metal layer 124; and constructing the first metal layer 113 and the fourth metal layer 124.

[0258] Although specific features or aspects of the present invention may have been disclosed in conjunction with only one of several implementations, such features or aspects may be combined with one or more other features or aspects in other implementations, as long as it is necessary or advantageous for any given or specific application. In addition, to a certain extent, the terms "including", "having", "having" or other variations of these words are used in the detailed description or claims, and such terms are similar to the term "including" and are both intended to include. Similarly, the terms "exemplary" and "for example" are only represented as examples, not the best or optimal. The terms "coupled" and "connected" and derivatives may be used. It should be understood that these terms can be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical contact or electrical contact, or they are not in direct contact with each other.

[0259] Although specific aspects have been illustrated and described herein, it will be appreciated by those skilled in the art that various alternative and / or equivalent implementations may be made to the specific aspects shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific aspects discussed herein.

[0260] Although elements in the following claims are listed in a specific order with corresponding labels, these elements are not necessarily limited to being implemented in this specific order unless the claim recitation otherwise implies a specific order for implementing some or all of these elements.

[0261] Based on the above guidance, many substitutions, modifications and variations are obvious to those skilled in the art. Of course, it is readily apparent to those skilled in the art that the present invention has many applications in addition to those described herein. Although the present invention has been described with reference to one or more specific embodiments, it will be appreciated by those skilled in the art that many changes may be made to the present invention without departing from the scope of the present invention. Therefore, it should be understood that the present invention may be implemented in a manner other than that specifically described herein, as long as it is within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor power entity (100), characterized in that: The semiconductor power entity comprises: A first laminate layer (110), the first laminate layer having a first laminate upper major surface (111) and a first laminate lower major surface (112) opposite to the first laminate upper major surface (111); A second laminate layer (120), the second laminate layer having a second laminate upper major surface (121) and a second laminate lower major surface (122) opposite to the second laminate upper major surface (121); an isolation layer (130), the isolation layer being disposed between the first laminate layer (110) and the second laminate layer (120); a first metal layer (113), the first metal layer being arranged on the first laminated upper main surface (111) of the first laminated layer (110); a second metal layer (114), the second metal layer being disposed at the first laminated lower main surface (112) of the first laminated layer (110); a third metal layer (123), the third metal layer being arranged at the second laminated upper main surface (121) of the second laminated layer (120); a fourth metal layer (124), the fourth metal layer being arranged at the second laminated lower main surface (122) of the second laminated layer (120); A connecting metal layer (160) is embedded in the isolation layer (130) between the first laminate layer (110) and the second laminate layer (120), wherein the connecting metal layer (160) forms an electrical connection with the second metal layer (114) and the third metal layer (123).

2. The semiconductor power entity (100) according to claim 1, characterized in that The connecting metal layer (160) forms a non-reflowable electrical and mechanical connection.

3. The semiconductor power entity (100) according to claim 1 or 2, characterized in that: The connection metal layer (160) forms a connection of a diffusion welding connection or a sintering connection.

4. The semiconductor power entity (100) according to any one of the preceding claims, characterized in that The first laminate layer (110) embeds a first power semiconductor (140); and / or The second laminate layer (120) embeds a second power semiconductor (150).

5. The semiconductor power entity (100) according to claim 4, characterized in that The connecting metal layer (160) vertically connects the second metal layer (114) and the third metal layer (123), providing a vertical electrical connection for the first power semiconductor (140) and the second power semiconductor (150).

6. The semiconductor power entity (100) according to claim 4 or 5, characterized in that The connection metal layer (160) forms a direct electrical connection path between the first power semiconductor (140) and the second power semiconductor (150) without detouring via a through hole laterally arranged to the two power semiconductors (140, 150).

7. The semiconductor power entity (100) according to any one of the preceding claims, characterized in that The second metal layer (114) and / or the third metal layer (123) include at least one of copper, gold, silver, palladium or nickel, or a combination thereof; In the case of diffusion welding connection, the connection metal layer (160) includes any one of the metals tin and indium and any one of the metals of the second metal layer (114) or the third metal layer (123) or an alloy thereof; In the case of a sintered connection, the connection metal layer (160) comprises a porous layer of silver or copper with an optional polymer filler.

8. The semiconductor power entity (100) according to any one of claims 4 to 6, characterized in that The first power semiconductor (140) and the second power semiconductor (150) are used to form a half-bridge configuration.

9. The semiconductor power entity (100) according to any one of claims 4 to 6 or 8, characterized in that The first power semiconductor (140) is a vertical device, comprising at least one first terminal (141, 143) opposite to the first laminated upper main surface (111) and a second terminal (142) opposite to the first laminated lower main surface (112); The second power semiconductor (150) is a vertical device comprising at least one first terminal (151, 153) opposite to the second laminate upper main surface (121) and a second terminal (152) opposite to the second laminate lower main surface (122).

10. The semiconductor power entity (100) according to claim 9, characterized in that The semiconductor power entity comprises: at least one first through hole (115) and at least one second through hole (116), the at least one first through hole and the at least one second through hole extending through the first laminate layer (110), wherein the at least one first through hole (115) forms an electrical connection between the at least one first terminal (141, 143) of the first power semiconductor (140) and the first metal layer (113), and the at least one second through hole (116) forms an electrical connection between the second terminal (142) of the first power semiconductor (140) and the second metal layer (114); At least one third through hole (125) and at least one fourth through hole (126), the at least one third through hole and the at least one fourth through hole extending through the second laminate layer (120), wherein the at least one third through hole (115) forms an electrical connection between the at least one first terminal (151, 153) of the second power semiconductor (150) and the third metal layer (123), and the at least one fourth through hole (126) forms an electrical connection between the second terminal (152) of the second power semiconductor (150) and the fourth metal layer (124).

11. The semiconductor power entity (100) according to claim 9, characterized in that The first power semiconductor (140) has a first semiconductor upper main surface and a first semiconductor lower main surface opposite to the first semiconductor upper main surface; The first semiconductor upper main surface is arranged coplanarly with the first laminate upper main surface (111) to form an electrical connection between the at least one first terminal (141, 143) of the first power semiconductor (140) and the first metal layer (113) at the first laminate upper main surface (111); The second terminal (142) of the first power semiconductor (140) is electrically connected to the second metal layer (114) at the first laminate lower main surface (111) through one or more micro-vias extending through the first laminate layer (110); or The first semiconductor lower main surface is arranged coplanarly with the first laminate lower main surface (112) to form an electrical connection between the second terminal (142) of the first power semiconductor (140) and the second metal layer (114) at the first laminate lower main surface (112); The at least one first terminal (141, 143) of the first power semiconductor (140) is electrically connected to the first metal layer (113) at the first laminate upper main surface (111) via one or more micro vias extending through the first laminate layer (110).

12. The semiconductor power entity (100) according to claim 9 or 11, characterized in that The second power semiconductor (150) comprises a second semiconductor upper main surface and a second semiconductor lower main surface opposite to the second semiconductor upper main surface; The second semiconductor upper main surface is arranged coplanarly with the second laminate upper main surface (121) to form an electrical connection between the at least one first terminal (151, 153) of the second power semiconductor (150) and the third metal layer (123) at the second laminate upper main surface (121); The second terminal (152) of the second power semiconductor (150) is electrically connected to the fourth metal layer (124) at the second laminate lower main surface (122) via one or more micro vias extending through the second laminate layer (120); or The second semiconductor lower main surface is arranged coplanarly with the second laminate lower main surface (122) to form an electrical connection between the second terminal (152) of the second power semiconductor (150) and the fourth metal layer (124) at the second laminate lower main surface (122); The at least one first terminal (151, 153) of the second power semiconductor (150) is electrically connected to the third metal layer (123) at the second laminate upper main surface (121) via one or more micro vias extending through the second laminate layer (120).

13. A method for producing a semiconductor power entity (100), characterized in that The method comprises: Providing a first laminate layer (110) embedded with a first power semiconductor (140), the first laminate layer (110) having a first laminate upper main surface (111) and a first laminate lower main surface (112) opposite to the first laminate upper main surface (111); wherein the first metal layer (113) is arranged at the first laminated upper main surface (111) of the first laminated layer (110), and the second metal layer (114) is arranged at the first laminated lower main surface (112) of the first laminated layer (110); Providing a second laminate layer (120) embedded with a second power semiconductor (150), the second laminate layer (120) having a second laminate upper main surface (121) and a second laminate lower main surface (122) opposite to the second laminate upper main surface (121); wherein the third metal layer (123) is arranged at the second laminated upper main surface (121) of the second laminated layer (120), and the fourth metal layer (124) is arranged at the second laminated lower main surface (122) of the second laminated layer (120); A bonding metal is applied at the second metal layer (114) of the first laminate layer (110) and / or at the third metal layer (123) of the second laminate layer (120), wherein the bonding metal is placed between the first power semiconductor (140) and the second power semiconductor (150) and / or between corresponding electrical contact pairs in the first laminate layer and the second laminate layer, An isolation layer (130) is provided between the second metal layer (114) of the first laminate layer (110) and the third metal layer (123) of the second laminate layer (120); Laying up and laminating the first lamination layer (110), the second lamination layer (120) and the isolation layer (130) to a semiconductor power entity (100), The lamination transforms the bonding metal into a connecting metal layer (160), and the connecting metal layer forms an electrical connection with the second metal layer (114) and the third metal layer (123).

14. The method according to claim 13, characterized in that The connection metal layer (160) is formed simultaneously with the lamination of the first lamination layer (110), the second lamination layer (120) and the isolation layer (130).

15. The method according to claim 13 or 14, characterized in that The method comprises: Prior to said laying up and laminating, applying said bonding metal at said second metal layer (114) of said first lamination layer (110); before said laying up and laminating, applying said isolation layer (130) at said third metal layer (123) of said second lamination layer (120), The isolation layer (130) is configured to form an opening for embedding the bonding metal.

16. The method according to claim 15, characterized in that Applying the bonding metal includes electroplating, printing or dispensing; Applying the isolation layer (130) includes printing, coating, laminating or dispensing.

17. The method according to claim 13 or 15, characterized in that The method comprises: before said laying up and laminating, applying said isolation layer (130) at said third metal layer (123) of said second lamination layer (120), wherein the isolation layer (130) is configured to form an opening for embedding the bonding metal; The bonding metal is placed in the opening of the isolation layer (130) on the third metal layer (123).

18. The method according to claim 13 or 14, characterized in that The method comprises: During the lay-up and lamination process, the isolation layer (130) is placed between the second metal layer (114) of the first laminate layer (110) and the third metal layer (123) of the second laminate layer (120), Wherein, the isolation layer (130) is unstructured.

19. The method according to claim 13 or 14, characterized in that The method comprises: During the lay-up and lamination process, the isolation layer (130) is placed between the second metal layer (114) of the first laminate layer (110) and the third metal layer (123) of the second laminate layer (120), The isolation layer (130) is configured to form an opening for embedding the bonding metal.

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