Test circuit and test method for semiconductor device

Abstract

The present application provides a test circuit and test method for semiconductor devices, the circuit comprising: a switch module, which is used to be electrically connected to the semiconductor device to be tested, including a first part switch device, a second part switch device and a third part switch device; wherein, by controlling the closing and opening of each switch device, multiple test loops are formed to perform various performance tests on the semiconductor device to be tested, and the various performance tests include aging test, threshold voltage test, breakdown voltage and drain leakage current test, on-resistance test and gate leakage test, and the test loops and performance tests correspond one to one. The circuit completes the rapid transition from the electrothermal aging test of SiC devices to the performance characterization parameter test by switching the switch matrix, which can avoid repeated plugging and unplugging of devices, improve test efficiency, and realize accurate testing of the degradation law of the performance characterization parameters of SiC devices during the electrothermal aging process.

Description

Technical Field

[0001] The present application relates to the field of SiC device testing, and in particular, to a test circuit for a semiconductor device and a method for testing a silicon carbide device using the test circuit for any semiconductor device. Background Art

[0002] Silicon carbide (SiC) devices are transistors made from SiC semiconductor materials. Compared with traditional silicon (Si) devices, SiC devices have the advantages of high voltage resistance, high temperature resistance, fast switching speed and low on-resistance, and can be widely used in railway traction converters, photovoltaic inverters, wind power generation equipment and electric vehicle drive systems. In practical applications, SiC devices will be subjected to the dual stress of electricity and heat caused by complex working conditions such as surge, radiation or electrostatic damage. The reliability of the device will gradually decrease over time, and the macroscopic manifestation is the degradation of the parameters characterizing the device performance, such as increased on-resistance, reduced breakdown voltage, increased leakage and threshold voltage drift.

[0003] At present, the traditional high-temperature reverse bias test first accelerates the aging of SiC devices under different voltage bias and temperature stress conditions. After a period of testing, the device is removed from the test fixture and the various performance characterization parameters of the device are retested offline. In order to accurately grasp the performance degradation law of the device during the electrothermal aging process, multiple retests are required. Repeated plugging and unplugging may cause mechanical damage to the device, which to a certain extent complicates the test steps and reduces the test efficiency. At the same time, for SiC devices, the changes in various performance parameters are closely related to the migration of mobile ions and carrier trapping and detrapping. After the electrothermal stress ends, the parameters that have changed will recover at an exponential rate, and the test time interval has a great influence on the test results. Therefore, the traditional offline test method cannot quickly and accurately test the various performance parameters of SiC devices during the aging process. Summary of the invention

[0004] The main purpose of the present application is to provide a test circuit for a semiconductor device and a method for testing a silicon carbide device using a test circuit for any semiconductor device, so as to at least solve the problem that the traditional device testing method requires repeated plugging and unplugging of the device for multiple retests, which to a certain extent complicates the test steps, reduces the test efficiency, causes certain mechanical damage to the device, and cannot quickly and accurately test the various performance parameters of the SiC device during the aging process.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a test circuit for a semiconductor device is provided, comprising: a switch module, which is used to be electrically connected to a semiconductor device to be tested, comprising a first part of switch devices, a second part of switch devices and a third part of switch devices, the semiconductor device to be tested having a first end, a second end and a control end, the first part of switch devices is electrically connected to at least one end of the semiconductor device to be tested, the second part of switch devices is electrically connected to at least one end of the semiconductor device to be tested, and the third part of switch devices is electrically connected to at least one end of the semiconductor device to be tested; wherein, by controlling the closing and opening of each of the switch devices, a plurality of test loops are formed to perform a variety of performance tests on the semiconductor device to be tested, the various performance tests include aging test, threshold voltage test, breakdown voltage and drain leakage current test, on-resistance test and gate leakage test, and the test loops correspond to the performance tests one by one.

[0006] Optionally, the test circuit also includes: a power supply unit electrically connected to each of the switching devices, the power supply unit being used to provide a test voltage to the semiconductor device to be tested; and a current detection unit electrically connected to each of the switching devices and the power supply unit, respectively, the current detection unit being used to detect a test current.

[0007] Optionally, the first part of the switching devices includes: a first switching device, a first end of the first switching device is electrically connected to the first end of the semiconductor device to be tested; a second switching device, a common end of the second switching device is electrically connected to the second end of the first switching device, a first terminal of the second switching device is used to receive a first voltage signal, and a second terminal of the second switching device is grounded; a third switching device, a first end of the third switching device is electrically connected to the control end of the semiconductor device to be tested, and a second end of the third switching device is used to receive a second voltage signal.

[0008] Optionally, the second part of the switching devices also includes: a fourth switching device, the common end of the fourth switching device is electrically connected to the control end of the semiconductor device under test, the first terminal of the fourth switching device is used to receive a third voltage signal, and the second terminal of the fourth switching device is grounded.

[0009] Optionally, the third part of the switching devices also includes: a fifth switching device, a first end of the fifth switching device is electrically connected to the control end of the semiconductor device to be tested, and a second end of the fifth switching device is electrically connected to the first end of the semiconductor device to be tested; a sixth switching device, a first end of the sixth switching device is electrically connected to the first end of the semiconductor device to be tested, a second end of the sixth switching device is electrically connected to the common end of the second switching device, a third end of the sixth switching device is electrically connected to the second end of the semiconductor device to be tested, and a fourth end of the sixth switching device is electrically connected to the first connection terminal of the second switching device.

[0010] Optionally, the power supply unit includes: a first voltage source, a positive terminal of the first voltage source is electrically connected to the second terminal of the third switching device in the test circuit, and a negative terminal of the first voltage source is grounded; a second voltage source, a negative terminal of the second voltage source is electrically connected to the first terminal of the fourth switching device in the test circuit, and a positive terminal of the second voltage source is grounded; a third voltage source, a positive terminal of the third voltage source is electrically connected to the first terminal of the second switching device in the test circuit, and a negative terminal of the third voltage source is electrically connected to the fourth terminal of the sixth switching device in the test circuit.

[0011] Optionally, the first voltage source, the second voltage source and the third voltage source are all DC voltage sources.

[0012] Optionally, the current detection unit includes: a first ammeter, a first end of the first ammeter is electrically connected to the negative end of the first voltage source in the power supply unit, and a second end of the first ammeter is grounded; a second ammeter, a first end of the second ammeter is electrically connected to the negative end of the third voltage source in the power supply unit, and a second end of the second ammeter is grounded.

[0013] According to another aspect of the present application, a method for testing a silicon carbide device using any one of the semiconductor device test circuits is provided, comprising: controlling the closing and opening of each switching device in the test circuit to perform a variety of performance tests on the semiconductor device to be tested.

[0014] Optionally, the closing and opening of each switching device in the test circuit is controlled to perform multiple performance tests on the semiconductor device to be tested, including: controlling the closing and opening of each switching device in the test circuit to switch the test circuit to an aging test circuit to perform an aging test on the semiconductor device to be tested; after completing the aging test on the semiconductor device to be tested, controlling the closing and opening of each switching device in the test circuit to test the performance parameters of the semiconductor device to be tested to determine the reliability degradation of the semiconductor device to be tested, the performance parameters including: the threshold voltage of the semiconductor device to be tested, the breakdown voltage of the semiconductor device to be tested, the drain leakage current of the semiconductor device to be tested, the on-resistance of the semiconductor device to be tested, and the gate leakage current of the semiconductor device to be tested.

[0015] Optionally, the test circuit of the semiconductor device includes a first switch device, a fourth switch device, a second switch device and a power supply unit, the fourth switch device and the second switch device are both single-pole double-throw switches, and the power supply unit includes a second voltage source and a third voltage source, which control the closing and opening of each of the switch devices in the test circuit, and switch the test circuit to an aging test circuit to perform an aging test on the semiconductor device to be tested, including: closing the first switch device, connecting the common end of the second switch device with the first terminal, connecting the common end of the fourth switch device with the second terminal, and adjusting the third voltage source to output any value between 0 and the rated operating voltage of the semiconductor device to be tested, so as to perform a high-temperature reverse bias test on the semiconductor device to be tested under zero gate voltage conditions; disconnecting the common end of the fourth switch device with the second terminal, connecting the common end of the fourth switch device with the first terminal, and adjusting the second voltage source to output any value between the minimum gate voltage of the semiconductor device to be tested and 0, so as to perform a high-temperature reverse bias test on the semiconductor device to be tested under negative gate voltage conditions.

[0016] Optionally, the test circuit of the semiconductor device includes a first switch device, a fifth switch device, a second switch device, a sixth switch device, a power supply unit and a current detection unit, the second switch device is a single-pole double-throw switch, the power supply unit includes a third voltage source, and the current detection unit includes a second ammeter. After the aging test of the semiconductor device to be tested is completed, the closing and opening of each of the switch devices in the test circuit are controlled to test the performance parameters of the semiconductor device to be tested, including: closing the first switch device and the fifth switch device, connecting the common end of the second switch device and the first terminal, closing the sixth switch device, and adjusting the third voltage source to gradually increase the voltage starting from 0 until the current value displayed by the second ammeter reaches a first preset value, at which time the actual voltage of the third voltage source is the threshold voltage of the semiconductor device to be tested.

[0017] Optionally, the test circuit of the semiconductor device includes a first switch device, a fourth switch device, a second switch device, a power supply unit and a current detection unit, the fourth switch device and the second switch device are both single-pole double-throw switches, the power supply unit includes a third voltage source, and the current detection unit includes a second ammeter. After the aging test of the semiconductor device to be tested is completed, the closing and opening of each of the switch devices in the test circuit are controlled to test the performance parameters of the semiconductor device to be tested, including: closing the first switch device, connecting the common end of the second switch device with the first terminal, connecting the common end of the fourth switch device with the second terminal, adjusting the third voltage source to gradually increase the voltage from 0 as the starting point until the rated working voltage of the semiconductor device to be tested is reached, at which time the displayed current of the second ammeter is the drain leakage current of the semiconductor device to be tested; increasing the voltage of the third voltage source until the displayed current of the second ammeter reaches a second preset value, at which time the actual voltage of the third voltage source is the breakdown voltage of the semiconductor device to be tested.

[0018] Optionally, the test circuit of the semiconductor device includes a first switching device, a third switching device, a second switching device, a power supply unit and a current detection unit, the second switching device is a single-pole double-throw switch, the power supply unit includes a first voltage source and a third voltage source, and the current detection unit includes a second ammeter. After the aging test of the semiconductor device to be tested is completed, the closing and opening of each of the switching devices in the test circuit are controlled to test the performance parameters of the semiconductor device to be tested, including: closing the first switching device, connecting the common end of the second switching device and the first terminal, closing the third switching device, adjusting the first voltage source to output the maximum operating gate voltage of the semiconductor device to be tested, and adjusting the third voltage source to gradually increase the voltage starting from 0 until the displayed current value of the second ammeter reaches the rated operating current of the semiconductor device to be tested. At this time, the ratio of the actual voltage of the third voltage source to the displayed current of the second ammeter is the on-resistance of the semiconductor device to be tested.

[0019] Optionally, the test circuit of the semiconductor device includes a first switching device, a third switching device, a second switching device, a power supply unit and a current detection unit, the second switching device is a single-pole double-throw switch, the power supply unit includes a first voltage source, and the current detection unit includes a first ammeter. After the aging test of the semiconductor device to be tested is completed, the closing and opening of each of the switching devices in the test circuit are controlled to test the performance parameters of the semiconductor device to be tested, including: closing the first switching device, connecting the common end of the second switching device and the second terminal, closing the third switching device, and adjusting the first voltage source to gradually increase the voltage from 0 as the starting point to the maximum operating gate voltage of the semiconductor device to be tested. At this time, the current displayed by the first ammeter is the gate leakage current of the semiconductor device to be tested.

[0020] Applying the technical solution of the present application, the test circuit of the above-mentioned semiconductor device includes: a switch module, which is used to be electrically connected to the semiconductor device to be tested, including a first part of switch devices, a second part of switch devices and a third part of switch devices, the semiconductor device to be tested has a first end, a second end and a control end, the first part of the switch devices is electrically connected to at least one end of the semiconductor device to be tested, the second part of the switch devices is electrically connected to at least one end of the semiconductor device to be tested, and the third part of the switch devices is electrically connected to at least one end of the semiconductor device to be tested; wherein, by controlling the closing and opening of each switch device, a plurality of test loops are formed to perform various performance tests on the semiconductor device to be tested, the various performance tests include aging test, threshold voltage test, breakdown voltage and drain leakage current test, on-resistance test and gate leakage test, and the test loops and performance tests correspond one to one. The circuit completes the rapid transition from the electrothermal aging test of SiC devices to the performance characterization parameter test through switching, which can avoid repeated plugging and unplugging of devices, improve test efficiency, and accurately test the degradation law of the performance characterization parameters of SiC devices during the electrothermal aging process. It solves the problem that the traditional device testing method requires repeated plugging and unplugging of devices for multiple retests, which to a certain extent complicates the test steps, reduces the test efficiency, causes certain mechanical damage to the device, and cannot quickly and accurately test the various performance parameters of SiC devices during the aging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0022] Figure 1 A structural diagram of a test circuit for a semiconductor device provided in an embodiment of the present application is shown;

[0023] Figure 2A structural diagram of a test circuit for a semiconductor device provided in an embodiment of the present application is shown;

[0024] Figure 3 A structural diagram of a non-disassembly test circuit for a high-temperature reverse bias test of a SiC MOSFET semiconductor device to be tested provided in an embodiment of the present application is shown;

[0025] Figure 4 A structural diagram of a non-disassembly test circuit for a high-temperature reverse bias test of a SiC IGBT semiconductor device to be tested provided in an embodiment of the present application is shown;

[0026] Figure 5 A logic schematic diagram of a method for testing a silicon carbide device using a test circuit of any semiconductor device provided in an embodiment of the present application is shown;

[0027] Figure 6 A structural diagram of a non-disassembly test circuit for performing a zero gate voltage high temperature reverse bias test on a semiconductor device to be tested according to an embodiment of the present application is shown;

[0028] Figure 7 A structural diagram of a non-disassembly test circuit for performing a negative gate voltage high temperature reverse bias test on a semiconductor device to be tested provided in an embodiment of the present application is shown;

[0029] Figure 8 A structural diagram of a non-disassembly test circuit for performing a threshold voltage test on a semiconductor device to be tested provided in an embodiment of the present application is shown;

[0030] Fig. 9 A structural diagram of a non-disassembly test circuit for performing an on-resistance test on a semiconductor device to be tested provided in an embodiment of the present application is shown;

[0031] Fig.10 A structural diagram of a non-disassembly test circuit for performing a gate leakage test on a semiconductor device to be tested provided in an embodiment of the present application is shown;

[0032] Fig.11 A logic schematic diagram of another method for testing a silicon carbide device using a test circuit of any semiconductor device provided in an embodiment of the present application is shown.

[0033] The above drawings include the following reference numerals:

[0034] 10. Semiconductor device to be tested; 20. Test circuit; 21. Switch module; 22. Power supply unit; 23. Current detection unit; R1. First switch device; R2. Second switch device; R3. Third switch device; R4. Fourth switch device; R5. Fifth switch device; R6. Sixth switch device; V1. First voltage source; V2. Second voltage source; V3. Third voltage source; M1. First ammeter; M2. Second ammeter. DETAILED DESCRIPTION

[0035] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0036] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] As introduced in the background technology, the current traditional high-temperature reverse bias test first accelerates the aging of SiC devices under different voltage bias and temperature stress conditions. After a period of testing, the device is removed from the test fixture and the various performance characterization parameters of the device are retested in an offline manner. In order to accurately grasp the performance degradation law of the device during the electrothermal aging process, multiple retests are required. Repeated plugging and unplugging may cause mechanical damage to the device, which to a certain extent complicates the test steps and reduces the test efficiency. At the same time, for SiC devices, the changes in various performance parameters are closely related to the migration of movable ions and the trapping and detrapping of carriers. After the electrothermal stress ends, the parameters that have changed will recover at an exponential rate, and the test time interval has a greater impact on the test results. Therefore, the traditional offline test method cannot quickly and accurately test the various performance parameters of SiC devices during the aging process.

[0039] In order to solve the problem that traditional device testing methods require repeated plugging and unplugging of devices for multiple retests, which to a certain extent complicates the test steps, reduces the test efficiency, causes certain mechanical damage to the device, and cannot quickly and accurately test various performance parameters of SiC devices during the aging process, the embodiments of the present application provide a test circuit for a semiconductor device and a method for testing a silicon carbide device using any one of the test circuits of a semiconductor device.

[0040] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0041] Figure 1 is a structural diagram of a test circuit of a semiconductor device according to an embodiment of the present application. Figure 1 As shown, the test circuit includes: a switch module, which is used to electrically connect to the semiconductor device to be tested, including multiple switch devices, a first part of the switch devices is directly connected to the control end of the above-mentioned semiconductor device to be tested, a second part of the switch devices is directly connected to the first end of the above-mentioned semiconductor device to be tested, and a third part of the switch devices is directly connected to the second end of the above-mentioned semiconductor device to be tested, and the above-mentioned first part of the switch devices, the above-mentioned second part of the switch devices and the above-mentioned third part of the switch devices are different; wherein, by controlling the closing and opening of each of the above-mentioned switch devices, multiple test loops are formed to perform multiple performance tests on the above-mentioned semiconductor device to be tested, and the above-mentioned multiple performance tests include aging test, threshold voltage test, breakdown voltage and drain leakage current test, on-resistance test and gate leakage test, and the above-mentioned test loops and the above-mentioned performance tests correspond one to one.

[0042] The semiconductor devices to be tested include but are not limited to various types of SiCMOSFETs, SiC IGBTs and other three-terminal transistor devices with insulated gate structures with different current capabilities / voltage levels.

[0043] The test circuit of the above-mentioned semiconductor device of the present application includes: a switch module, which is used to be electrically connected to the semiconductor device to be tested, including a first part of switch devices, a second part of switch devices and a third part of switch devices. The semiconductor device to be tested has a first end, a second end and a control end. The first part of the switch devices is electrically connected to at least one end of the semiconductor device to be tested, the second part of the switch devices is electrically connected to at least one end of the semiconductor device to be tested, and the third part of the switch devices is electrically connected to at least one end of the semiconductor device to be tested; wherein, by controlling the closing and opening of each switch device, a plurality of test loops are formed to perform various performance tests on the semiconductor device to be tested, and the various performance tests include aging test, threshold voltage test, breakdown voltage and drain leakage current test, on-resistance test and gate leakage test, and the test loops and performance tests correspond one to one. The circuit completes the rapid transition from the electrothermal aging test of SiC devices to the performance characterization parameter test through switching, which can avoid repeated plugging and unplugging of devices, improve test efficiency, and accurately test the degradation law of the performance characterization parameters of SiC devices during the electrothermal aging process. It solves the problem that the traditional device testing method requires repeated plugging and unplugging of devices for multiple retests, which to a certain extent complicates the test steps, reduces the test efficiency, causes certain mechanical damage to the device, and cannot quickly and accurately test the various performance parameters of SiC devices during the aging process.

[0044] Among them, the SiC device electrothermal aging test circuit and the performance characterization parameter test circuit are integrated into one system. By switching the switch matrix, the threshold voltage, breakdown voltage, on-resistance and leakage test of the SiC device can be quickly completed after the accelerated aging test. It can effectively avoid the potential mechanical damage to the device caused by repeated plugging and unplugging, simplify the test operation steps, shorten the test time interval, and realize the accurate test of the degradation law of the performance characterization parameters of the SiC device during the electrothermal aging process.

[0045] In some instances, such as Figure 2 As shown, the test circuit 20 further includes: a power supply unit 22, electrically connected to each of the switch devices, and used to provide a test voltage to the semiconductor device 10 under test; and a current detection unit 23, electrically connected to each of the switch devices and the power supply unit 22, and used to detect the test current.

[0046] According to the voltage value provided by the power supply unit and the current value detected by the current detection unit, the semiconductor device to be tested can be subjected to aging test, threshold voltage test, breakdown voltage and drain leakage current test, on-resistance test and gate leakage test to determine the operating parameters of the semiconductor device to be tested. The operating parameters of the semiconductor device to be tested include at least: the threshold voltage of the semiconductor device to be tested, the breakdown voltage of the semiconductor device to be tested, the drain leakage current of the semiconductor device to be tested, the on-resistance of the semiconductor device to be tested and the gate leakage current of the semiconductor device to be tested.

[0047] In some instances, such as Figure 3 As shown, the first part of the switching devices includes: a first switching device R1, a first end of the first switching device R1 is electrically connected to the first end of the semiconductor device to be tested; a second switching device R2, a common end of the second switching device R2 is electrically connected to the second end of the first switching device R1, a first connection terminal of the second switching device R2 is used to receive a first voltage signal, and a second connection terminal of the second switching device R2 is grounded; a third switching device R3, a first end of the third switching device R3 is electrically connected to the control end of the semiconductor device to be tested, and a second end of the third switching device R3 is used to receive a second voltage signal.

[0048] By controlling the closing or opening of the first switch device, the second switch device and the third switch device, the test circuit of the semiconductor device can be adjusted to an on-resistance test loop.

[0049] In some instances, such as Figure 3 As shown, the second part of the switching devices also includes: a fourth switching device R4, the common end of the fourth switching device R4 is electrically connected to the control end of the semiconductor device 10 to be tested, the first terminal of the fourth switching device R4 is used to receive a third voltage signal, and the second terminal of the fourth switching device R4 is grounded.

[0050] Among them, by controlling the closing or opening of the first switching device, the second switching device, the third switching device and the fourth switching device, the test circuit of the semiconductor device can be adjusted to one of the on-resistance test loop, the breakdown voltage and the drain leakage current test loop.

[0051] In some instances, such as Figure 3As shown, the above-mentioned third part of the switching devices also includes: a fifth switching device R5, a first end of the above-mentioned fifth switching device R5 is electrically connected to the control end of the above-mentioned semiconductor device 10 to be tested, and a second end of the above-mentioned fifth switching device R5 is electrically connected to the first end of the above-mentioned semiconductor device 10 to be tested; a sixth switching device R6, a first end of the above-mentioned sixth switching device R6 is electrically connected to the first end of the above-mentioned semiconductor device 10 to be tested, a second end of the above-mentioned sixth switching device R6 is electrically connected to the common end of the above-mentioned second switching device R2, a third end of the above-mentioned sixth switching device R6 is electrically connected to the second end of the above-mentioned semiconductor device 10 to be tested, and a fourth end of the above-mentioned sixth switching device R6 is electrically connected to the first connection terminal of the above-mentioned second switching device R2.

[0052] Among them, by controlling the closing or opening of the first switching device, the second switching device, the third switching device, the fourth switching device and the fifth switching device, the test circuit of the semiconductor device can be adjusted to one of a zero gate voltage high temperature reverse bias test circuit, a negative gate voltage high temperature reverse bias test circuit, a breakdown voltage and drain leakage current test, an on-resistance test circuit, and a gate leakage test circuit.

[0053] By controlling the closing or opening of the sixth switch device, the test circuit of the semiconductor device can be adjusted to a threshold voltage test loop.

[0054] In some instances, such as Figure 3 As shown, the first switch device R1, the fifth switch device R5 and the third switch device R3 are single-pole single-throw switches, and the fourth switch device R4 and the second switch device R2 are single-pole double-throw switches.

[0055] Among them, the rapid transition from the electrothermal aging test of SiC devices to the performance characterization parameter test is completed through circuit switching, which can avoid repeated plugging and unplugging of devices, improve test efficiency, and realize accurate testing of the degradation law of performance characterization parameters of SiC devices during the electrothermal aging process.

[0056] In some instances, such as Figure 3 As shown, the power supply unit includes: a first voltage source V1, the positive terminal of the first voltage source V1 is electrically connected to the second terminal of the third switch device R3 in the test circuit, and the negative terminal of the first voltage source V1 is grounded; a second voltage source V2, the negative terminal of the second voltage source V2 is electrically connected to the first terminal of the fourth switch device R4 in the test circuit, and the positive terminal of the second voltage source V2 is grounded; a third voltage source V3, the positive terminal of the third voltage source V3 is electrically connected to the first terminal of the second switch device R2 in the test circuit, and the negative terminal of the third voltage source V3 is electrically connected to the fourth terminal of the sixth switch device R6 in the test circuit.

[0057] Specifically, according to the voltages provided by the first voltage source, the second voltage source and the third voltage source, the semiconductor device to be tested can be subjected to aging test, threshold voltage test, breakdown voltage and drain leakage current test, on-resistance test and gate leakage test to determine the operating parameters of the semiconductor device to be tested.

[0058] In some instances, such as Figure 3 As shown, the first voltage source V1, the second voltage source V2 and the third voltage source V3 are all DC voltage sources.

[0059] Specifically, according to the DC voltage provided by the first voltage source, the second voltage source and the third voltage source, the semiconductor device to be tested can be subjected to aging test, threshold voltage test, breakdown voltage and drain leakage current test, on-resistance test and gate leakage test to determine the operating parameters of the semiconductor device to be tested.

[0060] In some instances, such as Figure 3 As shown, the current detection unit includes: a first ammeter M1, a first end of the first ammeter M1 is electrically connected to the negative end of the first voltage source V1 in the power supply unit, and a second end of the first ammeter M1 is grounded; a second ammeter M2, a first end of the second ammeter M2 is electrically connected to the negative end of the third voltage source V3 in the power supply unit, and a second end of the second ammeter M2 is grounded.

[0061] Specifically, according to the current values ​​detected by the first ammeter and the second ammeter, the semiconductor device under test can be subjected to aging test, threshold voltage test, breakdown voltage and drain leakage current test, on-resistance test and gate leakage test to determine the operating parameters of the semiconductor device under test.

[0062] The semiconductor device to be tested may be a SiC MOSFET or a SiC IGBT. Figure 3 As shown, Figure 3 The semiconductor device to be tested is SiC MOSFET, such as Figure 4 As shown, Figure 4 The semiconductor device to be tested is SiC IGBT.

[0063] Another embodiment of the present application also provides a method for testing a silicon carbide device using any of the above-mentioned semiconductor device test circuits, such as Figure 5 As shown, the above method comprises the following steps:

[0064] Step S101 , controlling the closing and opening of each switch device in the test circuit to perform various performance tests on the semiconductor device to be tested.

[0065] The above-mentioned method of testing silicon carbide devices using a test circuit of any semiconductor device in the present application controls the closing and opening of each switch device in the test circuit to perform various performance tests on the semiconductor device to be tested. This method completes the rapid transition from the electrothermal aging test of SiC devices to the performance characterization parameter test by switching, which can avoid repeated plugging and unplugging of devices, improve test efficiency, and achieve accurate testing of the performance characterization parameter degradation law of SiC devices during the electrothermal aging process. It solves the problem that the traditional device testing method requires repeated plugging and unplugging of devices for multiple retests, which to a certain extent complicates the test steps, reduces the test efficiency, and causes certain mechanical damage to the device, and cannot quickly and accurately test the various performance parameters of SiC devices during the aging process.

[0066] In some embodiments, controlling the closing and opening of each switch device in the test circuit to perform various performance tests on the semiconductor device to be tested includes the following steps:

[0067] Step S201, controlling the closing and opening of each of the switch devices in the test circuit, switching the test circuit to an aging test circuit, so as to perform an aging test on the semiconductor device to be tested;

[0068] Step S202, after completing the aging test on the above-mentioned semiconductor device to be tested, controlling the closing and opening of the above-mentioned switching devices in the above-mentioned test circuit to test the performance parameters of the above-mentioned semiconductor device to be tested to determine the reliability degradation of the above-mentioned semiconductor device to be tested, the above-mentioned performance parameters include: the threshold voltage of the above-mentioned semiconductor device to be tested, the breakdown voltage of the above-mentioned semiconductor device to be tested, the drain leakage current of the above-mentioned semiconductor device to be tested, the on-resistance of the above-mentioned semiconductor device to be tested and the gate leakage current of the above-mentioned semiconductor device to be tested.

[0069] Specifically, by switching the switch matrix, the threshold voltage, breakdown voltage, on-resistance and leakage test of the SiC device can be quickly completed after the accelerated aging test is completed, which can effectively avoid the potential mechanical damage to the device caused by repeated plugging and unplugging, simplify the test operation steps, shorten the test time interval, and realize accurate testing of the degradation law of the performance characterization parameters of the SiC device during the electrothermal aging process.

[0070] In some instances, such as Figure 6 and Figure 7As shown, the test circuit of the semiconductor device includes a first switch device R1, a fourth switch device R4, a second switch device R2 and a power supply unit, wherein the fourth switch device R4 and the second switch device R2 are both single-pole double-throw switches, and the power supply unit includes a second voltage source V2 and a third voltage source V3, which controls the closing and opening of each of the switch devices in the test circuit, switches the test circuit to an aging test circuit, and performs an aging test on the semiconductor device to be tested, including:

[0071] Step S2011, as Figure 6 As shown, the first switch device R1 is closed, the common terminal of the second switch device R2 is connected to the first terminal, the common terminal of the fourth switch device R4 is connected to the second terminal, and the third voltage source V3 is adjusted to output any value between 0 and the rated working voltage of the semiconductor device to be tested, so as to perform a high temperature reverse bias test on the semiconductor device to be tested under zero gate voltage conditions;

[0072] Specifically, this allows the device to be tested under high temperature reverse bias test under zero gate voltage conditions. The rated operating voltage of the SiC MOSFET device is V Dsmax and the device minimum operating gate voltage V GSmin All are read directly from the SiC MOSFET product data sheet under test.

[0073] Step S2012, as Figure 7 As shown, the common terminal and the second terminal of the fourth switch device R4 are disconnected, the common terminal and the first terminal of the fourth switch device R4 are connected, and the second voltage source V2 is adjusted to output the minimum gate voltage of the semiconductor device to be tested to any value between 0, so as to perform a high temperature reverse bias test on the semiconductor device to be tested under negative gate voltage conditions.

[0074] Specifically, this allows the device to be tested under high temperature reverse bias conditions with negative gate voltage. The rated operating voltage of the SiC MOSFET device is V Dsmax and the device minimum operating gate voltage V GSmin All are read directly from the SiC MOSFET product data sheet under test.

[0075] The semiconductor device to be tested is selected as SiC MOSFET to be tested, and SiC MOSFET is selected as a metal oxide semiconductor field effect transistor, and the three pins of the device are drain D, source S and gate G respectively.

[0076] Switch the switch matrix to the electrothermal aging test circuit to perform high temperature reverse bias test on the selected SiC MOSFET device. Figure 6 and Figure 7 As shown, switches R5, R3, and R6 do not need to be operated and remain in their original state, so they are omitted in the figure. Figure 6 and Figure 7 Among them, #1 is the first terminal, #2 is the second terminal, that is, R4#1 is the first terminal of the fourth switching device, R4#2 is the second terminal of the fourth switching device, R2#1 is the first terminal of the second switching device, and R2#2 is the second terminal of the second switching device. The above circuit also includes an ammeter M2.

[0077] After a period of aging test, the switch matrix is ​​switched to the performance characterization parameter test loop to test various parameters of the SiC MOSFET device to determine the reliability degradation of the device. The parameters to be tested include threshold voltage, breakdown voltage, drain (collector) leakage, on-resistance and gate leakage.

[0078] First, the threshold voltage of the SiC MOSFET device is tested. The circuit is as follows: Figure 8 As shown, switches R3 and R4 do not need to be operated and remain in the original state, so they are omitted in the figure. Figure 8 Among them, #1 is the first terminal, and #2 is the second terminal, that is, R2#1 is the first terminal of the second switching device, and R2#2 is the second terminal of the second switching device.

[0079] In some instances, such as Figure 8 As shown, the test circuit of the semiconductor device includes a first switch device R1, a fifth switch device R5, a second switch device R2, a sixth switch device R6, a power supply unit and a current detection unit, the second switch device R2 is a single-pole double-throw switch, the power supply unit includes a third voltage source V3, and the current detection unit includes a second ammeter M2. After the aging test of the semiconductor device to be tested is completed, the closing and opening of each of the switch devices in the test circuit are controlled to test the performance parameters of the semiconductor device to be tested, including: closing the first switch device R1 and the fifth switch device R5, connecting the common end of the second switch device R2 and the first connection terminal, closing the sixth switch device R6, and adjusting the third voltage source V3 to gradually increase the voltage starting from 0 until the current value displayed by the second ammeter M2 reaches a first preset value, at which time the actual voltage of the third voltage source V3 is the threshold voltage of the semiconductor device to be tested.

[0080] Among them, the three pins of the semiconductor device to be tested are the drain D, the source S and the gate G respectively.

[0081] Specifically, the threshold voltage of the semiconductor device to be tested can be accurately detected in this way.

[0082] After completing the device threshold voltage test, switch the switch matrix to test the device breakdown voltage and drain leakage. Figure 6The zero gate voltage high temperature reverse bias test circuit is the same. Close switches R1, R2#1, and R4#2 in sequence, and adjust the voltage source V3 to gradually increase the voltage from 0 to the rated working voltage V DSmax , at this time, the reading of the power meter M2 is the device drain leakage; further increase the voltage until the reading of the power meter M2 reaches 100μA, and the corresponding voltage at this time is the breakdown voltage of the SiC MOSFET device to be tested.

[0083] In some instances, such as Figure 6 As shown (breakdown voltage and drain leakage current test circuit structure and Figure 6 The test circuit of the semiconductor device comprises a first switch device R1, a fourth switch device R4, a second switch device R2, a power supply unit and a current detection unit. The fourth switch device R4 and the second switch device R2 are both single-pole double-throw switches. The power supply unit comprises a third voltage source V3. The current detection unit comprises a second ammeter M2. After the aging test of the semiconductor device to be tested is completed, the switch devices in the test circuit are controlled to be closed and opened to test the performance parameters of the semiconductor device to be tested, including: closing the above The first switch device R1 connects the common terminal of the second switch device R2 and the first terminal, connects the common terminal of the fourth switch device R4 and the second terminal, adjusts the third voltage source V3 to gradually increase the voltage starting from 0 until the rated working voltage of the semiconductor device to be tested is reached, at which time the displayed current of the second ammeter M2 is the drain leakage current of the semiconductor device to be tested; increases the voltage of the third voltage source V3 until the displayed current of the second ammeter M2 reaches the second preset value, at which time the actual voltage of the third voltage source V3 is the breakdown voltage of the semiconductor device to be tested.

[0084] Among them, the three pins of the semiconductor device to be tested are the drain D, the source S and the gate G respectively.

[0085] After completing the device breakdown voltage and drain leakage test, switch the switch matrix to test the device's on-resistance. The circuit form is as follows: Fig. 9 As shown, switches R5, R4, and R6 do not need to be operated and remain in their original state, so they are omitted in the figure. Fig. 9 #1 is the first terminal, #2 is the second terminal, that is, R2#1 is the first terminal of the second switch device, and R2#2 is the second terminal of the second switch device. The maximum operating gate voltage of the device is V GSmax Read directly from the SiC MOSFET product data sheet under test.

[0086] In some instances, such as Fig. 9As shown, the test circuit of the semiconductor device includes a first switch device R1, a third switch device R3, a second switch device R2, a power supply unit and a current detection unit, the second switch device R2 is a single-pole double-throw switch, the power supply unit includes a first voltage source V1 and a third voltage source V3, the current detection unit includes a second ammeter M2, and after the aging test of the semiconductor device to be tested is completed, the closing and opening of each of the switch devices in the test circuit are controlled to test the performance parameters of the semiconductor device to be tested, including: closing the first switch device R1, connecting the common end of the second switch device R2 and the first connection terminal, closing the third switch device R3, adjusting the first voltage source V1 to output the maximum working gate voltage of the semiconductor device to be tested, and adjusting the third voltage source V3 to gradually increase the voltage from 0 as the starting point until the current value displayed by the second ammeter M2 reaches the rated working current of the semiconductor device to be tested, at which time the ratio of the actual voltage of the third voltage source V3 to the current displayed by the second ammeter M2 is the on-resistance of the semiconductor device to be tested.

[0087] Among them, the three pins of the semiconductor device to be tested are the drain D, the source S and the gate G respectively.

[0088] Device maximum operating gate voltage V GSmax Read directly from the SiC MOSFET product data sheet under test.

[0089] Specifically, the on-resistance of the semiconductor device to be tested can be accurately detected in this way.

[0090] After completing the device on-resistance test, switch the switch matrix to test the device gate leakage. The circuit form is as follows: Fig.10 As shown, switches R5, R4, and R6 do not need to be operated and remain in their original state, so they are omitted in the figure. Fig.10 #1 is the first terminal, #2 is the second terminal, that is, R2#1 is the first terminal of the second switch device, and R2#2 is the second terminal of the second switch device. The maximum operating gate voltage of the device is V GSmax Read directly from the SiC MOSFET product data sheet under test.

[0091] In some instances, such as Fig.10As shown, the test circuit of the semiconductor device includes a first switch device R1, a third switch device R3, a second switch device R2, a power supply unit and a current detection unit, the second switch device R2 is a single-pole double-throw switch, the power supply unit includes a first voltage source V1, and the current detection unit includes a first ammeter M1. After the aging test of the semiconductor device to be tested is completed, the closing and opening of each of the switch devices in the test circuit are controlled to test the performance parameters of the semiconductor device to be tested, including: closing the first switch device R1, connecting the common end of the second switch device R2 and the second terminal, closing the third switch device R3, adjusting the first voltage source V1 to gradually increase the voltage from 0 as the starting point to the maximum working gate voltage of the semiconductor device to be tested, at this time, the current displayed by the first ammeter M1 is the gate leakage current of the semiconductor device to be tested.

[0092] Among them, the three pins of the semiconductor device to be tested are the drain D, the source S and the gate G respectively.

[0093] Device maximum operating gate voltage V GSmax Read directly from the SiC MOSFET product data sheet under test.

[0094] Specifically, in this way, the gate leakage current of the semiconductor device to be tested can be accurately detected.

[0095] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the method of the present application for testing a silicon carbide device using a test circuit of any semiconductor device will be described in detail below in combination with specific embodiments.

[0096] This embodiment relates to a specific method for testing a silicon carbide device using a test circuit of any semiconductor device, such as Figure 3 and Fig.11 As shown, the following steps are included:

[0097] Step S1: Select a SiC MOSFET to be tested, switch the switch matrix to the electric thermal aging test loop to perform a high temperature reverse bias test on the selected SiC MOSFET device;

[0098] Step S2: sequentially close switches R1, R2#1, and R4#2 to perform a high-temperature reverse bias test on the device under test under zero gate voltage conditions, or sequentially close switches R1, R2#1, and R4#1 to perform a high-temperature reverse bias test on the device under test under negative gate voltage conditions;

[0099] Step S3: After the aging test is completed, the switch matrix is ​​switched to the performance characterization parameter test loop to test various parameters of the SiC MOSFET device to determine the reliability degradation of the device;

[0100] Step S4: Close switches R1, R5, R2#1 and R6 in sequence to test the threshold voltage of the device under test;

[0101] Step S5: Close switches R1, R2#1, and R4#2 in sequence to test the breakdown voltage and drain (collector) leakage of the SiC MOSFET device to be tested.

[0102] Step S6: Close switches R1, R2#1, and R3 in sequence to test the on-resistance of the SiC MOSFET device to be tested.

[0103] Step S7: Close switches R1, R2#2, and R3 in sequence to test the gate leakage current of the SiC MOSFET device to be tested.

[0104] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0105] 1) The test circuit of the semiconductor device of the present application comprises: a switch module, which is used to be electrically connected to the semiconductor device to be tested, including a first part of switch devices, a second part of switch devices and a third part of switch devices, the semiconductor device to be tested has a first end, a second end and a control end, the first part of the switch devices is electrically connected to at least one end of the semiconductor device to be tested, the second part of the switch devices is electrically connected to at least one end of the semiconductor device to be tested, and the third part of the switch devices is electrically connected to at least one end of the semiconductor device to be tested; wherein, by controlling the closing and opening of each switch device, a plurality of test loops are formed to perform a variety of performance tests on the semiconductor device to be tested, the various performance tests include aging test, threshold voltage test, breakdown voltage and drain leakage current test, on-resistance test and gate leakage test, and the test loops and performance tests correspond one to one. The circuit completes the rapid transition from the electrothermal aging test of SiC devices to the performance characterization parameter test through switching, which can avoid repeated plugging and unplugging of devices, improve test efficiency, and accurately test the degradation law of the performance characterization parameters of SiC devices during the electrothermal aging process. It solves the problem that the traditional device testing method requires repeated plugging and unplugging of devices for multiple retests, which to a certain extent complicates the test steps, reduces the test efficiency, causes certain mechanical damage to the device, and cannot quickly and accurately test the various performance parameters of SiC devices during the aging process.

[0106] 2) The above-mentioned method of testing silicon carbide devices using any semiconductor device test circuit of the present application controls the closing and opening of each switch device in the test circuit to perform various performance tests on the semiconductor device to be tested. This method completes the rapid transition from the electrothermal aging test of SiC devices to the performance characterization parameter test by switching, which can avoid repeated plugging and unplugging of devices, improve test efficiency, and achieve accurate testing of the performance characterization parameter degradation law of SiC devices during the electrothermal aging process. It solves the problem that the traditional device testing method requires repeated plugging and unplugging of devices for multiple retests, which to a certain extent complicates the test steps, reduces the test efficiency, and causes certain mechanical damage to the device, and cannot quickly and accurately test the various performance parameters of SiC devices during the aging process.

[0107] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A test circuit for a semiconductor device, characterized in that: include: A switch module, used to be electrically connected to a semiconductor device to be tested, comprising a first part of switch devices, a second part of switch devices and a third part of switch devices, wherein the semiconductor device to be tested has a first end, a second end and a control end, the first part of switch devices is electrically connected to at least one end of the semiconductor device to be tested, the second part of switch devices is electrically connected to at least one end of the semiconductor device to be tested, and the third part of switch devices is electrically connected to at least one end of the semiconductor device to be tested; Wherein, by controlling the closing and opening of each of the switch devices, a plurality of test loops are formed to perform a plurality of performance tests on the semiconductor device to be tested, wherein the plurality of performance tests include an aging test, a threshold voltage test, a breakdown voltage and drain leakage current test, an on-resistance test, and a gate leakage test, and the test loops correspond to the performance tests one by one; The first part of the switching devices includes: a first switching device, a first end of the first switching device is electrically connected to the first end of the semiconductor device to be tested; a second switching device, a common end of the second switching device is electrically connected to the second end of the first switching device, a first connection terminal of the second switching device is used to receive a first voltage signal, and a second connection terminal of the second switching device is grounded; a third switching device, a first end of the third switching device is electrically connected to the control end of the semiconductor device to be tested, and a second end of the third switching device is used to receive a second voltage signal.

2. The test circuit according to claim 1, characterized in that: The test circuit further comprises: A power supply unit, electrically connected to each of the switch devices, and configured to provide a test voltage to the semiconductor device to be tested; A current detection unit is electrically connected to each of the switch devices and the power supply unit, and the current detection unit is used to detect a test current.

3. The test circuit according to claim 1, characterized in that: The second part of the switching devices includes: A fourth switch device, wherein the common terminal of the fourth switch device is electrically connected to the control terminal of the semiconductor device to be tested, the first terminal of the fourth switch device is used to receive a third voltage signal, and the second terminal of the fourth switch device is grounded.

4. The test circuit according to claim 1 or 3, characterized in that: The third part of the switch device comprises: a fifth switch device, wherein a first terminal of the fifth switch device is electrically connected to the control terminal of the semiconductor device under test, and a second terminal of the fifth switch device is electrically connected to the first terminal of the semiconductor device under test; A sixth switching device, wherein a first end of the sixth switching device is electrically connected to the first end of the semiconductor device to be tested, a second end of the sixth switching device is electrically connected to the common end of the second switching device, a third end of the sixth switching device is electrically connected to the second end of the semiconductor device to be tested, and a fourth end of the sixth switching device is electrically connected to the first connection terminal of the second switching device.

5. The test circuit according to claim 2, characterized in that: The power supply unit comprises: a first voltage source, wherein a positive terminal of the first voltage source is electrically connected to a second terminal of a third switch device in the test circuit, and a negative terminal of the first voltage source is grounded; a second voltage source, wherein a negative terminal of the second voltage source is electrically connected to a first terminal of a fourth switch device in the test circuit, and a positive terminal of the second voltage source is grounded; A third voltage source, wherein a positive terminal of the third voltage source is electrically connected to a first terminal of a second switching device in the test circuit, and a negative terminal of the third voltage source is electrically connected to a fourth terminal of a sixth switching device in the test circuit.

6. The test circuit according to claim 5, characterized in that: The first voltage source, the second voltage source and the third voltage source are all DC voltage sources.

7. The test circuit according to claim 2, characterized in that: The current detection unit comprises: a first ammeter, wherein a first end of the first ammeter is electrically connected to a negative terminal of a first voltage source in the power supply unit, and a second end of the first ammeter is grounded; A second ammeter, wherein a first end of the second ammeter is electrically connected to a negative terminal of a third voltage source in the power supply unit, and a second end of the second ammeter is grounded.

8. A method for testing a silicon carbide device using the semiconductor device test circuit according to any one of claims 1 to 7, characterized in that: include: The closing and opening of each switch device in the test circuit is controlled to perform various performance tests on the semiconductor device to be tested.

9. The method according to claim 8, characterized in that Controlling the closing and opening of each switch device in the test circuit to perform various performance tests on the semiconductor device under test, including: Controlling the closing and opening of each of the switch devices in the test circuit, switching the test circuit to an aging test circuit, so as to perform an aging test on the semiconductor device to be tested; After completing the aging test on the semiconductor device to be tested, the closing and opening of each of the switch devices in the test circuit are controlled to test the performance parameters of the semiconductor device to be tested to determine the reliability degradation of the semiconductor device to be tested, wherein the performance parameters include: the threshold voltage of the semiconductor device to be tested, the breakdown voltage of the semiconductor device to be tested, the drain leakage current of the semiconductor device to be tested, the on-resistance of the semiconductor device to be tested, and the gate leakage current of the semiconductor device to be tested.

10. The method according to claim 9, characterized in that The test circuit of the semiconductor device includes a first switch device, a fourth switch device, a second switch device and a power supply unit, wherein the fourth switch device and the second switch device are both single-pole double-throw switches, and the power supply unit includes a second voltage source and a third voltage source, and controls the closing and opening of each of the switch devices in the test circuit, switches the test circuit to an aging test circuit, and performs an aging test on the semiconductor device to be tested, including: Closing the first switch device, connecting the common terminal of the second switch device and the first terminal, connecting the common terminal of the fourth switch device and the second terminal, and adjusting the third voltage source to output any value between 0 and the rated operating voltage of the semiconductor device to be tested, so as to perform a high temperature reverse bias test on the semiconductor device to be tested under zero gate voltage conditions; Disconnect the common terminal and the second terminal of the fourth switch device, connect the common terminal and the first terminal of the fourth switch device, and adjust the second voltage source to output the minimum gate voltage of the semiconductor device to be tested to any value between 0, so as to perform a high temperature reverse bias test on the semiconductor device to be tested under negative gate voltage conditions.

11. The method according to claim 9, characterized in that The test circuit of the semiconductor device includes a first switch device, a fifth switch device, a second switch device, a sixth switch device, a power supply unit and a current detection unit, wherein the second switch device is a single-pole double-throw switch, the power supply unit includes a third voltage source, and the current detection unit includes a second ammeter. After the aging test of the semiconductor device to be tested is completed, the closing and opening of each of the switch devices in the test circuit are controlled to test the performance parameters of the semiconductor device to be tested, including: Close the first switch device and the fifth switch device, connect the common end of the second switch device and the first terminal, close the sixth switch device, and adjust the third voltage source to gradually increase the voltage starting from 0 until the current value displayed by the second ammeter reaches a first preset value. At this time, the actual voltage of the third voltage source is the threshold voltage of the semiconductor device to be tested.

12. The method according to claim 9, characterized in that The test circuit of the semiconductor device includes a first switch device, a fourth switch device, a second switch device, a power supply unit and a current detection unit, wherein the fourth switch device and the second switch device are single-pole double-throw switches, the power supply unit includes a third voltage source, and the current detection unit includes a second ammeter. After the aging test of the semiconductor device to be tested is completed, the closing and opening of each of the switch devices in the test circuit are controlled to test the performance parameters of the semiconductor device to be tested, including: The first switch device is closed, the common terminal of the second switch device is connected to the first terminal, the common terminal of the fourth switch device is connected to the second terminal, and the third voltage source is adjusted to gradually increase the voltage from 0 as the starting point until the rated working voltage of the semiconductor device to be tested is reached, and the current displayed by the second ammeter is the drain leakage current of the semiconductor device to be tested; The voltage of the third voltage source is increased until the current displayed by the second ammeter reaches a second preset value, at which time the actual voltage of the third voltage source is the breakdown voltage of the semiconductor device to be tested.

13. The method according to claim 9, characterized in that The test circuit of the semiconductor device includes a first switch device, a third switch device, a second switch device, a power supply unit and a current detection unit, wherein the second switch device is a single-pole double-throw switch, the power supply unit includes a first voltage source and a third voltage source, and the current detection unit includes a second ammeter. After the aging test of the semiconductor device to be tested is completed, the closing and opening of each of the switch devices in the test circuit are controlled to test the performance parameters of the semiconductor device to be tested, including: Close the first switch device, connect the common end of the second switch device and the first terminal, close the third switch device, adjust the first voltage source to output the maximum operating gate voltage of the semiconductor device to be tested, and adjust the third voltage source to gradually increase the voltage starting from 0 until the displayed current value of the second ammeter reaches the rated operating current of the semiconductor device to be tested. At this time, the ratio of the actual voltage of the third voltage source to the displayed current of the second ammeter is the on-resistance of the semiconductor device to be tested.

14. The method according to claim 9, characterized in that The test circuit of the semiconductor device includes a first switch device, a third switch device, a second switch device, a power supply unit and a current detection unit, wherein the second switch device is a single-pole double-throw switch, the power supply unit includes a first voltage source, and the current detection unit includes a first ammeter. After the aging test of the semiconductor device to be tested is completed, the closing and opening of each of the switch devices in the test circuit are controlled to test the performance parameters of the semiconductor device to be tested, including: Close the first switch device, connect the common end and the second terminal of the second switch device, close the third switch device, and adjust the first voltage source to gradually increase the voltage from 0 as the starting point to the maximum operating gate voltage of the semiconductor device to be tested. At this time, the current displayed by the first ammeter is the gate leakage current of the semiconductor device to be tested.

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