A test circuit and a test device

Abstract

The present application provides a test circuit and a test device, which relate to the field of semiconductor device technology, wherein the test circuit includes: a pulse control circuit and a DC bias circuit; wherein the DC bias circuit includes: a multi-stage inductor connected in series, one end of the first stage inductor in the multi-stage inductor is the output end of the DC bias circuit, and the other end of the last stage inductor in the multi-stage inductor is the input end of the DC bias circuit; the power supply end of the pulse control circuit is used to connect a preset DC power supply, the input end of the pulse control circuit is used to connect a preset pulse control end to receive a pulse test signal, the output end of the pulse control circuit is connected to the input end of the DC bias circuit, and the output end of the DC bias circuit is used to connect to the preset power supply end of the RF amplifier chip to be tested. The test circuit provided by the present application reduces the influence of temperature changes on the RF amplifier chip to be tested, and improves the accuracy of the test results of the RF amplifier chip to be tested.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor components, and in particular to a test circuit and a test device. Background Art

[0002] In the field of modern electronic technology, RF amplifier chips, as a key signal processing component, are widely used in audio equipment, wireless communications, radar systems and other fields. Since the performance of RF amplifier chips directly affects the stability and efficiency of the entire system, it is particularly important to test them accurately and efficiently.

[0003] Currently, only ordinary pulse amplifier chips can be tested. Traditional testing methods often require complex testing equipment and a long time, resulting in high testing costs. Secondly, the existing testing technology is difficult to meet the requirements of test accuracy and reliability when facing high-frequency and high-power application scenarios.

[0004] However, the RF amplifier chip generates severe heat during operation. Testing of ordinary pulse amplifier chips cannot solve the heating problem of the RF amplifier chip, which affects the accuracy of the results of the RF amplifier chip. Summary of the invention

[0005] The purpose of the present application is to provide a test circuit and a test device to address the deficiencies in the above-mentioned prior art, reduce the impact of temperature changes on the RF amplifier chip to be tested, and improve the accuracy of the test results of the RF amplifier chip to be tested.

[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0007] In a first aspect, an embodiment of the present application provides a test circuit, the circuit comprising:

[0008] A pulse control circuit, a DC bias circuit and a radio frequency microstrip line; wherein the DC bias circuit comprises: a multi-stage inductor connected in series, one end of the first stage inductor in the multi-stage inductor is the output end of the DC bias circuit, and the other end of the last stage inductor in the multi-stage inductor is the input end of the DC bias circuit;

[0009] The power supply end of the pulse control circuit is used to connect to a preset DC power supply, the input end of the pulse control circuit is used to connect to a preset pulse control end to receive a pulse test signal, the output end of the pulse control circuit is connected to the input end of the DC bias circuit, and the output end of the DC bias circuit is used to connect to a preset power supply end of the RF amplifier chip to be tested.

[0010] Optionally, the first-stage inductor is a high-frequency conical inductor, and the inductance values ​​of each stage of the multi-stage inductor from the second-stage inductor to the last-stage inductor increase sequentially.

[0011] Optionally, the DC bias circuit further includes: a plurality of first resistors;

[0012] Each of the inductors from the second inductor to the last inductor in the multi-stage inductor is connected in parallel with a first resistor.

[0013] Optionally, the DC bias circuit further includes: a first capacitor and a multi-stage second capacitor;

[0014] The other end of the first-stage inductor is connected to the ground in parallel through the first capacitor, and the other ends of the inductors from the second-stage inductor to the last-stage inductor in the multi-stage inductor are connected to the ground in parallel through the multi-stage second capacitors in sequence.

[0015] Optionally, the other ends of the inductors of each stage are connected to the ground in parallel through the multiple stages of second capacitors with successively increasing capacitance values;

[0016] The capacitance values ​​of the plurality of second capacitors are all greater than the capacitance value of the first capacitor.

[0017] Optionally, the multi-stage second capacitors are also respectively connected in series with a plurality of second resistors.

[0018] Optionally, the pulse control circuit includes: a first switch tube and a second switch tube;

[0019] Among them, the source of the first switch tube is the power supply end of the pulse control circuit, which is used to connect the preset DC power supply, the drain of the first switch tube is the output end of the pulse control circuit, a third resistor is connected in series between the source and the gate of the first switch tube, the gate of the first switch tube is connected to the drain of the second switch tube, the source of the second switch tube is grounded, and the gate of the second switch tube is the input end of the pulse control circuit, which is used to connect the preset pulse control end.

[0020] In a second aspect, another embodiment of the present application provides a testing device, the device comprising:

[0021] A base and two test circuit boards, each of which is provided with a test circuit as described in any one of the first aspects above, and a radio frequency microstrip line;

[0022] The two parts of the base are respectively connected to the RF microstrip lines on the two test circuit boards, the RF microstrip lines on the two test circuit boards are respectively used to connect the RF input terminal and the RF output terminal of the RF amplifier chip to be tested, the power supply terminal of the pulse control circuit in the test circuit on the two test circuit boards is respectively used to connect two preset DC power supplies, and the output terminal of the DC bias circuit in the test circuit on the two test circuit boards is respectively used to connect the gate power supply terminal and the drain power supply terminal of the RF amplifier chip to be tested.

[0023] Optionally, the first part of the two parts of the base is provided with a groove portion, and the second part of the two parts of the base is provided with a protrusion matching with the groove portion at a corresponding position, and the groove portion and the protrusion are butt-connected and slidably connected.

[0024] Optionally, an adjustable knob is provided on the groove portion at a position perpendicular to a preset sliding direction to lock the sliding position of the groove portion.

[0025] The beneficial effects of this application are:

[0026] The present application provides a test circuit and a test device, the test circuit includes a pulse control circuit and a DC bias circuit; wherein the DC bias circuit includes: a multi-stage inductor connected in series, one end of the first stage inductor in the multi-stage inductor is the output end of the DC bias circuit, and the other end of the last stage inductor in the multi-stage inductor is the input end of the DC bias circuit; the power supply end of the pulse control circuit is used to connect a preset DC power supply, the input end of the pulse control circuit is used to connect a preset pulse control end to receive a pulse test signal, the output end of the pulse control circuit is connected to the input end of the DC bias circuit, and the output end of the DC bias circuit is used to connect to the preset power supply end of the RF amplifier chip to be tested. The DC bias circuit in the present application can improve the quality factor of the inductor, increase the inductor isolation bandwidth, and improve the broadband performance of the DC bias circuit by connecting multiple stages of inductors in series. At the same time, the test circuit provided in the present application intermittently supplies power to the RF amplifier chip to be tested by receiving a pulse test signal sent by a preset pulse control end, reduces the heating of the RF amplifier chip to be tested, reduces the influence of temperature changes on the RF amplifier chip to be tested, and improves the accuracy of the test results of the RF amplifier chip to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1A schematic diagram of the structure of a first test circuit provided in an embodiment of the present application;

[0029] Figure 2 A schematic diagram of the structure of a second test circuit provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram of the structure of a third test circuit provided in an embodiment of the present application;

[0031] Figure 4 A schematic diagram of the structure of a fourth test circuit provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of the structure of a fifth test circuit provided in an embodiment of the present application;

[0033] Figure 6 A schematic diagram of the structure of a sixth test circuit provided in an embodiment of the present application;

[0034] Figure 7 A schematic diagram of the structure of a testing device provided in an embodiment of the present application;

[0035] Figure 8 A schematic diagram of the test results of a radio frequency amplifier chip to be tested provided in this application;

[0036] Fig. 9 A schematic diagram of the structure of a second testing device provided in an embodiment of the present application;

[0037] Fig.10 A schematic diagram of the structure of a third testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0039] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0041] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the invention is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0042] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0043] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0044] In order to clearly describe the test circuit provided in the embodiment of the present application, the test circuit provided in the present application is explained below in combination with multiple drawings. The RF amplifier chip to be tested in the present application can be an ultra-wideband pulse amplifier chip. Figure 1 A schematic diagram of the structure of the first test circuit provided in the embodiment of the present application is shown in FIG. Figure 1 As shown, the test circuit includes: a pulse control circuit 100 and a DC bias circuit 200; wherein the DC bias circuit 200 includes: a multi-stage inductor 201 connected in series, one end of the first stage inductor L1 in the multi-stage inductor L is the output end of the DC bias circuit 200, and the other end of the last stage inductor Ln in the multi-stage inductor 201 is the input end of the DC bias circuit 200;

[0045] The power supply terminal V of the pulse control circuit 100 is used to connect to a preset DC power supply DC, the input terminal IN1 of the pulse control circuit 100 is used to connect to a preset pulse control terminal to receive a pulse test signal TTL, the output terminal OUT1 of the pulse control circuit 100 is connected to the input terminal IN2 of the DC bias circuit 200, and the output terminal OUT2 of the DC bias circuit 200 is used to connect to a preset power supply terminal of a RF amplifier chip to be tested (not shown in the figure).

[0046] Among them, the pulse test signal TTL has a specific pulse shape, amplitude, width and repetition frequency. When the pulse test signal TTL is at a high level, the test circuit is turned on to supply power to the RF amplifier chip under test. When the pulse test signal TTL is at a low level, the test circuit is disconnected and power is stopped to the RF amplifier chip under test. The pulse test signal TTL can be used to provide intermittent power to the RF amplifier chip under test, effectively reducing the heat generated during the test of the RF amplifier chip under test, making the test temperature more accurate, and preventing the test heat from causing temperature changes that affect the test results of the RF amplifier chip under test.

[0047] When the input terminal IN1 of the pulse control circuit 100 receives the pulse test signal TTL of high level, the power supply terminal V and the output terminal OUT1 of the pulse control circuit 100 are turned on, so that the current of the preset DC power supply DC flows to the DC bias circuit 200. The DC bias circuit 200 includes a multi-stage inductor 201, and the multi-stage inductor 201 is connected in series to achieve the broadband characteristics of the multi-stage inductor 201.

[0048] The present application provides a test circuit, which includes a pulse control circuit and a DC bias circuit; wherein the DC bias circuit includes: a multi-stage inductor connected in series, one end of the first stage inductor in the multi-stage inductor is the output end of the DC bias circuit, and the other end of the last stage inductor in the multi-stage inductor is the input end of the DC bias circuit; the power supply end of the pulse control circuit is used to connect a preset DC power supply, the input end of the pulse control circuit is used to connect a preset pulse control end to receive a pulse test signal, the output end of the pulse control circuit is connected to the input end of the DC bias circuit, and the output end of the DC bias circuit is used to connect to the preset power supply end of the RF amplifier chip to be tested. The DC bias circuit in the present application can improve the quality factor of the inductor, increase the inductor isolation bandwidth, and improve the broadband performance of the DC bias circuit through multi-stage inductor sensing. At the same time, the test circuit provided in the present application intermittently supplies power to the RF amplifier chip to be tested by receiving a pulse test signal sent by a preset pulse control end, reduces the heating of the RF amplifier chip to be tested, reduces the influence of temperature changes on the RF amplifier chip to be tested, and improves the accuracy of the test results of the RF amplifier chip to be tested.

[0049] Based on the above embodiment, the present application also provides a structural schematic diagram of a second test circuit, Figure 2 A schematic diagram of the structure of a second test circuit provided in an embodiment of the present application is shown in FIG. Figure 2 As shown in the above Figure 1 On the basis of, the first-stage inductor L1 is a high-frequency conical inductor, and the inductance values ​​of each stage of the inductor from the second-stage inductor L2 to the last-stage inductor Ln in the multi-stage inductor 201 increase sequentially.

[0050] Among them, the first-stage inductor L1 is a high-frequency conical inductor, which has good high-frequency performance and can ensure the signal isolation between the high-frequency band in the DC current and the RF end. The inductance values ​​of each level of inductance from the second-stage L2 inductor to the last-stage inductor Ln in the multi-stage inductor 201 increase successively. The larger the inductance value of each level of inductance, the better the low-frequency isolation performance, which can ensure the signal isolation between the low-frequency band in the DC current and the RF end. At the same time, by connecting the multi-stage inductor 201 in series, the quality factor of the inductor can be improved, the isolation bandwidth of the multi-stage inductor 201 can be increased, and the broadband performance of the DC bias circuit 200 can be improved.

[0051] In the embodiment of the present application, the first-stage inductor in the multi-stage inductor in the DC bias circuit is a high-frequency conical inductor, and the inductance values ​​of each stage of the inductor from the second stage to the last stage increase in sequence. The high-frequency band signal and the low-frequency band signal in the DC current can be isolated, ensuring the accuracy of the test results of the RF amplifier chip to be tested.

[0052] Based on the above embodiments, the present application also provides a third test circuit: Figure 3 A schematic diagram of the structure of a third test circuit provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, in Figure 1 On the basis of, the DC bias circuit further includes: a plurality of first resistors R1; each level of the inductor from the second level inductor L2 to the last level inductor Ln in the multi-level inductor is connected in parallel with a first resistor R1.

[0053] Among them, multiple first resistors R1 are respectively connected in parallel with each level of inductance from the second-level inductor L2 to the last-level inductor Ln, which can reduce the resistance value of the equivalent resistance of the circuit after the multiple first resistors R1 are respectively connected in parallel with each level of inductance from the second-level inductor L2 to the last-level inductor Ln, and better play the characteristics of each level of inductance from the second-level inductor L2 to the last-level inductor Ln in the multi-level inductor.

[0054] In the embodiment of the present application, the DC bias circuit further includes: a plurality of first resistors; each of the inductors from the second to the last stage in the multi-stage inductor is connected in parallel with a first resistor, so as to better exert the inductance characteristics of the multi-stage inductor.

[0055] Based on the above embodiments, the present application also provides a fourth test circuit, Figure 4A schematic diagram of the structure of a fourth test circuit provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, in Figure 1 On the basis of, the DC bias circuit 200 further includes: a first capacitor C1 and a multi-stage second capacitor C2;

[0056] The other end of the first-stage inductor L1 is connected to the ground in parallel through the first capacitor C1 , and the other ends of each stage inductor 201 from the second-stage inductor L2 to the last-stage inductor Ln in the multi-stage inductor 201 are connected to the ground in parallel in sequence through the multi-stage second capacitors C2 .

[0057] The other end of each level of inductor 201 is connected to the ground in parallel through multiple levels of second capacitors C2 with increasing capacitance values; the capacitance values ​​of the multiple second capacitors C2 are all greater than the capacitance value of the first capacitor C1. The parallel connection of multiple levels of second capacitors C2 with different capacitance values ​​can increase the capacitor filtering bandwidth and improve the broadband performance.

[0058] The other end of the first-stage inductor L1 is connected to the ground in parallel through the first capacitor C1. The first capacitor C1 can filter out the power ripple in the first-stage inductor L1, absorb the pulse caused by power overshoot, and protect the RF amplifier chip under test. The other ends of the inductors 201 of the second-stage inductor L2 to the last-stage inductor Ln in the multi-stage inductor 201 are connected to the ground in parallel through the multi-stage second capacitor C2 in turn to filter out the power ripple in the inductors 201 of the second-stage inductor L2 to the last-stage inductor Ln in the multi-stage inductor 201, absorb the pulse caused by power overshoot, and protect the RF amplifier chip under test.

[0059] In an embodiment of the present application, the DC bias circuit further includes: a first capacitor and a multi-stage second capacitor; the other end of the first stage inductor is connected to the ground in parallel through the first capacitor, and the other ends of the inductors of the second stage inductor to the last stage inductor in the multi-stage inductor are connected to the ground in parallel in turn through the multi-stage second capacitor. In the present application, the parallel connection of the multi-stage second capacitors with different capacitance values ​​can improve the capacitor filtering bandwidth, improve the broadband performance, and can also protect the RF amplifier chip to be tested.

[0060] Based on the above embodiments, the present application also provides a fifth test circuit, Figure 5 A schematic diagram of the structure of a fifth test circuit provided in an embodiment of the present application is shown in FIG. Figure 5 As shown in the above Figure 4 On the basis of, the multi-stage second capacitors C2 are further connected in series with a plurality of second resistors R2.

[0061] The resistance values ​​of the plurality of second resistors R2 may be the same or different, and the embodiment of the present application does not limit this. The second resistor R2 is connected in series with the second capacitor C2, and the second resistor R2 plays a damping role, consuming the energy of the voltage on the path, thereby suppressing the oscillation of the test circuit.

[0062] Optionally, the first capacitor C1 may also be connected in series with a resistor, and the function of the resistor is the same as that of the second resistor R2 . The present application does not impose any limitation on the resistance value of the resistor.

[0063] In the embodiment of the present application, the multi-stage second capacitors are also respectively connected in series with multiple second resistors, which can be used to consume the voltage on the second capacitors, suppress the oscillation of the test circuit, and ensure the accuracy of the test results of the RF amplifier chip to be tested.

[0064] Based on the above embodiments, the present application also provides a sixth test circuit, Figure 6 A schematic diagram of the structure of a sixth test circuit provided in an embodiment of the present application is shown in FIG. Figure 6 As shown in the above Figure 1 On the basis of, the pulse control circuit includes: a first switch tube M1 and a second switch tube M2; in this application, the first switch tube M1 is described by taking a P-type field effect tube as an example, and the second switch tube is described by taking an N-type field effect tube as an example.

[0065] Among them, the source S of the first switch tube M1 is the power supply terminal V of the pulse control circuit 100, which is used to connect the preset DC power supply DC, the drain D of the first switch tube M1 is the output terminal OUT of the pulse control circuit 100, and the third resistor R3 is connected in series between the source S and the gate G of the first switch tube M1. The gate G of the first switch tube M1 is connected to the drain D of the second switch tube M2, the source S of the second switch tube M2 is grounded, and the gate G of the second switch tube M2 is the input terminal IN1 of the pulse control circuit 100, which is used to connect the preset pulse control terminal (not shown in the figure).

[0066] Optionally, when the pulse test signal TTL received by the gate G of the second switch tube M2 is at a high level, the drain D and source S of the second switch tube M2 are turned on, the second switch tube M2 receives the signal, the drain D and source S of the second switch tube M2 are turned on, and the preset DC power supply DC is connected to the DC bias circuit 200 through the second switch tube M2, and the DC bias circuit 200 supplies power to the RF amplifier chip to be tested. A third resistor R3 is connected in series between the source S and the gate G of the first switch tube M1, and the third resistor R3 is used to limit the current between the source S and the gate G of the first switch tube M1, thereby protecting the first switch tube M1 and the second switch tube M2.

[0067] In the application embodiment, the pulse control circuit includes: a first switch tube and a second switch tube; wherein the source of the first switch tube is the power supply end of the pulse control circuit, which is used to connect to a preset DC power supply, the drain of the first switch tube is the output end of the pulse control circuit, a third resistor is connected in series between the source and the gate of the first switch tube, the gate of the first switch tube is connected to the drain of the second switch tube, the source of the second switch tube is grounded, and the gate of the second switch tube is the input end of the pulse control circuit, which is used to connect to the preset pulse control end. The first switch tube and the second switch tube in the present application can accurately control the start and end of the test circuit to avoid inaccurate results caused by overheating of the RF amplifier chip to be tested due to long-term power-on. Improve the accuracy of the test results of the RF amplifier chip to be tested.

[0068] Another embodiment of the present application further provides a testing device, Figure 7 A schematic diagram of a test device provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the test device includes: a base 701 and two test circuit boards 702 , each of which is provided with any of the above-mentioned test circuits 1000 and a radio frequency microstrip line 2000 .

[0069] The two parts of the base 701 are respectively connected to the RF microstrip lines on the two test circuit boards 702. The RF microstrip lines 2000 on the two test circuit boards 702 are respectively used to connect the RF input terminal RFin and the RF output terminal RFout of the RF amplifier chip 3000 to be tested. The power supply terminal V of the pulse control circuit 100 in the test circuit 1000 on the two test circuit boards 702 is respectively used to connect two preset DC power supplies DC. The output terminal OUT2 of the DC bias circuit 200 in the test circuit 1000 on the two test circuit boards 702 is respectively used to connect the gate power supply terminal VGG and the drain power supply terminal VDD of the RF amplifier chip 3000 to be tested.

[0070] Optionally, the RF input terminal RFin can be connected to the RF microstrip line 2000, and the output terminal OUT2 of the DC bias circuit 200 can be connected to the gate power supply terminal VGG of the RF amplifier chip 3000 to be tested alone. Alternatively, the RF input terminal RFin can be connected to the RF microstrip line 2000 and the output terminal OUT2 of the DC bias circuit 200, that is, the RF input terminal RFin and the gate power supply terminal VGG of the RF amplifier chip 3000 to be tested are the same port. This allows the output terminal OUT2 of the DC bias circuit 200 to be directly connected to the microstrip line, and the characteristics of the microstrip line are not affected.

[0071] Optionally, the RF output terminal RFout can be connected to the RF microstrip line 2000, and the output terminal OUT2 of the DC bias circuit 200 is separately connected to the drain power supply terminal VDD of the RF amplifier chip 3000 to be tested. Alternatively, the RF output terminal RFout can be connected to the RF microstrip line 2000 and the output terminal OUT2 of the DC bias circuit 200, that is, the RF output terminal RFout of the RF amplifier chip 3000 to be tested and the drain power supply terminal VDD are the same port.

[0072] For example, Figure 8 A schematic diagram of the test results of a radio frequency amplifier chip to be tested provided in this application, such as Figure 8 As shown, the horizontal axis is the frequency Fre, in gigahertz GHz, and the vertical axis is decibel db, corresponding to the decibel value at different frequencies. The dotted line is the loss characteristic of the test circuit, and the solid line is the echo characteristic of the test circuit. The lower the echo characteristic, the better the isolation between the RF microstrip line of the test machine circuit and the test circuit.

[0073] The test device of the present application includes a base and two test circuit boards, each of which is provided with a test circuit and a radio frequency microstrip line; the two parts of the base are respectively connected to the radio frequency microstrip lines on the two test circuit boards, the radio frequency microstrip lines on the two test circuit boards are respectively used to connect the radio frequency input terminal and the radio frequency output terminal of the radio frequency amplifier chip to be tested, the power supply terminal of the pulse control circuit in the test circuit on the two test circuit boards is respectively used to connect two preset DC power supplies, and the output terminal of the DC bias circuit in the test circuit on the two test circuit boards is respectively used to connect the gate power supply terminal and the drain power supply terminal of the radio frequency amplifier chip to be tested. The test device in the present application optimizes the DC bias circuit and the pulse control circuit, so that the radio frequency path echo characteristics of the radio frequency microstrip line are better than 10dB, and the DC isolation is greater than 20dB, thereby improving the accuracy of the radio frequency amplifier chip to be tested.

[0074] Based on the above embodiment, the present application also provides a second testing device, Fig. 9 A schematic diagram of the structure of a second testing device provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the first part 7011 of the two parts of the base 701 is provided with a groove part, and the second part 7012 of the two parts of the base 701 is provided with a protrusion matching with the groove part at a corresponding position, and the groove part and the protrusion are butt-jointed and slidably connected.

[0075] In the embodiment of the present application, the first part of the two parts of the base is provided with a groove part, and the second part of the two parts of the base is provided with a protrusion matching with the groove part at a corresponding position, and the groove part and the protrusion are butt-jointed and slidably connected. The RF amplifier chip to be tested can be tightly fixed on the base to prevent the RF amplifier chip to be tested from slipping during the test.

[0076] Based on the above embodiments, the present application also provides a third testing device: Fig.10 A schematic diagram of the structure of a third test device provided in an embodiment of the present application is shown in FIG. Fig.10 As shown, an adjustable knob 703 is provided on the groove portion at a position perpendicular to the preset sliding direction to lock the sliding position of the groove portion.

[0077] In the embodiment of the present application, by setting an adjustable knob, the test device can be applied to the RF amplifier chip to be tested of any size, which improves the compatibility of the test device and makes the test device widely used in the test of RF amplifier chips.

[0078] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A test circuit, characterized in that: The test circuit includes: a pulse control circuit and a DC bias circuit; wherein the DC bias circuit includes: a multi-stage inductor connected in series, one end of the first stage inductor in the multi-stage inductor is the output end of the DC bias circuit, and the other end of the last stage inductor in the multi-stage inductor is the input end of the DC bias circuit; The power supply end of the pulse control circuit is used to connect to a preset DC power supply, the input end of the pulse control circuit is used to connect to a preset pulse control end to receive a pulse test signal, the output end of the pulse control circuit is connected to the input end of the DC bias circuit, and the output end of the DC bias circuit is used to connect to a preset power supply end of the RF amplifier chip to be tested; The first-stage inductor is a high-frequency conical inductor, and the inductance values ​​of each stage of the multi-stage inductor from the second-stage inductor to the last-stage inductor increase sequentially.

2. The test circuit according to claim 1, characterized in that: The DC bias circuit further includes: a plurality of first resistors; Each of the inductors from the second inductor to the last inductor in the multi-stage inductor is connected in parallel with a first resistor.

3. The test circuit according to claim 1, characterized in that: The DC bias circuit further includes: a first capacitor and a multi-stage second capacitor; The other end of the first-stage inductor is connected to the ground in parallel through the first capacitor, and the other ends of the inductors from the second-stage inductor to the last-stage inductor in the multi-stage inductor are connected to the ground in parallel through the multi-stage second capacitors in sequence.

4. The test circuit according to claim 3, characterized in that: The other ends of the inductors of each stage are connected to the ground in parallel through the second capacitors of the multiple stages with increasing capacitance values ​​in sequence; The capacitance values ​​of the multi-stage second capacitors are all greater than the capacitance value of the first capacitor.

5. The test circuit according to claim 4, characterized in that: The multi-stage second capacitors are also respectively connected in series with a plurality of second resistors.

6. The test circuit according to claim 1, characterized in that: The pulse control circuit comprises: a first switch tube and a second switch tube; Among them, the source of the first switch tube is the power supply end of the pulse control circuit, which is used to connect the preset DC power supply, the drain of the first switch tube is the output end of the pulse control circuit, a third resistor is connected in series between the source and the gate of the first switch tube, the gate of the first switch tube is connected to the drain of the second switch tube, the source of the second switch tube is grounded, and the gate of the second switch tube is the input end of the pulse control circuit, which is used to connect the preset pulse control end.

7. A testing device, characterized in that: The test device comprises: a base and two test circuit boards, each of which is provided with a test circuit as described in any one of claims 1 to 6, and a radio frequency microstrip line; The two parts of the base are respectively connected to the RF microstrip lines on the two test circuit boards, the RF microstrip lines on the two test circuit boards are respectively used to connect the RF input terminal and the RF output terminal of the RF amplifier chip to be tested, the power supply terminal of the pulse control circuit in the test circuit on the two test circuit boards is respectively used to connect two preset DC power supplies, and the output terminal of the DC bias circuit in the test circuit on the two test circuit boards is respectively used to connect the gate power supply terminal and the drain power supply terminal of the RF amplifier chip to be tested.

8. The testing device according to claim 7, characterized in that: The first part of the two parts of the base is provided with a groove part, and the second part of the two parts of the base is provided with a protrusion matching with the groove part at a corresponding position, and the groove part and the protrusion are butt-jointed and slidably connected.

9. The testing device according to claim 8, characterized in that: An adjustable knob is provided on the groove portion at a position perpendicular to the preset sliding direction to lock the sliding position of the groove portion.

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