Storage system

Abstract

The invention provides a storage system which improves the error correction capability of data of the storage system. A memory system according to an embodiment includes a semiconductor memory including a plurality of first memory cells each configured to store data in a non-volatile manner in accordance with a threshold voltage, and a controller configured to generate a first soft bit voltage based on first hard bit data and first soft bit data acquired using a plurality of first soft bit voltages. A first error correction is performed on the plurality of first memory cells, and when a first condition based on correction data corrected by the first error correction is satisfied, a second shift voltage different from the first shift voltage is determined based on the first shift voltage which is a potential difference related to the plurality of first soft bit voltages.

Description

[0001] This application claims the priority of Japanese Patent Application No. 2023-100906 (filing date: June 20, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0002] Embodiments relate to storage systems. Background Art

[0003] A storage system including a storage device capable of storing data in a nonvolatile manner and a controller for controlling the storage device is known. The storage system corrects data errors when reading data, for example. Summary of the invention

[0004] Improve the data error correction capability of the storage system.

[0005] A storage system according to an embodiment includes a semiconductor memory and a controller, wherein the semiconductor memory includes a plurality of first storage cells each configured to store data in a nonvolatile manner based on a threshold voltage, wherein the controller is configured to perform a first error correction on the plurality of first storage cells based on first hard bit data and first soft bit data obtained using a plurality of first soft bit voltages, and determine a second shift voltage different from the first shift voltage based on a first shift voltage that is a potential difference associated with the plurality of first soft bit voltages when a first condition based on corrected data corrected by the first error correction is satisfied. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a block diagram showing an example of the configuration of an information processing system including a storage system and a host device according to an embodiment.

[0007] Figure 2 This is a block diagram showing an example of the structure of a NAND memory involved in the embodiment.

[0008] Figure 3 This is a circuit diagram for explaining an example of the configuration of a block included in a memory cell array of a NAND memory according to an embodiment.

[0009] Figure 4 A diagram for explaining the distribution of threshold voltages of memory cell transistors included in the NAND memory according to the embodiment.

[0010] Figure 5 This is a diagram for explaining an example of the configuration of an ECC circuit included in the storage system according to the embodiment.

[0011] Figure 6This is a block diagram for explaining an example of the structure of data stored in the built-in memory included in the storage system according to the embodiment.

[0012] Figure 7 This is a flowchart for explaining the overall flow of a read operation using the storage system according to the embodiment.

[0013] Figure 8 It is a diagram for explaining changes in threshold voltage distribution of memory cell transistors included in the NAND memory according to the embodiment.

[0014] Fig. 9 This is a diagram for explaining an example of soft bit reading in the storage system according to the embodiment.

[0015] Fig.10 This is a flowchart for explaining the flow of correction processing based on soft bit data in the storage system according to the embodiment.

[0016] Fig.11 This is a diagram for explaining a log-likelihood ratio table used for error correction in a storage system according to an embodiment.

[0017] Fig.12 This is a diagram for explaining generation of a channel matrix executed in the storage system according to the embodiment.

[0018] Fig.13 This is a diagram for explaining calculation of a shift voltage in soft bit reading executed in the storage system according to the embodiment.

[0019] Fig.14 FIG. 1 is a diagram for explaining soft bit reading using a calculated shift voltage executed in the memory system according to the embodiment.

[0020] Fig.15 This is a flowchart for explaining the flow of correction processing based on soft bit data in the storage system according to the third modification.

[0021] Description of Reference Numerals

[0022] 1…storage system, 2…host device, 10…controller, 11…processor, 12…built-in memory, 13…buffer memory, 14…host I / F, 15…NAND I / F, 16…ECC circuit, 20…storage device, 21…storage cell array, 22…input / output circuit, 23…logic control circuit, 24…register, 25…sequencer, 26…voltage generating circuit, 27…row decoder module, 28…readout amplifier module, 121…LLR table, 122…channel matrix, 123…shift voltage table, 161…encoding circuit, 162…decoding circuit, 162a…hard decision decoding circuit, 162b…soft decision decoding circuit, 163…channel matrix generating circuit, 164…shift voltage calculating circuit. DETAILED DESCRIPTION

[0023] The following describes the embodiments with reference to the accompanying drawings. In addition, in the following description, the same reference numerals are used to mark the components having substantially the same function and configuration. In the case of specially distinguishing the components having the same configuration from each other, sometimes different characters or numbers are added to the end of the same reference numeral.

[0024] 1. Implementation Method

[0025] 1.1 Composition

[0026] 1.1.1 Storage System

[0027] use Figure 1 A configuration example of a storage system is described. Figure 1 This is a block diagram showing an example of the configuration of an information processing system including a storage system and a host device according to an embodiment.

[0028] The storage system 1 includes a controller 10 and a storage device 20 .

[0029] The storage system 1 is, for example, an SSD (solid state drive), an SD TM The storage system 1 communicates with, for example, an external host device 2. The storage system 1 stores data from the host device 2. In addition, the storage system 1 reads data to the host device 2.

[0030] The controller 10 is composed of an integrated circuit such as a SoC (system-on-a-chip). The controller 10 receives a command from the host device 2. The functions of each part of the controller 10 can be implemented by dedicated hardware, a processor that executes a program (firmware), or a combination thereof. The controller 10 controls the storage device 20 based on the received command. Specifically, the controller 10 writes the data commanded to be written to the storage device 20 based on the write command received from the host device 2. In addition, the controller 10 reads the data commanded to be read by the host device 2 from the storage device 20 based on the read command received from the host device 2 and sends it to the host device 2.

[0031] The storage device 20 is, for example, a semiconductor memory. In addition, the storage device 20 is, for example, a NAND flash memory. Hereinafter, the storage device 20 is referred to as a NAND memory 20. The NAND memory 20 includes a plurality of memory cell transistors. The NAND memory 20 stores data in a nonvolatile manner. The NAND memory 20 is connected to the controller 10 via a NAND bus.

[0032] The NAND bus transmits and receives various signals that comply with the NAND interface via separate signal lines. The various signals include, for example, IO<7:0>, / CE, CLE, ALE, / WE, / RE, and / RB. Signal / CE is a chip enable signal. Signal / CE is a signal for enabling the NAND memory 20. Signal CLE is a command latch enable signal. Signal CLE notifies the NAND memory 20 that the signal IO<7:0> sent to the NAND memory 20 is a command while signal CLE is at an "H (High)" level. Signal ALE is an address latch enable signal. Signal ALE notifies the NAND memory 20 that the signal IO<7:0> sent to the NAND memory 20 is an address while signal ALE is at an "H" level. Signal / WE is a write enable signal. Signal / WE indicates that the signal IO<7:0> is taken into the NAND memory 20. Signal / RE is a read enable signal. Signal / RE indicates outputting signal IO<7:0> to NAND memory 20. Signal / RB is a ready / busy signal. Signal / RB indicates whether NAND memory 20 is in a ready state (a state of receiving commands from the outside) or a busy state (a state of not receiving commands from the outside).

[0033] The signal IO<7:0> is, for example, an 8-bit wide signal. The signal IO<7:0> is transmitted and received between the controller 10 and the NAND memory 20. The signal IO<7:0> includes an address, a command, and data. The command is a signal for controlling the entire NAND memory 20. The data includes read data and write data.

[0034] 1.1.2 Controller

[0035] The controller 10 includes a processor (CPU: Central Processing Unit) 11, a built-in memory 12, a buffer memory 13, a host I / F (host interface circuit) 14, a NAND I / F (NAND interface circuit) 15, and an ECC (Error Checking and Correcting) circuit 16.

[0036] The processor 11 controls the overall operation of the controller 10. For example, the processor 11 issues a command for instructing the NAND memory 20 to execute various operations including a write operation, a read operation, and an erase operation.

[0037] The built-in memory 12 is a semiconductor memory such as SRAM (Static Random Access Memory) and is used as a work area of ​​the processor 11. The built-in memory 12 stores firmware for managing the NAND memory 20 and various management tables including a plurality of compressed data tables.

[0038] The buffer memory 13 is, for example, a semiconductor memory such as a DRAM (Dynamic Random Access Memory). The buffer memory 13 temporarily stores write data received from the host device 2 and read data received by the controller 10 from the NAND memory 20. In addition, the buffer memory 13 may also be provided outside the controller 10.

[0039] The host interface circuit 14 is connected to the host device 2 via a host bus. The host bus is, for example, a bus compliant with PCI Express (PCIEXPRESS TM (Peripheral component interconnect express)), UFS (Universal FlashStorage), SD TMInterface, SAS (Serial attached SCSI (small computer system interface)), SATA (Serial ATA (advanced technology attachment)), or NVMe (NVM EXPRESS TM The host interface circuit 14 is responsible for the communication between the controller 10 and the host device 2. The host interface circuit 14 transmits the command and data received from the host device 2 to the processor 11 and the buffer memory 13, respectively.

[0040] The NAND interface circuit 15 is connected to the NAND memory 20 via a NAND bus. The NAND bus is, for example, a bus that complies with ToggleNAND (Toggle DDR) and ONFI (Open NAND Flash Interface). The NAND interface circuit 15 is responsible for communicating with the NAND memory 20. The NAND interface circuit 15 sends commands, addresses, and write data to the NAND memory 20 according to the instructions of the processor 11. In addition, the NAND interface circuit 15 receives read data from the NAND memory 20.

[0041] The ECC circuit 16 performs error detection and error correction related to the data stored in the NAND memory 20. More specifically, the ECC circuit 16 generates an error correction code when writing data. In addition, the ECC circuit 16 assigns an error correction code (parity check bit) to the written data. Then, the ECC circuit 16 uses the error correction code to perform error correction when reading data. Error correction includes hard decision decoding (hard bit correction) and soft decision decoding (soft bit correction). In addition, in the following description and drawings, hard bits are also simply referred to as HB, and soft bits are also simply referred to as SB. The success probability of error correction by soft bit correction can be higher than the success probability of error correction by hard bit correction. In hard bit correction, for example, hard decision decoding codes such as BCH (Bose-Chaudhuri-Hocquenghem) codes and RS (Reed-Solomon) codes are used as error correction codes. In soft bit correction, for example, soft decision decoding codes such as LDPC (Low-Density Parity-Check) codes are used as error correction codes. In the following description, error correction is also referred to as decoding.

[0042] 1.1.3 Composition of NAND Memory

[0043] Next, use Figure 2 A configuration example of the NAND memory 20 according to the embodiment will be described. Figure 2This is a block diagram showing an example of the structure of a NAND memory involved in the embodiment.

[0044] The NAND memory 20 includes a memory cell array 21 , an input / output circuit 22 , a logic control circuit 23 , a register 24 , a sequencer 25 , a voltage generating circuit 26 , a row decoder block 27 , and a sense amplifier block 28 .

[0045] The memory cell array 21 includes a plurality of blocks BLK0, BLK1, ..., and BLK(k-1) (k is an integer greater than or equal to 2). Hereinafter, the plurality of blocks BLK0, BLK1, ..., and BLK(k-1) are also simply referred to as blocks BLK. Each block BLK is a collection of a plurality of memory cell transistors capable of storing data in a non-volatile manner, and is used, for example, as a unit of erasing data. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 21. For example, one memory cell transistor is associated with one bit line and one word line.

[0046] The input / output circuit 22 transmits and receives the signal IO<7:0> to the controller 10. The input / output circuit 22 transmits the command and address in the signal IO<7:0> to the register 24. The input / output circuit 22 transmits and receives write data and read data to the sense amplifier module 28.

[0047] The logic control circuit 23 receives the signals / CE, CLE, ALE, / WE, and / RE from the controller 10 . In addition, the logic control circuit 23 transmits the signal / RB to the controller 10 .

[0048] The register 24 holds commands and addresses and transmits addresses to the row decoder module 27 and the sense amplifier module 28 , and transmits commands to the sequencer 25 .

[0049] The sequencer 25 receives a command and controls the entire NAND memory 20 according to a sequence based on the received command.

[0050] The voltage generation circuit 26 generates voltages required for operations such as writing, reading, and erasing data based on instructions from the sequencer 25 . The voltage generation circuit 26 supplies the generated voltages to the memory cell array 21 , the row decoder block 27 , and the sense amplifier block 28 .

[0051] The row decoder module 27 receives the row address of the addresses from the register 24 and selects the block BLK based on the row address. Then, the voltage from the voltage generating circuit 26 is transmitted to the selected block BLK via the row decoder module 27 .

[0052] When reading data, the sense amplifier module 28 reads the read data read from the memory cell transistor to the bit line, and transmits the read data to the input / output circuit 22. When writing data, the sense amplifier module 28 transmits the write data written via the bit line to the memory cell transistor. In addition, the sense amplifier module 28 receives the column address of the address from the register 24, and outputs the data of the column based on the column address.

[0053] 1.1.4 Composition of Memory Cell Array

[0054] Next, use Figure 3 The configuration of each block BLK included in the memory cell array 21 of the NAND memory 20 according to the embodiment will be described. Figure 3 This is a circuit diagram for explaining an example of the configuration of a block included in a memory cell array of a NAND memory according to an embodiment.

[0055] The block BLK includes, for example, four string units SU0, SU1, SU2, and SU3. Hereinafter, the four string units SU0, SU1, SU2, and SU3 are also simply referred to as string units SU. Each string unit SU includes a plurality of NAND strings NS. In addition, the number of string units SU is not limited.

[0056] Each NAND string NS includes, for example, 8 memory cell transistors MT (MT0 to MT7), and selection transistors ST1 and ST2. In addition, the number of memory cell transistors MT of each NAND string NS is not limited. Each memory cell transistor MT includes a stacked gate including a control gate and a charge accumulation layer. Each memory cell transistor MT is connected in series between the selection transistors ST1 and ST2. In addition, in the following description, connection also includes a case where there is a conductive element different from the two structures between the two structures.

[0057] In each block BLK, the gates of the selection transistors ST1 of the string units SU0 to SU3 are connected to the selection gate lines SGD0 to SGD3, respectively. In addition, the gates of the selection transistors ST2 of all the string units SU in the block BLK are commonly connected to the selection gate line SGS. The control gates of the memory cell transistors MT0 to MT7 in the same block BLK are connected to the word lines WL0 to WL7, respectively. That is, the word lines WL of the same address are commonly connected to all the string units SU in the same block BLK, and the selection gate line SGS is commonly connected to all the string units SU in the same block BLK. In addition, the selection gate line SGD is connected to only one of the string units SU in the same block BLK.

[0058] In addition, the other end of the selection transistor ST1 of the NAND string NS located in the same row among the NAND strings NS arranged in a matrix in the memory cell array 21 is connected to any one of the m bit lines BL0 to BL(m-1) (m is an integer greater than 2). Hereinafter, the m bit lines BL0 to BL(m-1) are also simply referred to as bit lines BL. In addition, the bit lines BL are commonly connected to the NAND strings NS in the same column in a plurality of blocks BLK.

[0059] In addition, the other end of the selection transistor ST2 is connected to a source line SL. The source line SL is commonly connected to a plurality of NAND strings NS in a plurality of blocks BLK.

[0060] As described above, data erasure is performed on, for example, storage cell transistors MT located in the same block BLK. In contrast, data reading and writing can be performed on a plurality of storage cell transistors MT commonly connected to any word line WL in any string unit SU of any block BLK. Such a group of storage cell transistors MT that share a word line WL in one string unit SU is, for example, referred to as a cell unit CU. That is, a cell unit CU is a group of storage cell transistors MT that perform write operations or read operations together. A cell unit CU is, for example, equivalent to a group of one or more storage areas. A write operation or a read operation performed on a cell unit CU is performed on a group of the storage area. Such a unit of storage area is referred to as a page. Hereinafter, various data including a data length of one page will be referred to as page data.

[0061] 1.1.5 Threshold Distribution of Memory Cell Transistors

[0062] use Figure 4 The threshold voltage distribution of the memory cell transistors MT included in the NAND memory 20 according to the embodiment will be described. Figure 4 This is a diagram for explaining an example of the threshold voltage distribution of the memory cell transistor included in the NAND memory according to the embodiment. Figure 4 An example of threshold voltage distribution of the memory cell transistors MT in the NAND memory 20 according to the embodiment is shown. Figure 4 The vertical axis of the threshold voltage distribution shown corresponds to the number of memory cell transistors MT, and the horizontal axis corresponds to the threshold voltage of the memory cell transistor MT. Figure 4 In the following description, the number and threshold voltage of the memory cell transistors MT are also referred to as NMTs and Vth, respectively.

[0063] like Figure 4As shown, in the threshold voltage distribution of the memory cell transistor MT of the NAND memory 20 involved in the embodiment, for example, two states are formed according to the threshold voltages of the plurality of memory cell transistors MT. Hereinafter, the two states are referred to as the "Er" state and the "A" state in the order of the threshold voltage from low to high.

[0064] The “Er” state corresponds to, for example, a data erase state. The threshold voltage of the memory cell transistor MT included in the “Er” state is, for example, lower than the voltage AR(0).

[0065] The “A” state corresponds to a state in which charges are injected into the charge storage layer of the memory cell transistor MT. The threshold voltage of the memory cell transistor MT included in the “A” state is, for example, equal to or higher than the voltage AR(0).

[0066] When a voltage is applied to the control gate, the memory cell transistor MT is turned on when the memory cell transistor MT has a threshold voltage lower than the applied voltage. When a voltage is applied to the control gate, the memory cell transistor MT is turned off when the memory cell transistor MT has a threshold voltage higher than the applied voltage.

[0067] Different 1-bit data are assigned to the "Er" state and the "A" state. For example, "1" data is assigned to the "Er" state. For example, "0" data is assigned to the "A" state.

[0068] When such data allocation is applied, one page of data consisting of data ("1" data and "0" data) held by the memory cell transistor MT is determined by, for example, a data read process using the voltage AR(0). Hereinafter, a process of obtaining a result of determining which of the two allocated data is obtained based on one read voltage set for two adjacent states is referred to as hard bit read. In addition, the one read voltage is referred to as a hard bit voltage. In addition, page data obtained by hard bit read for a certain page in the block BLK is referred to as hard bit data. In addition, each bit of the hard bit data is referred to as a hard bit (hard decision value).

[0069] 1.1.6 ECC Circuit

[0070] use Figure 5 The configuration of the ECC circuit 16 included in the controller 10 according to the embodiment will be described. Figure 5 This is a diagram for explaining an example of the configuration of an ECC circuit included in the storage system according to the embodiment.

[0071] The ECC circuit 16 includes an encoding circuit 161 , a decoding circuit 162 , a channel matrix generating circuit 163 , and a shift voltage calculating circuit 164 .

[0072] The encoding circuit 161 is a circuit that performs encoding processing. The encoding circuit 161 generates an error correction code during the encoding processing. In addition, the encoding circuit 161 adds an error correction code to write data during the encoding processing.

[0073] The decoding circuit 162 includes a hard decision decoding circuit 162a and a soft decision decoding circuit 162b.

[0074] The hard decision decoding circuit 162a is a circuit that performs hard bit correction. The hard decision decoding circuit 162a uses hard decision decoding code to perform error correction. More specifically, the hard decision decoding circuit 162a detects an error in the data read using the hard decision decoding code for hard bit data. When an error is detected, the hard decision decoding circuit 162a corrects the error in the read data.

[0075] The soft decision decoding circuit 162b is a circuit for performing soft bit correction. The soft decision decoding circuit 162b uses a log-likelihood ratio (LLR) table and soft decision decoding code to perform error correction. The LLR table will be described later, but the LLR table is a table related to the likelihood of data read from the memory cell transistor MT. In the soft bit correction, the soft decision decoding circuit 162b repeatedly calculates the hard bit data and the soft bit data using the LLR table and the soft decision decoding code in units of ECC frames. The soft bit data is page data obtained by soft bit reading for a certain page in the block BLK. The soft bit reading will be described later, but the soft bit reading is a process of calculating the soft bit by reading data using a plurality of read voltages (soft bit voltages) set with the hard bit voltage as a reference. The soft bit is each bit included in the soft bit data. In addition, the ECC frame is, for example, a unit of data for which the soft decision decoding is performed by the soft decision decoding circuit 162b. The hard bit data and the soft bit data may include more than one ECC frame. The soft decision decoding circuit 162b corrects errors in the read data based on the result of repeated calculation.

[0076] The channel matrix generation circuit 163 is a circuit that generates a channel matrix using hard bit data and soft bit data. The channel matrix is ​​a matrix related to the expected value of the number of memory cell transistors MT having "0" data and the expected value of the number of memory cell transistors MT having "1" data. Details of the channel matrix will be described later. The channel matrix generation circuit 163 generates a channel matrix for each ECC frame, for example.

[0077] The shift voltage calculation circuit 164 is a circuit for determining a plurality of soft bit voltages. The shift voltage calculation circuit 164, for example, calculates a shift voltage dRu related to a difference between the plurality of soft bit voltages. The calculated shift voltage dRu is, for example, stored in the built-in memory 12. The shift voltage calculation circuit 164, for example, updates the stored shift voltage dRu each time the shift voltage dRu is calculated. The shift voltage dRu will be described later. In addition, the shift voltage calculation circuit 164 may also be included in a configuration different from the ECC circuit 16 in the controller 10.

[0078] 1.1.7 Composition of data stored in built-in memory

[0079] use Figure 6 The structure of data stored in the built-in memory 12 will be described. Figure 6 This is a block diagram for explaining an example of the structure of data stored in the built-in memory included in the storage system according to the embodiment.

[0080] The built-in memory 12 includes, for example, an LLR table 121 , a channel matrix 122 , and a shift voltage table 123 .

[0081] The LLR table 121 includes a log likelihood ratio (LLR value). The LLR value is information that expresses the likelihood of a bit stored in the memory cell transistor MT being "0" and the likelihood of being "1" in the form of a logarithmic ratio. The LLR value is information related to the likelihood of data read by a certain read voltage. In the threshold voltage distribution of the memory cell transistor MT, an LLR value is allocated to each threshold voltage range divided into a plurality of threshold voltage ranges. In addition, in the description of the operation described later, an example of the LLR table 121 in the embodiment is shown.

[0082] In addition, the built-in memory 12 may include a plurality of LLR tables 121. The plurality of LLR tables are set in consideration of changes in the threshold voltage of the memory cell transistor MT caused by various influences. One of the plurality of LLR tables used for soft bit correction may be selected by the ECC circuit 16.

[0083] The channel matrix 122 holds the expected value of the number of memory cell transistors MT having "0" data and the expected value of the number of memory cell transistors MT having "1" data for each range of the plurality of threshold voltages in the LLR table 121. In addition, in the description of the operation to be described later, an example of the channel matrix 122 in the embodiment is shown.

[0084] The shift voltage table 123 holds, for example, the calculated shift voltage dRu and the shift voltage dRdef. The shift voltage dRdef is used as an initial value when determining a plurality of soft bit voltages for soft bit reading. The shift voltage dRdef can be set to a fixed value, for example. In the following description, when the shift voltage dRu and dRdef are not distinguished, the shift voltage dRu and dRdef are also simply referred to as the shift voltage dR.

[0085] 1.2 Action

[0086] Hereinafter, a reading operation using the storage system 1 according to the embodiment will be described.

[0087] 1.2.1 Overall Action

[0088] First, use Figure 7 The overall flow of a read operation using the storage system 1 according to the embodiment will be described. Figure 7 This is a flowchart for explaining the overall flow of a read operation using the storage system according to the embodiment. Hereinafter, a process related to read data of a certain page in the block BLK will be explained.

[0089] In S1, the controller 10 applies a hard bit voltage to the selected word line WL when starting the read operation. Then, a hard bit read is performed to obtain hard bit data corresponding to one page in the selected block BLK. The hard bit voltage is set to, for example, a default read voltage AR(0) or a voltage shifted from the read voltage AR(0). The read hard bit data is stored in the buffer memory 13. Then, the process enters S2. In addition, the hard bit read in S1 of the embodiment is referred to as the first hard bit read. In addition, the hard bit data read by the first hard bit read is referred to as the first hard bit data.

[0090] In S2, the hard decision decoding circuit 162a performs hard bit correction for each ECC frame using, for example, the first hard bit data. Then, the process proceeds to S3.

[0091] In S3, the controller 10 determines whether the hard bit correction of all ECC frames included in the first hard bit data is successful. If the hard bit correction of all ECC frames included in the first hard bit data is successful (S3: Yes), the reading operation is terminated. If the first hard bit data includes an ECC frame in which the hard bit correction fails (S3: No), the process proceeds to S4.

[0092] The process of S3 is supplemented. After the write operation, the threshold voltage distribution is, for example, Figure 4As shown, the "Er" state and the "A" state diverge from each other. With such a threshold voltage distribution, for example, correct page data can be read by performing the first hard bit read and hard bit correction using the default read voltage AR(0).

[0093] However, if Figure 8 As shown, since the memory cell transistor MT is affected by various factors, two adjacent states may overlap in the threshold voltage distribution. Figure 8 It is a diagram for explaining changes in threshold voltage distribution of memory cell transistors included in the NAND memory according to the embodiment.

[0094] In this case, the controller 10 may not be able to determine the state of a certain memory cell transistor MT during writing by the first hard bit read using the read voltage AR(0). Such a bit that cannot be determined is called a fail bit. More specifically, for example, Figure 8 In the threshold voltage distribution shown in FIG. 1 , when the first hard bit read is performed using the read voltage AR(0), as shown in FIG. Figure 8 As shown in the shaded portion in , the memory cell transistors MT with a threshold voltage greater than the read voltage AR(0) among the memory cell transistors MT included in the "Er" state and the memory cell transistors MT with a threshold voltage less than the read voltage AR(0) among the memory cell transistors MT included in the "A" state become memory cell transistors MT whose states during writing cannot be determined. When the number of failed bits exceeds the number of correctable errors of hard bit correction, the hard bit correction of the controller 10 fails.

[0095] Back to Figure 7 If the hard bit correction fails (S3: No), in S4, the controller 10 performs, for example, threshold voltage tracking. Thus, the controller 10 calculates, for example, Figure 8 The read voltage (tracking voltage) ARt at which the number of failed bits decreases as shown by the arrow in FIG. That is, the tracking voltage is, for example, a read voltage that becomes a threshold voltage near the intersection of the “Er” state and the “A” state.

[0096] In S5, for example, the controller 10 determines whether the shift voltage calculation circuit 164 holds the shift voltage dRu. If the shift voltage calculation circuit 164 holds the shift voltage dRu (S5: Yes), the process proceeds to S7. If the shift voltage calculation circuit 164 does not hold the shift voltage dRu (S5: No), the process proceeds to S6. The details of the shift voltage dR will be described later.

[0097] In S6, the controller 10 sets the shift voltage dR to the shift voltage dRdef held as an initial value. Then, the process proceeds to S8.

[0098] In S7, the controller 10 sets the shift voltage dR to the held calculated shift voltage dRu. Then, the process proceeds to S8.

[0099] In S8, first, the controller 10 performs a hard bit read using the tracking voltage Art. In addition, the hard bit read using the tracking voltage Art is referred to as a second hard bit read. In addition, the hard bit data read by the second hard bit read is referred to as second hard bit data. Then, the controller 10 performs a soft bit read using a plurality of soft bit voltages based on the tracking voltage ARt and the set shift voltage dR. Thus, the controller 10 obtains the soft bit data. Then, the process enters S9. In addition, the details of the soft bit read will be described later.

[0100] In S9, the controller 10 executes correction processing based on the soft bit data. The correction processing based on the soft bit data includes soft bit correction. The correction processing based on the soft bit data will be described later.

[0101] As described above, the reading operation using the storage system 1 according to the embodiment is completed.

[0102] 1.2.2 Soft Bit Reading

[0103] use Fig. 9 Soft bit reading is described. Fig. 9 This is a diagram for explaining an example of soft bit reading in the storage system according to the embodiment.

[0104] The soft bit read includes, for example, a data read process using a plurality of soft bit voltages set based on the shift voltage dR with the tracking voltage Art as a reference. The shift voltage dR includes shift voltages dR1 and dR2. Fig. 9 , the soft bit voltages are voltages ARt(-3), ARt(-2), ARt(-1), ARt(+1), ARt(+2), and ARt(+3). Voltage ARt(-3) is lower than voltage ARt(-2) by a shift voltage dR1. Voltage ARt(-2) is lower than voltage ARt(-1) by a shift voltage dR1. Voltage ARt(-1) is lower than tracking voltage Art by a shift voltage dR1. Voltage ARt(+1) is higher than tracking voltage Art by a shift voltage dR2. Voltage ARt(+2) is higher than voltage ARt(+1) by a shift voltage dR2. Voltage ARt(+3) is higher than voltage ARt(+2) by a shift voltage dR2. Shift voltages dR1 and dR2 may be different from each other or the same.

[0105] The shift voltage dRdef in the initial state includes a shift voltage dRdef1 used as a shift voltage dR1 and a shift voltage dRdef2 used as a shift voltage dR2. The shift voltages dRdef1 and dRdef2 may be different from each other or the same. In addition, the calculated shift voltage dRu includes a shift voltage dRu1 used as a shift voltage dR1 and a shift voltage dRu2 used as a shift voltage dR2. In addition, the combination of the plurality of soft bit voltages is not limited to the above combination.

[0106] According to the soft bit voltage and tracking voltage as described above, the threshold voltage is classified into 8 regions. Hereinafter, the 8 regions are designated by indexes 1 "1" to "8" in order of threshold voltage from low to high. The region of index 1 "1" is a region where the threshold voltage is less than voltage ARt (-3). The region of index 1 "2" is a region where the threshold voltage is greater than voltage ARt (-3) and less than voltage ARt (-2). The region of index 1 "3" is a region where the threshold voltage is greater than voltage ARt (-2) and less than voltage ARt (-1). The region of index 1 "4" is a region where the threshold voltage is greater than voltage ARt (-1) and less than tracking voltage Art. The region of index 1 "5" is a region where the threshold voltage is greater than tracking voltage ARt and less than voltage ARt (+1). The region of index 1 "6" is a region where the threshold voltage is greater than voltage ARt (+1) and less than voltage ARt (+2). The region of index 1 "7" is a region where the threshold voltage is greater than voltage ARt (+2) and less than voltage ARt (+3). The region of index 1 "8" is a region where the threshold voltage is equal to or higher than voltage ARt(+3).

[0107] The hard bit included in the second hard bit data obtained by the second hard bit read using the tracking voltage Art is referred to as a hard bit HB2. When the threshold voltage of the memory cell transistor MT is included in the region specified by the index 1 "1" to "4", the hard bit HB2 is "1". When the threshold voltage of the memory cell transistor MT is included in the region specified by the index 1 "5" to "8", the hard bit HB2 is "0".

[0108] In addition, the soft bit read includes a process of obtaining a result of a logic operation using the data obtained by the read process using the plurality of read voltages. The result of the logic operation obtained as page data by the soft bit read is soft bit data. The soft bit data includes first soft bit data and second soft bit data. Hereinafter, the soft bit included in the first soft bit data is referred to as the first soft bit SB1. In addition, the soft bit included in the second soft bit data is referred to as the second soft bit SB2.

[0109] The first soft bit data is obtained by, for example, performing an ENOR operation on a plurality of data read from the memory cell transistor MT using the voltages ARt(-2) and ARt(+2) respectively. When the threshold voltage of the memory cell transistor MT is included in the region specified by the index 1 "1", "2", "7" and "8", the first soft bit SB1 is "1". When the threshold voltage of the memory cell transistor MT is included in the region specified by the index 1 "3" to "6", the first soft bit SB1 is "0".

[0110] The second soft bit data is obtained by performing an ENOR operation on a plurality of data read from the memory cell transistor MT using the voltages ARt(-3), ARt(-1), ARt(+1), and ARt(+3), respectively. When the threshold voltage of the memory cell transistor MT is included in the region specified by the index 1 "1", "4", "5", and "8", the second soft bit SB2 is "1". When the threshold voltage of the memory cell transistor MT is included in the region specified by the index 1 "2", "3", "6", and "7", the second soft bit SB2 is "0".

[0111] In addition, Fig. 9 In the example, the memory cell transistor MT whose threshold voltage in the memory cell transistor MT included in the "Er" state is included in the memory cell transistor MT in the area specified by the index 1 "8" and the memory cell transistor MT whose threshold voltage in the memory cell transistor MT included in the "A" state is included in the area specified by the index 1 "1" are referred to as memory cell transistors MT having a hard error state. When the number of memory cell transistors MT having a hard error state increases, the success rate of soft bit correction decreases. Therefore, it is desirable to have a small number of memory cell transistors MT having a hard error state.

[0112] 1.2.3 Correction processing based on soft bit data

[0113] use Fig.10 The correction process of the soft bit data based on S9 is described. Fig.10 This is a flowchart for explaining the flow of correction processing based on soft bit data in the storage system according to the embodiment.

[0114] In S11, a variable i1 is initialized (i1=0). Then, the process proceeds to S12.

[0115] In S12, the soft decision decoding circuit 162b converts the combination of the hard bit HB2, the first soft bit SB1, and the second soft bit SB2 into LLR values ​​for the i1-th ECC frame using the LLR table 121. The soft decision decoding circuit 162b performs soft bit correction for the i1-th ECC frame using the converted LLR values ​​and the soft decision decoding code given to the data by the ECC circuit 16. Then, the channel matrix generation circuit 163 generates the channel matrix 122. Thereafter, the process proceeds to S13. In addition, the generation of the channel matrix 122 will be described later.

[0116] use Fig.11 The LLR table 121 is supplemented. Fig.11 This is a diagram for explaining a log-likelihood ratio table used for error correction in a storage system according to an embodiment.

[0117] The LLR table stores LLR values ​​for each index 1, for example. That is, in the LLR table, LLR values ​​are stored for each combination of hard bit HB2, first soft bit SB1, and second soft bit SB2. The LLR value is set to a larger value (positive value) as the likelihood of the memory cell transistor MT holding "0" data is higher. The LLR value takes a smaller value (negative value) as the likelihood of the memory cell transistor MT holding "1" data is higher.

[0118] For example, the LLR value of the memory cell transistor MT whose threshold voltage is included in the range of the threshold voltage specified by the index 1 "1" is -9. In addition, when the threshold voltage of the memory cell transistor MT is included in the range of the threshold voltage specified by the index 1 "1", as Fig. 9 As shown in FIG. 1 , the hard bit HB2, the first soft bit SB1, and the second soft bit SB2 read from the memory cell transistor MT are “1”, “1”, and “1”, respectively. In addition, the LLR value of the memory cell transistor MT whose threshold voltage is included in the threshold voltage range specified by the index 1 “5” is +1. In addition, when the threshold voltage of the memory cell transistor MT is included in the threshold voltage range specified by the index 1 “5”, as shown in FIG. Fig. 9 As shown, the hard bit HB2, the first soft bit SB1, and the second soft bit SB2 read from the memory cell transistor MT are "0", "0", and "1", respectively.

[0119] Back to Fig.10 , continue to explain the correction processing based on soft bit data.

[0120] In S13, the controller 10 determines whether the soft bit correction is successful for the i1th ECC frame. If the soft bit correction is successful for the i1th ECC frame (S13: Yes), the process proceeds to S14. If the soft bit correction is unsuccessful for the i1th ECC frame (S13: No), the process proceeds to S15.

[0121] In S14, the controller 10 determines whether the HE condition is satisfied based on the channel matrix 122, for example, for the i1th ECC frame. In the embodiment, the HE condition is, for example, the presence of one or more memory cell transistors MT in a hard error state with a threshold voltage less than the voltage ARt(-3) or greater than the voltage ARt(+3). For the i1th ECC frame, if the HE condition is satisfied (S14: Yes), the process proceeds to S16. For the i1th ECC frame, if the HE condition is not satisfied (S14: No), the process proceeds to S17.

[0122] In S15, the controller 10 performs other processing except soft bit correction and performs error correction. Then, the process proceeds to S17. In addition, in the embodiment, the process of S15 may not be performed. In this case, when the soft bit correction of the i1th ECC frame fails (S13: No), the process proceeds to S17.

[0123] In S16, the shift voltage calculation circuit 164 calculates the shift voltages dRu1 and dRu2 based on the generated channel matrix 122. Then, the shift voltage calculation circuit 164 updates the shift voltages dRu1 and dRu2 held by the shift voltage calculation circuit 164. The update of the shift voltages dRu1 and dRu2 will be described later. Then, the process proceeds to S17.

[0124] In S17, it is determined whether the i1th ECC frame is the last ECC frame in the page. If the i1th ECC frame is the last ECC frame (S17: Yes), the process ends. If the i1th ECC frame is not the last ECC frame (S17: No), the process proceeds to S18.

[0125] In S18, the controller 10 increments the variable i1 (i1++). Then, the process proceeds to S12.

[0126] As described above, the controller 10 repeats the processes of S11 to S18 until the i1th ECC frame becomes the last ECC frame.

[0127] As described above, correction processing based on soft bit data is performed.

[0128] 1.2.4 Generation of channel matrix

[0129] use Fig.12 The generation of the channel matrix 122 will be described. Fig.12 This is a diagram for explaining generation of a channel matrix executed in the storage system according to the embodiment. Fig.12 (A) is a table showing the channel matrix 122. Fig.12(B) is a graph showing the number of “0” data in the channel matrix 122 . Fig.12 (C) is a graph showing the number of “1” data in the channel matrix 122 .

[0130] In the example involved in the implementation, the size of the channel matrix 122 is 2 rows and 8 columns. The row represents the number DLECNT of "0" data and "1" data in the data corrected by soft bit correction. The values ​​N1[1] to N1[8] are the number of "1" data. The values ​​N0[1] to N0[8] are the number of "0" data. The column represents index 1.

[0131] The value N1[1] is, for example, the number of memory cell transistors MT whose bit value of the corrected data is "1" and whose threshold voltage is included in the range of threshold voltages specified by the index 1 "1". In addition, the value N0[1] is, for example, the number of memory cell transistors MT whose bit value of the corrected data is "0" and whose threshold voltage is included in the range of threshold voltages specified by the index 1 "1".

[0132] Similarly, the value N1[5] is, for example, the number of memory cell transistors MT whose bit value of the corrected data is "1" and whose threshold voltage is included in the range of the threshold voltage specified by the index 1 "5". In addition, the value N0[5] is, for example, the number of memory cell transistors MT whose bit value of the corrected data is "0" and whose threshold voltage is included in the range of the threshold voltage specified by the index 1 "5".

[0133] In addition, Fig.12 In the channel matrix 122 shown, the value N1[8] is the number of memory cell transistors MT in the hard error state where the bit value of the corrected data is "1". In addition, the value N0[1] is the number of memory cell transistors MT in the hard error state where the bit value of the corrected data is "0".

[0134] 1.2.5 Calculation of shift voltage

[0135] use Fig.13 , the calculation of the shift voltage is explained. Fig.13 This is a diagram for explaining calculation of a shift voltage in soft bit reading executed in the storage system according to the embodiment. Fig.13 (A) is a graph for explaining the calculation of the shift voltage dRu1 using the number DLECNT of "0" data. Fig.13 In (A), the horizontal axis as a linear axis shows the index 2 described later, and the vertical axis as a logarithmic axis shows the number DLECNT. Fig.13 (B) is a graph for explaining the calculation of the shift voltage dRu2 using the number of "1" data DLECNT. Fig.13In (B), the horizontal axis as a linear axis shows the index 3 described later, and the vertical axis as a logarithmic axis shows the number DLECNT.

[0136] When the HE condition is satisfied, the shift voltage calculation circuit 164 updates the shift voltage dRu based on the number DLECNT in the channel matrix 122. More specifically, the HE condition includes a first HE condition and a second HE condition. The first HE condition is that there is a memory cell transistor MT in a hard error state where the value of a bit in the corrected data is "0" (value N0[1])≥1). In addition, the second HE condition is that there is a memory cell transistor MT in a hard error state where the value of a bit in the corrected data is "1" (value N1[8])≥1). When the first HE condition is satisfied, the shift voltage calculation circuit 164 changes the shift voltage dRu1. In addition, when the second HE condition is satisfied, the shift voltage calculation circuit 164 changes the shift voltage dRu2.

[0137] Hereinafter, a case where the shift voltage dRu1 is changed and a case where the shift voltage dRu2 is changed will be described respectively.

[0138] (Case of Changing the Shift Voltage dRu1)

[0139] The shift voltage calculation circuit 164 performs fitting on the memory cell transistors MT whose bit values ​​in the corrected data are “0”, based on the number DLECNT in the channel matrix 122 .

[0140] More specifically, if Fig.13 As shown in (A), the shift voltage calculation circuit 164 uses the values ​​N0[2] to N0[7] of the channel matrix 122 to fit the index 2 corresponding to these values. That is, the shift voltage calculation circuit 164 uses the data other than the values ​​N0[1] and N0[8] to perform fitting. In the example of the embodiment, the index 2 is the index obtained by adding 2 to the index 1 (index2=index1+2).

[0141] The fitting is performed on a value N0[index2-2] that is an integer greater than or equal to 4 and less than or equal to 9 with respect to index 2, using, for example, a function Fit0 represented by the following equation (1).

[0142] Fit0=a×e b×index2 (1)

[0143] In the above formula (1), the values ​​a and b are fitting parameters.

[0144] In the following description, for the value of a function of each index, "[index]" is added to the end of the function. For example, the value of the function Fit0 of index2 is referred to as value Fit0[index2].

[0145] Through the above fitting, the shift voltage calculation circuit 164 estimates the number DLECNT corresponding to index 2 "1" to "9" as the value Fit0[index2]. Fig.13 In (A), the value Fit0[index2] estimated by fitting is indicated by “△”.

[0146] The shift voltage calculation circuit 164 adds the values ​​Fit0[index2] whose index 2 is 3 or less in descending order, and determines the index 2max at which the sum after addition exceeds the value N0[1] for the first time. That is, the shift voltage calculation circuit 164 determines the largest index 2max that satisfies the following formula (2) among the indexes 2 that are 3 or less.

[0147]

[0148] The shift voltage calculation circuit 164 calculates the shift voltage dRu1 based on the index 2max so that the threshold voltage of the memory cell transistor MT in the hard error state is included in the range above the voltage ARt(-3). Specifically, the shift voltage calculation circuit 164 calculates the shift voltage dRu1 so that the voltage ARt(-3) is reduced by the value obtained by subtracting the index 2max from 4 and multiplying the shift voltage dR1 used in S8 ((4-index2max)×dR1). Thus, the calculated shift voltage dRu1 is a voltage ((3×dR1+(4-index2max)×dR1) / 3).

[0149] The shift voltage dRu1 is calculated as described above.

[0150] (Case of Changing the Shift Voltage dRu2)

[0151] The shift voltage calculation circuit 164 performs fitting on the memory cell transistors MT whose bit values ​​in the corrected data are “1”, based on the number DLECNT in the channel matrix 122 .

[0152] like Fig.13 As shown in (B), the shift voltage calculation circuit 164 uses the values ​​N1[2] to N1[7] of the channel matrix 122 to fit the index 3 corresponding to these values. That is, the shift voltage calculation circuit 164 uses the data other than the values ​​N1[1] and N1[8] to perform fitting. In the example of the embodiment, the index 3 is the index obtained by subtracting the index 1 from 11 (index3=11-index1).

[0153] The fitting is performed on a value N1 [11-index3] that is an integer greater than or equal to 4 and less than or equal to 9 with respect to index 3, using, for example, a function Fit1 represented by the following equation (3).

[0154] Fit1=c×e d×index3 (3)

[0155] In the above formula (3), the values ​​c and d are fitting parameters.

[0156] Through the above fitting, the shift voltage calculation circuit 164 estimates the number DLECNT corresponding to index 3 "1" to "9" as the value Fit1[index3]. Fig.13 In (B), the value Fit1[index3] estimated by fitting is indicated by “△”.

[0157] The shift voltage calculation circuit 164 adds the values ​​Fit1[index3] whose index 3 is 3 or less in descending order, and determines the index 3max whose sum exceeds the value N1[8] for the first time. That is, the shift voltage calculation circuit 164 determines the largest index 3max that satisfies the following equation (4) among the indexes 3 that are 3 or less.

[0158]

[0159] The shift voltage calculation circuit 164 calculates the shift voltage dRu2 based on the index 3max so that the threshold voltage of the memory cell transistor MT in the hard error state is included in the range above the voltage ARt(-3). Specifically, the shift voltage calculation circuit 164 calculates the shift voltage dRu2 so that the voltage ARt(-3) is reduced by the value obtained by subtracting the index 3max from 4 and multiplying the shift voltage dR2 used in S8 ((4-index3max)×dR2). Thus, the calculated shift voltage dRu2 is a voltage ((3×dR2+(4-index3max)×dR2) / 3).

[0160] The shift voltage dRu2 is calculated as described above.

[0161] As described above, the controller 10 is configured to calculate the shift voltage dRu, for example, when performing soft bit reading in the next or subsequent reading operations. Fig.14 The updated shift voltage dRu is used as shown. Fig.14 FIG. 2 is a diagram for explaining soft bit reading using a calculated shift voltage performed in a storage system according to an embodiment. Fig.14 , a case where both the shift voltages dRu1 and dRu2 are updated is shown.

[0162] exist Fig.14, the tracking voltage ARt' is shown as a hard bit voltage for the second hard bit read in the next and subsequent read operations. In addition, voltages ARt'(-3), ARt'(-2), ARt'(-1), ARt'(+1), ARt'(+2), and ARt'(+3) based on the tracking voltage ARt' and the shift voltages dRu1 and dRu2 are shown as soft bit voltages for the soft bit read in the next and subsequent read operations. The voltage ARt'(-3) is lower than the voltage ARt'(-2) by the shift voltage dRu1. The voltage ARt'(-2) is lower than the voltage ARt'(-1) by the shift voltage dRu1. The voltage ARt'(-1) is lower than the tracking voltage ARt' by the shift voltage dRu1. The voltage ARt'(+1) is higher than the tracking voltage ARt' by the shift voltage dRu2. The voltage ARt'(+2) is higher than the voltage ARt'(+1) by the shift voltage dRu2. The voltage ARt'(+3) is higher than the voltage ARt'(+2) by the shift voltage dRu2.

[0163] The shift voltages dRu1 and dRu2 after updating are higher than the shift voltages dR1 and dR2 before updating, respectively. Therefore, the voltage ARt'(-3) is lower than the voltage ARt(-3). In addition, the voltage ARt'(+3) is higher than the voltage ARt(+3).

[0164] According to the above, when the shift voltage dR is updated in a read operation of a certain page, after the read operation, in the soft bit read of the next read operation, the updated shift voltage dRu is used, as shown in FIG. Fig.14 As shown, the memory cell transistor MT is suppressed from being in a hard error state.

[0165] 1.3 Effects of implementation methods

[0166] According to the embodiment, it is possible to improve the error correction capability of data in the storage system 1. The effects of the embodiment will be described below.

[0167] In the memory system 1 according to the embodiment, the controller 10 is configured to perform soft bit correction on a plurality of memory cell transistors MT included in a certain page (page 1) based on the second hard bit data, the first soft bit data, and the second soft bit data. In addition, the controller 10 is configured to determine a new shift voltage dRu based on the shift voltage dRu when the HE condition based on the correction data corrected by the soft bit correction is satisfied. More specifically, when the data corrected by the soft bit correction related to the page 1 includes a memory cell transistor MT in a hard error state with data "0", the controller 10 calculates the shift voltage dRu1 so that the voltage ARt (-3) becomes a low voltage. In addition, when the data corrected by the soft bit correction related to the page 1 includes a memory cell transistor MT in a hard error state with data "1", the controller 10 calculates the shift voltage dRu2 so that the voltage ARt (+3) becomes a high voltage. In addition, when the memory cell transistor MT in a hard error state with data "0" is not included, the controller 10 maintains the shift voltage dRu1. In addition, in the case where there is no memory cell transistor MT in a hard error state having "1" data, the controller 10 maintains the shift voltage dRu2. Furthermore, the controller 10 is configured to use the shift voltage dRu calculated as described above in the soft bit reading of the reading operation of the second page different from the first page after the reading operation of the first page. By the above configuration, it is possible to suppress the generation of the memory cell transistor MT in a hard error state during the soft bit reading of the second page after the soft bit reading of the first page. Therefore, it is possible to suppress the failure of soft bit correction due to the presence of the memory cell transistor MT in the hard error state. Therefore, it is possible to improve the error correction capability of the data of the storage system 1.

[0168] 2. Modifications

[0169] The above-described embodiment can be modified in various ways.

[0170] Hereinafter, a storage system according to a modified example will be described.

[0171] 2.1 First Modification

[0172] In the embodiment, the HE condition is described as the case where the memory cell transistor MT has a hard error state, but the present invention is not limited thereto. The HE condition may also be set for each state based on at least one of the ratio and the number of memory cell transistors MT in the hard error state. In addition, the configuration of the memory system 1 involved in the first variant is substantially the same as the configuration of the memory system involved in the embodiment, so the description thereof is omitted. The following mainly describes the differences between the operation of the memory system 1 involved in the first variant and the operation of the memory system involved in the embodiment.

[0173] The HE conditions in the first modification example include the first HE condition and the second HE condition, similarly to the HE conditions in the embodiment.

[0174] In the first variant, the first HE condition is that, for the memory cell transistors MT whose bit value in the channel matrix 122 is "0", the ratio R0HE (%) of the memory cell transistors MT in the hard error state to the number of failed bits is greater than the reference ratio R0c0 (R0HE ≥ R0c0). Here, the number of failed bits is the number of memory cell transistors MT whose bit value in the channel matrix 122 is "0" and which become failed bits when read with the tracking voltage Art. Thus, the ratio R0HE is the ratio of the value N0[1] to the sum of the values ​​N0[1], N0[2], N0[3], and N0[4]. In addition, the ratio R0c0 is, for example, 5%.

[0175] In addition, the second HE condition is that, for the memory cell transistors MT whose bit value in the channel matrix 122 is "1", the ratio R1HE (%) of the memory cell transistors MT in the hard error state to the number of failed bits is greater than the reference ratio R1c0 (R1HE ≥ R1c0). Here, the number of failed bits is the number of memory cell transistors MT whose bit value in the channel matrix 122 is "1" and which become failed bits when read with the tracking voltage Art. Thus, the ratio R1HE is the ratio of the value N1[8] to the sum of the values ​​N1[5], N1[6], N1[7], and N1[8]. In addition, the ratio R1c0 is, for example, 5%.

[0176] When the first HE condition is satisfied, the shift voltage calculation circuit 164 can change the shift voltage dRu1. When the second HE condition is satisfied, the shift voltage calculation circuit 164 can change the shift voltage dRu2.

[0177] In the first variant, the first HE condition may be that the number of memory cell transistors MT in the hard error state with a bit value of "0" in the channel matrix 122 is 5 or more (5 bits) (N0[1]≥5), instead of the condition regarding the above ratio R0HE (R0HE≥R0c0). In this case, the second HE condition may be that the number of memory cell transistors MT in the hard error state with a bit value of "1" in the channel matrix 122 is 5 or more (5 bits) (N1[8]≥5), instead of the condition regarding the above ratio R1HE (R1HE≥R1c0).

[0178] Furthermore, in the first variant, the first HE condition may be that the condition regarding the above ratio R0HE (R0HE ≥ R0c0) and the condition regarding the number of memory cell transistors MT in a hard error state (N0[1] ≥ 5) are both satisfied, instead of the above condition. In this case, the second HE condition may be that the condition regarding the above ratio R1HE (R1HE ≥ R1c0) and the condition regarding the number of memory cell transistors MT in a hard error state (N1[8] ≥ 5) are both satisfied.

[0179] Note that the calculation method of the shift voltages dRu1 and dRu2 can be the same as the calculation method of the shift voltages dRu1 and dRu2 according to the embodiment, and therefore the description thereof will be omitted.

[0180] According to the first modification example, the same effects as those of the embodiment can be achieved.

[0181] 2.2 Second Modification

[0182] In the embodiment and the first variant, the case where the shift voltage dRu is calculated based on the fitting result of the data in the channel matrix 122 is shown, but it is not limited to this. For example, the shift voltage dRu can also be determined based on the ratio of the memory cell transistors MT in the hard error state. In addition, the structure of the memory system 1 involved in the second variant is substantially the same as the structure of the memory system involved in the embodiment and the first variant, so its description is omitted. In the following, the operation of the memory system 1 involved in the second variant is mainly described in which the operation of the memory system 1 involved in the second variant is different from the operation of the memory system involved in the embodiment and the first variant.

[0183] In the second variation, when the first HE condition is satisfied, in the process of S16, the shift voltage calculation circuit 164 calculates the shift voltage dRu1 based on the ratio R0HE of the hard error state memory cell transistors MT whose bit value in the channel matrix 122 is "0".

[0184] More specifically, the shift voltage calculation circuit 164 calculates the shift voltage dRu1 based on, for example, the ratio R0HE and a plurality of reference ratios R0c1 and R0c2 (%). When the ratio R0HE is less than the ratio R0c1, the shift voltage calculation circuit 164 calculates the shift voltage dRu1, for example, in such a manner that the voltage ARt(-3) is reduced by the shift voltage dR1 used in S8. That is, the calculated shift voltage dRu1 is a voltage (4×dR1 / 3). When the ratio R0HE is greater than or equal to the ratio R0c1 and less than the ratio R0c2, the shift voltage calculation circuit 164 calculates the shift voltage dRu1, for example, in such a manner that the voltage ARt(-3) is reduced by a voltage (2×dR1) obtained by multiplying the shift voltage dR1 used in S8 by 2. That is, the calculated shift voltage dRu1 is a voltage (5×dR1 / 3). In addition, when the ratio R0HE is greater than or equal to the ratio R0c2, the shift voltage calculation circuit 164 calculates the shift voltage dRu1 in such a manner that the voltage ARt (-3) is reduced by a voltage (3×dR1) obtained by multiplying 3 by the shift voltage dR1 used in S8. That is, the calculated shift voltage dRu1 is a voltage (2×dR1). In addition, the ratios R0c1 and R0c2 are, for example, 10% and 20%, respectively. In addition, the reference ratios for calculating the shift voltage dRu1 may be one or more than three.

[0185] When the second HE condition is satisfied, in the process of S16 , the shift voltage calculation circuit 164 calculates the shift voltage dRu2 based on the ratio R1HE of the hard error state memory cell transistors MT whose bit value in the channel matrix 122 is “1”.

[0186] More specifically, the shift voltage calculation circuit 164 calculates the shift voltage dRu2 based on, for example, the ratio R1HE and a plurality of reference ratios R1c1 and R1c2 (%). When the ratio R1HE is less than the ratio R1c1, the shift voltage calculation circuit 164 calculates the shift voltage dRu2 in a manner such that, for example, the voltage ARt (+3) is increased by the shift voltage dR2 used in S8. That is, the calculated shift voltage dRu2 is a voltage (4×dR2 / 3). When the ratio R1HE is greater than or equal to the ratio R1c1 and less than the ratio R1c2, the shift voltage calculation circuit 164 calculates the shift voltage dRu2 in a manner such that, for example, the voltage ARt (+3) is increased by a voltage (2×dR2) obtained by multiplying 2 by the shift voltage dR2 used in S8. That is, the calculated shift voltage dRu2 is a voltage (5×dR2 / 3). In addition, when the ratio R1HE is greater than or equal to the ratio R1c2, the shift voltage calculation circuit 164 calculates the shift voltage dRu2 in such a manner that the voltage ARt (+3) is increased by a voltage (3×dR2) obtained by multiplying 3 by the shift voltage dR2 used in S8. That is, the calculated shift voltage dRu2 is a voltage (2×dR2). In addition, the ratios R1c1 and R1c2 are, for example, 10% and 20%, respectively. In addition, the reference ratios for calculating the shift voltage dRu2 may be one or more than three.

[0187] According to the second modification example, the same effects as those of the embodiment and the first modification example are achieved.

[0188] 2.3 Third Modification

[0189] In the embodiment, the first variant, and the second variant, the case where the shift voltage dRu is calculated when the soft bit correction is successful is shown, but the present invention is not limited thereto. The controller 10 may also be configured to calculate the shift voltage dRu based on the channel matrix 122 when the soft bit correction fails, even when the soft bit correction fails. In addition, the configuration of the storage system 1 involved in the third variant is substantially the same as the configuration of the storage system involved in the embodiment, the first variant, and the second variant, and therefore the description thereof is omitted. In the following, the operation of the storage system 1 involved in the third variant is mainly described in terms of the difference between the operation of the storage system 1 involved in the embodiment, the first variant, and the second variant.

[0190] use Fig.15 The read operation of the storage system 1 according to the third modification example will be described. Fig.15 This is a flowchart for explaining the flow of correction processing based on soft bit data in the storage system according to the third modification. The overall flow of the read operation in the third modification can be made the same as the overall flow of the read operation according to the embodiment, and therefore the description thereof is omitted.

[0191] In S21, variables i2 and i3 are initialized (i2=i3=0). Then, the process proceeds to S22. The processes of S22 and S24 to S27 can be respectively similar to the processes of S11, S12, S14, and S16 to S18 except that variable i2 is used instead of variable i1.

[0192] In S23, the controller 10 determines whether the soft bit correction is successful for the i2th ECC frame. If the soft bit correction of the i2th ECC frame is successful (S23: Yes), the process proceeds to S24. If the soft bit correction of the i2th ECC frame fails (S23: No), the process proceeds to S28.

[0193] In S28, the controller 10 determines whether the variable i3 is equal to or greater than a preset value. Fig.15 In the example of , the preset value is 2, but the present invention is not limited thereto. The preset value may be an integer greater than 1 or 3. When the variable i3 is greater than the preset value (S28: Yes), the process proceeds to S26. When the variable i3 is less than the preset value (S28: No), the process proceeds to S29. By the process of S28, the number of times the process of S29 described later is executed is set to less than the preset value.

[0194] In S29, the controller 10 calculates the shift voltages dRu1 and dRu2 based on the channel matrix when the soft bit correction fails, for example. The soft bit correction fails, for example, when there are many memory cell transistors MT in the hard error state. The calculation of the shift voltages dRu1 and dRu2 can be, for example, the same as the calculation of the shift voltages dRu1 and dRu2 in the embodiment, the first variant, and the second variant. Then, the process proceeds to S30.

[0195] In S30, the controller 10 increments the variable i3 (i3++). Then, the process proceeds to S31.

[0196] In S31, the controller 10 performs the same process as that in S8 using the shift voltage dRu calculated in S29. In S31, the second hard bit data may be the same as that in S8, for example. Then, the process proceeds to S22.

[0197] As described above, the controller 10 repeats the processes of S22 to S31 until the i2 th ECC frame becomes the last ECC frame in S26 .

[0198] The correction process based on the soft bit data in the third modification is performed as described above.

[0199] Furthermore, in the third modification, when the soft bit correction fails in S23 , the generation of soft bit data may be executed a plurality of times in the read operation for the same page.

[0200] According to the third modification, the same effects as those of the embodiment, the first modification, and the second modification can be achieved.

[0201] 3 Others

[0202] In the above-mentioned embodiment, first variant, second variant and third variant, the case where the second hard bit data and the soft bit data are obtained by the second hard bit read and the soft bit read in the process of S8 is shown. However, it is not limited to this. The second hard bit data and the soft bit data can also be generated based on the result of the threshold voltage tracking of S4 instead of performing the second hard bit read and the soft bit read. In addition, in the threshold voltage tracking, the controller 10 performs a reading process using a plurality of read voltages. The plurality of read voltages are set, for example, with the threshold voltage (central voltage) estimated to be close to the intersection of the "Er" state and the "A" state as the center. And the controller 10 calculates the tracking voltage ARt using these reading results. In the threshold voltage tracking as described above, the number of read voltages used in the threshold voltage tracking is greater than the number of read voltages used to obtain the second hard bit data and the soft bit data. Thus, in other examples, the controller 10 can generate the second hard bit data and the soft bit data using the reading results of the read voltages closest to the voltages ARt(-3), ARt(-2), ARt(-1), ARt(+1), ARt(+2), ARt(+3) and the tracking voltage Art among the multiple read voltages used for threshold voltage tracking.

[0203] In addition, in the above-mentioned embodiment, the first variant, the second variant, and the third variant, the case where the threshold voltage distribution includes two states is shown, but it is not limited to this. The storage system 1 can also be configured such that, based on the threshold voltages of multiple memory cell transistors MT, the threshold voltage distribution includes four, eight, or more states. In this case, for example, the shift voltage calculation circuit 164 can also be configured to calculate the shift voltage dRdef based on the result of threshold voltage tracking. More specifically, the shift voltage dRdef can be determined based on the difference in threshold voltages between adjacent states, etc. In addition, the calculation of the shift voltage dRdef can be performed in the process of S6.

[0204] Several embodiments have been described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and / or spirit of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A storage system comprising a semiconductor memory and a controller, The semiconductor memory includes a plurality of first storage cells each configured to store data in a nonvolatile manner according to a threshold voltage. The controller is configured as follows: performing first error correction on the plurality of first memory cells based on the first hard bit data and the first soft bit data obtained using the plurality of first soft bit voltages, When a first condition based on the corrected data corrected by the first error correction is satisfied, a second shift voltage different from the first shift voltage is determined based on a first shift voltage that is a potential difference associated with the plurality of first soft bit voltages.

2. The storage system according to claim 1, The semiconductor memory further includes a plurality of second storage cells each configured to store data in a nonvolatile manner according to a threshold voltage. The controller is configured to, after the first error correction, performing second error correction on the plurality of second storage cells based on the second hard bit data and the second soft bit data obtained using the plurality of second soft bit voltages, The plurality of second soft bit voltages are determined using the second shift voltage.

3. The storage system according to claim 1, The first hard bit data is obtained using a first hard bit voltage between a lowest first voltage among the plurality of first soft bit voltages and a highest second voltage among the plurality of first soft bit voltages. The first shift voltage is a potential difference between adjacent voltages among the plurality of first soft bit voltages within a range below the first hard bit voltage. The controller is configured as follows: When the second condition is satisfied, a fourth shift voltage different from the third shift voltage is determined based on a third shift voltage which is a potential difference between adjacent voltages among the plurality of first soft bit voltages within a range not less than the first hard bit voltage.

4. The storage system according to claim 3, The second shift voltage is higher than the first shift voltage, and the fourth shift voltage is higher than the third shift voltage.

5. The storage system according to claim 3, The controller is configured as follows: When the first error correction is successful, the second shift voltage and the fourth shift voltage can be determined.

6. The storage system according to claim 5, The controller, based on the result of the first error correction, Calculate a first number of the plurality of second storage cells included in the plurality of first storage cells and storing the first value in the correction data, wherein the threshold voltage is less than the first voltage, and a second number of the plurality of third storage cells included in the plurality of first storage cells and storing the second value different from the first value in the correction data, wherein the threshold voltage is greater than the second voltage.

7. The storage system according to claim 6, The first condition includes that the first number is greater than 1, The second condition includes that the first number is 1 or more.

8. The storage system according to claim 7, The controller is configured as follows: calculating the second shift voltage based on a fitting result using the number of the second memory cells included in each of a plurality of threshold voltage ranges included between the first voltage and the second voltage, The fourth shift voltage is calculated based on a fitting result using the number of the third memory cells included in each of a plurality of threshold voltage ranges included between the first voltage and the second voltage.

9. The storage system according to claim 8, The controller is configured as follows: the second shift voltage being calculated so that the plurality of second memory cells are not included in a range less than a lowest voltage among the plurality of first soft bit voltages when a potential difference between the first hard bit data and adjacent voltages among the plurality of first soft bit voltages is changed from the first shift voltage to the second shift voltage below the first hard bit voltage, The fourth shift voltage is calculated in such a manner that the plurality of third memory cells are not included in a range above a highest voltage among the plurality of first soft bit voltages when the potential difference between the first hard bit data and adjacent voltages among the plurality of first soft bit voltages is changed from the third shift voltage to the fourth shift voltage above the first hard bit voltage.

10. The storage system according to claim 6, The first condition includes a condition that a first ratio with respect to the first number is equal to or greater than a first reference ratio. The second condition includes a condition that a second ratio with respect to the second number is equal to or greater than a second reference ratio.

11. The storage system according to claim 10, The first ratio is a ratio of the first number to the number of the plurality of second memory cells having a threshold voltage lower than the first hard bit voltage. The second ratio is a ratio of the second number to the number of the plurality of third memory cells having a threshold voltage equal to or higher than the first hard bit voltage.

12. The storage system according to claim 6, The first condition includes a condition that the first number is greater than or equal to a first reference number. The second condition includes a condition that the second number is equal to or greater than a second reference number.

13. The storage system according to claim 6, The controller is configured as follows: The second shift voltage is determined according to a first ratio of the first number. The fourth shift voltage is determined according to a magnitude of a second ratio with respect to the second number.

14. The storage system according to claim 1, The semiconductor memory further comprises: a first word line connected to the plurality of first memory cells; and a plurality of second memory cells each configured to store data in a nonvolatile manner according to a threshold voltage and connected to the first word line together with the plurality of first memory cells; The first hard bit data and the first soft bit data include data on the first storage unit and the plurality of second storage units, respectively.

15. The storage system according to claim 5, The controller is configured as follows: When the first error correction fails, at least one of a fifth shift voltage different from the first shift voltage and a sixth shift voltage different from the second shift voltage is calculated; A second error correction is performed on the plurality of first memory cells based on the second hard bit data and the second soft bit data obtained using a plurality of second soft bit voltages determined using at least one of the fifth shift voltage and the sixth shift voltage.

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