Self-checking method and device of server, electronic equipment and storage medium

Abstract

The invention provides a server self-checking method and device, electronic equipment and a storage medium. The server comprises a complex programmable logic device (CPLD) and a plurality of hardware components. The method comprises the following steps: receiving a target signal through the CPLD and a signal line; performing identification processing on the target signal through a logic circuit of the CPLD to obtain target information corresponding to the target signal, and determining a target hardware component corresponding to the target signal through a signal line corresponding to the target signal; determining a corresponding target verification strategy according to the target information and the target hardware component, and performing verification processing according to the target signal and the target verification strategy to obtain a verification result; and if the verification result is that the work is abnormal, debugging the target hardware component, and sending alarm information to alarm equipment connected with the CPLD. According to the scheme, the CPLD is used for receiving the target signal generated when the hardware component works, the hardware component is subjected to self-inspection according to the target signal, manual self-inspection is replaced, and therefore the maintenance efficiency of the server is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a self-checking method, device, electronic device and storage medium of a server. Background Art

[0002] With the development of servers, servers can provide multiple functions in multiple scenarios, thereby greatly improving work efficiency. Servers may fail during the development period or operation, affecting the use of the server. Especially in the early stages of development, a large number of failures will occur.

[0003] In the related art, when a server fails, a technician identifies the failure based on his / her experience and knowledge and performs targeted repairs to ensure that the server can operate normally.

[0004] However, manual maintenance requires a step-by-step investigation of the fault phenomenon before the cause of the fault can be found, which results in low maintenance efficiency. Summary of the invention

[0005] The present application provides a server self-check method, device, electronic device and storage medium, which are used to improve the maintenance efficiency of the server.

[0006] In a first aspect, the present application provides a self-check method for a server, wherein the server comprises a complex programmable logic device (CPLD) and a plurality of hardware components, wherein the CPLD is connected to the plurality of hardware components via signal lines, respectively, and the method comprises: receiving a target signal via the CPLD and the signal line; identifying and processing the target signal via a logic circuit of the CPLD to obtain target information corresponding to the target signal, and determining a target hardware component corresponding to the target signal via a signal line corresponding to the target signal; determining a corresponding target verification strategy based on the target information and the target hardware component, and performing verification processing based on the target signal and the target verification strategy to obtain a verification result, wherein the verification result comprises normal operation or abnormal operation; if the verification result is abnormal operation, debugging the target hardware component, and sending the alarm information to an alarm device connected to the CPLD.

[0007] In a possible implementation, the target signal is identified and processed by the logic circuit of the CPLD to obtain target information corresponding to the target signal, including: performing feature detection processing on the target signal by the logic circuit of the CPLD to obtain a target signal feature of the target signal, wherein the target signal feature includes at least one of the following: an address value, a level feature, a timing feature, a protocol feature, or a state feature; and determining the target information corresponding to the target signal according to the target signal feature.

[0008] In one possible implementation, the target information is first command information, and the target hardware component is a CPU; verification processing is performed according to the target signal and the target verification strategy to obtain a verification result, including: determining a target state machine, the target state machine including multiple normal command information; if the target state machine includes the first command information, determining that the verification result is passed; if the target state machine does not include the first command information, a first timer starts timing; if a first resend command information is received before the first timer times out, determining that the verification result is passed, the target state machine includes the first resend command information, and the first resend command information is sent by the CPU; if the first resend command information is not received before the first timer times out, determining that the verification result is failed.

[0009] In a possible implementation, the target information is second command information, and the target hardware component is a baseboard management controller BMC; verification processing is performed according to the target signal and the target verification strategy to obtain a verification result, including: determining the current status information of the BMC; determining the correspondence between the command information and the status information; if the second command information and the current status information conform to the correspondence, determining that the verification result is passed; if the second command information and the current status information do not conform to the correspondence, a second timer starts timing; if a second resend command information is received before the second timer times out, determining that the verification result is passed, the second resend command information and the current status information conform to the correspondence, and the second resend command information is sent by the BMC; if the second resend command information is not received before the target timer times out, determining that the verification result is failed.

[0010] In one possible implementation, the target information is a control signal, and the target hardware component is a control integrated circuit; verification processing is performed according to the target signal and the target verification strategy to obtain a verification result, including: determining the real-time control state and the real-time output state of the control integrated circuit; if the real-time control state does not match the real-time output state, a third timer starts timing; obtaining the real-time control state and the real-time output state of the control integrated circuit; if the real-time control state matches the real-time output state, determining that the verification result is a passed verification; if the real-time control state does not match the real-time output state, a third timer starts timing; if the real-time control state matches the real-time output state before the third timer times out, determining that the verification result is a passed verification; if the real-time control state matches the real-time output state before the third timer times out, determining that the verification result is a failed verification.

[0011] In one possible implementation, debugging the target hardware component includes: sending a retry instruction to the target hardware component, wherein the retry instruction is used to instruct the target hardware component to re-execute a previous operation; or, sending a non-maskable interrupt signal to the target hardware component, wherein the non-maskable interrupt signal is used to instruct the target hardware component to stop working.

[0012] In a second aspect, the present application provides a self-test device for a server, wherein the server includes a complex programmable logic device (CPLD) and multiple hardware components, wherein the CPLD is connected to the multiple hardware components through signal lines respectively, and the device includes: a receiving module, used to receive a target signal through the CPLD and the signal line; an identification module, used to identify and process the target signal through a logic circuit of the CPLD, obtain target information corresponding to the target signal, and determine the target hardware component corresponding to the target signal through the signal line corresponding to the target signal; a verification module, used to determine a corresponding target verification strategy based on the target information and the target hardware component, and perform verification processing based on the target signal and the target verification strategy to obtain a verification result, wherein the verification result includes normal operation or abnormal operation; a debugging module, used to debug the target hardware component if the verification result is abnormal operation, and send the alarm information to the alarm device connected to the CPLD.

[0013] In a possible implementation, the identification module is specifically used to perform feature detection processing on the target signal through the logic circuit of the CPLD to obtain the target signal feature of the target signal, and the target signal feature includes at least one of the following: address value, level feature, timing feature, protocol feature, or state feature; the identification module is also specifically used to determine the target information corresponding to the target signal according to the target signal feature.

[0014] In a possible implementation, the target information is first command information, and the target hardware component is a CPU; the device also includes: a first execution module, used to determine a target state machine, the target state machine includes multiple normal command information; the first execution module is also used to determine that the verification result is a passed verification if the target state machine includes the first command information; the first execution module is also used to start a first timer if the target state machine does not include the first command information; the first execution module is also used to determine that the verification result is a passed verification if a first resend command information is received before the first timer times out, the target state machine includes the first resend command information, and the first resend command information is sent by the CPU; the first execution module is also used to determine that the verification result is a failed verification if the first resend command information is not received before the first timer times out.

[0015] In a possible implementation, the target information is second command information, and the target hardware component is a baseboard management controller BMC; the device also includes: a second execution module, used to determine the current status information of the BMC; the second execution module is also used to determine the correspondence between command information and status information; the second execution module is also used to determine that the verification result is a passed verification if the second command information and the current status information conform to the correspondence; the second execution module is also used to start a second timer if the second command information and the current status information do not conform to the correspondence; the second execution module is also used to determine that the verification result is a passed verification if the second resend command information is received before the second timer times out, the second resend command information and the current status information conform to the correspondence, and the second resend command information is sent by the BMC; the second execution module is also used to determine that the verification result is a failed verification if the second resend command information is not received before the target timer times out.

[0016] In a possible implementation, the target information is a control signal, and the target hardware component is a control integrated circuit; the device further includes: a third execution module, used to determine the real-time control state and the real-time output state of the control integrated circuit; the third execution module is also used to start a third timer if the real-time control state does not match the real-time output state; the third execution module is also used to obtain the real-time control state and the real-time output state of the control integrated circuit; the third execution module is also used to determine that the verification result is a passed verification if the real-time control state matches the real-time output state; the third execution module is also used to start a third timer if the real-time control state does not match the real-time output state; the third execution module is also used to determine that the verification result is a passed verification if the real-time control state matches the real-time output state before the third timer times out; the third execution module is also used to determine that the verification result is a failed verification if the real-time control state matches the real-time output state before the third timer times out.

[0017] In one possible implementation, the device further includes: a processing module, used to send a retry instruction to the target hardware component, wherein the retry instruction is used to instruct the target hardware component to re-execute a previous operation; or, the processing module is also used to send a non-maskable interrupt signal to the target hardware component, wherein the non-maskable interrupt signal is used to instruct the target hardware component to stop working.

[0018] In a third aspect, the present application provides an electronic device comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement any method described in the first aspect.

[0019] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are executed by a processor as described in any one of the methods in the first aspect.

[0020] In a fifth aspect, the present application provides a computer program product, comprising a computer program, wherein the computer program is executed by a processor as in any one of the methods in the first aspect.

[0021] The self-check method, device, electronic device and storage medium of the server provided by the present application, the method includes: the server includes a complex programmable logic device CPLD and multiple hardware components, the CPLD and the multiple hardware components are respectively connected through signal lines, the method includes: receiving a target signal through the CPLD and the signal line; identifying and processing the target signal through the logic circuit of the CPLD to obtain the target information corresponding to the target signal, and determining the target hardware component corresponding to the target signal through the signal line corresponding to the target signal; determining the corresponding target verification strategy according to the target information and the target hardware component, and performing verification processing according to the target signal and the target verification strategy to obtain a verification result, the verification result includes normal operation or abnormal operation; if the verification result is abnormal operation, the target hardware component is debugged and processed, and the alarm information is sent to the alarm device connected to the CPLD. The above scheme receives the target signal generated by the hardware component when it is working through the CPLD, and performs self-check on the hardware component according to the target signal, instead of manual self-check, thereby improving the maintenance efficiency of the server. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0023] Figure 1 A schematic diagram of an application scenario of a self-check method for a server provided in an embodiment of the present application;

[0024] Figure 2 A flowchart of a self-checking method of a server provided in an embodiment of the present application;

[0025] Figure 3 A flowchart of a self-checking method of a server provided in an embodiment of the present application;

[0026] Figure 4 A schematic diagram of performing verification processing according to first command information provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of performing verification processing according to second command information provided in an embodiment of the present application;

[0028] Figure 6 A schematic diagram of performing verification processing according to third command information provided in an embodiment of the present application;

[0029] Figure 7 A schematic diagram of the structure of a self-checking device of a server provided in an embodiment of the present application;

[0030] Figure 8A schematic diagram of the structure of a self-checking device of a server provided in an embodiment of the present application;

[0031] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0032] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0033] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0034] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, processing, transmission, provision, disclosure and application of the relevant data comply with the relevant laws, regulations and standards of the relevant countries and regions, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0035] In addition, this application involves big data analysis of user information (including but not limited to personal biometrics, identity data, consumption data, asset data, electronic terminal operation data, etc.), and the use of artificial intelligence technology for automated decision-making, and a technical solution for making decisions that have a significant impact on personal rights and interests based on the results of automated decision-making. The application provides users with corresponding operation entrances for them to choose to agree or reject the results of automated decision-making; if the user chooses to reject, the expert decision-making process will be entered.

[0036] It should be noted that the self-check method, device, electronic device and storage medium of the server of the present application can be used in the field of computer technology, and can also be used in any field other than computers. The application field of the self-check method, device, electronic device and storage medium of the server of the present application is not limited.

[0037] Figure 1A schematic diagram of an application scenario of a self-check method for a server provided in an embodiment of the present application is given as an example in combination with the illustrated scenario: the server includes a mainboard, and the mainboard includes multiple hardware components. When a hardware component fails, the cause of the failure needs to be found and debugged to ensure that the server can work normally.

[0038] In the related art, when a server fails, it needs to be repaired. The repair includes identifying the fault and debugging according to the fault. Based on their experience and knowledge, technicians identify the fault by measuring the voltage of each node, measuring the working status of hardware components, or analyzing logs, and take corresponding debugging measures for the fault to ensure that the server can work normally.

[0039] However, manual troubleshooting requires step-by-step troubleshooting to accurately identify the fault, which is inefficient.

[0040] The server self-check method provided in this application is intended to solve the above technical problems in the prior art.

[0041] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0042] Figure 2 A flow chart of a self-check method of a server provided in an embodiment of the present application, the method comprising the following steps:

[0043] S201, receiving a target signal through the CPLD and the signal line.

[0044] The server includes a complex programmable logic device (CPLD) and multiple hardware components, and the CPLD is connected to the multiple hardware components via signal lines.

[0045] Among them, Complex Programmable Logic Device (CPLD) is an integrated circuit that allows users to define its logic functions through programming. CPLD combines the characteristics of high density and high performance and is suitable for realizing complex digital logic functions.

[0046] The hardware components include at least one of the following: a CPU, a baseboard management controller (BMC for short), or a control integrated circuit.

[0047] Exemplarily, while the server is operating, the CPLD monitors signals of multiple hardware components, thereby detecting faults in a timely manner.

[0048] In combination with the scenario example, the CPLD is connected to each hardware component through a corresponding signal line, thereby avoiding interference between signals of different hardware components.

[0049] S202, identifying and processing the target signal through the logic circuit of the CPLD to obtain target information corresponding to the target signal, and determining the target hardware component corresponding to the target signal through the signal line corresponding to the target signal.

[0050] The target information is used to reflect the current working status of the hardware component.

[0051] Optionally, the target signal includes but is not limited to at least one of the following: a low pin count (LPC) signal, a non-maskable interrupt (NMI) signal, a universal asynchronous receiver / transmitter (UART) signal, an inter-integrated circuit (I2C) signal, a control signal, or an enable signal.

[0052] Exemplarily, the CPLD is connected to each hardware component via a corresponding signal line, and there is a corresponding relationship between the hardware components and the signal lines. The target hardware component of the target signal source can be determined based on the corresponding relationship.

[0053] Combined with the scenario example, the target hardware components are determined so that targeted debugging can be performed on the target hardware components.

[0054] S203, determining a corresponding target verification strategy according to the target information and the target hardware component, and performing verification processing according to the target signal and the target verification strategy to obtain a verification result, where the verification result includes normal operation or abnormal operation.

[0055] Exemplarily, each target hardware has different functions and may cause different faults. Corresponding verification strategies are determined for different hardware components to accurately perform verification processing.

[0056] Combined with the scenario example, CPLD performs real-time detection on the target hardware components. Through the verification strategy, it can determine in real time whether the target hardware has faults, so as to debug in time.

[0057] S204: If the verification result is that the operation is abnormal, the target hardware component is debugged and an alarm message is sent to an alarm device connected to the CPLD.

[0058] Among them, the alarm information is used to remind users or technicians of the current fault.

[0059] Exemplarily, a corresponding debugging method is determined according to a target signal, and a debugging process is performed on the target hardware component by using the corresponding debugging method.

[0060] Optionally, fault information is determined based on the verification result, and alarm information is generated based on the fault information.

[0061] Optionally, the alarm device includes but is not limited to at least one of the following: a light emitting diode (LED), a buzzer, a connector Header, or a VGA connector, etc.

[0062] For example, LED is used to display fault status, and different lighting effects are displayed for different fault status. Lighting effects can be flexibly customized for motherboards of different designs. For example, if the CPU fails, LED1 and LED2 will light up and other lights will go out. If the BMC fails, LED3 and LED4 will light up and other lights will go out. The buzzer is used to report that a serious fault has occurred on the motherboard, and the buzzer is directly driven by the CPLD. For example, if the CPU is abnormal when starting up or the key chip is abnormal, it will remind the user that a serious error has occurred on the server and needs to be checked. The Header is used to print logs. As mentioned above, the key components on the motherboard are connected to the CPLD, and the CPLD can feedback their working status to the Header in the form of UART. At the same time, the UART of the CPU and the UART of the BMC are both connected to the CPLD, and the CPLD can also output them directly to the Header for debugging by R&D and maintenance personnel. The VGA connector is based on the supplement of the Header, and the content is still to print out the content reflected in the Header. Because the Header prints logs, it needs to carry a computer and a corresponding serial port line to receive the relevant UART signals normally. In other application scenarios, only a VGA display device needs to be connected. The log information can be printed on the screen. Thanks to the professional video display effect, the content printed by VGA will be richer than using the Header directly. VGA will be directly driven by CPLD.

[0063] Combined with the scenario example, users or technicians can promptly determine the current status of the server based on the response of the alarm device and take timely measures.

[0064] The self-check method of the server provided in the embodiment of the present application, the server includes a complex programmable logic device CPLD and multiple hardware components, the CPLD and the multiple hardware components are respectively connected through signal lines, and the method includes: receiving a target signal through the CPLD and the signal line; identifying and processing the target signal through the logic circuit of the CPLD to obtain the target information corresponding to the target signal, and determining the target hardware component corresponding to the target signal through the signal line corresponding to the target signal; determining the corresponding target verification strategy according to the target information and the target hardware component, and performing verification processing according to the target signal and the target verification strategy to obtain a verification result, and the verification result includes normal operation or abnormal operation; if the verification result is abnormal operation, the target hardware component is debugged and processed, and an alarm message is sent to the alarm device connected to the CPLD. The above scheme receives the target signal generated by the hardware component when it is working through the CPLD, and performs self-check on the hardware component according to the target signal, instead of manual self-check, thereby improving the maintenance efficiency of the server.

[0065] Based on any of the above embodiments, Figure 3 , the detailed process of the server's self-check is explained.

[0066] Figure 3 The following is a flow chart of a self-checking method of a server provided in an embodiment of the present application. Figure 3 As shown, the method includes:

[0067] S301, receiving a target signal through the CPLD and the signal line.

[0068] It should be noted that the execution process of S301 refers to S201 and will not be repeated here.

[0069] S302 , performing feature detection processing on the target signal through the logic circuit of the CPLD to obtain the target signal feature of the target signal.

[0070] The target signal characteristic includes at least one of the following: an address value, a level characteristic, a timing characteristic, a protocol characteristic, or a state characteristic.

[0071] For example, an address value represents a value used to identify a specific location or resource during communication or data transmission. A level feature represents the voltage or current level of a signal at a specific time point. A timing feature is the change pattern of a signal on a time axis. A protocol feature is the behavior characteristics specified by the communication protocol followed by the signal. A state feature is the state or condition represented by a signal at different time points.

[0072] S303: Determine target information corresponding to the target signal according to the target signal characteristics.

[0073] The target information includes at least one of the following: an LPC signal, an NMI signal, a UART signal, command information, a control signal, or an enable signal.

[0074] Exemplarily, the CPLD identifies the LPC signal by identifying the address value on the LPC address line, the data on the data line, and the control signal on the control line. The CPLD identifies the NMI signal by detecting the level change on the NMI input pin. The CPLD identifies the UART signal by identifying the start bit and stop bit on the UART data pin.

[0075] Combined with the scenario example, the LPC and UART interfaces of the CPU are directly connected to the CPLD, and the relevant LPC and UART signals are sent to the CPLD. The CPLD parses the LPC and UART signals to obtain the command information of the CPU. The UART interface and I2C interface of the BMC are directly connected to the CPLD, and the relevant UART and I2C signals are sent to the CPLD. The CPLD parses the I2C and UART signals to obtain the command information of the BMC. Control signals usually have clear level definitions. For example, the enable signal is high or low when it is valid. The logic circuit inside the CPLD can identify the control signal of the control integrated circuit according to the level change.

[0076] S304, determining a corresponding target verification strategy according to the target information and the target hardware component, and performing verification processing according to the target signal and the target verification strategy to obtain a verification result, where the verification result includes normal operation or abnormal operation.

[0077] A feasible implementation method, the target information is the first command information, and the target hardware component is the CPU; the verification process can be performed by the following method: determining a target state machine, the target state machine includes multiple normal command information; if the target state machine includes the first command information, determining that the verification result is passed; if the target state machine does not include the first command information, the first timer starts timing; if the first resend command information is received before the first timer times out, determining that the verification result is passed, the target state machine includes the first resend command information, and the first resend command information is sent by the CPU; if the first resend command information is not received before the first timer times out, determining that the verification result is failed.

[0078] The state machine is a mathematical model used to describe how a system or object changes state in response to external input in different states. Normal command information is the command information issued by the CPU when it works normally.

[0079] Exemplarily, if the target state machine does not include the first command information, it means that the first command information indicates that the CPU is not working properly. The CPU has a retry mechanism and retries through a first timer. If the first resend command information is received before the first timer times out, it means that the CPU has successfully retried, and the verification result is still determined to be verification passed. If the first resend command information is not received before the first timer times out, it means that the CPU has not successfully retried.

[0080] Next, combine Figure 4 The verification process performed according to the first command information is described.

[0081] Figure 4 This is a schematic diagram of performing verification processing according to the first command information provided in an embodiment of the present application. Figure 4 As shown, the CPLD receives the first command information sent by the CPU, determines whether the state machine includes the first command information, and if the state machine does not include the first command information, further determines through the timer. If the first resend command information included in the state machine sent by the CPU is received before the timer times out, the verification is passed, otherwise, the verification is not passed.

[0082] In combination with the scenario example, the CPU will perform a self-test during the boot process, and after the self-test is completed, the Basic Input / Output System (BIOS) program will be loaded. If the CPLD detects that the BIOS program is not loaded after the CPU self-test is completed, an alarm will be triggered and the NMI interrupt will be activated.

[0083] Combined with the scenario example, when the boot action time issued by the CPU is greater than the preset time of the CPLD, the CPLD notifies the BIOS through the I / O port, instructing the BIOS to start the backup plan to boot.

[0084] In this feasible implementation, the first timer can effectively control the execution of the CPU retry mechanism to avoid false fault detection, thereby improving the accuracy of verification.

[0085] A feasible implementation method, the target information is the second command information, and the target hardware component is the baseboard management controller BMC; the verification process can be performed by the following method: determining a target register, the target register stores a target signal sent by the BMC and the current status information of the mainboard; determining the corresponding relationship between the command information and the status information; if the second command information and the current status information are in accordance with the corresponding relationship, determining that the verification result is a passed verification; if the second command information and the current status information are not in accordance with the corresponding relationship, a second timer starts timing; if the second resent command information is received before the second timer times out, determining that the verification result is a passed verification, the second resent command information and the current status information are in accordance with the corresponding relationship, and the second resent command information is sent by the BMC; if the second resent command information is not received before the target timer times out, determining that the verification result is a failed verification.

[0086] Optionally, the second command information is obtained through a target register, where the target register is a simple general-purpose input / output (SGPIO) register.

[0087] Among them, the SGPIO register usually exists in a microcontroller, a microprocessor or other integrated circuits, and is used to configure the working mode of the general input / output port, read the input status, control the output status, etc.

[0088] Optionally, the CPLD monitors the signal sent by the BMC by reading the SGPIO register.

[0089] Exemplarily, the second command information and the current state information of the BMC are determined. If the second command information matches the current state information, it means that the BMC is working normally. If the second command information does not match the current state information, it means that the BMC is not working normally. The BMC has a retry mechanism, and retries are performed through a second timer. If the second resend command information matching the current state information is received before the second timer times out, it means that the BMC has successfully retried, and the verification result is still determined to be verification passed. Otherwise, it means that the BMC has not successfully retried.

[0090] Next, combine Figure 5 The verification process performed according to the second command information is described.

[0091] Figure 5 This is a schematic diagram of performing verification processing according to the second command information provided in an embodiment of the present application. Figure 5 As shown, the CPLD receives the second command information sent by the BMC, determines whether the second command information is consistent with the status information, and if not, further determines through the timer. If the second resent command information is consistent with the status information before the timer times out, the verification is passed, otherwise, the verification is not passed.

[0092] Combined with the scenario example, when the BMC program is loaded, it will send a loading completion signal BMC_READY_N to the CPLD. This signal will only become low level after the BMC is loaded. If the BMC is loaded and this signal is set to a low level, but it is not actually pulled low, the CPLD will report to the BMC that the action has not been executed. When the BMC senses this state, it should pull the signal low again.

[0093] In this feasible implementation, the second timer can effectively control the execution of the BMC retry mechanism, avoid false fault detection, and thus improve the accuracy of verification.

[0094] A feasible implementation method, the target information is a control signal, and the target hardware component is a control integrated circuit; the verification process can be performed by the following method: determining the real-time control state and the real-time output state of the control integrated circuit; if the real-time control state and the real-time output state do not match, a third timer starts timing; obtaining the real-time control state and the real-time output state of the control integrated circuit; if the real-time control state and the real-time output state match, determining that the verification result is passed; if the real-time control state and the real-time output state do not match, a third timer starts timing; if the real-time control state and the real-time output state match before the third timer times out, determining that the verification result is passed; if the real-time control state and the real-time output state match before the third timer times out, determining that the verification result is failed.

[0095] The real-time control state indicates the state of the control signal, such as whether it is at a high level, and the control integrated circuit is the actual output state, such as whether it is in an active state.

[0096] Exemplarily, if the real-time control state matches the real-time output state, it means that the control integrated circuit works normally. If the real-time control state does not match the real-time output state, it means that the control integrated circuit does not work normally. The control integrated circuit has a retry mechanism, and the retry is performed through the third timer. If the real-time control state matches the real-time output state before the third timer times out, it means that the control integrated circuit retry succeeds, and the verification result is still determined to be verification passed. Otherwise, it means that the control integrated circuit did not retry successfully.

[0097] Optionally, the first timer, the second timer, or the third timer is determined based on historical retry records.

[0098] Combined with the scenario example, the historical retry record reflects the relationship between the retry duration and whether the retry is successful. The historical retry record can be used to determine the accuracy of the timer.

[0099] Next, combine Figure 6The verification process performed based on the control signal will be described.

[0100] Figure 6 This is a schematic diagram of performing verification processing according to a control signal provided in an embodiment of the present application. Figure 6 As shown, the CPLD obtains the real-time control state and the real-time output state, and determines whether the real-time control state matches the real-time output state. If not, further determination is made through the timer. If the real-time control state matches the real-time output state before the timer times out, the verification is passed, otherwise, the verification fails.

[0101] Combined with the scenario example, for example, after the power chip is enabled, the chip will output stable power and send out a power stable flag signal. If the CPLD detects that the chip is enabled but does not receive the power stable flag signal, an alarm will be triggered.

[0102] In this feasible implementation, the third timer can effectively control the execution of the integrated circuit retry mechanism to avoid false fault detection, thereby improving the accuracy of verification.

[0103] S305: Send a retry instruction to the target hardware component, where the retry instruction is used to instruct the target hardware component to re-execute a previous operation.

[0104] Exemplarily, if the power on / off instruction or command instruction issued by the CPU is invalid, the CPLD issues a retry instruction to retry.

[0105] Combined with the scenario example, the retry process can be automatically executed without human intervention, so that timely debugging can be carried out when a failure occurs, indicating the stability of the server.

[0106] S306: Send a non-maskable interrupt signal to the target hardware component, where the non-maskable interrupt signal is used to instruct the target hardware component to stop working.

[0107] Exemplarily, for serious faults, such as memory errors or power failures, the process of the target hardware component is interrupted by a non-maskable interrupt signal.

[0108] Combined with the scenario example, the non-maskable interrupt signal causes the processor to suspend the currently executing task and switch to the pre-defined NMI handler. The NMI handler checks the error type and tries to solve the problem. After handling the error, it returns to the state before the interrupt and continues to execute. The non-maskable interrupt signal has a high priority and cannot be masked or ignored by software. The non-maskable interrupt signal will be responded to immediately, thereby improving the reliability of the server.

[0109] Figure 7 This is a schematic diagram of the structure of a self-checking device of a server provided in an embodiment of the present application. Figure 7 As shown, the self-checking device 70 of the server may include: a receiving module 71, an identification module 72, a verification module 73, and a debugging module 74, wherein:

[0110] The receiving module 71 is used to receive the target signal through the CPLD and the signal line.

[0111] The identification module 72 is used to identify and process the target signal through the logic circuit of the CPLD, obtain the target information corresponding to the target signal, and determine the target hardware component corresponding to the target signal through the signal line corresponding to the target signal.

[0112] The verification module 73 is used to determine the corresponding target verification strategy according to the target information and the target hardware component, and perform verification processing according to the target signal and the target verification strategy to obtain a verification result, and the verification result includes normal operation or abnormal operation.

[0113] The debugging module 74 is used to debug the target hardware component and send an alarm message to the alarm device connected to the CPLD if the verification result shows that the operation is abnormal.

[0114] Optionally, the receiving module 71 may execute Figure 2 S201 in the embodiment.

[0115] Optionally, the identification module 72 may execute Figure 2 S202 in the embodiment.

[0116] Optionally, the verification module 73 may execute Figure 2 S203 in the embodiment.

[0117] Optionally, the debugging module 74 may execute Figure 2 S204 in the embodiment.

[0118] It should be noted that the self-check device of the server shown in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0119] In a possible implementation, the identification module 72 is specifically configured to:

[0120] Performing feature detection processing on the target signal through the logic circuit of the CPLD to obtain a target signal feature of the target signal, wherein the target signal feature includes at least one of the following: an address value, a level feature, a timing feature, a protocol feature, or a state feature;

[0121] According to the target signal characteristics, the target information corresponding to the target signal is determined.

[0122] Figure 8A schematic diagram of the structure of a self-checking device of a server provided in an embodiment of the present application. Figure 7 Based on the embodiment shown, Figure 8 As shown, the self-checking device 80 of the server further includes: a first execution module 75, a second execution module 76, a third execution module 77, and a processing module 78, wherein:

[0123] The first execution module 75 is used to:

[0124] Determine a target state machine, the target state machine including a plurality of normal command information;

[0125] If the target state machine includes the first command information, determining that the verification result is verification passed;

[0126] If the target state machine does not include the first command information, the first timer starts timing;

[0127] If the first resend command information is received before the first timer times out, it is determined that the verification result is passed, the target state machine includes the first resend command information, and the first resend command information is sent by the CPU;

[0128] If the first resend command information is not received before the first timer times out, it is determined that the verification result is verification failure.

[0129] The second execution module 76 is used to:

[0130] Determine the current status information of the BMC;

[0131] Determine the correspondence between command information and status information;

[0132] If the second command information and the current state information are in a corresponding relationship, then the verification result is determined to be verification passed;

[0133] If the second command information does not correspond to the current state information, the second timer starts timing;

[0134] If the second resend command information is received before the second timer times out, it is determined that the verification result is verification passed, the second resend command information and the current state information are in a corresponding relationship, and the second resend command information is sent by the BMC;

[0135] If the second resend command information is not received before the target timer times out, the verification result is determined to be verification failure.

[0136] The third execution module 77 is used to:

[0137] Determine the real-time control state and the real-time output state of the control integrated circuit;

[0138] If the real-time control state does not match the real-time output state, the third timer starts timing;

[0139] Obtaining the real-time control status and real-time output status of the control integrated circuit;

[0140] If the real-time control state matches the real-time output state, the verification result is determined to be verification passed;

[0141] If the real-time control state does not match the real-time output state, the third timer starts timing;

[0142] If the real-time control state matches the real-time output state before the third timer times out, the verification result is determined to be verification passed;

[0143] If the real-time control state matches the real-time output state before the third timer times out, the verification result is determined to be verification failure.

[0144] The processing module 78 is used to:

[0145] Sending a retry instruction to the target hardware component, where the retry instruction is used to instruct the target hardware component to re-execute a previous operation; or,

[0146] A non-maskable interrupt signal is sent to the target hardware component, where the non-maskable interrupt signal is used to instruct the target hardware component to stop working.

[0147] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the electronic device includes:

[0148] The electronic device includes a processor 291 and a memory 292; it may also include a communication interface 293 and a bus 294. The processor 291, the memory 292, and the communication interface 293 may communicate with each other through the bus 294. The communication interface 293 may be used for information transmission. The processor 291 may call the logic instructions in the memory 292 to execute the method of the above embodiment.

[0149] In addition, the logic instructions in the above-mentioned memory 292 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0150] The memory 292 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present application. The processor 291 executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory 292, that is, implementing the methods in the above method embodiments.

[0151] The memory 292 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 292 may include a high-speed random access memory and may also include a non-volatile memory.

[0152] An embodiment of the present application provides a non-temporary computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method as described in the above embodiment.

[0153] An embodiment of the present application provides a computer program product, including a computer program, which implements the method of the above embodiment when the computer program is executed by a processor.

[0154] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0155] It should be further noted that, although the various steps in the flowchart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowchart may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0156] It should be understood that the above-mentioned device embodiments are only illustrative, and the device of the present application can also be implemented in other ways. For example, the division of units / modules in the above-mentioned embodiments is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units, modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0157] In addition, unless otherwise specified, each functional unit / module in each embodiment of the present application may be integrated into one unit / module, each unit / module may exist physically separately, or two or more units / modules may be integrated together. The above-mentioned integrated unit / module may be implemented in the form of hardware or in the form of a software program module.

[0158] If the integrated unit / module is implemented in the form of hardware, the hardware may be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes but is not limited to transistors, memristors, etc. The processor may be any appropriate hardware processor, such as a CPU, a GPU, an FPGA, a DSP, and an ASIC, etc. The storage unit may be any appropriate magnetic storage medium or magneto-optical storage medium, such as a resistive random access memory RRAM (Resistive Random Access Memory), a dynamic random access memory DRAM (Dynamic Random Access Memory), a static random access memory SRAM (Static Random-Access Memory), an enhanced dynamic random access memory EDRAM (Enhanced Dynamic Random Access Memory), a high-bandwidth memory HBM (High-Bandwidth Memory), a hybrid memory cube HMC (Hybrid Memory Cube), etc.

[0159] If the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0160] In the above embodiments, the description of each embodiment has its own emphasis. For the part not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0161] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0162] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A self-checking method for a server, characterized in that: The server includes a complex programmable logic device (CPLD) and a plurality of hardware components, wherein the CPLD is connected to the plurality of hardware components via signal lines respectively, and the method includes: Receiving a target signal through the CPLD and the signal line; The target signal is identified and processed by the logic circuit of the CPLD to obtain target information corresponding to the target signal, and the target hardware component corresponding to the target signal is determined by the signal line corresponding to the target signal; Determine a corresponding target verification strategy according to the target information and the target hardware component, and perform verification processing according to the target signal and the target verification strategy to obtain a verification result, wherein the verification result includes normal operation or abnormal operation; If the verification result is that the operation is abnormal, the target hardware component is debugged and the alarm information is sent to the alarm device connected to the CPLD.

2. The method according to claim 1, characterized in that The target signal is identified and processed by the logic circuit of the CPLD to obtain target information corresponding to the target signal, including: Performing feature detection processing on the target signal through the logic circuit of the CPLD to obtain a target signal feature of the target signal, wherein the target signal feature includes at least one of the following: an address value, a level feature, a timing feature, a protocol feature, or a state feature; According to the target signal characteristics, target information corresponding to the target signal is determined.

3. The method according to claim 1, characterized in that The target information is the first command information, and the target hardware component is the CPU; performing verification processing according to the target signal and the target verification strategy to obtain a verification result includes: determining a target state machine, wherein the target state machine includes a plurality of normal command information; If the target state machine includes the first command information, determining that the verification result is verification passed; If the target state machine does not include the first command information, the first timer starts timing; If the first resend command information is received before the first timer times out, it is determined that the verification result is verification passed, the target state machine includes the first resend command information, and the first resend command information is sent by the CPU; If the first resend command information is not received before the first timer times out, the verification result is determined to be verification failure.

4. The method according to claim 1, characterized in that: The target information is second command information, and the target hardware component is a baseboard management controller BMC; Performing verification processing according to the target signal and the target verification strategy to obtain a verification result includes: Determine the current status information of the BMC; Determine the correspondence between command information and status information; If the second command information and the current state information conform to the corresponding relationship, determining that the verification result is verification passed; If the second command information and the current state information do not conform to the corresponding relationship, the second timer starts timing; If the second resend command information is received before the second timer times out, it is determined that the verification result is verification passed, the second resend command information and the current state information meet the corresponding relationship, and the second resend command information is sent by the BMC; If the second resend command information is not received before the target timer times out, it is determined that the verification result is verification failure.

5. The method according to claim 1, characterized in that The target information is a control signal, and the target hardware component is a control integrated circuit; performing verification processing according to the target signal and the target verification strategy to obtain a verification result includes: Determining the real-time control state and the real-time output state of the control integrated circuit; If the real-time control state does not match the real-time output state, the third timer starts timing; Acquiring the real-time control state and real-time output state of the control integrated circuit; If the real-time control state matches the real-time output state, determining that the verification result is verification passed; If the real-time control state does not match the real-time output state, the third timer starts timing; If the real-time control state matches the real-time output state before the third timer times out, determining that the verification result is verification passed; If the real-time control state matches the real-time output state before the third timer times out, the verification result is determined to be verification failure.

6. The method according to any one of claims 1 to 5, characterized in that Debugging the target hardware component includes: Sending a retry instruction to the target hardware component, wherein the retry instruction is used to instruct the target hardware component to re-execute a previous operation; or, A non-maskable interrupt signal is sent to the target hardware component, where the non-maskable interrupt signal is used to instruct the target hardware component to stop working.

7. A self-checking device for a server, characterized in that: The server includes a complex programmable logic device (CPLD) and a plurality of hardware components, wherein the CPLD is connected to the plurality of hardware components via signal lines respectively, and the device includes: A receiving module, used for receiving a target signal through the CPLD and the signal line; An identification module, used for identifying and processing the target signal through the logic circuit of the CPLD, obtaining target information corresponding to the target signal, and determining the target hardware component corresponding to the target signal through the signal line corresponding to the target signal; A verification module, used to determine a corresponding target verification strategy according to the target information and the target hardware component, and perform verification processing according to the target signal and the target verification strategy to obtain a verification result, wherein the verification result includes normal operation or abnormal operation; The debugging module is used to debug the target hardware component if the verification result is abnormal operation, and send the alarm information to the alarm device connected to the CPLD.

8. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 6 when executed by a processor.

10. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 6 when being executed by a processor.

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