Baseband signal generator based on programmable logic device

Abstract

The invention discloses a baseband signal generator based on a programmable logic device, and relates to the technical field of radars, a method is realized by using programmable logic resources in a universal programmable logic device, after an output frequency is generated, a phase parameter is obtained by calculating and accumulating a phase increment, and the output frequency is output. The phase parameter is used as the query address of the sine and cosine lookup table to query and output the digital baseband signal, and the method of directly reading the pre-stored data from the lookup table greatly reduces the calculation amount, saves the operation time and resources of a processor, and especially in a scene where continuous sine and cosine signals need to be generated at a high speed, greatly improves the calculation efficiency. The response speed of the system can be remarkably improved, the signal processing task with the high real-time requirement is met, the system delay time is shortened, the overall power consumption of the system is reduced, the frequency synthesis chip mounted outside the chip is reduced, and the hardware overhead is reduced.

Description

Technical Field

[0001] The present application relates to the field of radar technology, and in particular to a baseband signal generator based on a programmable logic device. Background Art

[0002] In the field of modern science and technology, target detection and ranging technology are of vital importance. Traditional target detection methods have gradually exposed their limitations in terms of accuracy, real-time performance, and the ability to cope with complex environments, making it difficult to meet the growing and diverse needs. Radar systems, with their unique radio wave detection principles, can effectively detect and measure targets under various complex conditions, thus becoming one of the core technologies in the current target detection field.

[0003] The signal transceiver module plays a pivotal role in the operation of the entire radar system. It undertakes the task of signal transmission between the antenna and is responsible for sending specific radar signals to the antenna and receiving echo signals from the antenna, thereby realizing information interaction between the radar system and the target. The baseband signal generator is an important part of the baseband design of the signal transceiver module. How to achieve high efficiency, low latency, miniaturization, and low power consumption is the top priority of baseband design, which directly affects the operating performance of the radar system. Summary of the invention

[0004] In view of the above problems and technical requirements, the present application proposes a baseband signal generator based on a programmable logic device. The technical solution of the present application is as follows:

[0005] A baseband signal generator based on a programmable logic device, the baseband signal generator comprising an output frequency calculation module implemented by programmable logic resources inside the programmable logic device, a phase increment calculation module instantiated by a floating-point multiplier implemented by the programmable logic resources, a phase accumulation module instantiated by an accumulator implemented by the programmable logic resources, and a sine-cosine lookup table instantiated by a ROM implemented by the programmable logic resources, wherein the sine-cosine lookup table stores amplitude data points under different phase parameters obtained by discretely sampling baseband waveform data of a complete baseband cycle according to the clock frequency of a system clock clk;

[0006] The output frequency calculation module generates an output frequency Fout under the triggering of the system clock clk and provides it to a multiplication input terminal of the phase increment calculation module. Another multiplication input terminal of the phase increment calculation module obtains the clock accuracy of the system clock clk. The phase increment calculation module performs a multiplication operation on the output frequency Fout and the clock accuracy to obtain a phase increment and provides it to an addition input terminal of the phase accumulation module.

[0007] Another addition input terminal of the phase accumulation module is connected to the output terminal of the phase accumulation module. The phase accumulation module performs addition operation on the phase parameter outputted from the output terminal and the phase increment under the triggering of the system clock clk to obtain a new phase parameter.

[0008] The sine-cosine lookup table is used to output amplitude data points corresponding to the phase parameters output by the phase accumulation module to generate a digital baseband signal.

[0009] Its further technical solution is that the amplitude data points obtained by performing each discrete sampling on the fundamental frequency waveform data of a complete fundamental frequency cycle include: performing discrete sampling on the sine fundamental wave data under the corresponding phase parameter to obtain the sine amplitude data point, and performing discrete sampling on the cosine fundamental wave data under the corresponding phase parameter to obtain the cosine amplitude data point, and recording the mapping relationship between the phase parameter corresponding to the discrete sampling and the storage address in the sine-cosine lookup table for storing the amplitude data point obtained by the discrete sampling;

[0010] The sine-cosine lookup table is used to output amplitude data points corresponding to the phase parameters output by the phase accumulation module, including: determining a storage address that has a mapping relationship with the phase parameters output by the phase accumulation module, and reading corresponding sine amplitude data points and cosine amplitude data points from the storage address.

[0011] A further technical solution is that the baseband signal generator also includes a data synchronization module obtained by instantiating a delay chain using programmable logic resources inside a programmable logic device;

[0012] The data synchronization module obtains the sine amplitude data points and cosine amplitude data points output by the sine-cosine lookup table, and delays the obtained sine amplitude data points and / or cosine amplitude data points by one beat each time the system clock clk is triggered. After several beats of delay, the sine amplitude data points and cosine amplitude data points with a phase difference of 90° are output as the I-channel data and Q-channel data of the digital baseband signal.

[0013] Its further technical solution is that the data storage depth of the sine-cosine lookup table is twice the total number of sampling times performed on the fundamental frequency waveform data of a complete fundamental frequency cycle, and the sine amplitude data points and cosine amplitude data points obtained by each discrete sampling are stored at different storage addresses respectively. The storage addresses that have a mapping relationship with the phase parameters corresponding to one discrete sampling include: a storage address for storing the sampled sine amplitude data points and a storage address for storing the sampled cosine amplitude data points.

[0014] A further technical solution is that the output frequency calculation module includes a sampling period accumulation module instantiated by an accumulator implemented by programmable logic resources, a frequency increment calculation module instantiated by a floating point multiplier implemented by programmable logic resources, and an adder implemented by programmable logic resources;

[0015] An addition input terminal of the sampling cycle accumulation module obtains the cycle duration of the clock cycle of the system clock clk, and another addition input terminal of the sampling cycle accumulation module is connected to the output terminal of the sampling cycle accumulation module. The sampling cycle accumulation module performs an addition operation on the sampling duration outputted from the output terminal and the cycle duration under the triggering of the system clock clk to obtain a new sampling duration;

[0016] A multiplication input terminal of the frequency increment calculation module is connected to the output terminal of the sampling period accumulation module to obtain the sampling duration, another multiplication input terminal of the frequency increment calculation module obtains the frequency modulation slope floating point number, and the frequency increment calculation module performs multiplication operation on the sampling duration and the frequency modulation slope floating point number to obtain the frequency increment and inputs it into an input terminal of the adder;

[0017] The starting frequency floating point number is input into another input terminal of the adder, and the adder performs an addition operation on the starting frequency floating point number and the frequency increment to obtain an output frequency.

[0018] A further technical solution is that the output frequency calculation module also includes a first format conversion module instantiated by a floating point multiplier implemented by programmable logic resources;

[0019] One multiplication input terminal of the first format conversion module obtains a frequency modulation slope input value, and another multiplication input terminal obtains a first unit conversion value. The first format conversion module performs a multiplication operation on the frequency modulation slope input value and the first unit conversion value, and outputs a frequency modulation slope floating point number with a target slope unit.

[0020] A further technical solution is that the output frequency calculation module also includes a second format conversion module instantiated by a floating point multiplier implemented by programmable logic resources;

[0021] One multiplication input terminal of the second format conversion module obtains the starting frequency input value, and another multiplication input terminal obtains the second unit conversion value. The first format conversion module performs a multiplication operation on the starting frequency input value and the second unit conversion value, and then outputs a starting frequency floating point number with a target frequency unit.

[0022] A further technical solution is that the output frequency calculation module also includes a first delay device and a second delay device respectively instantiated by a delay chain implemented by programmable logic resources, the output end of the frequency increment calculation module is connected to the adder after passing through the first delay device, and the starting frequency floating point number is connected to the adder after passing through the second delay device;

[0023] The first delay device delays the frequency increment output by the frequency increment calculation module by one beat each time when triggered by the system clock clk, and the second delay device delays the starting frequency floating-point number by one beat each time when triggered by the system clock clk; the frequency increment and the starting frequency floating-point number are synchronously input into the adder after being delayed for several beats respectively.

[0024] Its further technical solution is that the floating point multiplier implemented by programmable logic resources includes a multiplier, a two-to-one selector, an inverter and a bit width conversion module;

[0025] The two input ends of the multiplier are used as the two multiplication input ends of the floating-point multiplier, the output end of the multiplier is connected to the fixed end of the two-choice selector, one active end of the two-choice selector is connected to the bit width conversion module through an inverter, the other active end of the two-choice selector is directly connected to the bit width conversion module, and the output end of the bit width conversion module is used as the output end of the floating-point multiplier;

[0026] The floating-point multiplier is instantiated to form a module according to the configuration parameters of each module. The configuration parameters include the format parameters of the input multiplier, the format parameters of the intermediate calculation results, and the format parameters of the output results. The format parameters of the input multiplier include the total bit width W of the input multiplier. in , decimal point position OLD_BIN_PT and whether there is a sign bit. The format parameters of the output result include the total bit width W of the output result. out , decimal point position NEW_BIN_PT and whether there is a sign bit, the format parameters of the intermediate calculation results at least include whether the intermediate calculation results are negated MULT_NEG_EN; when the floating-point multiplier is instantiated to form a module, the active end of the two-to-one selector is configured according to whether the intermediate calculation result is negated MULT_NEG_EN, and the bit width conversion operation performed by the bit width conversion module is configured according to the configuration parameters.

[0027] A further technical solution is that the bit width conversion operation performed by the bit width conversion module includes:

[0028] Extract low D in input data in =OLD_BIN_PT+1 bit to get the decimal part of the input data; when the configuration parameter indicates that the input multiplier has a signed bit, extract the I bit except the highest bit and the decimal part of the input data in =(W in -1)-D in When the configuration parameter indicates that the input multiplier has no sign bit, the I bit other than the decimal part of the input data is extracted. in =W in -D in Get the integer part of the input data;

[0029] When the decimal point position of the output result is NEW_BIN_PT ≤ OLD_BIN_PT, the high D in the decimal part of the input data is taken. out The decimal part of the output result is taken as the low I bit of the integer part of the input data. out bits as the integer part of the output result; where D out =NEW_BIN_PT+1, when the output result has no sign bit, I out =W out -D out ; When the output result has a sign bit, I out =(W out -1)-D out ;

[0030] When the decimal point position of the output result is NEW_BIN_PT>OLD_BIN_PT, the low digits of the decimal part of the input data are filled with zeros to D out The decimal part of the output result is obtained by filling the high digits of the integer part of the input data with zeros as the integer part of the output result;

[0031] When the configuration parameter indicates that the output result has no sign bit, the integer part of the output result is used as the high bit and the decimal part of the output result is used as the low bit for data concatenation to obtain the output result; when the configuration parameter indicates that the output result has a sign bit, the integer part of the output result is used as the high bit and the decimal part of the output result is used as the low bit for data concatenation, and the sign bit of the input data is added to the highest bit to obtain the output result.

[0032] The beneficial technical effects of this application are:

[0033] The present application discloses a baseband signal generator based on a programmable logic device. The baseband signal generator can be implemented by using a general programmable logic device. The functions required by the baseband signal generator can be realized by using a small amount of programmable logic resources. After the output frequency is generated, the phase parameter is obtained by calculating the phase increment and accumulating it. Then, the phase parameter is used as the query address of the sine-cosine lookup table to query the output digital baseband signal. The method of directly reading the pre-stored data from the lookup table greatly reduces the amount of calculation, saves the processor's operation time and resources, and can significantly improve the system's response speed, especially in the scenario where continuous sine-cosine signals need to be generated at high speed, meet the signal processing tasks with high real-time requirements, and reduce the system delay time, reduce the overall power consumption of the system, and reduce the hardware overhead by reducing the frequency synthesis chip mounted outside the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a logical structure block diagram of a baseband signal generator according to an embodiment of the present application.

[0035] Figure 2 It is a logical structure block diagram of an output frequency calculation module in another embodiment of the present application.

[0036] Figure 3 It is a structural diagram of a floating-point multiplier implemented using programmable logic resources in one embodiment of the present application.

[0037] Figure 4 It is a structural diagram of a delay chain implemented using programmable logic resources in one embodiment of the present application. DETAILED DESCRIPTION

[0038] The specific implementation of the present application is further described below in conjunction with the accompanying drawings.

[0039] This application discloses a baseband signal generator based on a programmable logic device, please refer to Figure 1 As shown in the structural diagram, the baseband signal generator mainly includes the following modules which are implemented by programmable logic resources inside the programmable logic device:

[0040] 1. Output frequency calculation module

[0041] The output frequency calculation module is implemented by programmable logic resources inside the programmable logic device, and the output frequency calculation module is used to generate the required output frequency Fout under the triggering of the system clock clk.

[0042] In the actual application of the baseband signal generator, the output frequency is generated in sequence according to the input starting frequency input value and the frequency modulation slope input value, starting from the starting frequency input value and following the frequency modulation slope input value according to the clock frequency of the system clock clk, to achieve frequency sweep. And generally, the output frequency is generated starting from the negative domain so that it can cross the requirements of the positive and negative domains.

[0043] Therefore, in one embodiment, Figure 1 As shown, the output frequency calculation module includes a sampling period accumulation module, a frequency increment calculation module, and an adder implemented using programmable logic resources:

[0044] (1) Sampling period accumulation module

[0045] The sampling period accumulation module is obtained by instantiating the accumulator implemented by programmable logic resources. Please refer to Figure 1Each accumulator implemented by programmable logic resources in the present application includes two addition input terminals, one output terminal, and also includes a clock input terminal and a reset terminal. One addition terminal of the accumulator is connected to the output terminal of the accumulator to achieve accumulation. The clock input terminal of the accumulator obtains the system clock clk, so that the data of the two addition input terminals are added under the triggering of the rising edge or falling edge of the system clock clk to achieve the accumulation effect. The reset terminal of the accumulator obtains the reset signal rst, and the accumulator clears and resets the signal at the output terminal when the reset signal rst is enabled. The accumulator implemented by programmable logic resources will be instantiated multiple times, and different modules will be realized by configuring different input and output interface constraints.

[0046] An addition input terminal of the sampling period accumulation module implemented by the accumulator instantiation obtains the period duration of the clock period of the system clock clk, and another addition input terminal of the sampling period accumulation module is connected to the output terminal of the sampling period accumulation module. The period duration of the clock period of the system clock clk input to the sampling period accumulation module is a numerical representation in a predetermined value unit. For example, if the system clock clk is 30MHz, when the numerical unit of the period duration input to the sampling period accumulation module is seconds, the input period duration is the hexadecimal representation result of 1 / 30000000.

[0047] The sampling period accumulation module, triggered by the system clock clk, adds the sampling duration T0 output by the current output end to the period duration to obtain a new sampling duration T0, so that the phase accumulation module accumulates the period duration in real time according to the clock frequency of the system clock clk and outputs the sampling duration T0.

[0048] (2) Frequency increment calculation module

[0049] The frequency increment calculation module is instantiated using a floating-point multiplier implemented using programmable logic resources. The floating-point multiplier implemented using programmable logic resources in the present application includes two multiplication input terminals and one output terminal. The floating-point multiplier is used to perform multiplication operations on the data of the two multiplication input terminals and output them from the output terminal. The floating-point multiplier implemented using programmable logic resources will be instantiated multiple times, and different modules will be implemented by configuring different input and output interface constraints.

[0050] The floating-point multiplier instantiation obtains a multiplication input terminal of the frequency increment calculation module, which is connected to the output terminal of the sampling period accumulation module to obtain the sampling duration T0, and the other multiplication input terminal of the frequency increment calculation module obtains the frequency modulation slope floating point number S. The frequency modulation slope floating point number S is a floating point result with a preset target slope unit. The sampling duration T0 is input under the triggering of the system clock clk, and triggers the frequency increment calculation module to perform a multiplication operation on the sampling duration T0 and the frequency modulation slope floating point number S to obtain a frequency increment S*T0 and input it into an input terminal of the adder.

[0051] (3) Adder implemented using programmable logic resources.

[0052] One input end of the adder is connected to the output end of the frequency increment calculation module to obtain the frequency increment S*T0, and the other input end of the adder obtains the input starting frequency floating point number F0, which is a floating point result with a preset target frequency unit. The frequency increment S*T0 is input under the triggering of the system clock clk, and triggers the adder to perform an addition operation on the starting frequency floating point number F0 and the frequency increment S*T0 to obtain the output frequency Fout=S*T0+F0, thereby achieving the effect of sequentially generating the output frequency Fout from the starting frequency floating point number F0 according to the clock frequency of the system clock clk along the frequency modulation slope floating point number S.

[0053] As mentioned above, the above operation process needs to ensure that the value units of different parameters match, including the value units of the sampling time length T0, the frequency modulation slope floating point number S, the starting frequency floating point number F0 and the output frequency Fout. Therefore, after determining the value units of the sampling time length T0 and the output frequency Fout, the frequency modulation slope floating point number S needs to use the preset target slope unit, and the starting frequency floating point number F0 needs to use the preset target frequency unit. For example, in one example, the value unit used by the sampling time length T0 is seconds, the value unit of the output frequency Fout is KHz, the target slope unit used by the frequency modulation slope floating point number S is KHz / s, and the target frequency unit used by the starting frequency floating point number F0 is KHz.

[0054] However, the external input starting frequency and frequency modulation slope may not meet the above value unit requirements. In order to ensure that the value units match the requirements during the operation and improve the versatility, in one embodiment, Figure 2 As shown, the output frequency calculation module also includes a first format conversion module instantiated by a floating-point multiplier implemented using programmable logic resources. One multiplication input terminal of the first format conversion module obtains a frequency modulation slope input value, and another multiplication input terminal obtains a first unit conversion value. The first format conversion module performs a multiplication operation on the frequency modulation slope input value and the first unit conversion value, thereby outputting a frequency modulation slope floating point number S with a target slope unit. The first unit conversion value is a value representation result for converting the value unit of the frequency modulation slope input value to the target slope unit. For example, if the value unit of the frequency modulation slope input value is Hz / ms, and the target slope unit of the frequency modulation slope floating point number S is KHz / s, then the first unit conversion value is a hexadecimal representation of 0.0000001, and the same applies to other situations.

[0055] Similarly, in another embodiment, the output frequency calculation module also includes a second format conversion module instantiated by a floating-point multiplier implemented using programmable logic resources. One multiplication input terminal of the second format conversion module obtains the starting frequency input value, and the other multiplication input terminal obtains the second unit conversion value. The first format conversion module performs a multiplication operation on the starting frequency input value and the second unit conversion value, and then outputs a starting frequency floating-point number F0 with a target frequency unit. The second unit conversion value is used to convert the value unit of the starting frequency input value into a value representation result of the target frequency unit. For example, if the value unit of the starting frequency input value is Hz, and the target frequency unit of the starting frequency floating-point number F0 is KHz, then the second unit conversion value is a hexadecimal representation of 0.001, and the same is true for other cases.

[0056] In addition, since the starting frequency of the frequency sweep bandwidth starts from the negative domain to meet the requirement of crossing the positive and negative domains, the starting frequency floating-point number F0 needs to be taken as a negative number. Therefore, in order to take the multiplication result of the starting frequency input value and the second unit conversion value as a negative number, the floating-point multiplier implemented by the programmable resources in this application does not only include the multiplier itself, please refer to Figure 3 The floating-point multiplier implemented by programmable logic resources includes a multiplier, a two-choice selector MUX, an inverter and a bit width conversion module. The two input ends of the multiplier are used as two multiplication input ends of the floating-point multiplier to obtain two input multipliers a and b, the output end of the multiplier is connected to the fixed end of the two-choice selector MUX, one active end of the two-choice selector MUX is connected to the bit width conversion module through the inverter, the other active end of the two-choice selector MUX is directly connected to the bit width conversion module, and the output end of the bit width conversion module is used as the output end of the floating-point multiplier.

[0057] Under this structure of the floating-point multiplier, when the floating-point multiplier is instantiated to form different modules, the configuration parameters of the different modules need to be configured so as to realize the functions of the corresponding modules. The configuration parameters include the format parameters of the input multiplier of the floating-point multiplier, the format parameters of the intermediate calculation results, and the format parameters of the output results. Among them, the format parameters of the input multiplier include the total bit width W of the input multiplier. in , decimal point position OLD_BIN_PT. The format parameters of the intermediate calculation results at least include whether the intermediate calculation results output by the multiplier are negated MULT_NEG_EN, and whether the intermediate calculation results have a sign bit. Whether the intermediate calculation results have a sign bit is generally consistent with whether the input multiplier has a sign bit. The format parameters of the output results include the total bit width W of the output results out, decimal point position NEW_BIN_PT and whether there is a sign bit. When the floating-point multiplier is instantiated to form a module, the active end of the two-choice selector is configured according to whether the intermediate calculation result is negated MULT_NEG_EN. For example, when the second format conversion module is instantiated, the active end of the inverter needs to be configured by using whether the intermediate calculation result is negated MULT_NEG_EN. In addition, the data format of the preliminary multiplication calculation and the bit width conversion operation performed by the bit width conversion module need to be configured according to the configuration parameters.

[0058] As can be seen from the above structure, the floating-point multiplier implemented in the present application also includes a bit width conversion module. When the floating-point multiplier is instantiated, the conversion strategy of the bit width conversion module is configured by configuring parameters. The bit width conversion module can be used to perform bit width conversion on the multiplication result of the input multiplier to output the output result in the required bit width format, thereby meeting the input and output bit width requirements and data accuracy requirements of different modules.

[0059] The bit width conversion operations performed by the bit width conversion module include:

[0060] (a) First, extract the decimal part and integer part of the input data Data_in of the bit width conversion module.

[0061] The input data Data_in of the bit width conversion module is the intermediate calculation result obtained by multiplying the two input multipliers a and b of the floating point multiplier, or the inverse result of the intermediate calculation result obtained by multiplying the two input multipliers a and b of the floating point multiplier. Therefore, the format parameters of the input data Data_in of the bit width conversion module are consistent with the format parameters of the input multiplier. First, the bit widths occupied by the decimal part and the integer part of the input data Data_in are determined according to the format parameters of the input multiplier:

[0062] According to the decimal point position OLD_BIN_PT of the input multiplier, the bit width D of the decimal part of the input data Data_in can be determined. in =OLD_BIN_PT+1.

[0063] When the input data Data_in has a sign bit, the input data is the sign bit, the integer part and the decimal part from high to low. At this time, the total bit width W in Except for the highest bit, the remaining W in -1 bit is the integer part and the decimal part, the bit width of the integer part is I in =(W in -1)-D in .

[0064] When the input data Data_in has no sign bit, the input data is the integer part and the decimal part from high to low, and the total bit width Win Both are integer part and decimal part, the bit width of the integer part is I in =W in -D in .

[0065] Therefore, the bit width conversion module extracts the low D in =OLD_BIN_PT+1 bit to get the decimal part of the input data.

[0066] Then, it is necessary to determine whether the input data Data_in has a sign bit according to whether the input multiplier has a sign bit and then extract the integer part of the input data Data_in:

[0067] When the configuration parameter indicates that the input multiplier has a sign bit, it can be determined that the input data Data_in of the bit width conversion module also has a sign bit and according to the data specification, the sign bit is located at the highest bit. At this time, the I bits other than the highest bit and the decimal part of the input data are extracted. in =(W in -1)-D in The integer part of the input data is obtained.

[0068] When the configuration parameter indicates that the input multiplier has no sign bit, it can be determined that the input data Data_in of the bit width conversion module also has no sign bit, and the I bits other than the decimal part of the input data are directly extracted. in =W in -D in The integer part of the input data is obtained.

[0069] (b) The decimal part and integer part of the output result are obtained according to the decimal part and integer part of the input data Data_in.

[0070] Similarly, first determine the bit widths of the decimal part and integer part of the output result according to the format parameter of the output result. Similarly, determine the bit width of the decimal part of the output result as D according to the decimal point position NEW_BIN_PT of the output result. out = NEW_BIN_PT + 1. When the output result has a signed bit, the integer part of the output result has a bit width of I out =(W out -1)-D out When the output result has no sign bit, the integer part of the output result has a bit width of I out =W out -D out .

[0071] Then, the two parts of data are extracted according to the bit width of the decimal part and the integer part of the output result, which can be divided into two cases:

[0072] Case 1: When the decimal point position of the output result is NEW_BIN_PT ≤ OLD_BIN_PT, the high D in the decimal part of the input data Data_in is taken. out The decimal part of the output result is taken as the low I of the integer part of the input data Data_in. out bits as the integer part of the output result.

[0073] For example, in an example, assuming that the input data Data_in has no sign bit and is 12'b0101_0011_0000, the total bit width of the input data Data_in is 12 bits, and the decimal point position OLD_BIN_PT=5, it can be determined that the decimal part of the input data Data_in has a bit width of 6 and is 11_0000, and the integer part of the input data Data_in has a bit width of 6 and is 0101_00.

[0074] Assuming that the output result also has no sign bit, the total bit width is 10 bits and the decimal point position NEW_BIN_PT=4, it can be determined that the decimal part bit width of the output result is 5 and the integer part bit width is 5. Since NEW_BIN_PT≤OLD_BIN_PT, the upper 5 bits [5:1]=11_000 of the decimal part of the input data Data_in are taken as the decimal part of the output result, and the lower 5 bits [4:0]=101_00 of the integer part of the input data Data_in are taken as the integer part of the output result.

[0075] Case 2: When the decimal point position of the output result is NEW_BIN_PT>OLD_BIN_PT, the low digits of the decimal part of the input data Data_in are filled with zeros to D out The decimal part of the output result is obtained by filling the high bits of the integer part of the input data Data_in with zeros to I out The integer part of the output result is I out -I in Bit.

[0076] For example, in the above example, assuming that the output result has no sign bit, the total bit width is 15 bits and the decimal point position NEW_BIN_PT=6, it can be determined that the decimal part of the output result has a bit width of 7 and an integer part of 8. At this time, since NEW_BIN_PT>OLD_BIN_PT, the low bits of the decimal part of the input data Data_in are padded with zeros to 7 bits to obtain 11_0000_0 as the decimal part of the output result, and the high bits of the integer part of the input data Data_in are padded with zeros to 8 bits to obtain 00_0101_00 as the integer part of the output result.

[0077] (c) Obtain the output result based on the decimal part and the integer part of the output result.

[0078] When the configuration parameter indicates that the output result has no sign bit, the integer part of the output result is used as the high bit and the decimal part of the output result is used as the low bit to concatenate the data to obtain the output result.

[0079] When the configuration parameter indicates that the output result has a signed bit, the integer part of the output result is used as the high bit and the decimal part of the output result is used as the low bit for data concatenation, and the sign bit of the input data is added to the highest bit to obtain the output result.

[0080] In another embodiment, Figure 2 As shown, the output frequency calculation module also includes a first delay device and a second delay device respectively instantiated by a delay chain implemented by programmable logic resources. The delay chain implemented in the present application is as shown in FIG. Figure 4 As shown, it includes a plurality of D flip-flops cascaded in sequence, and the clock input end of each D flip-flop in the delay chain is connected to the system clock clk to perform a register action under the triggering of the system clock clk. The reset end of each D flip-flop in the delay chain is also connected to the clear signal SCLR, and the delay chain is reset when the clear signal SCLR is enabled. The delay chain implemented by programmable logic resources will be instantiated multiple times, and different modules are implemented by configuring different input and output interface constraints.

[0081] The output end of the frequency increment calculation module is connected to the adder after passing through the first delay device, and the starting frequency floating point number F0 is connected to the adder after passing through the second delay device. The first delay device delays the frequency increment S*T0 output by the frequency increment calculation module by one beat each time triggered by the system clock clk, and the second delay device delays the starting frequency floating point number F0 by one beat each time triggered by the system clock clk. The frequency increment and the starting frequency floating point number are synchronously input into the adder after being delayed for several beats respectively. This method can delay the intermediate data to ensure the stability of the data.

[0082] 2. Phase increment calculation module

[0083] The phase increment calculation module is obtained by instantiating a floating point multiplier implemented by programmable logic resources inside a programmable logic device.

[0084] One multiplication input terminal of the phase increment calculation module is connected to the output terminal of the output frequency calculation module to obtain the output frequency Fout, and the other multiplication input terminal of the phase increment calculation module obtains the clock accuracy A of the input system clock clk. clk The input clock accuracy is A clk The clock precision of the system clock clk is converted into a numerical result representation that matches the value unit of the output frequency Fout. For example, in actual applications, the value unit of the output frequency Fout is usually configured as KHz, then the clock precision Aclk The value unit is configured as 1 / KHz. When the system clock clk is 30MHz, the clock accuracy is A clk That is 1 / 30000, and its hexadecimal representation result is taken as the input of the phase increment calculation module.

[0085] The output frequency Fout is input under the trigger of the system clock clk, and triggers the phase increment calculation module to perform multiplication operation on the output frequency Fout and the clock accuracy to obtain the phase increment To provide an adding input terminal of the phase accumulation module.

[0086] 3. Phase accumulation module

[0087] The phase accumulation module is instantiated by an accumulator implemented by programmable logic resources. An addition input terminal of the phase accumulation module is connected to the output terminal of the phase increment calculation module to obtain the phase increment. The other addition input terminal is connected to the output terminal of the phase accumulation module. The phase accumulation module converts the phase parameter output by the current output terminal into the phase parameter output by the current output terminal under the triggering of the system clock clk. Phase increment with new input After performing the addition operation, the new phase parameter is obtained Thereby, the phase accumulation module accumulates and outputs the phase parameter in real time according to the clock frequency of the system clock clk.

[0088] 4. Sin and Cosine Lookup Table

[0089] The sine-cosine lookup table is instantiated by a ROM (Read-Only Memory) implemented by programmable logic resources inside a programmable logic device. The sine-cosine lookup table stores amplitude data points under different phase parameters obtained by discretely sampling the fundamental frequency waveform data of a complete fundamental frequency cycle according to the clock frequency of the system clock clk. Specifically, each discrete sampling of the fundamental frequency waveform data of a complete fundamental frequency cycle includes: discrete sampling of the sine fundamental wave data under the corresponding phase parameter to obtain the sine amplitude data point, and discrete sampling of the cosine fundamental wave data under the corresponding phase parameter to obtain the cosine amplitude data point. Then, the sine amplitude data points and cosine amplitude data points obtained by each discrete sampling are stored in the sine-cosine lookup table, and the mapping relationship between the phase parameter corresponding to the discrete sampling and the storage address in the sine-cosine lookup table for storing the amplitude data points obtained by discrete sampling is recorded.

[0090] Then the phase parameter output by the phase accumulation module is As the query address of the sine-cosine lookup table, query the phase parameter from the sine-cosine lookup table The corresponding amplitude data points generate digital baseband signal output, including determining the phase parameters output by the phase accumulation module There is a storage address of the mapping relationship, and the corresponding sine amplitude data point sin_lut and cosine amplitude data point cos_lut are read from the storage address to generate a digital baseband signal.

[0091] The data storage depth of the sine-cosine lookup table is determined according to the number of discrete sampling times performed on the fundamental frequency waveform data of a complete fundamental frequency cycle, and the data storage width of the sine-cosine lookup table is set according to the accuracy of the amplitude data points obtained by sampling. In one embodiment, the data storage depth of the sine-cosine lookup table is twice the total number of sampling times performed on the fundamental frequency waveform data of a complete fundamental frequency cycle, and the data storage width of the sine-cosine lookup table is set according to the accuracy requirements of each sine amplitude data point / cosine amplitude data point, so as to accurately represent the amplitude change of the fundamental frequency waveform data. Then, the sine amplitude data points and cosine amplitude data points obtained by each discrete sampling performed under the same phase parameter are stored at different storage addresses respectively. When recording the mapping relationship between the phase parameter corresponding to the discrete sampling and the storage address of the amplitude data point, the corresponding relationship between the phase parameter corresponding to the discrete sampling and the storage address sin_addr for storing the sampled sine amplitude data point sin_lut and the storage address cos_addr for storing the sampled cosine amplitude data point cos_lut are recorded respectively. Then, when reading the phase parameter When the corresponding amplitude data point is obtained, first determine the phase parameter The corresponding storage address sin_addr and storage address cos_addr then read the phase parameter from the storage address sin_addr The corresponding sine amplitude data point sin_lut, reads the phase parameter from the storage address cos_addr The corresponding cosine amplitude data point is cos_lut.

[0092] In another embodiment, please refer to Figure 1 The baseband signal generator also includes a data synchronization module instantiated by a delay chain implemented by programmable logic resources inside a programmable logic device. The data synchronization module obtains the sine amplitude data point sin_lut and the cosine amplitude data point cos_lut output by the sine-cosine lookup table, and delays the obtained sine amplitude data point sin_lut and / or cosine amplitude data point cos_lut by one beat each time the system clock clk is triggered, and after several beats of delay, the sine amplitude data point SINE and the cosine amplitude data point COSINE with a phase difference of 90° are output as the I-channel data and Q-channel data of the digital baseband signal.

[0093] Compared with calculating the digital baseband signal in real time through mathematical formulas of trigonometric functions (such as Taylor series expansion, etc.), directly reading the pre-stored amplitude data points from the sine and cosine lookup table greatly reduces the amount of calculation, saves processor operation time and resources, and can significantly improve the system response speed, especially in scenarios where high-speed generation of continuous digital baseband signals is required, to meet signal processing tasks with high real-time requirements. In addition, as the accumulation proceeds, when the phase parameter After the phase accumulation module reaches the maximum value that can be represented, an overflow will occur. However, due to the phase parameter accumulated It is used as the query address for the sine-cosine lookup table, and the data of the sine-cosine lookup table is periodic data. Therefore, even if the phase accumulation module overflows, the actual search result is correct, so the overflow phenomenon of the phase accumulation module is recognized.

[0094] The above is only a preferred embodiment of the present application, and the present application is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the protection scope of the present application.

Claims

1. A baseband signal generator based on a programmable logic device, characterized in that: The baseband signal generator includes an output frequency calculation module implemented by programmable logic resources inside a programmable logic device, a phase increment calculation module instantiated by a floating-point multiplier implemented by programmable logic resources, a phase accumulation module instantiated by an accumulator implemented by programmable logic resources, and a sine-cosine lookup table instantiated by a ROM implemented by programmable logic resources, wherein the sine-cosine lookup table stores amplitude data points under different phase parameters obtained by discretely sampling baseband waveform data of a complete baseband cycle according to the clock frequency of a system clock clk; The output frequency calculation module generates an output frequency Fout under the triggering of the system clock clk and provides it to a multiplication input terminal of the phase increment calculation module. Another multiplication input terminal of the phase increment calculation module obtains the clock accuracy of the system clock clk. The phase increment calculation module performs a multiplication operation on the output frequency Fout and the clock accuracy to obtain a phase increment and provides it to an addition input terminal of the phase accumulation module. Another addition input end of the phase accumulation module is connected to the output end of the phase accumulation module. The phase accumulation module performs an addition operation on the phase parameter outputted from the output end and the phase increment under the triggering of the system clock clk to obtain a new phase parameter; The sine-cosine lookup table is used to output amplitude data points corresponding to the phase parameters output by the phase accumulation module to generate a digital baseband signal.

2. The baseband signal generator according to claim 1, characterized in that: The amplitude data points obtained by performing each discrete sampling of the fundamental frequency waveform data of a complete fundamental frequency cycle include: performing discrete sampling of the sine fundamental wave data under the corresponding phase parameter to obtain the sine amplitude data points, and performing discrete sampling of the cosine fundamental wave data under the corresponding phase parameter to obtain the cosine amplitude data points, and recording the mapping relationship between the phase parameter corresponding to the discrete sampling and the storage address in the sine-cosine lookup table for storing the amplitude data points obtained by the discrete sampling; The sine-cosine lookup table is used to output amplitude data points corresponding to the phase parameters output by the phase accumulation module, including: determining a storage address that has a mapping relationship with the phase parameters output by the phase accumulation module, and reading corresponding sine amplitude data points and cosine amplitude data points from the storage address.

3. The baseband signal generator according to claim 2, characterized in that: The baseband signal generator also includes a data synchronization module obtained by instantiating a delay chain using programmable logic resources inside a programmable logic device; The data synchronization module obtains the sine amplitude data points and cosine amplitude data points output by the sine-cosine lookup table, and delays the obtained sine amplitude data points and / or cosine amplitude data points by one beat each time the system clock clk is triggered, and after several beats of delay, outputs the sine amplitude data points and cosine amplitude data points with a phase difference of 90° as the I-channel data and Q-channel data of the digital baseband signal.

4. The baseband signal generator according to claim 2, characterized in that: The data storage depth of the sine-cosine lookup table is twice the total number of sampling times performed on the fundamental frequency waveform data of a complete fundamental frequency cycle. The sine amplitude data points and cosine amplitude data points obtained by each discrete sampling are respectively stored at different storage addresses. The storage addresses that have a mapping relationship with the phase parameters corresponding to one discrete sampling include: a storage address for storing the sampled sine amplitude data points and a storage address for storing the sampled cosine amplitude data points.

5. The baseband signal generator according to claim 1, characterized in that: The output frequency calculation module includes a sampling period accumulation module instantiated by an accumulator implemented by programmable logic resources, a frequency increment calculation module instantiated by a floating point multiplier implemented by programmable logic resources, and an adder implemented by programmable logic resources; One addition input end of the sampling period accumulation module obtains the period duration of the clock period of the system clock clk, and another addition input end of the sampling period accumulation module is connected to the output end of the sampling period accumulation module. The sampling period accumulation module performs addition operation on the sampling duration outputted from the output end and the period duration under the triggering of the system clock clk to obtain a new sampling duration; One multiplication input terminal of the frequency increment calculation module is connected to the output terminal of the sampling period accumulation module to obtain the sampling duration, and another multiplication input terminal of the frequency increment calculation module obtains the frequency modulation slope floating point number. The frequency increment calculation module performs multiplication operation on the sampling duration and the frequency modulation slope floating point number to obtain the frequency increment and inputs the frequency increment into one input terminal of the adder; The starting frequency floating point number is input into another input terminal of the adder, and the adder performs an addition operation on the starting frequency floating point number and the frequency increment to obtain an output frequency.

6. The baseband signal generator according to claim 5, characterized in that: The output frequency calculation module also includes a first format conversion module instantiated by a floating point multiplier implemented by programmable logic resources; One multiplication input terminal of the first format conversion module obtains a frequency modulation slope input value, and another multiplication input terminal obtains a first unit conversion value. The first format conversion module performs a multiplication operation on the frequency modulation slope input value and the first unit conversion value, and outputs a frequency modulation slope floating point number with a target slope unit.

7. The baseband signal generator according to claim 5, characterized in that: The output frequency calculation module also includes a second format conversion module instantiated by a floating point multiplier implemented by programmable logic resources; One multiplication input terminal of the second format conversion module obtains a starting frequency input value, and another multiplication input terminal obtains a second unit conversion value. The first format conversion module performs a multiplication operation on the starting frequency input value and the second unit conversion value and then outputs a starting frequency floating point number with a target frequency unit.

8. The baseband signal generator according to claim 5, characterized in that: The output frequency calculation module also includes a first delay device and a second delay device respectively instantiated by a delay chain implemented by programmable logic resources, the output end of the frequency increment calculation module is connected to the adder after passing through the first delay device, and the starting frequency floating point number is connected to the adder after passing through the second delay device; The first delay device delays the frequency increment output by the frequency increment calculation module by one beat each time when triggered by the system clock clk, and the second delay device delays the starting frequency floating-point number by one beat each time when triggered by the system clock clk; the frequency increment and the starting frequency floating-point number are synchronously input into the adder after being delayed for several beats respectively.

9. The baseband signal generator according to claim 1, characterized in that: The floating-point multiplier implemented by programmable logic resources includes a multiplier, a two-to-one selector, an inverter and a bit width conversion module; The two input ends of the multiplier serve as the two multiplication input ends of the floating-point multiplier, the output end of the multiplier is connected to the fixed end of the two-choice selector, one active end of the two-choice selector is connected to the bit width conversion module via an inverter, the other active end of the two-choice selector is directly connected to the bit width conversion module, and the output end of the bit width conversion module serves as the output end of the floating-point multiplier; The floating-point multiplier is instantiated according to the configuration parameters of each module to form the module, wherein the configuration parameters include the format parameters of the input multiplier, the format parameters of the intermediate calculation result and the format parameters of the output result, and the format parameters of the input multiplier include the total bit width W of the input multiplier. in , decimal point position OLD_BIN_PT and whether there is a sign bit. The format parameters of the output result include the total bit width W of the output result. out , decimal point position NEW_BIN_PT and whether there is a sign bit, the format parameters of the intermediate calculation result at least include whether the intermediate calculation result is negated MULT_NEG_EN; when the floating-point multiplier is instantiated to form the module, the active end of the two-to-one selector is configured according to whether the intermediate calculation result is negated MULT_NEG_EN, and the bit width conversion operation performed by the bit width conversion module is configured according to the configuration parameters.

10. The baseband signal generator according to claim 9, characterized in that: The bit width conversion operations performed by the bit width conversion module include: Extract low D in input data in =OLD_BIN_PT+1 bit to get the decimal part of the input data; when the configuration parameter indicates that the input multiplier has a signed bit, extract the I bit except the highest bit and the decimal part of the input data in =(W in -1)-D in When the configuration parameter indicates that the input multiplier has no sign bit, the I bit other than the decimal part of the input data is extracted. in =W in -D in Get the integer part of the input data; When the decimal point position of the output result is NEW_BIN_PT ≤ OLD_BIN_PT, the high D in the decimal part of the input data is taken. out The decimal part of the output result is taken as the low I bit of the integer part of the input data. out bits as the integer part of the output result; where D out =NEW_BIN_PT+1, when the output result has no sign bit, I out =W out -D out ; When the output result has a sign bit, I out =(W out -1)-D out ; When the decimal point position of the output result is NEW_BIN_PT>OLD_BIN_PT, the low digits of the decimal part of the input data are filled with zeros to D out The decimal part of the output result is obtained by filling the high digits of the integer part of the input data with zeros as the integer part of the output result; When the configuration parameter indicates that the output result has no sign bit, the integer part of the output result is used as the high bit and the decimal part of the output result is used as the low bit for data splicing to obtain the output result; when the configuration parameter indicates that the output result has a sign bit, the integer part of the output result is used as the high bit and the decimal part of the output result is used as the low bit for data splicing, and then the sign bit of the input data is added to the highest bit to obtain the output result.

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